AD8233 [ADI]
Fitness and activity heart rate monitors;
| 型号： | AD8233 |
| 厂家： | 
ADI |
| 描述： | Fitness and activity heart rate monitors |
| 文件： | 总30页 (文件大小：772K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
50 μA, 2 mm × 1.7 mm WLCSP, Low Noise,
Heart Rate Monitor for Wearable Products
Data Sheet
AD8233
FEATURES
FUNCTIONAL BLOCK DIAGRAM
A4
B4
A3
A2
A1
Fully integrated, single-lead electrocardiogram (ECG) front end
Low quiescent supply current: 50 μA (typical)
Leads on/off detection while in shutdown (<1 μA)
Common-mode rejection ratio: 80 dB (dc to 60 Hz)
2 or 3 electrode configurations
High signal gain (G = 100) with dc blocking capabilities
2-pole adjustable high-pass filter
Accepts up to 300 mV of half cell potential
Fast restore feature improves filter settling
Uncommitted op amp
3-pole adjustable low-pass filter with adjustable gain
Integrated right leg drive (RLD) amplifier with shutdown
Single-supply operation: 1.7 V to 3.5 V
Integrated reference buffer generates virtual ground
Rail-to-rail output
HPSENSE
HPDRIVE
IAOUT
REFIN
+V
GND
S
A5
FR
AC/DC
SDN
B3
B2
B1
S1 10kΩ
A3
+IN
B5
IA
–IN
C5
150kΩ
AD8233
C4
RLDFB
RLD SDN C2
LOD
D5
A2
RLD
LEADS OFF
DETECTION
C1
C
S2
10kΩ
A1
SW
OPAMP+ REFOUT OPAMP–
OUT
D4
D3
C3
D2
D1
Internal RFI filter
8 kV human body model (HBM) ESD rating
Shutdown pin
Figure 1.
2 mm × 1.7 mm WLCSP
APPLICATIONS
Fitness and activity heart rate monitors
Portable ECG
Wearable and remote health monitors
Gaming peripherals
Biopotential signal acquisition, such as EMG
includes an amplifier for driven lead applications, RLD.
GENERAL DESCRIPTION
The AD8233 includes a fast restore function that reduces the
duration of the otherwise long settling tails of the high-pass
filters. After an abrupt signal change that rails the amplifier
(such as a leads off condition), the AD8233 automatically
adjusts to a higher filter cutoff. This feature allows the AD8233
to recover quickly, and therefore, to take valid measurements
soon after connecting the electrodes to the subject.
The AD8233 is an integrated signal conditioning block for ECG
and other biopotential measurement applications. It is designed
to extract, amplify, and filter small biopotential signals in the
presence of noisy conditions, such as those created by motion or
remote electrode placement. This design allows an ultralow
power analog-to-digital converter (ADC) or an embedded
microcontroller to easily acquire the output signal.
The AD8233 is available in a 2 mm × 1.7 mm, 20-ball WLCSP
package. Performance is specified from 0°C to 70°C and is
operational from −40°C to +85°C.
The AD8233 implements a two-pole high-pass filter for
eliminating motion artifacts and the electrode half cell potential.
This filter is tightly coupled with the instrumentation architec-
ture of the amplifier to allow both large gain and high-pass
filtering in a single stage, thereby saving space and cost.
Table 1. AD8232 vs. AD8233 Comparison
Parameter
AD8232
AD8233
50 μA
Supply Current
170 μA
An uncommitted operational amplifier enables the AD8233 to
create a three-pole, low-pass filter to remove additional noise.
The user can select the frequency cutoff of all filters to suit
different types of applications.
Peak-to-Peak Voltage Noise
(f = 0.5 Hz to 40 Hz)
14 μV p-p
8.5 μV
Leads On/Off Detection in
Shutdown
Not included
Not included
Included
Right Leg Drive Shutdown
Package Size
Included
To improve the common-mode rejection of the line frequencies
in the system and other undesired interferences, the AD8233
4 mm × 4 mm ×
0.75 mm
2 mm × 1.7 mm ×
0.5 mm
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2016 Analog Devices, Inc. All rights reserved.
www.analog.com
AD8233* Product Page Quick Links
Last Content Update: 11/01/2016
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• AD8233: 50 μA, 2 mm × 1.7 mm WLCSP, Low Noise,
Heart Rate Monitor for Wearable Products Data Sheet
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User Guides
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WLCSP, Low Noise, Heart Rate Monitor for Wearable
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Tools and Simulations
• AD8232/AD8233 Filter Design Tool
• AD8233 SPICE Macro-Model
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AD8233
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Fast Restore Circuit.................................................................... 18
Leads On/Off Detection............................................................ 19
Standby Operation ..................................................................... 20
Input Protection ......................................................................... 21
Radio Frequency Interference (RFI)........................................ 21
Power Supply Regulation and Bypassing ................................ 21
Input Referred Offsets ............................................................... 21
Layout Recommendations ........................................................ 21
Applications Information.............................................................. 22
Eliminating Electrode Offsets................................................... 22
High-Pass Filtering..................................................................... 22
Low-Pass Filtering and Gain..................................................... 24
Driven Electrode ........................................................................ 25
Application Circuits ....................................................................... 26
Heart Rate Measurement (HRM) Next to the Heart............. 26
Exercise Application—Heart Rate Measured at the Hands.. 26
Holter Monitor Configuration ................................................. 27
Synchronized ECG and PPG Measurement ........................... 28
Packaging and Ordering Information ......................................... 29
Outline Dimensions................................................................... 29
Ordering Guide .......................................................................... 29
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Instrumentation Amplifier Performance Characteristics....... 8
Operational Amplifier Performance Characteristics............. 11
Right Leg Drive (RLD) Amplifier Performance
Characteristics ............................................................................ 14
Reference Buffer Performance Characteristics....................... 15
System Performance Characteristics ....................................... 16
Theory of Operation ...................................................................... 17
Architecture Overview .............................................................. 17
Instrumentation Amplifier........................................................ 17
Operational Amplifier ............................................................... 17
Right Leg Drive Amplifier......................................................... 18
Reference Buffer ......................................................................... 18
REVISION HISTORY
8/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 29
Data Sheet
AD8233
SPECIFICATIONS
SDN
DC
= high, AC/
SDN
+VS = 1.8 V to 3 V 5.5%, VREF = +VS/2, VCM = +VS/2, TA = 25°C, FR = low,
= low, RLD
= low, unless otherwise noted.
Table 2.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
INSTRUMENTATION AMPLIFIER
Common-Mode Rejection Ratio,
DC to 60 Hz
CMRR
V
CM = 0.35 V to +VS − 150 mV, VDIFF = 0 V
80
86
dB
VCM = 0.35 V to +VS − 150 mV, VDIFF = 0.3 V
+VS = 1.8 V to 3.5 V
80
90
dB
dB
Power Supply Rejection Ratio
Offset Voltage (RTI)
PSRR
VOS
76
Instrumentation Amplifier Inputs
DC Blocking Input1
1
25
6
mV
μV
Average Offset Drift
Instrumentation Amplifier Inputs
DC Blocking Input1
Input Bias Current
2
μV/°C
μV/°C
pA
nA
pA
0.05
50
1
25
1
IB
200
100
TA = 0°C to 70°C
TA = 0°C to 70°C
Input Offset Current
IOS
nA
Input Impedance
Differential
Common Mode
10||7.5
5||15
GΩ||pF
GΩ||pF
Input Voltage Noise (RTI)
Spectral Noise Density
Peak-to-Peak Voltage Noise
f = 1 kHz
150
10
8.5
nV/√Hz
μV p-p
μV p-p
V
f = 0.1 Hz to 10 Hz
f = 0.5 Hz to 40 Hz
TA = 0°C to 70°C
Input Voltage Range
DC Differential Input Range
Output
0.2
−300
+VS
+300
VDIFF
mV
Output Swing
Short-Circuit Current
Gain
RL = 50 kΩ
0.1
+VS − 0.1
V
IOUT
AV
6.3
100
0.4
1
12
1
mA
V/V
%
Gain Error
VDIFF = 0 V
VDIFF = −300 mV to +300 mV
TA = 0°C to 70°C
4
%
Average Gain Drift
Bandwidth
RFI Filter Cutoff (Each Input)
OPERATIONAL AMPLIFIER (A1)
Offset Voltage
ppm/°C
kHz
MHz
BW
1
VOS
TC
IB
1
1
100
1
100
1
5
mV
μV/°C
pA
nA
pA
nA
V
dB
dB
dB
V
Average Temperature Coefficient
Input Bias Current
TA = 0°C to 70°C
TA = 0°C to 70°C
Input Offset Current
IOS
TA = 0°C to 70°C
Input Voltage Range
0.1
0.1
+VS − 0.1
+VS − 0.1
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Range
CMRR
PSRR
AVO
VCM = 0.5 V to +VS − 0.5 V
100
100
110
RL = 50 kΩ
Short-Circuit Current Limit
Gain Bandwidth Product
IOUT
GBP
12
15
mA
kHz
Rev. 0 | Page 3 of 29
AD8233
Data Sheet
Parameter
Symbol Test Conditions/Comments
Min
Typ
0.01
120
7
Max
Unit
Slew Rate
Voltage Noise Density (RTI)
Peak-to-Peak Voltage Noise (RTI)
SR
V/μs
en
f = 1 kHz
nV/√Hz
μV p-p
μV p-p
en p-p
f = 0.1 Hz to 10 Hz
f = 0.5 Hz to 40 Hz
9
RIGHT LEG DRIVE AMPLIFIER (A2)
Quiescent Supply Current
Output Swing
7.5
10
+VS − 0.1
μA
V
RL = 50 kΩ
0.1
Short-Circuit Current
Integrator Input Resistor
Gain Bandwidth Product
REFERENCE BUFFER (A3)
Offset Error
Input Bias Current
Short-Circuit Current Limit
Voltage Range
IOUT
11
150
20
mA
kΩ
kHz
120
180
GDP
VOS
IB
IOUT
RL > 50 kΩ
RL = 50 kΩ
1
100
12
mV
pA
mA
V
0.1
+VS − 0.7
DC LEADS OFF COMPARATORS
Threshold Voltage
Hysteresis
+VS − 0.27
125
1.5
V
mV
μs
Propagation Delay
AC LEADS OFF DETECTOR
Square Wave Frequency
Square Wave Amplitude
Input Currents in Shutdown Mode2
fAC
IAC
IDC
50
10
8
100
200
250
−300
20
175
kHz
nA p-p
nA
+IN, SDN = low
−IN, SDN = low
nA
Impedance Threshold
Detection Delay
Between +IN and −IN, SDN = high
MΩ
ꢀs
100
FAST RESTORE CIRCUIT
Switches
S1 and S2
On Resistance
Off Leakage
RON
10
100
12
kΩ
pA
Window Comparator
Threshold Voltage
Propagation Delay
Switch Timing Characteristics
From either rail
100
2
mV
μs
Feedback Recovery Switch On Time tS1
+VS = 3 V
+VS = 1.8 V
+VS = 3 V
+VS = 1.8 V
+VS = 3 V
+VS = 1.8 V
160
80
80
40
3
ms
ms
μs
Filter Recovery Switch On Time
Fast Restore Reset
tS2
tRST
1.5
LOGIC INTERFACE
Input Characteristics
Input Voltage (AC/DC, FR, and
RLD SDN)
Low
High
VIL
VIH
0.41 × +VS
0.45 × +VS
V
V
Input Voltage (SDN)
Low
High
VIL
VIH
0.6 × +VS
0.3 × +VS
V
V
Output Characteristics
Output Voltage
Low
LOD terminal
RL = 100 kΩ
VOL
VOH
0.05
+VS − 0.05
V
V
High
Rev. 0 | Page 4 of 29
Data Sheet
AD8233
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
70
Unit
SYSTEM SPECIFICATIONS
Quiescent Supply Current
50
60
0.65
0.75
0.5
0.6
μA
μA
μA
μA
μA
μA
TA = 0°C to 70°C
SDN = low, LOD = low
TA = 0°C to 70°C
SDN = low, LOD = high
TA = 0°C to 70°C
Wakeup Current
1.5
1
Shutdown Current
Peak-to-Peak Voltage Noise (RTI)
VDIFF = 0 V
f = 0.5 Hz to 40 Hz
f = 0.05 Hz to 150 Hz
VDIFF = 0.3 V
9
15
μV p-p
μV p-p
f = 0.5 Hz to 40 Hz
f = 0.05 Hz to 150 Hz
11
21
μV p-p
μV p-p
V
Supply Range
1.7
0
3.5
70
Specified Temperature Range
Operational Temperature Range
°C
−40
+85
°C
1 Offset referred to the input of the instrumentation amplifier inputs.
2 In ac leads off and shutdown mode, the dc leads off comparator at the +IN pin trips the LOD pin.
Rev. 0 | Page 5 of 29
AD8233
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Supply Voltage
3.6 V
Output Short-Circuit Current Duration
Maximum Voltage, Any Terminal1
Minimum Voltage, Any Terminal1
Storage Temperature Range
Operating Temperature Range
Maximum Junction Temperature
ESD Rating
Indefinite
+VS + 0.3 V
−0.3 V
−65°C to +125°C
−40°C to +85°C
140°C
Table 4. Thermal Resistance
θJA (°C/W)
Package
Type
θJC
PCB
Power (W) 0 ms
1 ms 2 ms (°C/W)
CP-20-13
1S0P1
0.25
1.25
0.25
1.25
108.5
101.1
47.9
89.0
87.3
43.4
43.3
82.3
87.3
42.1
42.1
0.6
0.6
0.7
0.7
2S2P2
HBM
8 kV
1 kV
46.8
Charged Device Model (FICDM)
1 Simulated thermal numbers per JESD51-9: 1-layer PCB (1S0P), low effective
thermal conductivity test board.
1 This level or the maximum specified supply voltage, whichever is the lesser,
indicates the superior voltage limit for any terminal. If input voltages beyond
the specified minimum or maximum voltages are expected, place resistors in
series with the inputs to limit the current to less than 5 mA.
2 4-layer PCB (2S2P), high effective thermal conductivity test board.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. 0 | Page 6 of 29
Data Sheet
AD8233
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
AD8233
INDICATOR
1
2
3
4
5
GND
+V
REFIN HPSENSE HPDRIVE
S
A
SDN
AC/DC
FR
IAOUT
+IN
B
C
D
LOD RLD SDN REFOUT RLDFB
–IN
OUT
OPAMP– OPAMP+
SW
RLD
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
A1
A2
A3
A4
GND
+VS
REFIN
HPSENSE
Power Supply Ground.
Power Supply Terminal.
Reference Buffer Input. Use REFIN, a high impedance input terminal, to set the level of the reference buffer.
High-Pass Sense Input for Instrumentation Amplifier. Connect HPSENSE to the junction of R and C that sets the
corner frequency of the dc blocking circuit.
A5
HPDRIVE
High-Pass Driver Output. Connect HPDRIVE to the capacitor in the first high-pass filter. The AD8233 drives this pin
to keep HPSENSE at the same level as the reference voltage.
B1
B2
SDN
Shutdown Control Input. Drive SDN low to enter the low power shutdown mode.
AC/DC
Leads Off Mode Control Input. Drive the AC/DC pin low for dc leads off mode. Drive the AC/DC pin high for ac
leads off mode.
B3
B4
B5
C1
C2
C3
FR
IAOUT
+IN
LOD
RLD SDN
REFOUT
Fast Restore Control Input. Drive FR high to enable fast recovery mode; otherwise, drive it low.
Instrumentation Amplifier Output Terminal.
Instrumentation Amplifier, Positive Input. +IN is typically connected to the left arm (LA) electrode.
Leads Off Detection (LOD) Comparator Output.
Right Leg Drive Shutdown Control Input. Drive RLD SDN low to power down the RLD amplifier.
Reference Buffer Output. The instrumentation amplifier output is referenced to this potential. Use REFOUT as a
virtual ground for any point in the circuit that requires a signal reference.
C4
C5
D1
RLDFB
−IN
OUT
Right Leg Drive Feedback Input. RLDFB is the feedback terminal for the right leg drive circuit.
Instrumentation Amplifier, Negative Input. −IN is typically connected to the right arm (RA) electrode.
Operational Amplifier Output. The fully conditioned heart rate signal is present at this output. OUT can be
connected to the input of an ADC.
D2
D3
D4
D5
OPAMP−
OPAMP+
SW
Operational Amplifier Inverting Input.
Operational Amplifier Noninverting Input.
Fast Restore Switch Terminal. Connect this terminal to the output of the second high-pass filter.
Right Leg Drive Output. Connect the driven electrode (typically, right leg) to the RLD pin.
RLD
Rev. 0 | Page 7 of 29
AD8233
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
+VS = 3 V, VREF = 1.5 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted.
INSTRUMENTATION AMPLIFIER PERFORMANCE CHARACTERISTICS
2100
1750
1400
1050
700
350
0
100
80
60
40
20
0
–20
–40
–60
–80
–100
–120
–90
–60
–30
0
30
60
90
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
CMRR (µV/V)
INPUT COMMON-MODE VOLTAGE (V)
Figure 3. CMRR Distribution
Figure 6. Input Bias Current vs. Input Common-Mode Voltage
3500
3000
2500
1500
1000
500
50
NO DC OFFSET
300mV OFFSET
40
30
20
10
0
0
–2.0
–10
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
1
10
100
1k
10k
100k
GAIN ERROR (%)
FREQUENCY (Hz)
Figure 4. Gain Error Distribution
Figure 7. Gain vs. Frequency
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
120
100
80
60
40
NO DC OFFSET
+300mV OFFSET
–300mV OFFSET
–0.5
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
10
100
1k
10k
100k
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 5. Input Common-Mode Voltage vs. Output Voltage
Figure 8. CMRR vs. Frequency (RTI)
Rev. 0 | Page 8 of 29
Data Sheet
AD8233
100
90
80
70
60
50
40
30
20
10
0
5µV/DIV
200ms/DIV
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 9. PSRR vs. Frequency (RTI)
Figure 12. 0.5 Hz to 40 Hz Noise (RTI)
10k
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1k
100
10
0.1
1
10
100
1k
10k
100k
0
50
100
150
200
250
300
FREQUENCY (Hz)
DC OFFSET (mV)
Figure 10. Voltage Noise Spectral Density (RTI)
Figure 13. Gain Error vs. DC Offset
22pF
470pF
1nF
5µV/DIV
400µs/DIV
50mV/DIV
1s/DIV
Figure 11. 0.1 Hz to 10 Hz Noise (RTI)
Figure 14. Small Signal Pulse Response
Rev. 0 | Page 9 of 29
AD8233
Data Sheet
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
80
70
60
50
40
30
20
10
0
I
I
B
OS
–0.5
–1.0
–10
–20
400µs/DIV
0.5V/DIV
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 15. Large Signal Pulse Response
Figure 18. Input Bias Current (IB) and Input Offset Current (IOS) vs.
Temperature
0.5
0.4
1.5
1.0
0.3
0.2
0.5
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.5
–1.0
–1.5
–40°C
+25°C
+85°C
100
1k
10k
100k
1M
–40
–20
0
20
40
60
80
100
LOAD (ꢀ)
TEMPERATURE (°C)
Figure 16. Output Voltage Swing vs. Load
Figure 19. Gain Error vs. Temperature
0.4
0.3
10
8
6
0.2
0.1
4
2
0
0
–2
–4
–6
–8
–10
–0.1
–0.2
–0.3
–0.4
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. DC Blocking Input Offset Drift
Figure 20. CMRR vs. Temperature
Rev. 0 | Page 10 of 29
Data Sheet
AD8233
OPERATIONAL AMPLIFIER PERFORMANCE CHARACTERISTICS
1000
800
600
400
200
0
0.5V/DIV
400µs/DIV
–4
–2
0
2
4
OFFSET VOLTAGE (mV)
Figure 21. Offset Distribution
Figure 24. Large Signal Transient Response
120
100
80
0
10k
1k
GAIN
PHASE MARGIN
–20
–40
–60
–80
–100
–120
–140
–160
–180
60
40
20
0
100
–20
–40
–60
10
0.1
0.1
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25. Voltage Noise Spectral Density vs. Frequency
Figure 22. Open-Loop Gain and Phase Margin vs. Frequency
22pF
470pF
1nF
5µV/DIV
100µs/DIV
20mV/DIV
1s/DIV
Figure 23. Small Signal Response for Various Capacitive Loads
Figure 26. 0.1 Hz to 10 Hz Noise
Rev. 0 | Page 11 of 29
AD8233
Data Sheet
1.5
1.0
0.5
5µV/DIV
0
–0.5
–1.0
–1.5
–40°C
+25°C
+85°C
200ms/DIV
100
1k
10k
100k
1M
LOAD (ꢀ)
Figure 27. 0.5 Hz to 40 Hz Noise
Figure 29. Output Voltage Swing vs. Load
100
80
120
110
100
90
60
40
80
20
70
0
60
50
–20
–40
–60
–80
40
30
20
10
–100
0
0
0.1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1
10
100
1k
10k
100k
INPUT COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 28. Input Bias Current vs. Input Common-Mode Voltage
Figure 30. Power Supply Rejection Ratio
Rev. 0 | Page 12 of 29
Data Sheet
AD8233
1k
100
10
1
50mV/DIV
100µs/DIV
0.1
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 31. Load Transient Response (100 μA Load Change)
Figure 33. Input Bias Current vs. Temperature
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 32. Offset vs. Temperature
Rev. 0 | Page 13 of 29
AD8233
Data Sheet
RIGHT LEG DRIVE (RLD) AMPLIFIER PERFORMANCE CHARACTERISTICS
140
120
100
80
0
GAIN
PHASE MARGIN
–20
–40
–60
–80
–100
–120
–140
–160
–180
5µV/DIV
60
40
20
0
–20
–40
1s/DIV
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 34. Open-Loop Gain and Phase Margin vs. Frequency
Figure 37. 0.1 Hz to 10 Hz Noise
1.5
1.0
0.5
0
5µV/DIV
–0.5
–40°C
+25°C
+85°C
–1.0
200ms/DIV
–1.5
100
1k
10k
100k
1M
LOAD (ꢀ)
Figure 35. Output Voltage Swing vs. Load
Figure 38. 0.5 Hz to 40 Hz Noise
12
10
10k
1k
AC/DC = LOW, RLD SDN = HIGH
8
6
4
2
0
100
+V = 1.8V
S
+V = 3V
S
+V = 3.5V
S
10
0.1
–40
–20
0
20
40
60
80
100
1
10
100
1k
10k
100k
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 39. RLD Supply Current vs. Temperature
Figure 36. Voltage Spectral Noise Density vs. Frequency
Rev. 0 | Page 14 of 29
Data Sheet
AD8233
REFERENCE BUFFER PERFORMANCE CHARACTERISTICS
15
100k
10k
SOURCE
SINK
10
5
0
1k
100
10
–5
–10
–15
0.01
1
0.1
0.1
1
10
1
10
100
1k
10k
100k
LOAD CURRENT (mA)
FREQUENCY (Hz)
Figure 40. Load Regulation
Figure 42. Output Impedance vs. Frequency
1k
100
10
1
50mV/DIV
100µs/DIV
0.1
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 41. Load Transient Response (100 μA Load Change)
Figure 43. Input Bias Current vs. Temperature
Rev. 0 | Page 15 of 29
AD8233
Data Sheet
SYSTEM PERFORMANCE CHARACTERISTICS
80
10k
1k
SDN = HIGH, AC/DC = LOW, RLD SDN = LOW
70
60
50
40
30
20
100
+V = 1.8V
S
10
+V = 3V
S
+V = 3.5V
S
0
–40
10
0.1
–20
0
20
40
60
80
100
1
10
100
1k
10k
100k
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 47. Voltage Noise Spectral Density (RTI) (Measured at IAOUT)
Figure 44. Supply Current vs. Temperature
900
800
700
SDN = LOW, AC/DC = LOW
RLD SDN = LOW, LOD = HIGH
600
500
5µV/DIV
400
300
200
100
+V = 1.8V
S
+V = 3V
S
200ms/DIV
+V = 3.5V
S
0
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 45. Shutdown Current vs. Temperature
Figure 48. 0.5 Hz to 40 Hz Noise (RTI) (Measured at IAOUT)
1000
900
SDN = LOW, AC/DC = LOW
RLD SDN = LOW, LOD = LOW
800
700
600
500
10µV/DIV
400
300
200
100
0
+V = 1.8V
S
+V = 3V
S
2s/DIV
+V = 3.5V
S
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 46. Wakeup Current vs. Temperature
Figure 49. 0.05 Hz to 150 Hz Noise (RTI) (Measured at IAOUT)
Rev. 0 | Page 16 of 29
Data Sheet
AD8233
THEORY OF OPERATION
+V
HPDRIVE
A5
HPSENSE
A4
IAOUT
B4
SW
D4
OPAMP+
D3
OPAMP–
D2
S
A2
10kꢀ
CHARGE
PUMP
+V
S
D1
A1
OUT
S2
AC/DC
–IN
+IN
C5
B5
HPA
10kꢀ
RFI
FILTER
S1
GM1
GM2
R
B3
B1
FR
V
CM
+V – 0.1V
S
99R
AC/DC
SDN
C1
0.1V
B2 AC/DC
INSTRUMENTATION AMPLIFIER (IA)
S1
S2
SWITCH
TIMING
SYNC
RECTIFIER
RLDFB C4
0.7V
C2
D5
RLD SDN
RLD
C1
LOD
+V – 0.27V
A2
150kꢀ
S
AC/DC
A1 GND
A3
C3
REFOUT
REFIN
A3
*ALL SWITCHES SHOWN IN DC LEADS OFF DETECTION POSITION AND FAST RESTORE DISABLED
= REFOUT
Figure 50. Simplified Schematic Diagram
across Capacitor C1. The resulting voltage appears at the output
of the instrumentation amplifier.
ARCHITECTURE OVERVIEW
The AD8233 is an integrated front end for signal conditioning
of cardiac biopotentials for heart rate monitoring. It consists of
a specialized instrumentation amplifier (IA), an operational
amplifier (A1), a right leg drive amplifier (A2), and a midsupply
reference buffer (A3). In addition, the AD8233 includes leads
on/off detection circuitry and an automatic fast restore circuit
that restores the signal shortly after leads are reconnected.
The feedback of the amplifier is applied via GM2 through two
separate paths: the two resistors divide the output signal to set
an overall gain of 100, whereas the dc blocking amplifier integrates
any deviation from the reference level. Consequently, dc offsets
as large as 300 mV across the GM1 inputs appear inverted and
with the same magnitude across the inputs of GM2, all without
saturating the signal of interest.
The AD8233 contains a specialized instrumentation amplifier
that amplifies the ECG signal while rejecting the electrode half
cell potential on the same stage. The amplification of the ECG
signal and the rejection of the electrode half cell potential are
possible with an indirect current feedback architecture, which
reduces size and power compared with traditional
implementations.
To increase the common-mode voltage range of the instrumen-
tation amplifier, a charge pump boosts the supply voltage for the
two transconductance amplifiers. This boost in supply voltage
further prevents saturation of the amplifier in the presence of
large common-mode signals, such as line interference. The charge
pump runs from an internal oscillator, the frequency of which is
set around 500 kHz.
INSTRUMENTATION AMPLIFIER
OPERATIONAL AMPLIFIER
The instrumentation amplifier is shown in Figure 50 as
The general-purpose operational amplifier (A1) is a rail-to-rail
device that can be used for low-pass filtering and to add additional
gain. The following sections provide details and example circuits
that use this amplifier.
comprised by two well matched transconductance amplifiers
(GM1 and GM2), the dc blocking amplifier (HPA), and an
integrator formed by C1 and an op amp. The transconductance
amplifier, GM1, generates a current that is proportional to the
voltage present at its inputs. When the feedback is satisfied, an
equal voltage appears across the inputs of the transconductance
amplifier, GM2, thereby matching the current generated by
GM1. The difference generates an error current that is integrated
Rev. 0 | Page 17 of 29
AD8233
Data Sheet
voltage. For example, if there is zero differential input voltage,
the voltage at the output of the instrumentation amplifier is this
reference voltage.
RIGHT LEG DRIVE AMPLIFIER
The right leg drive (RLD) amplifier inverts the common-mode
signal that is present at the instrumentation amplifier inputs.
When the right leg drive output current is injected into the
subject, it counteracts common-mode voltage variations, thus
improving the common-mode rejection of the system.
The reference voltage level is set at the REFIN pin. It can be set
with a voltage divider or by driving the REFIN pin from some
other point in the circuit (for example, from the ADC reference).
The voltage is available at the REFOUT pin for the filtering
circuits or for an ADC input.
The common-mode signal that is present across the inputs of
the instrumentation amplifier is derived from the transconduct-
ance amplifier, GM1. It is then connected to the inverting input
of A2 through a 150 kΩ resistor.
+V
S
R1
R2
REFIN
A3
A3
An integrator can be built by connecting a capacitor between the
RLD FB and RLD terminals. A good starting point is a 1 nF
capacitor, which places the crossover frequency at about 1 kHz
(the frequency at which the amplifier has an inverting unity gain).
This configuration results in about 26 dB of loop gain available
at a frequency range from 50 Hz to 60 Hz for common-mode line
rejection. Higher capacitor values reduce the crossover frequency,
thereby reducing the gain that is available for rejection and,
consequently, increasing the line noise. Lower capacitor values
move the crossover frequency to higher frequencies, allowing
increased gain. The tradeoff is that with higher gain, the system
can become unstable and saturate the output of the right leg
amplifier.
C1
Figure 52. Setting the Internal Reference
To limit the power consumption of the voltage divider, the use
of large resistors is recommended, such as 10 MΩ. The designer
must keep in mind that high resistor values make it easier for
interfering signals to appear at the input of the reference buffer.
To minimize noise pickup, it is recommended to place the resistors
close to each other and as near as possible to the REFIN terminal.
Furthermore, use a capacitor in parallel with the lower resistor
on the divider for additional filtering, as shown in Figure 52.
Keep in mind that a large capacitor results in better noise
filtering but it takes longer to settle the reference after power-up.
The total time it takes the reference to settle within 1% can be
estimated with the formula
When using this amplifier to drive an electrode, place a resistor
in series with the output to limit the current to be always less
than 10 μA, even in fault conditions. For example, if the supply
used is 3.0 V, ensure that the resistor is greater than 330 kΩ to
account for component and supply variations.
R1 R2 C1
R1 R2
t
SETTLE_REFERENCE = 5
Note that disabling the AD8233 with the shutdown terminal
does not discharge this capacitor.
RLDFB
C4
FAST RESTORE CIRCUIT
1nF
Because of the low cutoff frequency used in high-pass filters in
ECG applications, signals may require several seconds to settle.
This settling time can result in a frustrating delay for the user
after a step response: for example, when the electrodes are first
connected.
RLD
D5
V
CM
150kꢀ
A2
R*
TO DRIVEN
ELECTRODE
REFOUT
*LIMIT CURRENT TO LESS THAN 10µA.
Figure 51. Typical Configuration of Right-Leg Drive Circuit
This fast restore function is implemented internally, as shown in
Figure 53. The output of the instrumentation amplifier is connec-
ted to a window comparator. The window comparator detects a
saturation condition at the output of the instrumentation amplifier
when its voltage approaches 0.1 V from either supply rail.
In two electrode configurations, A2 can be shut down by setting
SDN
RLD
low for additional power savings. If left in shutdown,
it is recommended to leave both RLD and RLDFB floating.
Alternatively, RLD can be used to bias the inputs through
10 MΩ resistors as described in the Leads On/Off Detection
section. When the AD8233 is in shutdown and dc leads off
detection mode, RLD pulls down towards ground. This pull-
down acts as an LOD wake-up function, pulling the inputs
down when the electrodes are reconnected.
B3
FR
S1
+V – 0.1V
S
+IN
B5
SWITCH
TIMING
IA
S2
IAOUT
0.1V
C5
–IN
LOD C1
REFERENCE BUFFER
Figure 53. Fast Restore Circuit
The AD8233 operates from a single supply. To simplify the
design of single-supply applications, the AD8233 includes a
reference buffer to create a virtual ground between the supply
voltage and the system ground. The signals present at the out-
put of the instrumentation amplifier are referenced around this
Rev. 0 | Page 18 of 29
Data Sheet
AD8233
SATURATION DETECTED
tS1
NO SATURATION
S1
S2
tS2
tRST
LEADS OFF
LEADS ON
Figure 54. Timing Diagram for Fast Restore Switches (Time Base Not to Scale)
If this saturation condition is present when both input electrodes
are attached to the subject, the comparator triggers a timing
circuit that automatically closes Switch S1 and Switch S2 (see
Figure 54 for a timing diagram).
two electrode dc mode. A pull-up resistor on +IN and a pull-
down resistor on −IN creates a voltage divider when the
electrodes are connected, setting the input common mode to
midsupply. When the electrodes disconnect, the comparator
monitoring +IN sets LOD high when the input pulls to +VS.
These two switches (S1 and S2) enable two different 10 kΩ
resistor paths: one between HPSENSE and IAOUT and another
between SW and REFOUT. During the time Switch S1 and
Switch S2 are enabled, these internal resistors appear in parallel
with their corresponding external resistors forming high-pass
filters. The result is that the equivalent lower resistance shifts
the pole to a higher frequency, delivering a quicker settling
time. Note that the fast restore settling time depends on how
quickly the internal 10 kΩ resistors of the AD8233 can drain the
capacitors in the high-pass circuit. Smaller capacitor values
result in a shorter settling time.
+V
S
10Mꢀ
B5
C5
IA
10Mꢀ
Figure 55. Circuit Configuration for Two Electrode DC Leads Off Detection
For three electrode dc mode, each input must have a pull-up
resistor connected to the positive supply. During normal operation,
the potential of the subject must be inside the common-mode
range of the instrumentation amplifier, which is only possible if
a third electrode is connected to the output of the right leg drive
amplifier.
If, by the end of the timing, the saturation condition persists,
the cycle repeats. Otherwise, the AD8233 returns to its normal
operation. If either of the leads off comparator outputs is indi-
cating that an electrode is disconnected, the timing circuit is
prevented from triggering because it is assumed that no valid
signal is present. To disable fast restore, drive the FR pin low or
tie it permanently to GND.
+V
S
10Mꢀ
10Mꢀ
B5
C5
LEADS ON/OFF DETECTION
IA
The AD8233 includes leads off detection. It features ac and dc
detection modes that both work with two and three electrode
configurations. Ultralow power comparators allow the leads
on/off detection to remain functional in shutdown mode,
allowing power savings at the system level when the LOD
output is used as a wake-up signal for the microcontroller.
TO DRIVEN
ELECTRODE
D5
RLD
Figure 56. Circuit Configuration for Three Electrode DC Leads Off Detection
The AD8233 indicates when any electrode is disconnected by
setting the LOD pin high. To use this mode, connect the
DC Leads On/Off Detection
The dc leads off detection mode can be used in two or three
electrode configurations. It works by sensing when either
instrumentation amplifier input voltage is within 0.27 V from
the positive rail. The lowest power use case for the AD8233 is
DC
AC/
pin to ground.
Rev. 0 | Page 19 of 29
AD8233
Data Sheet
The ac leads off detection mode continues to function in shutdown
mode as well. To keep the power under 1 μA, the clock is disabled
and the ac currents become dc currents. The current source on
+IN is 250 nA, while the current sink on –IN is −300 nA. The
stronger pull-down current on −IN acts as a wake-up function,
pulling LOD low when the electrodes are reconnected.
AC Leads On/Off Detection
The ac leads off detection mode is useful when using two
electrodes. In this case, a conduction path must exist between
the two electrodes, which is usually formed by two resistors, as
shown in Figure 57.
These resistors also provide a path for bias return on each input.
Connect each resistor to REFOUT or RLD to maintain the inputs
within the common-mode range of the instrumentation
amplifier.
STANDBY OPERATION
SDN
The AD8233 includes a shutdown pin (
) that further
enhances the flexibility and ease of use in portable applications
where power consumption is critical. A logic level signal can be
applied to this pin to switch to shutdown mode, even when the
supply is still on.
+V
S
A2
B5
C5
SDN
Driving the
and draws less than 1 μA of supply current, offering considerable
SDN
pin low places the AD8233 in shutdown mode
IA
10Mꢀ
10Mꢀ
power savings. To enter normal operation, drive
SDN
high;
to +VS.
when not using this feature, permanently tie
C3
REFOUT
During shutdown operation, the AD8233 cannot maintain the
REFOUT voltage, but it does not drain the REFIN voltage,
thereby maintaining this additional conduction path from the
supply to ground.
Figure 57. Circuit Configuration for Two Electrode AC Leads Off Detection
The AD8233 detects when an electrode is disconnected by
forcing a small 100 kHz current into the input terminals. This
current flows through the external resistors from IN+ to IN−
and develops a differential voltage across the inputs, which is
then synchronously detected and compared to an internal
threshold. The recommended value for these external resistors
is 10 MΩ. Low resistance values make the differential drop too
low to be detected and lower the input impedance of the amplifier.
When the electrodes are attached to the subject, the impedance
of this path must be less than 3 MΩ to maintain the drop below
the threshold of the comparator.
When emerging from a shutdown condition, the charge stored
in the capacitors on the high-pass filters can saturate the instru-
mentation amplifier and subsequent stages. The use of the fast
restore feature helps reduce the recovery time and, therefore,
minimize on time in power sensitive applications.
Using leads on/off detection in shutdown mode allows system
level power saving. The microcontroller enters sleep mode
when the electrodes are disconnected, and the LOD signal acts
as an interrupt to wake up the microcontroller. An example of
this functionality is shown in Figure 59.
DC
To use the ac leads off mode, tie the AC/
pin to the positive
supply rail. Note that, whereas REFOUT is at a constant voltage
value, using the RLD output as the input bias may be more effective
in rejecting common-mode interference at the expense of
additional power.
OUT
SDN
LOD
3 -
MCU WAKES UP
AND SETS SDN HIGH.
1 -
AT LEAST ONE ELECTRODE IS OFF
AND THEREFORE LOD OUTPUT IS HIGH.
MCU IS OFF AND SDN IS LOW.
(AD8233 SHUTDOWN CURRENT < 1µA)
In three electrode ac leads off detection mode, as shown in
Figure 58, pull-up resistors are not required, which improves
the input impedance of the circuit. This mode is beneficial for
dry electrode applications. The ac mode currents contribute 1/f
noise to the system; therefore, depending on the application, it
may be advantageous to use ac leads off detection as a spot check
and then switching to dc mode for improved ECG acquisition.
4 -
AD8233 IS ACTIVE (~50µA)
AND MONITORING ECG.
2 -
LOD GOES LOW WHEN BOTH
ELECTRODES ARE CONNECTED.
A FALLING EDGE AT LOD WAKES UP
THE MCU.
250mV/DIV
400ms/DIV
+V
S
Figure 59. Electrode Connection and System Wakeup Sequence
A2
B5
C5
IA
TO DRIVEN
ELECTRODE
D5
RLD
Figure 58. Circuit Configuration for Three Electrode AC Leads Off Detection
Rev. 0 | Page 20 of 29
Data Sheet
AD8233
INPUT PROTECTION
POWER SUPPLY REGULATION AND BYPASSING
All terminals of the AD8233 are protected against ESD. In
addition, the input structure allows dc overload conditions that
are a diode drop above the positive supply and a diode drop
below the negative supply. Voltages beyond a diode drop of the
supplies cause the ESD diodes to conduct and enable current to
flow through the diode. Therefore, use an external resistor in
series with each of the inputs to limit current for voltages
beyond the supplies. In either scenario, the AD8233 safely
handles a continuous 5 mA current at room temperature.
The AD8233 is designed to be powered directly from a single
3 V battery, such as CR2032 type. It can also operate from
rechargeable Li-Ion batteries, but the designer must take into
account that the voltage during a charge cycle may exceed the
absolute maximum ratings of the AD8233. To avoid damage to
the device, use a power switch or a low power, low dropout
regulator, such as the ADP150 or ADP160.
In addition, excessive noise on the supply pins can adversely
affect performance. As in all linear circuits, bypass capacitors
must be used to decouple the chip power supplies. Place a 0.1 ꢀF
capacitor close to the supply pin. A 1 ꢀF capacitor can be used
farther away from the device. In most cases, the capacitor can
be shared by other integrated circuits. Keep in mind that excessive
decoupling capacitance increases power dissipation during
power cycling.
For applications where the AD8233 encounters extreme over-
load voltages, such as in cardiac defibrillators, use external series
resistors and gas discharge tubes (GDT). Neon lamps are com-
monly used as an inexpensive alternative to GDTs. These devices
can handle the application of large voltages but do not maintain
the voltage below the absolute maximum ratings for the AD8233.
A complete solution includes further clamping to either supply
using additional resistors and low leakage diode clamps, such as
BAV199 or FJH1100.
INPUT REFERRED OFFSETS
Because of its internal architecture, the instrumentation amplifier
must be used always with the dc blocking amplifier, shown as HPA
in Figure 50.
As a safety measure, place a resistor between the input pin and
the electrode that is connected to the subject to ensure that the
current flow never exceeds 10 μA. Calculate the value of this
resistor to be equal to the supply voltage across the AD8233
divided by 10 μA.
As described in the Theory of Operation section, the dc blocking
amplifier attenuates the input referred offsets present at the
inputs of the instrumentation amplifier; however, this is true
only when the dc blocking amplifier is used as an integrator. In
this configuration, the input offsets from the dc blocking
amplifier dominate appearing directly at the output of the
instrumentation amplifier.
RADIO FREQUENCY INTERFERENCE (RFI)
Radio frequency (RF) rectification is often a problem in
applications where there are large RF signals. The problem
appears as a dc offset voltage at the output. The AD8233 has a
15 pF gate capacitance and 10 kΩ resistors at each input. This
forms a low-pass filter on each input that reduces rectification
at high frequency (see Figure 60) without the addition of
external elements.
If the dc blocking amplifier is used as a follower instead of its
intended function as an integrator, the input referred offsets of
the in-amp are amplified by a factor of 100.
LAYOUT RECOMMENDATIONS
It is important to follow good layout practices to optimize
system performance. In low power applications, most resistors
are of a high value to minimize additional supply current. The
challenge of using high value resistors is that high impedance
nodes become even more susceptible to noise pickup and board
parasitics, such as capacitance and surface leakages. Keep all of
the connections between high impedance nodes as short as
possible to avoid introducing additional noise and errors from
corrupting the signal.
10kꢀ
+IN
C
G
10kꢀ
IAOUT
AD8233
–IN
C
G
Figure 60. RFI Filter Without External Capacitors
For increased filtering, additional resistors can be added in
series with each input. They must be placed as close as possible
to the instrumentation amplifier inputs. These can be the same
resistors used for overload and patient protection.
To maintain high CMRR over frequency, keep the input traces
symmetrical and length matched. Place safety and input bias
resistors in the same position relative to each input. In addition,
the use of a ground plane significantly improves the noise
rejection of the system.
For WLCSP layout best practices, refer to the AN-617
Application Note.
Rev. 0 | Page 21 of 29
AD8233
Data Sheet
APPLICATIONS INFORMATION
As with any high-pass filter with low frequency cutoff, a fast
change in dc offset requires a long time to settle. If such a
change saturates the instrumentation amplifier output, the S1
switch briefly enables the 10 kΩ resistor path, thus moving the
cutoff frequency to
ELIMINATING ELECTRODE OFFSETS
The instrumentation amplifier in the AD8233 is designed to
apply gain and to filter out near dc signals simultaneously. This
capability allows the device to amplify a small ECG signal by a
factor of 100 while rejecting electrode offsets as large as 300 mV.
100(R 104 )
2RC(104 )
To achieve offset rejection, connect an RC network between the
output of the instrumentation amplifier, HPSENSE, and
HPDRIVE, as shown in Figure 61.
fC =
(2)
For values of R greater than 100 kΩ, the expression in Equation 2
can be approximated by
C
R
1
A5
A4
B4
fC =
(3)
HPDRIVE
HPSENSE
IAOUT
200C
IN+
This higher cutoff frequency reduces the settling time and
enables faster recovery of the ECG signal. For more
information, see the Fast Restore Circuit section.
B5
HPA
10kꢀ
S1
GM1
GM2
R
C5
V
CM
IN–
99R
ELECTRODE
OFFSETS
HIGH-PASS FILTERING
C1
= REFOUT
The AD8233 can implement higher order high-pass filters. A
higher filter order yields better artifact rejection at the cost of
increased signal distortion and more passive components on the
PCB.
Figure 61. Eliminating Electrode Offsets
This RC network forms an integrator that feeds any near dc signals
back into the instrumentation amplifier, thus eliminating the offsets
without saturating any node and maintaining high signal gain.
Two-Pole High-Pass Filter
A two-pole architecture can be implemented by adding a simple
ac coupling RC at the output of the instrumentation amplifier,
as shown in Figure 63.
In addition to blocking offsets present across the inputs of the
instrumentation amplifier, this integrator also works as a high-
pass filter that minimizes the effect of slow moving signals, such
as baseline wander. The cutoff frequency of the filter is given by
the following equation:
TO NEXT
C1
C2
R1
STAGE
A5
A4
B4
D4
100
2RC
HPDRIVE HPSENSE
IAOUT
SW
10kꢀ
fC =
(1)
R2
HPA
+IN
10kꢀ
where R is in Ω and C is in farads.
S2
S1
B5
Note that the filter cutoff is 100 times higher than is typically
expected from a single-pole filter. Because of the feedback
architecture of the instrumentation amplifier, the typical filter
C5
REFOUT C3
–IN
cutoff equation is modified by a gain of 100 from the
= REFOUT
instrumentation amplifier.
Figure 63. Schematic for a Two-Pole High-Pass Filter
50
Note that the right side of C2 connects to the SW terminal. As
with S1, S2 reduces the recovery time for this ac coupling network
by placing 10 kΩ in parallel with R2. See the Fast Restore
Circuit section for additional details on switch timing and
trigger conditions.
40
30
Note that, if this passive network is not buffered, it exhibits
higher output impedance at the input of a subsequent low-pass
filter, such as with Sallen-Key filter topologies. Careful component
selection results in reliable performance without a buffer. See
the Low-Pass Filtering and Gain section for additional
information on component selection.
20dB PER
DECADE
20
10
0
0.01
0.1
1
10
100
FREQUENCY (Hz)
Figure 62. Frequency Response of a Single-Pole DC Blocking Circuit
Rev. 0 | Page 22 of 29
Data Sheet
AD8233
Additional High-Pass Filtering Options
The selection of RCOMP to be 0.14 times the value of the other
two resistors optimizes the filter for a maximally flat pass band.
Reduce the value of RCOMP to increase the Q and, consequently,
the peaking of the filter. Note that a very low RCOMP value may
result in an unstable circuit. The selection of values based on
these criteria results in a transfer function similar to what is
shown in Figure 65. When additional low frequency rejection is
desired, a high-order, high-pass filter can be implemented by
adding an ac coupling network at the output of the instrumentation
amplifier, as shown in Figure 65. The SW terminal is connected
to the ac coupling network to obtain the best settling time
response when fast restore engages.
In addition to the topologies explained in the previous sections,
an additional pole may be added to the dc blocking circuit for
the rejection of low frequency signals. This configuration is
shown in Figure 64.
TO NEXT
STAGE
C1
R1
R2
R
COMP
A5
A4
B4
D4
HPDRIVE HPSENSE
IAOUT
SW
10kꢀ
C2
HPA
+IN
10kꢀ
TO NEXT
S2
S1
C1
C3
R1
R2
STAGE
B5
C5
R
REFOUT C3
COMP
–IN
A5
A4
B4
D4
HPDRIVE HPSENSE
IAOUT
SW
10kꢀ
= REFOUT
C2
R3
Figure 64. Schematic for an Alternative Two-Pole, High-Pass Filter
HPA
+IN
10kꢀ
S2
S1
An extra benefit of this circuit topology is that it allows a lower
B5
cutoff frequency with lower R and C values. The resistor, RCOMP
can also be used to control the quality factor (Q) of the filter to
achieve narrow band-pass filters (for heart rate detection) or
maximum pass-band flatness (for cardiac monitoring).
,
C5
REFOUT C3
–IN
= REFOUT
Figure 65. Schematic for a Three-Pole, High-Pass Filter
With this circuit topology, the filter attenuation reverts to a
single-pole roll-off at very low frequencies. Because the initial
roll-off is 40 dB per decade, this reversion to 20 dB per decade
has little impact on the ability of the filter to reject out of band
low frequency signals.
60
40
40dB PER
DECADE
60dB PER
DECADE
20dB PER
DECADE
20
The designer may choose different values to achieve the desired
filter performance. To simplify the design process, use the following
recommendations as a starting point for component value selection.
0
R1 = R2 ≥ 100 kΩ
C1 = C2
–20
–40
–60
40dB PER
R
COMP = 0.14 × R1
DECADE
THREE-POLE FILTER
TWO-POLE FILTER
The cutoff frequency is located at
0.01
0.1
1
10
100
10
FREQUENCY (Hz)
fC =
2 R1C1 R2 C2
Figure 66. Frequency Response of the Circuits Shown in Figure 64 and Figure 65
Careful analysis and adjustment of all of the component values
in practice is recommended to optimize the filter characteristics.
To reduce the value of RCOMP, increase the peaking of the active
filter to overcome the additional roll-off introduced by the ac
coupling network. Proper adjustment yields the best pass-band
flatness.
Rev. 0 | Page 23 of 29
AD8233
Data Sheet
Table 6. Comparison of High-Pass Filtering Options
Figure to Filter
Reference Order
Capacitor
Sizes/Values
Signal
Output
Component Count
Low Frequency Rejection
Distortion1
Impedance2
Figure 61
Figure 63
Figure 64
Figure 65
1
2
2
3
2
4
5
7
Good
Better
Better
Best
Large
Large
Smaller
Smaller
Low
Low
Higher
Low
Medium
Medium
Highest
Higher
1 The signal distortion is for the equivalent corner frequency location.
2 Output impedance refers to the drive capability of the high-pass filter before the low-pass filter. Low output impedance is desirable to allow flexibility in the selection
of values for a low-pass filter, as explained in the Low-Pass Filtering and Gain section.
The design of the high-pass filter involves trade-offs between
signal distortion, component count, low frequency rejection,
and component size. For example, a single-pole, high-pass filter
results in the least distortion to the signal, but the associated
rejection of low frequency artifacts is the lowest of the available
filter options. Table 6 compares the recommended filtering options.
The following equations describe the low-pass cutoff frequency
(fC), gain, and Q:
fC = 1/(2π√(R1 × C1 × R2 × C2))
Gain = 1 + R3/R4
R1 C1 R2 C2
Q =
LOW-PASS FILTERING AND GAIN
R1 C2 R2 C2 R1 C1(1 Gain)
The AD8233 includes an uncommitted op amp that can be used
for extra gain and filtering. For applications that do not require
a high order filter, a simple RC low-pass filter is sufficient, and
the op amp can buffer or further amplify the signal.
Note that changing the gain has an effect on Q and vice versa.
Common values for Q are 0.5, to avoid peaking, or 0.7 for max-
imum flatness and a sharp cutoff frequency. Use a high Q value
in narrow-band applications to increase peaking and the
selectivity of the band-pass filter.
FROM IN-AMP
STAGE
R
FILTERED
SIGNAL
A common design procedure is to set R1 = R2 = R and C1 = C2 =
C, simplifying the expressions for the cutoff frequency and Q to
A1
C
fC = 1/(2πRC)
REFOUT
1
Q =
Figure 67. Schematic for a Single-Pole, Low-Pass Filter and Additional Gain
3 Gain
A Sallen-Key filter topology can be implemented for applications
that require a steeper roll-off or a sharper cutoff frequency, as
shown in Figure 68.
Note that Q can be controlled by setting the gain with R3 and
R4; however, this limits the gain to be less than 3. For gain
values equal to or greater than 3, the circuit becomes unstable.
A simple modification that allows higher gains is to make the
value of C2 at least four times larger than C1.
C1
FROM IN-AMP
STAGE
R1
R2
C2
FILTERED
SIGNAL
Note that these design equations only hold true in a case where
the output impedance of the previous stage is much lower than
the input impedance of the Sallen-Key filter. The design equations
do not hold true when using an ac coupling network between
the instrumentation amplifier output and the input of the low-
pass filter without a buffer.
A1
R3
REFOUT
R4
Figure 68. Schematic for a Two-Pole, Low-Pass Filter
To connect these two filtering stages properly without a buffer,
make the value of R1 at least 10 times larger than the resistor of
the ac coupling network (labeled as R2 in Figure 63).
Rev. 0 | Page 24 of 29
Data Sheet
AD8233
Driving ADCs
mode voltage from the instrumentation amplifier inputs and
makes it available through the RLD amplifier to drive an opposing
signal into the patient. This functionality maintains the voltage
between the patient and the AD8233 at a near constant, greatly
improving the CMRR.
The ability of AD8233 to drive capacitive loads makes it ideal
for driving an ADC without an additional buffer. However,
depending on the input architecture of the ADC, a simple, low-
pass RC network may be required to decouple the transients
from the switched capacitor input typical of modern ADCs.
This RC network also acts as an additional filter that can help
reduce noise and aliasing. Follow the recommended guidelines
from the ADC data sheet for the selection of proper R and C
values. Table 7 lists compatible ADCs by category.
As a safety measure, place a resistor between the RLD pin
(Pin D5) and the electrode connected to the subject to ensure
that current flow never exceeds 10 μA. Calculate the value of
this resistor to be equal to the supply voltage across the AD8233
divided by 10 μA.
The AD8233 implements an integrator formed by an internal
150 kΩ resistor and an external capacitor to drive this electrode.
The choice of the integrator capacitor is a trade-off between line
rejection capability and stability. It is recommended that the
capacitor be small to maintain as much loop gain as possible,
around 50 Hz and 60 Hz, which is typical for line frequencies.
For stability, it is recommended that the gain of the integrator
be less than unity gain at the frequency of any other poles in the
loop, such as those formed by the capacitance and the safety
resistors of the patient. The suggested application circuits use a
1 nF capacitor, which results in a loop gain of about 20 at line
frequencies, with a crossover frequency of about 1 kHz.
Table 7. Compatible ADCs by Category
Analog-to-
Digital
Converters Microcontrollers Sensors
Optical
Accelerometers
AD7091
ADuCM350
ADPD103 ADXL363
AD7988-1
ADPD105
AD8233
R
A1
D1
ADC
C
Figure 69. Driving an ADC
In a 2-lead configuration, the RLD pin (Pin D5) amplifier can
be shut down or used to drive the bias current resistors on the
inputs. Although not as effective as a true driven electrode, this
configuration can provide some common-mode rejection
improvement if the sense electrode impedance is small and well
matched.
DRIVEN ELECTRODE
A driven lead (or reference electrode) is often used to minimize
the effects of common-mode voltages induced by the power line
and other interfering sources. The AD8233 extracts the common-
Rev. 0 | Page 25 of 29
AD8233
Data Sheet
APPLICATION CIRCUITS
HEART RATE MEASUREMENT (HRM) NEXT TO THE
HEART
The input terminals in this configuration use two 180 kΩ resistors
to protect the user from fault conditions. Two 10 MΩ resistors
provide input bias. Use higher values for electrodes with high
output impedance, such as cloth electrodes.
For wearable exercise devices, the AD8233 is typically placed in
a pod near the heart. The two sense electrodes are placed under
the pectoral muscles; no driven electrode is used. Because the
distance from the heart to the AD8233 is small, the heart signal
is strong and there is less muscle artifact interference.
The schematic also shows two 10 MΩ resistors to set the
midscale reference voltage. If there is already a reference voltage
available, it can be driven into the REFIN input to eliminate
these two 10 MΩ resistors.
In this wearable device configuration, space is at a premium. By
using as few external components as possible, the circuit in
Figure 70 is optimized for size.
EXERCISE APPLICATION—HEART RATE
MEASURED AT THE HANDS
In this application, the heart rate signal is measured at the
hands with stainless steel electrodes. The arm and upper body
movement of the user create large motion artifacts, and the long
lead length makes the system susceptible to common-mode
interference. A very narrow band-pass characteristic is required
to separate the heart signal from the interferers.
0.22µF
ELECTRODE
HPDRIVE
+IN
HPSENSE
IAOUT
INTERFACE
10Mꢀ
+V
180kꢀ
180kꢀ
S
10Mꢀ
–IN
REFIN
10Mꢀ
0.1µF
10Mꢀ
+V
S
RLDFB
RLD
10Mꢀ
+V
S
0.22µF
0.1µF
1nF
GND
FR
AD8233
10Mꢀ
SW
HPDRIVE
+IN
HPSENSE
10Mꢀ
10Mꢀ
+V
180kꢀ
180kꢀ
OPAMP+
REFOUT
OPAMP–
OUT
AC/DC
RLD SDN
SDN
+V
LA
RA
IAOUT
REFIN
S
S
–IN
10Mꢀ
0.1µF
0.22µF
+V
S
10Mꢀ
RLDFB
RLD
TO DIGITAL
INTERFACE
1nF
0.1µF
360kꢀ
RL
GND
FR
LOD
AD8233
SW
SIGNAL
OUTPUT
1Mꢀ
1Mꢀ
OPAMP+
REFOUT
OPAMP–
OUT
AC/DC
RLD SDN
SDN
100kꢀ 22nF
100kꢀ
Figure 70. Circuit for HRM Next to the Heart
+V
S
A shorter distance from the AD8233 to the heart makes this
application less vulnerable to common-mode interference.
However, because RLD (Pin D5) is not used to drive an
electrode, it can be used to improve the common-mode
rejection by maintaining the midscale voltage through the
SDN
3.3nF
TO DIGITAL
INTERFACE
1Mꢀ
LOD
SIGNAL OUTPUT
Figure 72. Circuit for HRM at Hands
The circuit in Figure 72 uses a two-pole, high-pass filter set at
7 Hz. A two-pole, low-pass filter at 24 Hz follows the high-pass
filters to eliminate any other artifacts and line noise.
70
10 MΩ bias resistors. Alternatively, tie RLD
power, and tie the bias resistors to REFOUT.
low to save
A single-pole, high-pass filter is set at 7 Hz, and there is no low-pass
filter. No gain is used on the output op amp, thereby reducing the
number of resistors for a total system gain of 100. (see Figure 71).
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
0.1
1
10
100
1k
FREQUENCY (Hz)
0.1
1
10
100
1k
10k
Figure 73. Frequency Response for HRM Circuit Taken at the Hands
FREQUENCY (Hz)
Figure 71. Frequency Response for HRM Next to the Heart Circuit
Rev. 0 | Page 26 of 29
Data Sheet
AD8233
70
60
50
40
30
20
10
The overall narrow-band nature of the two-pole, low-pass filter
filter combination distorts the ECG waveform significantly.
Therefore, it is only suitable to determine the heart rate, and not
to analyze the ECG signal characteristics.
The low-pass filter stage also includes a gain of 11, bringing the
total system gain close to 1100. Because the ECG signal is
measured at the hands, it is weaker than when measured closer
to the heart.
The RLD circuit drives to the third electrode, which can also be
located at the hands, to cancel common-mode interference.
HOLTER MONITOR CONFIGURATION
0
0.01
0.1
1
10
100
1k
The circuit in Figure 75 is designed for monitoring the shape of
the ECG waveform.
FREQUENCY (Hz)
Figure 74. Frequency Response of Holter Monitor Circuit
To obtain an ECG waveform with minimal distortion, the
AD8233 is configured with a 0.5 Hz, single-pole, high-pass
filter, followed by a two-pole, 40 Hz, low-pass filter. A third
electrode is driven for optimum common-mode rejection.
In addition to 40 Hz filtering, the op amp stage is configured for
a gain of 2, resulting in a total system gain of 200. Keeping the
gain lower helps with any motion artifacts picked up in band.
To optimize the dynamic range of the system, the gain level is
adjustable, depending on the input signal amplitude (which
may vary with electrode placement) and ADC input range.
3.3µF
+V
S
ELECTRODE
INTERFACE
HPDRIVE
+IN
HPSENSE
IAOUT
10Mꢀ
10Mꢀ
10Mꢀ
+V
150kꢀ
150kꢀ
LA
RA
(= +2.5V)
0.1µF
S
+V
S
–IN
10Mꢀ
10Mꢀ
0.1µF
RLDFB
RLD
REFIN
GND
FR
10Mꢀ 1nF
300kꢀ
499kꢀ
RL
AD8233
+V
S
SW
1Mꢀ
OPAMP+
REFOUT
OPAMP–
OUT
AC/DC
5.6nF
+V
RLD SDN
S
1Mꢀ
1Mꢀ
5.6nF
...TO MCU
...TO MCU
SDN
LOD
...TO 11-13 ENOB ADC
0.5Hz TO 40Hz
GAIN = ×200
Figure 75. Holter Monitor Circuit
Rev. 0 | Page 27 of 29
AD8233
Data Sheet
ADPD105 channel that processes the ECG signal must be set up
in either pulse connect mode or transimpedance amplifier (TIA)
ADC mode, and the input bias voltage must be set to the 0.9 V
setting. The TIA gain setting can be set to optimize the dynamic
range of the signal path. The channel used to process the PPG
signal is configured in its normal operating mode. Figure 76
shows a plot of a synchronized ECG and PPG measurement
using the AD8233 with the ADPD105.
SYNCHRONIZED ECG AND PPG MEASUREMENT
In wearable devices developed for monitoring the health care of
patients, it is often necessary to have synchronized measurements
of biomedical signals. For example, a synchronous measurement of
a ECG and photoplethysmograph (PPG) can be used to determine
the pulse wave transit time (PWTT), which can then be used to
estimate blood pressure.
The circuit shown in Figure 77 shows a synchronous ECG and
PPG measurement using the AD8233 and the ADPD105
photometric front end. The AD8233 implements a two-pole,
high-pass filter with a cutoff frequency of 0.3 Hz, and a two-pole,
low-pass filter with a cutoff frequency of 37 Hz. The output of
the AD8233 is fed to one of the current inputs of the ADPD105
through a 50 kꢁ resistor to convert the voltage output of the
AD8233 into a current. The PPG signal is acquired by the
ADPD105, which is a complete optical transceiver with
SHOWN WITH fSAMPLE = 100Hz
PPG
ECG
integrated LED drivers, multiple photodiode current inputs, an
integrated, 14-bit, successive approximation (SAR) ADC, and a
FIFO. In the circuit shown, the chip scale ADPD105 is used; the
ADPD105 is a two input device. The ADPD105 is configured to
alternately measure the photodiode signal and the ECG signal
from the AD8233 on consecutive time slots to provide fully
synchronized PPG and ECG measurements. Data can be read
out of the on-chip FIFO or straight from the data registers. The
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TIME (Seconds)
Figure 76. Synchronous ECG and PPG Measurement Using the AD8233 with
the ADPD105
1.8V
4.7µF
10Mꢀ
HPDRIVE
+IN
HPSENSE
IAOUT
10Mꢀ
10Mꢀ
1.8V
180kꢀ
180kꢀ
LA
RA
–IN
REFIN
10Mꢀ
0.1µF
4.7µF
+V
S
RLDFB
RLD
10Mꢀ
1nF
0.1µF
360kꢀ
RL
GND
FR
AD8233
1.8V
SW
1Mꢀ
1Mꢀ
OPAMP+
REFOUT
OPAMP–
OUT
AC/DC
SDN
100kꢀ 6.8nF
250kꢀ
TO DIGITAL
INTERFACE
RLD SDN
LOD
2.7nF
1Mꢀ
1.8V
ADPD105
50kꢀ
DVDD
AVDD
PD1-2
0.1µF
0.1µF
VLED
PDC
AGND
DGND
LGND
1.8V
PD3-4
10kꢀ 10kꢀ
LEDX1
SCL
SDA
VREF
TO DIGITAL
INTERFACE
1µF
GPIO0
GPIO1
Figure 77. Synchronous ECG and PPG Measurement Circuit
Rev. 0 | Page 28 of 29
Data Sheet
AD8233
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
2.080
2.040
2.000
BOTTOM VIEW
(BALL SIDE UP)
5
4
3
2
1
A
BALL A1
IDENTIFIER
1.20
REF
1.745
1.705
1.665
B
C
0.40
BSC
D
0.252
REF
0.18 REF
TOP VIEW
(BALL SIDE DOWN)
0.26
REF
1.60 REF
0.330
0.560
0.500
0.440
0.300
0.270
SIDE VIEW
COPLANARITY
0.04
SEATING
PLANE
0.300
0.260
0.220
0.230
0.200
0.170
Figure 78. 20-Ball, Backside-Coated, Wafer Level Chip Scale Package [WLCSP]
(CB-20-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
AD8233ACBZ-R7
AD8233CB-EBZ
−40°C to +85°C
20-Ball, Backside-Coated, Wafer Level Chip Scale Package [WLCSP]
Evaluation Board
CP-20-13
1 Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13737-0-8/16(0)
Rev. 0 | Page 29 of 29
相关型号：
AD8233ACBZ-R7
50 µA, 2 mm x 1.7 mm WLCSP, Low Noise, Heart Rate Monitor for Wearable Products
ADI
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