AD8109 [ADI]
325 MHz, 8 x 8 Buffered Video Crosspoint Switches; 325兆赫, 8× 8缓冲式视频交叉点开关型号: | AD8109 |
厂家: | ADI |
描述: | 325 MHz, 8 x 8 Buffered Video Crosspoint Switches |
文件: | 总28页 (文件大小:436K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
325 MHz, 8
؋
8 Buffered Video a
Crosspoint Switches
AD8108/AD8109*
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
8
؋
8 High Speed Nonblocking Sw itch Arrays AD8108: G = +1
SER/PAR
D0 D1 D2 D3
AD8109: G = +2
A0
A1
Serial or Parallel Program m ing of Sw itch Array
Serial Data Out Allow s “Daisy Chaining” of Multiple
8
؋
8s to Create Larger Sw itch Arrays Outp ut Disable Allow s Connection of Multiple Devices
Pin Com patible w ith AD8110/ AD8111 16
؋
8 Sw itch Arrays
CLK
A2
32-BIT SHIFT REGISTER
WITH 4-BIT
PARALLEL LOADING
DATA OUT
DATA IN
UPDATE
32
For 16
؋
16 Arrays See AD8116 Com plete Solution
Buffered Inputs
PARALLEL LATCH
CE
RESET
32
8
DECODE
8
؋
4:8 DECODERS Eight Output Am plifiers,
AD8108 (G = +1),
AD8109 (G = +2)
Drives 150 ⍀ Loads
OUTPUT
AD8108/AD8109
BUFFER
G = +1,
G = +2
64
Excellent Video Perform ance
60 MHz 0.1 dB Gain Flatness
0.02%/ 0.02؇ Differential Gain/ Differential Phase Error
(RL = 150 ⍀)
SWITCH
MATRIX
Excellent AC Perform ance
AD8108
325 MHz
400 V/ s
AD8109
250 MHz
480 V/ s
8 OUTPUTS
8 INPUTS
–3 dB Bandw idth
Slew Rate
Low Pow er of 45 m A
Low All Hostile Crosstalk of –83 dB @ 5 MHz
Reset Pin Allow s Disabling of All Outputs (Connected
Through a Capacitor to Ground Provides “Pow er-
On” Reset Capability)
Excellent ESD Rating: Exceeds 4000 V Hum an Body
Model
80-Lead TQFP Package (12 m m
؋
12 m m ) phase of better than 0.02% and 0.02° respectively along with
0.1 dB flatness out to 60 MHz make the AD8108/AD8109 ideal
for video signal switching.
APPLICATIONS
T he AD8108 and AD8109 include eight independent output
buffers that can be placed into a high impedance state for paral-
leling crosspoint outputs so that off channels do not load the
output bus. T he AD8108 has a gain of +1, while the AD8109
offers a gain of +2. T hey operate on voltage supplies of ±5 V
while consuming only 45 mA of idle current. The channel switch-
ing is performed via a serial digital control (which can accommo-
date “daisy chaining” of several devices) or via a parallel control
allowing updating of an individual output without re-programing
the entire array.
Routing of High Speed Signals Including:
Com posite Video (NTSC, PAL, S, SECAM.)
Com ponent Video (YUV, RGB)
Com pressed Video (MPEG, Wavelet)
3-Level Digital Video (HDB3)
P RO D UCT D ESCRIP TIO N
T he AD8108 and AD8109 are high speed 8 × 8 video cross-
point switch matrices. T hey offer a –3 dB signal bandwidth
greater than 250 MHz and channel switch times of less than
25 ns with 1% settling. With –83 dB of crosstalk and –98 dB
isolation (@ 5 MHz), the AD8108/AD8109 are useful in many
high speed applications. T he differential gain and differential
T he AD8108/AD8109 is packaged in an 80-lead T QFP package
and is available over the extended industrial temperature range
of –40°C to +85°C.
*Patent Pending.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
AD8108/AD8109–SPECIFICATIONS (V = ؎5 V, T = +25؇C, R = 1 k⍀ unless otherwise noted)
S
A
L
AD 8108/AD 8109
Typ
Reference
Figure No.
P aram eter
Conditions
Min
Max
Units
DYNAMIC PERFORMANCE
–3 dB Bandwidth
200 mV p-p, RL = 150 Ω
2 V p-p, RL = 150 Ω
2 V p-p, RL = 150 Ω
2 V Step, RL = 150 Ω
0.1%, 2 V Step, RL = 150 Ω
0.05 dB, 200 mV p-p, RL = 150 Ω
0.05 dB, 2 V p-p, RL = 150 Ω
0.1 dB, 200 mV p-p, RL = 150 Ω
0.1 dB, 2 V p-p, RL = 150 Ω
240/150
325/250
140/160
5
400/480
40
60/50
60/50
70/65
80/50
MHz
MHz
ns
V/µs
ns
MHz
MHz
MHz
MHz
6, 12
6, 12
Propagation Delay
Slew Rate
Settling T ime
Gain Flatness
11, 17
6, 12
6, 12
6, 12
6, 12
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
NT SC or PAL, RL = 1 kΩ
NT SC or PAL, RL = 150 Ω
NT SC or PAL, RL = 1 kΩ
NT SC or PAL, RL = 150 Ω
f = 5 MHz
f = 10 MHz
f = 10 MHz, RL =150 Ω, One Channel
0.01 MHz to 50 MHz
0.01
0.02
0.01
0.02
83/85
76/83
93/98
15
%
%
Differential Phase Error
Crosstalk, All Hostile
Degrees
Degrees
dB
dB
dB
7, 13
7, 13
22, 28
19, 25
Off Isolation, Input-Output
Input Voltage Noise
nV/√Hz
DC PERFORMANCE
Gain Error
RL = 1 kΩ
0.04/0.1
0.07/0.5
%
RL = 150 Ω
0.15/0.25
%
Gain Matching
No Load, Channel-Channel
RL = 1 kΩ, Channel-Channel
0.02/1.0
0.09/1.0
%
%
Gain T emperature Coefficient
0.5/8
ppm/°C
OUT PUT CHARACT ERIST ICS
Output Impedance
DC, Enabled
Disabled
Disabled
Disabled, AD8108 Only
No Load
0.2
10/0.001
2
1/NA
±3
40
Ω
MΩ
pF
µA
V
mA
mA
23, 29
20, 26
Output Disable Capacitance
Output Leakage Current
Output Voltage Range
Output Current
±2.5
20
Short Circuit Current
65
INPUT CHARACT ERIST ICS
Input Offset Voltage
Worst Case (All Configurations)
T emperature Coefficient
5
12
20
5
mV
µV/°C
V
pF
MΩ
µA
34, 40
35, 41
Input Voltage Range
Input Capacitance
Input Resistance
±2.5/±1.25 ±3/±1.5
Any Switch Configuration
Per Output Selected
2.5
10
2
1
Input Bias Current
SWIT CHING CHARACT ERIST ICS
Enable On T ime
60
ns
Switching T ime, 2 V Step
Switching T ransient (Glitch)
50% UPDATE to 1% Settling
Measured at Output
25
20/30
ns
mV p-p
21, 27
POWER SUPPLIES
Supply Current
AVCC, Outputs Enabled, No Load
AVCC, Outputs Disabled
AVEE, Outputs Enabled, No Load
AVEE, Outputs Disabled
DVCC
33
10
33
10
mA
mA
mA
mA
mA
V
10
Supply Voltage Range
PSRR
±4.5 to ±5.5
73/78
55/58
f = 100 kHz
f = 1 MHz
dB
dB
18, 24
OPERAT ING T EMPERAT URE RANGE
T emperature Range
θJA
Operating (Still Air)
Operating (Still Air)
–40 to +85
48
°C
°C/W
Specifications subject to change without notice.
–2–
REV. 0
AD8108/AD8109
TIMING CHARACTERISTICS (Serial)
Lim it
Typ
P aram eter
Sym bol
Min
Max
Units
Serial Data Setup T ime
CLK Pulsewidth
Serial Data Hold T ime
CLK Pulse Separation, Serial Mode
CLK to UPDATE Delay
UPDATE Pulsewidth
CLK to DAT A OUT Valid, Serial Mode
Propagation Delay, UPDATE to Switch On or Off
Data Load T ime, CLK = 5 MHz, Serial Mode
CLK, UPDATE Rise and Fall T imes
RESET T ime
t1
t2
t3
t4
t5
t6
t7
–
20
100
20
100
0
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
50
180
8
–
–
–
6.4
100
200
t2
t4
1
CLK
0
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
t1
t3
1
0
DATA IN
OUT7 (D3)
OUT7 (D2)
OUT00 (D0)
t6
t5
1 = LATCHED
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
UPDATE
0 = TRANSPARENT
t7
DATA OUT
Figure 1. Tim ing Diagram , Serial Mode
Table I. Logic Levels
VIH
VIL
VO H
VO L
IIH
IIL
IO H
IO L
RESET, SER/PAR
CLK, DAT A IN,
CE, UPDATE
RESET, SER/PAR
CLK, DAT A IN,
CE, UPDATE
RESET, SER/PAR RESET, SER/PAR
CLK, DAT A IN,
CLK, DAT A IN,
DAT A OUT
2.7 V min
DAT A OUT
0.5 V max
CE, UPDATE
CE, UPDATE
DAT A OUT
DAT A OUT
3.0 mA min
2.0 V min
0.8 V max
20 µA max
–400 µA min
–400 µA max
REV. 0
–3–
AD8108/AD8109
TIMING CHARACTERISTICS (Parallel)
Lim it
P aram eter
Sym bol
Min
Max
Units
Data Setup T ime
CLK Pulsewidth
Data Hold T ime
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulsewidth
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall T imes
RESET T ime
t1
t2
t3
t4
t5
t6
–
20
100
20
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
8
100
–
–
200
t2
t4
1
CLK
0
t1
t3
1
0
D0–D3
A0–A2
t5
t6
1 = LATCHED
UPDATE
0 = TRANSPARENT
Figure 2. Tim ing Diagram , Parallel Mode
Table II. Logic Levels
VIH
VIL
VO H
VO L
IIH
IIL
IO H
IO L
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
DAT A OUT
2.7 V min
DAT A OUT
0.5 V max
DAT A OUT
–400 µA max
DAT A OUT
3.0 mA min
2.0 V min
0.8 V max
20 µA max
–400 µA min
–4–
REV. 0
AD8108/AD8109
ABSO LUTE MAXIMUM RATINGS1
MAXIMUM P O WER D ISSIP ATIO N
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V
T he maximum power that can be safely dissipated by the
AD8108/AD8109 is limited by the associated rise in junction
temperature. T he maximum safe junction temperature for plas-
tic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately +150°C. T emporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the pack-
age. Exceeding a junction temperature of +175°C for an ex-
tended period can result in device failure.
Internal Power Dissipation2
AD8108/AD8109 80-Lead Plastic T QFP (ST ) . . . . . 2.6 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage T emperature Range . . . . . . . . . . . . –65°C to +125°C
Lead T emperature Range (Soldering 10 sec) . . . . . . . . +300°C
NOT ES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air (T A = +25°C):
While the AD8108/AD8109 is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junc-
tion temperature (+150°C) is not exceeded under all conditions.
T o ensure proper operation, it is necessary to observe the maxi-
mum power derating curves shown in Figure 3.
80-lead plastic T QFP (ST ): θJA = 48°C/W.
5.0
T
= 150؇C
J
4.0
3.0
2.0
1.0
0
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ؇C
Figure 3. Maxim um Power Dissipation vs. Tem perature
O RD ERING GUID E
P ackage
Tem perature
Range
P ackage
O ption
Model
D escription
AD8108AST
AD8109AST
AD8108-EB
AD8109-EB
–40°C to +85°C
–40°C to +85°C
80-Lead Plastic T QFP (12 mm × 12 mm)
80-Lead Plastic T QFP (12 mm × 12 mm)
Evaluation Board
ST -80A
ST -80A
Evaluation Board
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8108/AD8109 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. T herefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
AD8108/AD8109
Table III. O peration Truth Table
SER/
P AR
CE
UPDATE CLK
D ATA IN
D ATA O UT
RESET
O peration/Com m ent
1
0
X
1
X
f
X
Data
X
Data
X
1
X
0
No change in logic.
T he data on the serial DAT A IN line is loaded
into serial register. T he first bit clocked into
the serial register appears at DAT A OUT 32
clocks later.
i
i-32
0
1
f
D0 . . . D3,
A0 . . . A2
NA in Parallel
Mode
1
1
0
1
T he data on the parallel data lines, D0–D3, are
loaded into the 32-bit serial shift register loca-
tion addressed by A0–A2.
Data in the 32-bit shift register transfers into the
parallel latches that control the switch array.
Latches are transparent.
0
0
X
X
X
X
X
X
X
X
X
X
Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
D0
D1
D2
D3
PARALLEL DATA
(OUTPUT ENABLE)
SER/PAR
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
D Q
CLK
Q
Q
D
Q
Q
D Q
CLK
Q
D
Q
Q
D
Q
Q
D
Q
D
Q
D
Q
Q
D
Q
Q
Q
D
Q
Q
DATA IN
(SERIAL)
DATA
OUT
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CE
UPDATE
OUT0 EN
OUT1 EN
OUT2 EN
OUT3 EN
OUT4 EN
OUT5 EN
OUT6 EN
OUT7 EN
A0
A1
A2
D
D
D
D
D
D
D
D
D
D
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
OUT0
B0
OUT0
B1
OUT0
B2
OUT0
EN
OUT1
B0
OUT6
EN
OUT7
B0
OUT7
B1
OUT7
B2
OUT7
EN
Q
Q
Q
Q
Q
Q
Q
CLR
Q
CLR
Q
CLR Q
RESET
(OUTPUT ENABLE)
DECODE
8
OUTPUT ENABLE
64
SWITCH MATRIX
Figure 4. Logic Diagram
–6–
REV. 0
AD8108/AD8109
P IN FUNCTIO N D ESCRIP TIO NS
P in D escription
P in Nam e
P in Num bers
INxx
1, 3, 5, 7, 9, 11, 13, 15
Analog Inputs; xx = Channel Numbers 00 Through 07.
Serial Data Input, TTL Compatible.
DATA IN
CLK
57
58
59
56
Clock, TTL Compatible. Falling Edge Triggered.
Serial Data Out, TTL Compatible.
DATA OUT
UPDATE
Enable (Transparent) “Low.” Allows serial register to connect directly to switch
matrix. Data latched when “High.”
RESET
CE
61
Disable Outputs, Active “Low.”
60
Chip Enable, Enable “Low.” Must be “low” to clock in and latch data.
Selects Serial Data Mode, “Low” or Parallel Data Mode, “High.” Must be connected.
Analog Outputs yy = Channel Numbers 00 Through 07.
Analog Ground for Inputs and Switch Matrix.
SER/PAR
OUTyy
AGND
DVCC
DGND
AVEE
AVCC
AGNDxx
AVCCxx/yy
AVEExx/yy
A0
55
41, 38, 35, 32, 29, 26, 23, 20
2, 4, 6, 8, 10, 12, 14, 16, 46
63, 79
+5 V for Digital Circuitry.
62, 80
Ground for Digital Circuitry.
17, 45
–5 V for Inputs and Switch Matrix.
18, 44
+5 V for Inputs and Switch Matrix
42, 39, 36, 33, 30, 27, 24, 21
Ground for Output Amp, xx = Output Channel Numbers 00 Through 07. Must be connected.
+5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
–5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
Parallel Data Input, T T L Compatible (Output Select LSB).
Parallel Data Input, T T L Compatible (Output Select).
Parallel Data Input, T T L Compatible (Output Select MSB).
Parallel Data Input, T T L Compatible (Input Select LSB).
Parallel Data Input, T T L Compatible (Input Select).
Parallel Data Input, T T L Compatible (Input Select MSB).
Parallel Data Input, T T L Compatible (Output Enable).
Not Connected.
43, 37, 31, 25, 22, 19
40, 34, 28, 22
54
A1
53
A2
52
D0
51
D1
50
D2
49
D3
48
NC
47, 64–78
V
CC
V
V
CC
CC
20k⍀
ESD
ESD
ESD
ESD
OUTPUT
RESET
INPUT
1k⍀
(AD8109 ONLY)
ESD
ESD
AVEE
DGND
AVEE
a. Analog Input
b. Analog Output
c. Reset Input
V
V
CC
CC
ESD
ESD
2k⍀
ESD
ESD
OUTPUT
INPUT
DGND
DGND
d. Logic Input
e. Logic Output
Figure 5. I/O Schem atics
REV. 0
–7–
AD8108/AD8109
P IN CO NFIGURATIO N
1
2
60
59
58
CE
IN00
AGND
IN01
PIN 1
IDENTIFIER
DATA OUT
CLK
3
4
57 DATA IN
AGND
IN02
5
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
UPDATE
SER/PAR
A0
6
AGND
IN03
7
8
A1
AGND
IN04
9
A2
AD8108/AD8109
10
11
12
13
14
15
16
17
18
19
20
D0
AGND
IN05
TOP VIEW
(Not to Scale)
D1
D2
AGND
IN06
D3
NC
AGND
IN07
AGND
AVEE
AVCC
AVCC00
AGND00
OUT00
AGND
AVEE
AVCC
AVCC07
OUT07
NC = NO CONNECT
–8–
REV. 0
AD8108/AD8109
5
4
0.4
0.3
0.2
0.1
0
R
= 150⍀
L
3
+50mV
+25mV
0
2
FLATNESS
1
200mV p-p
–25mV
–50mV
–0.1
0
GAIN
–0.2
–0.3
–0.4
–1
–2
–3
2V p-p
10ns/DIV
100k
1M
10M
FREQUENCY – Hz
100M
1G
Figure 9. AD8108 Step Response, 100 m V Step
Figure 6. AD8108 Frequency Response
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
R
= 1k⍀
L
+1.0V
+0.5V
0
ALL HOSTILE
–0.5V
–1.0V
ADJACENT
10ns/DIV
0.2
1
10
100 200
FREQUENCY – MHz
Figure 7. AD8108 Crosstalk vs. Frequency
Figure 10. AD8108 Step Response, 2 V Step
–30
–40
–50
–60
–70
–80
–90
–100
R
= 150⍀
= 2V p-p
L
V
OUT
2V STEP
R
= 150⍀
L
0.2
2ND HARMONIC
0.1
0
–0.1
–0.2
3RD HARMONIC
0
10 20 30 40 50 60 70 80
10ns/DIV
100k
1M
10M
FREQUENCY – Hz
100M
Figure 8. AD8108 Distortion vs. Frequency
Figure 11. AD8108 Settling Tim e
REV. 0
–9–
AD8108/AD8109
5
4
3
0.4
0.3
0.2
0.1
2V p-p
+50mV
+25mV
0
2
FLATNESS
200mV p-p
1
0
0
–0.1
–25mV
–50mV
GAIN
–0.2
–0.3
–0.4
–1
2V p-p
–2
–3
10ns/DIV
100k
1M
10M
FREQUENCY – Hz
100M
1G
Figure 12. AD8109 Frequency Response
Figure 15. AD8109 Step Response, 100 m V Step
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
R
= 1k⍀
L
+1.0V
+0.5V
0
ADJACENT
–0.5V
–1.0V
ALL HOSTILE
10ns/DIV
300k
1M
10M
FREQUENCY – Hz
100M 200M
Figure 16. AD8109 Step Response, 2 V Step
Figure 13. AD8109 Crosstalk vs. Frequency
–30
–40
–50
–60
–70
–80
–90
–100
R
= 150⍀
= 2V p-p
L
2V STEP RTO
L
V
OUT
R
= 150⍀
0.2
2ND HARMONIC
0.1
0
–0.1
–0.2
3RD HARMONIC
0
20
40
60
80
100k
1M
10M
FREQUENCY – Hz
100M
10ns/DIV
Figure 14. AD8109 Distortion vs. Frequency
Figure 17. AD8109 Settling Tim e
–10–
REV. 0
AD8108/AD8109
–30
–40
–50
–60
–70
–80
–90
R
= 150⍀
L
5
4
SWITCHING BETWEEN
TWO INPUTS
3
UPDATE INPUT
2
1
0
10
0
TYPICAL VIDEO OUT (RTO)
–10
50ns/DIV
10k
100k
1M
10M
FREQUENCY – Hz
Figure 18. AD8108 PSRR vs. Frequency
Figure 21. AD8108 Switching Transient (Glitch)
–40
100
56.3
31.6
17.8
10
V
= 2V p-p
–50
–60
IN
R
= 150⍀
L
–70
–80
–90
–100
–110
–120
–130
5.63
3.16
–140
100k
1M
10M
100M
500M
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 22. AD8108 Off Isolation, Input-Output
Figure 19. AD8108 Voltage Noise vs. Frequency
1M
1k
100
10
100k
10k
1k
1
100
0.1
100k
1
0.1
10
100
500
1M
10M
100M
500M
FREQUENCY – MHz
FREQUENCY – Hz
Figure 20. AD8108 Output Im pedance, Disabled
Figure 23. AD8108 Output Im pedance, Enabled
REV. 0
–11–
AD8108/AD8109
–30
R
= 150⍀
L
SWITCHING BETWEEN
TWO INPUTS
–40
–50
–60
–70
–80
–90
5
4
3
2
1
0
UPDATE INPUT
10
0
TYPICAL VIDEO OUT (RTO)
–10
50ns/DIV
10k
100k
1M
10M
FREQUENCY – Hz
Figure 24. AD8109 PSRR vs. Frequency
Figure 27. AD8109 Switching Transient (Glitch)
–40
100
56.3
31.6
17.8
10
V
= 2V p-p
–50
–60
OUT
R
= 150⍀
L
–70
–80
–90
–100
–110
–120
–130
–140
5.63
3.16
1M
100k
10M
100M
500M
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 28. AD8109 Off Isolation, Input-Output
Figure 25. AD8109 Voltage Noise vs. Frequency
1k
100
10
100k
10k
1k
1
100
0.1
100k
1
100k
1M
10M
100M
500M
1M
10M
100M
500M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 29. AD8109 Output Im pedance, Enabled
Figure 26. AD8109 Output Im pedance, Disabled
–12–
REV. 0
AD8108/AD8109
1M
100k
10k
1k
V
OUT
1
0
INPUT 1 AT +1V
–1
INPUT 0 AT –1V
5
0
UPDATE
100
30k
50ns/DIV
100k
1M
10M
100M
500M
FREQUENCY – Hz
Figure 30. AD8108 Input Im pedance vs. Frequency
Figure 33. AD8108 Switching Tim e
900
800
700
600
500
400
300
200
100
0
V
R
= 200mV
= 150⍀
IN
8
6
L
C
= 18pF
L
4
2
C
= 12pF
0
L
–2
–4
–6
–8
30k 100k
1M
10M
100M
1G
3G
–0.020
–0.010
0.000
0.010
0.020
FREQUENCY – Hz
OFFSET VOLTAGE – Volts
Figure 31. AD8108 Frequency Response vs. Capacitive Load
Figure 34. AD8108 Offset Voltage Distribution
0.5
2.0
1.5
V
R
= 200mV
= 150⍀
IN
0.4
0.3
L
C
= 18pF
L
1.0
0.2
0.5
0.1
0
0.0
C
= 12pF
L
–0.1
–0.2
–0.3
–0.5
–1.0
–1.5
–2.0
–0.4
–0.5
30k 100k
1M
10M
FREQUENCY – Hz
100M
1G
3G
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE – ؇C
Figure 32. AD8108 Flatness vs. Capacitive Load
Figure 35. AD8108 Offset Voltage Drift vs. Tem perature
(Norm alized at +25 °C)
REV. 0
–13–
AD8108/AD8109
1M
V
OUT
100k
10k
1k
1
0
INPUT 1 AT +1V
INPUT 0 AT –1V
–1
5
0
UPDATE
100
30k
50ns/DIV
100k
1M
10M
100M
500M
FREQUENCY – Hz
Figure 36. AD8109 Input Im pedance vs. Frequency
Figure 39. AD8109 Switching Tim e
320
300
280
260
240
220
200
180
160
140
120
100
80
V
R
= 100mV
= 150⍀
IN
8
6
L
C
= 18pF
L
4
2
0
–2
–4
–6
–8
C
= 12pF
L
60
40
0
30k 100k
1M
10M
100M
1G
3G
–0.020
–0.010
0.000
0.010
0.020
FREQUENCY – Hz
OFFSET VOLTAGE – Volts
Figure 37. AD8109 Frequency Response vs. Capacitive Load
Figure 40. AD8109 Offset Voltage Distribution (RTI)
2.0
1.5
V
R
= 100mV
= 150⍀
IN
0.4
0.3
L
C
= 18pF
L
1.0
0.2
0.5
0.1
0
0.0
C
= 12pF
L
–0.1
–0.2
–0.3
–0.4
–0.5
–1.0
–1.5
–2.0
30k 100k
1M
10M
100M
1G
3G
–60
–40
–20
0
20
40
60
80
100
FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 38. AD8109 Flatness vs. Capacitive Load
Figure 41. AD8109 Offset Voltage Drift vs. Tem perature
(Norm alized at +25 °C)
–14–
REV. 0
AD8108/AD8109
TH EO RY O F O P ERATIO N:
T he UPDATE signal should be HIGH during the time that data
is shifted into the device’s serial port. Although the data will still
shift in when UPDATE is LOW, the transparent, asynchronous
latches will allow the shifting data to reach the matrix. T his will
cause the matrix to try to update to every intermediate state as
defined by the shifting data.
T he AD8108 (G = +1) and AD8109 (G = +2) share a common
core architecture consisting of an array of 64 transconductance
(gm) input stages organized as eight 8:1 multiplexers with a
common, 8-line analog input bus. Each multiplexer is basically
a folded-cascode high impedance voltage feedback amplifier
with eight input stages. T he input stages are NPN differential
pairs whose differential current outputs are combined at the
output stage, which contains the high impedance node, com-
pensation and a complementary emitter follower output buffer.
In the AD8108, the output of each multiplexer is fed back di-
rectly to the inverting inputs of its eight gm stages. In the
AD8109, the feedback network is a voltage divider consisting of
a two equal resistors.
T he data at DAT A IN is clocked in at every down edge of CLK.
A total of 32 data bits must be shifted in to complete the pro-
gramming. For each of the eight outputs, there are three bits
(D0–D2) that determine the source of its input followed by one
bit (D3) that determines the enabled state of the output. If D3
is LOW (output disabled), the three associated bits (D0–D2) do
not matter because no input will be switched to that output.
T he most-significant-output-address data is shifted in first, then
following in sequence until the least-significant-output-address
data is shifted in. At this point UPDATE can be taken LOW,
which will cause the programming of the device according to the
data that was just shifted in. T he UPDATE registers are asyn-
chronous and when UPDATE is LOW, they are transparent.
T his switched-gm architecture results in a low power crosspoint
switch that is able to directly drive a back terminated video load
(150 Ω) with low distortion (differential gain and differential
phase errors are better than 0.02% and 0.02°, respectively).
T his design also achieves high input resistance and low input
capacitance without the signal degradation and power dissipa-
tion of additional input buffers. However, the small input bias
current at any input will increase almost linearly with the num-
ber of outputs programmed to that input.
If more than one AD8108/AD8109 device is to be serially pro-
grammed in a system, the DAT A OUT signal from one device
can be connected to the DAT A IN of the next device to form a
serial chain. All of the CLK, CE, UPDATE and SER/PAR
pins should be connected in parallel and operated as de-
scribed above. T he serial data is input to the DAT A IN pin of
the first device of the chain, and it will ripple on through to the
last. T herefore, the data for the last device in the chain should
come at the beginning of the programming sequence. The length
of the programming sequence will be 32 times the number of
devices in the chain.
T he output disable feature of these crosspoints allows larger
switch matrices to be built by simply busing together the out-
puts of multiple 8 × 8 ICs. However, while the disabled output
impedance of the AD8108 is very high (10 MΩ), that of the
AD8109 is limited by the resistive feedback network (which has
a nominal total resistance of 1 kΩ that appears in parallel with
the disabled output. If the outputs of multiple AD8109s are
connected through separate back termination resistors, the
loading due to these finite output impedances will lower the
effective back termination impedance of the overall matrix. T his
problem is eliminated if the outputs of multiple AD8109s are
connected directly and share a single back termination resistor
for each output of the overall matrix. T his configuration in-
creases the capacitive loading of the disabled AD8109s on the
output of the enabled AD8109.
P ARALLEL P RO GRAMMING
When using the parallel programming mode, it is not neces-
sary to reprogram the entire device when making changes to
the matrix. In fact, parallel programming allows the modifica-
tion of a single output at a time. Since this takes only one CLK/
UPDATE cycle, significant time savings can be realized by
using parallel programming.
AP P LICATIO NS
One important consideration in using parallel programming is
that the RESET signal DOES NOT RESET ALL REGIST ERS
in the AD8108/AD8109. When taken low, the RESET signal
will only set each output to the disabled state. T his is helpful
during power-up to ensure that two parallel outputs will not be
active at the same time.
T he AD8108/AD8109 have two options for changing the pro-
gramming of the crosspoint matrix. In the first, a serial word of
32 bits can be provided that will update the entire matrix each
time. T he second option allows for changing a single output’s
programming via a parallel interface. T he serial option requires
fewer signals, but requires more time (clock cycles) for changing
the programming, while the parallel programming technique re-
quires more signals, but can change a single output at a time and
requires fewer clock cycles to complete programming.
After initial power-up, the internal registers in the device will
generally have random data, even though the RESET signal was
asserted. If parallel programming is used to program one out-
put, that output will be properly programmed but the rest of the
device will have a random program state depending on the inter-
nal register content at power-up. T herefore, when using parallel
programming, it is essential that ALL OUT PUT S BE PRO-
GRAMMED T O A DESIRED ST AT E AFT ER POWER-UP.
T his will ensure that the programming matrix is always in a
known state. From then on, parallel programming can be used
to modify a single, or more, output at a time.
Ser ial P r ogr am m ing
T he serial programming mode uses the device pins CE, CLK,
DAT A IN, UPDATE, and SER/PAR. T he first step is to assert
a LOW on SER/PAR in order to enable the serial program-
ming mode. CE for the chip must be LOW to allow data to be
clocked into the device. T he CE signal can be used to address
an individual device when devices are connected in parallel.
REV. 0
–15–
AD8108/AD8109
Gain Selection
In a similar fashion, if both CE and UPDATE are taken LOW
after initial power-up, the random power-up data in the shift
register will be programmed into the matrix. T herefore, in order
to prevent the crosspoint from being programmed into an un-
known state DO NOT APPLY LOW LOGIC LEVELS T O
BOT H CE AND UPDATE AFT ER POWER IS INIT IALLY
APPLIED. Programming the full shift register one time to a
desired state by either serial or parallel programming after initial
power-up will eliminate the possibility of programming the
matrix to an unknown state.
T he 8 × 8 crosspoints come in two versions depending on the
desired gain of the analog circuit paths. T he AD8108 device is
unity gain and can be used for analog logic switching and other
applications where unity gain is desired. T he AD8108 can also
be used for the input and interior sections of larger crosspoint
arrays where termination of output signals is not usually used.
T he AD8108 outputs have a very high impedance when their
outputs are disabled.
For devices that will be used to drive a terminated cable with its
outputs, the AD8109 can be used. T his device has a built-in
gain of two that eliminates the need for a gain-of-two buffer to
drive a video line. Because of the presence of the feedback net-
work in these devices, the disabled output impedance is about
1 kΩ.
T o change an output’s programming via parallel programming,
SER/PAR and UPDATE should be taken HIGH and CE should
be taken LOW. T he CLK signal should be in the HIGH state.
T he address of the output that is to be programmed should be
put on A0–A2. T he first three data bits (D0–D2) should contain
the information that identifies the input that is programmed to
the output that is addressed. T he fourth data bit (D3) will de-
termine the enabled state of the output. If D3 is LOW (output
disabled) the data on D0–D2 does not matter.
If external amplifiers will be used to provide a G = +2, our
AD8079 is a fixed gain of +2 buffer.
Cr eating Lar ger Cr osspoint Ar r ays
T he AD8108/AD8109 are high density building blocks for cre-
ating crosspoint arrays of dimensions larger than 8 × 8. Various
features such as output disable, chip enable, and gain-of-one
and -two options are useful for creating larger arrays. For very
large arrays, they can be used along with the AD8116, a 16 × 16
video crosspoint device. In addition, systems that require more
inputs than outputs can use the AD8110 and/or the AD8111,
which are (gain-of-one and gain-of-two) 16 × 8 crosspoint
switches.
After the desired address and data signals have been established,
they can be latched into the shift register by a HIGH to LOW
transition of the CLK signal. The matrix will not be programmed,
however, until the UPDATE signal is taken low. T hus, it is
possible to latch in new data for several or all of the outputs first
via successive negative transitions of CLK while UPDATE is
held high, and then have all the new data take effect when
UPDATE goes LOW. T his is the technique that should be
used when programming the device for the first time after
power-up when using parallel programming.
T he first consideration in constructing a larger crosspoint is to
determine the minimum number of devices required. T he 8 × 8
architecture of the AD8108/AD8109 contains 64 “points,”
which is a factor of 16 greater than a 4 × 1 crosspoint. T he PC
board area and power consumption savings are readily apparent
when compared to using these smaller devices.
P O WER-O N RESET
When powering up the AD8108/AD8109 it is usually desirable
to have the outputs come up in the disabled state. T he RESET
pin, when taken LOW will cause all outputs to be in the dis-
abled state. However, the RESET signal DOES NOT RESET
ALL REGIST ERS in the AD8108/AD8109. T his is important
when operating in the parallel programming mode. Please refer
to that section for information about programming internal
registers after power-up. Serial programming will program the
entire matrix each time, so no special considerations apply.
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the avail-
ability of that input to be a source for any other outputs.
Some nonblocking crosspoint architectures will require more
than this minimum as calculated above. Also, there are blocking
architectures that can be constructed with fewer devices than
this minimum. T hese systems have connectivity available on a
statistical basis that is determined when designing the overall
system.
Since the data in the shift register is random after power-up,
they should not be used to program the matrix or else the matrix
can enter unknown states. T o prevent this, DO NOT APPLY
LOGIC LOW SIGNALS T O BOT H CE AND UPDATE
INIT IALLY AFT ER POWER-UP. T he shift register should
first be loaded with the desired data, and then UPDATE can be
taken LOW to program the device.
T he basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to “wire-
OR” the outputs together in the vertical direction. T he meaning
of horizontal and vertical can best be understood by looking at a
diagram.
T he RESET pin has a 20 kΩ pull-up resistor to DVDD that can
be used to create a simple power-up reset circuit. A capacitor
from RESET to ground will hold RESET LOW for some time
while the rest of the device stabilizes. T he LOW condition will
cause all the outputs to be disabled. T he capacitor will then
charge through the pull-up resistor to the HIGH state, thus
allowing full programming capability of the device.
An 8 input by 16 output crosspoint array can be constructed as
shown in Figure 42. T his configuration parallels two inputs per
channel and does not require paralleling of any outputs. Inputs
are easier to parallel than outputs, because there are lower
parasitics involved. For a 16 × 8 crosspoint, the AD8110 (gain
of one) or AD8111 (gain of two) device can be used. T hese
devices are already configured into a 16 × 8 crosspoint in a
single device.
–16–
REV. 0
AD8108/AD8109
At some point, the number of outputs that are wire-ORed be-
comes too great to maintain system performance. T his will vary
according to which system specifications are most important.
For example, a 64 × 8 crosspoint can be created with eight
AD8108/AD8109s. T his design will have 64 separate inputs and
have the corresponding outputs of each device wire-ORed to-
gether in groups of eight.
AD8108
OR
AD8109
8
8
8
8 INPUTS
IN 00–07
AD8108
OR
AD8109
ONE
TERMINATION
PER INPUT
Using additional crosspoint devices in the design can lower the
number of outputs that have to be wire-ORed together. Figure
45 shows a block diagram of a system using eight AD8108s and
two AD8109s to create a nonblocking, gain-of-two, 64 × 8 cross-
point that restricts the wire-ORing at the output to only four
outputs. T he rank 1 wire-ORed devices are the AD8108,
which has a higher disabled output impedance than the AD8109.
8
8
16 OUTPUTS
OUT 00–15
Figure 42. 8 × 16 Crosspoint Array Using Two AD8108s
(Unity Gain) or Two AD8109s (Gain-of-Two)
Figure 43 illustrates a 16 × 16 crosspoint array, while a 24 × 24
crosspoint is illustrated in Figure 44. T he 16 × 16 crosspoint
requires that each input driver drive two inputs in parallel and
each output be wire-ORed with one other output. T he 24 × 24
crosspoint requires driving three inputs in parallel and having
the outputs wire-ORed in groups of three. It is required of the
system programming that only one output of a wired-OR node
be active at a time.
RANK 1
(64:16)
4
8
AD8108
AD8108
AD8108
AD8108
AD8108
AD8108
AD8108
AD8108
IN 00–07
IN 08–15
IN 16–23
IN 24–31
IN 32–39
4
4
4
8
8
8
8
8
8
8
RANK 2
16:8 NONBLOCKING
16:16 BLOCKING
4
4
4
4
OUT 00–07
NONBLOCKING
AD8109
4
1k⍀
4
4
4
1k⍀
8
00–07
8
؋
8 8
؋
8 IN 00–07
8
ADDITIONAL
8 OUTPUTS
(SUBJECT TO
BLOCKING)
4
4
4
4
R
TERM
8
8
AD8109
4
4
4
4
1k⍀
1k⍀
IN 40–47
IN 48–55
IN 56–63
8
08–15
8
؋
8 8
؋
8 IN 08–15
4
4
8
R
TERM
8
8
4
4
OUT 00–07
OUT 08–15
Figure 43. 16 × 16 Crosspoint Array Using Four
AD8108s or AD8109s
Figure 45. Nonblocking 64 × 8 Array with Gain-of-Two
(64 × 16 Blocking)
Additionally, by using the lower four outputs from each of the
two Rank 2 AD8109s, a blocking 64 × 16 crosspoint array can
be realized. T here are, however, some drawbacks to this tech-
nique. T he offset voltages of the various cascaded devices will
accumulate and the bandwidth limitations of the devices will
compound. In addition, the extra devices will consume more
current and take up more board space. Once again, the overall
system design specifications will determine how to make the
various tradeoffs.
8
IN 00–07
IN 08–15
8
؋
8 8
؋
8 8
؋
8 8
R
TERM
8
8
8
8
8
؋
8 8
؋
8 8
؋
8 8
R
TERM
8
8
8
Multichannel Video
T he excellent video specifications of the AD8108/AD8109 make
them ideal candidates for creating composite video crosspoint
switches. T hese can be made quite dense by taking advantage
of the AD8108/AD8109’s high level of integration and the fact
that composite video requires only one crosspoint channel per
system video channel. T here are, however, other video formats
that can be routed with the AD8108/AD8109 requiring more
than one crosspoint channel per video channel.
8
8
؋
8 8
؋
8 8
؋
8 IN 16–23
8
R
8
8
8
TERM
OUT 00–07
OUT 16–23
OUT 08–15
Figure 44. 24 × 24 Crosspoint Array Using Nine AD8108s
or AD8109s
REV. 0
–17–
AD8108/AD8109
Some systems use twisted-pair wiring to carry video signals.
T hese systems utilize differential signals and can lower costs
because they use lower cost cables, connectors and termination
methods. T hey also have the ability to lower crosstalk and reject
common-mode signals, which can be important for equipment
that operates in noisy environments or where common-mode
voltages are present between transmitting and receiving equipment.
When there are many signals in close proximity in a system, as
will undoubtedly be the case in a system that uses the AD8108/
AD8109, the crosstalk issues can be quite complex. A good
understanding of the nature of crosstalk and some definition of
terms is required in order to specify a system that uses one or
more AD8108/AD8109s.
TYP ES O F CRO SSTALK
In such systems, the video signals are differential; there is a
positive and negative (or inverted) version of the signals. T hese
complementary signals are transmitted onto each of the two
wires of the twisted pair, yielding a first order zero common-
mode signal. At the receive end, the signals are differentially
received and converted back into a single-ended signal.
Crosstalk can be propagated by means of any of three methods.
T hese fall into the categories of electric field, magnetic field and
sharing of common impedances. T his section will explain these
effects.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. T he electric field crosstalk mechanism
occurs when the electric field created by the transmitter propa-
gates across a stray capacitance (e.g., free space) and couples
with the receiver and induces a voltage. T his voltage is an un-
wanted crosstalk signal in any channel that receives it.
When switching these differential signals, two channels are
required in the switching element to handle the two differential
signals that make up the video channel. T hus, one differential
video channel is assigned to a pair of crosspoint channels, both
input and output. For a single AD8108/AD8109, four differen-
tial video channels can be assigned to the eight inputs and eight
outputs. T his will effectively form a 4 × 4 differential crosspoint
switch.
Currents flowing in conductors create magnetic fields that circu-
late around the currents. T hese magnetic fields will then gener-
ate voltages in any other conductors whose paths they link. T he
undesired induced voltages in these other channels are crosstalk
signals. T he channels that crosstalk can be said to have a mutual
inductance that couples signals from one channel to another.
Programming such a device will require that inputs and outputs
be programmed in pairs. T his information can be deduced by
inspection of the programming format of the AD8108/AD8109
and the requirements of the system.
T he power supplies, grounds and other signal return paths of a
multichannel system are generally shared by the various chan-
nels. When a current from one channel flows in one of these
paths, a voltage that is developed across the impedance becomes
an input crosstalk signal for other channels that share the com-
mon impedance.
T here are other analog video formats requiring more than one
analog circuit per video channel. One two-circuit format that is
commonly being used in systems such as satellite T V, digital
cable boxes and higher quality VCRs, is called S-video or Y/C
video. T his format carries the brightness (luminance or Y) por-
tion of the video signal on one channel and the color (chromi-
nance, chroma or C) on a second channel.
All these sources of crosstalk are vector quantities, so the
magnitudes cannot simply be added together to obtain the
total crosstalk. In fact, there are conditions where driving addi-
tional circuits in parallel in a given configuration can actually
reduce the crosstalk.
Since S-video also uses two separate circuits for one video chan-
nel, creating a crosspoint system requires assigning one video
channel to two crosspoint channels as in the case of a differen-
tial video system. Aside from the nature of the video format,
other aspects of these two systems will be the same.
Ar eas of Cr osstalk
For a practical AD8108/AD8109 circuit, it is required that it be
mounted to some sort of circuit board in order to connect it to
power supplies and measurement equipment. Great care has
been taken to create a characterization board (also available as
an evaluation board) that adds minimum crosstalk to the intrin-
sic device. This, however, raises the issue that a system’s crosstalk
is a combination of the intrinsic crosstalk of the devices in addi-
tion to the circuit board to which they are mounted. It is impor-
tant to try to separate these two areas of crosstalk when attempting
to minimize its effect.
T here are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
blue) directly from the image sensors. RGB is also the usual
format used by computers internally for graphics. RGB can also
be converted to Y, R–Y, B–Y format, sometimes called YUV
format. T hese three-circuit, video standards are referred to as
component analog video.
T he component video standards require three crosspoint chan-
nels per video channel to handle the switching function. In a
fashion similar to the two-circuit video formats, the inputs and
outputs are assigned in groups of three and the appropriate logic
programming is performed to route the video signals.
In addition, crosstalk can occur among the inputs to a cross-
point and among the outputs. It can also occur from input to
output. T echniques will be discussed for diagnosing which part
of a system is contributing to crosstalk.
CRO SSTALK
Measur ing Cr osstalk
Many systems, such as broadcast video, that handle numerous
analog signal channels have strict requirements for keeping the
various signals from influencing any of the others in the system.
Crosstalk is the term used to describe the coupling of the signals
of other nearby channels to a given channel.
Crosstalk is measured by applying a signal to one or more chan-
nels and measuring the relative strength of that signal on a de-
sired selected channel. T he measurement is usually expressed as
dB down from the magnitude of the test signal. T he crosstalk is
expressed by:
| XT| = 20 log10 (Asel(s)/Atest(s))
–18–
REV. 0
AD8108/AD8109
where s = jω is the Laplace transform variable, Asel(s) is the
amplitude of the crosstalk-induced signal in the selected channel
and Atest(s) is the amplitude of the test signal. It can be seen
that crosstalk is a function of frequency, but not a function of
the magnitude of the test signal (to first order). In addition, the
crosstalk signal will have a phase relative to the test signal asso-
ciated with it.
All the other inputs are driven in parallel with the same test
signal (practically provided by a distribution amplifier), with all
other outputs except OUT 03 disabled. Since grounded IN03
is programmed to drive OUT 03, there should be no signal
present. Any signal that is present can be attributed to the other
seven hostile input signals, because no other outputs are driven
(they are all disabled). T hus, this method measures the all-
hostile input contribution to crosstalk into IN03. Of course, the
method can be used for other input channels and combinations
of hostile inputs.
A network analyzer is most commonly used to measure crosstalk
over a frequency range of interest. It can provide both magni-
tude and phase information about the crosstalk signal.
For output crosstalk measurement, a single input channel is
driven (IN00 for example) and all outputs other than a given
output (IN03 in the middle) are programmed to connect to
IN00. OUT 03 is programmed to connect to IN07 (far away
from IN00), which is terminated to ground. T hus OUT 03
should not have a signal present since it is listening to a quiet
input. Any signal measured at the OUT 03 can be attributed to
the output crosstalk of the other seven hostile outputs. Again,
this method can be modified to measure other channels and
other crosspoint matrix combinations.
As a crosspoint system or device grows larger, the number of
theoretical crosstalk combinations and permutations can be-
come extremely large. For example, in the case of the 8 × 8
matrix of the AD8108/AD8109, we can examine the number of
crosstalk terms that can be considered for a single channel,
say IN00 input. IN00 is programmed to connect to one of the
AD8108/AD8109 outputs where the measurement can be made.
We can first measure the crosstalk terms associated with driving
a test signal into each of the other seven inputs one at a time.
We can then measure the crosstalk terms associated with driving
a parallel test signal into all seven other inputs taken two at a
time in all possible combinations; and then three at a time, etc.,
until, finally, there is only one way to drive a test signal into all
seven other inputs.
Effect of Im pedances on Cr osstalk
T he input side crosstalk can be influenced by the output imped-
ance of the sources that drive the inputs. T he lower the im-
pedance of the drive source, the lower the magnitude of the
crosstalk. T he dominant crosstalk mechanism on the input side
is capacitive coupling. T he high impedance inputs do not have
significant current flow to create magnetically induced crosstalk.
However, significant current can flow through the input termi-
nation resistors and the loops that drive them. T hus, the PC
board on the input side can contribute to magnetically coupled
crosstalk.
Each of these cases is legitimately different from the others and
might yield a unique value depending on the resolution of the
measurement system, but it is hardly practical to measure all
these terms and then to specify them. In addition, this describes
the crosstalk matrix for just one input channel. A similar
crosstalk matrix can be proposed for every other input. In addi-
tion, if the possible combinations and permutations for connect-
ing inputs to the other (not used for measurement) outputs are
taken into consideration, the numbers rather quickly grow to
astronomical proportions. If a larger crosspoint array of multiple
AD8108/AD8109s is constructed, the numbers grow larger still.
From a circuit standpoint, the input crosstalk mechanism looks
like a capacitor coupling to a resistive load. For low frequencies
the magnitude of the crosstalk will be given by:
| XT| = 20 log10 [(RS CM) × s]
Obviously, some subset of all these cases must be selected to be
used as a guide for a practical measure of crosstalk. One com-
mon method is to measure “all hostile” crosstalk. T his term
means that the crosstalk to the selected channel is measured,
while all other system channels are driven in parallel. In general,
this will yield the worst crosstalk number, but this is not always
the case due to the vector nature of the crosstalk signal.
where RS is the source resistance, CM is the mutual capacitance
between the test signal circuit and the selected circuit, and s is
the Laplace transform variable.
From the equation it can be observed that this crosstalk mecha-
nism has a high pass nature; it can also be minimized by reduc-
ing the coupling capacitance of the input circuits and lowering
the output impedance of the drivers. If the input is driven from
a 75 Ω terminated cable, the input crosstalk can be reduced by
buffering this signal with a low output impedance buffer.
Other useful crosstalk measurements are those created by one
nearest neighbor or by the two nearest neighbors on either side.
T hese crosstalk measurements will generally be higher than
those of more distant channels, so they can serve as a worst case
measure for any other one-channel or two-channel crosstalk
measurements.
On the output side, the crosstalk can be reduced by driving a
lighter load. Although the AD8108/AD8109 is specified with
excellent differential gain and phase when driving a standard
150 Ω video load, the crosstalk will be higher than the minimum
obtainable due to the high output currents. T hese currents will
induce crosstalk via the mutual inductance of the output pins
and bond wires of the AD8108/AD8109.
Input and O utput Cr osstalk
T he flexible programming capability of the AD8108/AD8109
can be used to diagnose whether crosstalk is occurring more on
the input side or the output side. Some examples are illustra-
tive. A given input channel (IN03 in the middle for this ex-
ample) can be programmed to drive OUT 03. T he input to IN03
is just terminated to ground (via 50 Ω or 75 Ω) and no signal is
applied.
REV. 0
–19–
AD8108/AD8109
Each output also has an on-chip compensation capacitor that
is individually tied the nearby analog ground pins AGND00
through AGND07. T his technique reduces crosstalk by prevent-
ing the currents that flow in these paths from sharing a common
impedance on the IC and in the package pins. T hese AGNDxx
signals should all be directly connected to the ground plane.
From a circuit standpoint, this output crosstalk mechanism
looks like a transformer, with a mutual inductance between the
windings, that drives a load resistor. For low frequencies, the
magnitude of the crosstalk is given by:
| XT| = 20 log10 (Mxy × s/RL)
where Mxy is the mutual inductance of output x to output y and
RL is the load resistance on the measured output. T his crosstalk
mechanism can be minimized by keeping the mutual inductance
low and increasing RL. T he mutual inductance can be kept low
by increasing the spacing of the conductors and minimizing
their parallel length.
T he input and output signals will have minimum crosstalk if
they are located between ground planes on layers above and
below, and separated by ground in between. Vias should be
located as close to the IC as possible to carry the inputs and
outputs to the inner layer. T he only place the input and output
signals surface is at the input termination resistors and the out-
put series back termination resistors. T hese signals should also
be separated, to the extent possible, as soon as they emerge from
the IC package.
P CB Layout
Extreme care must be exercised to minimize additional crosstalk
generated by the system circuit board(s). T he areas that must be
carefully detailed are grounding, shielding, signal routing and
supply bypassing.
Evaluation Boar d
A four-layer evaluation board for the AD8108/AD8109 is avail-
able. T he exact same board and external components are used
for each device. T he only difference is the device itself, which
offers a selection of a gain of unity or gain of two through the
analog channels. T his board has been carefully laid out and
tested to demonstrate the specified high speed performance of
the device. Figure 46 shows the schematic of the evaluation
board. Figure 47 shows the component side silk-screen. T he
layouts of the board’s four layers are given in Figures 48, 49, 50
and 51.
T he packaging of the AD8108/AD8109 is designed to help keep
the crosstalk to a minimum. Each input is separated from each
other input by an analog ground pin. All of these AGNDs
should be directly connected to the ground plane of the circuit
board. T hese ground pins provide shielding, low impedance
return paths and physical separation for the inputs. All of these
help to reduce crosstalk.
Each output is separated from its two neighboring outputs by an
analog ground pin in addition to an analog supply pin of one
polarity or the other. Each of these analog supply pins provides
power to the output stages of only the two nearest outputs.
T hese supply pins and analog grounds provide shielding, physi-
cal separation and a low impedance supply for the outputs.
Individual bypassing of each of these supply pins, with a 0.01 µF
chip capacitor directly to the ground plane, minimizes high
frequency output crosstalk via the mechanism of sharing com-
mon impedances.
T he evaluation board package includes the following:
• Fully populated board with BNC-type connectors.
• Windows™ based software for controlling the board from a
PC via the printer port.
• Custom cable to connect evaluation board to PC.
• Disk containing Gerber files of board layout.
All trademarks are property of their respective holders.
–20–
REV. 0
AD8108/AD8109
DVCC DGND NC
AVEE AGND AVCC
P1-3 P1-4 P1-6
P1-5
NC
P1-7
P1-1 P1-2
+
+
CR1
CR2
1N4148
DVCC
0.01F
DVCC
0.01F
AVCC
0.01F
AVCC
0.01F
AVEE
0.01F
+
0.1F 10F
0.1F 10F
0.1F 10F
80
79
63
43
44
45
46
DGND DVCC
DVCC
AVCC
AVCC
AVEE
AGND
42
AGND
1
2
INPUT 00
INPUT 00
75⍀
41
AGND
OUTPUT 00
75⍀
75⍀
75⍀
75⍀
75⍀
75⍀
75⍀
75⍀
40
AVEE
AGND
AVEE
0.01F
75⍀
39
38
3
4
INPUT 01
INPUT 02
INPUT 03
INPUT 04
INPUT 05
INPUT 06
INPUT 07
INPUT 01
AGND
OUTPUT 01
37
36
AVCC
AGND
AVCC
AVEE
AVCC
AVEE
AVCC
AVEE
0.01F
75⍀
5
6
35
INPUT 02
AGND
OUTPUT 02
34
33
AVEE
AGND
0.01F
75⍀
32
7
8
OUTPUT 03
INPUT 03
AGND
31
30
AD8108 OR AD8109
AVCC
AGND
0.01F
75⍀
29
OUTPUT 04
9
INPUT 04
AGND
10
28
27
AVEE
AGND
0.01F
75⍀
26
OUTPUT 05
11
12
INPUT 05
AGND
25
24
AVCC
AGND
0.01F
75⍀
23
OUTPUT 06
13
14
22
21
INPUT 06
AGND
AVEE
AGND
0.01F
75⍀
20
19
OUTPUT 07
AVCC
15
16
INPUT 07
AGND
AVCC
AVCC
0.01F
0.01F
0.01F
18
17
59
57
AVCC
AVEE
DATA OUT
DATA IN
AVEE
P2-5
P2-4
P2-2
P2-3
P2-1
P2-6
62 61 60 58 56 55 54 53 52 51 50 49 48
R25
20k⍀
DVCC
NC
SERIAL MODE
JUMP
NC = NO CONNECT
Figure 46. Evaluation Board Schem atic
REV. 0
–21–
AD8108/AD8109
Figure 47. Com ponent Side Silkscreen
Figure 48. Board Layout (Com ponent Side)
–22–
REV. 0
AD8108/AD8109
Figure 49. Board Layout (Signal Layer)
Figure 50. Board Layout (Power Plane)
REV. 0
–23–
AD8108/AD8109
Figure 51. Board Layout (Bottom Layer)
Optimized for video applications, all signal inputs and outputs
are terminated with 75 Ω resistors. Stripline techniques are used
to achieve a characteristic impedance on the signal input and
output lines also of 75 Ω. Figure 52 shows a cross-section of one
of the input or output tracks along with the arrangement of the
PCB layers. It should be noted that unused regions of the four
layers are filled up with ground planes. As a result, the input
and output traces, in addition to having controlled impedances,
are well shielded.
T he three power supply pins AVCC, DVCC and AVEE should
be connected to good quality, low noise, ±5 V supplies. Where
the same ±5 V power supplies are used for analog and digital,
separate cables should be run for the power supply to the evalu-
ation board’s analog and digital power supply pins.
As a general rule, each power supply pin (or group of adjacent
power supply pins) should be locally decoupled with a 0.01 µF
capacitor. If there is a space constraint, it is more important to
decouple analog power supply pins before digital power supply
pins. A 0.1 µF capacitor, located reasonably close to the pins,
can be used to decouple a number of power supply pins. Finally
a 10 µF capacitor should be used to decouple power supplies as
they come on to the board.
w = 0.008"
(0.2mm)
TOP LAYER
t = 0.00135" (0.0343mm)
b = 0.024"
(0.6mm)
a = 0.008"
(0.2mm)
Contr olling the Evaluation Boar d fr om a P C
SIGNAL LAYER
POWER LAYER
BOTTOM LAYER
T he evaluation board include Windows-based control software
and a custom cable that connects the board’s digital interface to
the printer port of the PC. T he wiring of this cable is shown in
Figure 53. T he software requires Windows 3.1 or later to oper-
ate. T o install the software, insert the disk labeled “Disk # 1 of
2” in the PC and run the file called SET UP.EXE. Additional
installation instructions will be given on-screen. Before begin-
ning installation, it is important to terminate any other Windows
applications that are running.
h = 0.011325"
(0.288mm)
Figure 52. Cross Section of Input and Output Traces
T he board has 16 BNC type connectors: eight inputs and eight
outputs. T he connectors are arranged in two crescents around
the device. As can be seen from Figure 49, this results in all
eight input signal traces and all eight signal output traces having
the same length. T his is useful in tests such as All-H ostile
Crosstalk where the phase relationship and delay between sig-
nals needs to be maintained from input to output.
–24–
REV. 0
AD8108/AD8109
MOLEX 0.100" CENTER
CRIMP TERMINAL HOUSING
can be connected with one or more outputs by simply clicking
on the appropriate radio buttons in the 8 × 8 on-screen array.
Each time a button is clicked on, the software automatically
sends and latches the required 32-bit data stream to the evalua-
tion board. An output can be turned off by clicking the appro-
priate button in the Off column. T o turn off all outputs, click on
RESET.
D-SUB 25 PIN (MALE)
RESET
1
1
14
CLK
CE
UPDATE
DATA IN
DGND
6
T he software offers volatile and nonvolatile storage of configu-
rations. For volatile storage, up to two configurations can be
stored and recalled using the Memory 1 and Memory 2 Buffers.
T hese function in an identical fashion to the memory on a
pocket calculator. For nonvolatile storage of a configuration, the
Save Setup and Load Setup functions can be used. T his stores
the configuration as a data file on disk.
MOLEX
TERMINAL HOUSING
D-SUB-25
SIGNAL
2
3
4
5
6
25
3
1
4
5
2
6
CE
RESET
UPDATE
25
13
DATA IN
CLK
DGND
O ver shoot on P C P r inter P or ts’ D ata Lines
EVALUATION BOARD
PC
T he data lines on some printer ports have excessive overshoot.
Overshoot on the pin that is used as the serial clock (Pin 6 on
the D-Sub-25 connector) can cause communication problems.
T his overshoot can be eliminated by connecting a capacitor
from the CLK line on the evaluation board to ground. A pad
has been provided on the solder-side of the evaluation board to
allow this capacitor to be soldered into place. Depending upon
the overshoot from the printer port, this capacitor may need to
be as large as 0.01 µF.
Figure 53. Evaluation Board-PC Connection Cable
When you launch the crosspoint control software, you will be
asked to select the printer port you are using. Most modern PCs
have only one printer port, usually called LPT 1. However, some
laptop computers use the PRN port.
Figure 54 shows the main screen of the control software in its
initial reset state (all outputs off). Using the mouse, any input
AD8108/AD8109
Figure 54. Evaluation Board Control Panel
–25–
REV. 0
AD8108/AD8109
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
80-Lead P lastic TQFP
(ST-80A)
0.559 (14.20)
0.543 (13.80)
0.476 (12.10)
0.469 (11.90)
0.063 (1.60)
MAX
0.030 (0.75)
0.020 (0.50)
80
1
61
60
SEATING
PLANE
TOP VIEW
(PINS DOWN)
20
0.003 (0.08)
MAX
41
40
21
0.006 (0.15)
0.002 (0.05)
0.011 (0.27)
0.007 (0.17)
0.020 (0.50)
BSC
0.057 (1.45)
0.053 (1.35)
–26–
REV. 0
–27–
–28–
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