AD8023 [ADI]
High Current Output, Triple Video Amplifier; 高电流输出，三路视频放大器
| 型号： | AD8023 |
| 厂家： | 
ADI |
| 描述： | High Current Output, Triple Video Amplifier |
| 文件： | 总12页 (文件大小：559K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Current Output,
Triple Video Amplifier
a
AD8023
FEATURES
Drives 13 V Output
PIN CONFIGURATION
14-Lead SOIC
Drives Unlimited Capacitive Load
High Current Output Drive: 70 mA
Excellent Video Specifications (RL = 150 ꢀ)
Gain Flatness 0.1 dB to 10 MHz
0.06% Differential Gain Error
0.02ꢁ Differential Phase Error
Power
Operates on ꢂ2.5 V to ꢂ7.5 V Supply
10.0 mA/Amplifier Max Power Supply Current
High Speed
1
2
3
4
5
6
7
14
OUT 2
DISABLE 1
DISABLE 2
DISABLE 3
13 –IN 2
12 +IN 2
–V
+V
S
AD8023
11
10
9
S
+IN 3
+IN 1
–IN 1
–IN 3
OUT 1
8
OUT 3
250 MHz Unity Gain Bandwidth (3 dB)
1200 V/ꢃs Slew Rate
Fast Settling Time of 35 ns (0.1%)
High Speed Disable Function
Turn-Off Time 30 ns
Easy to Use
200 mA Short Circuit Current
Output Swing to 1 V of Rails
The AD8023 uses maximum supply current of 10.0 mA per
amplifier and runs on 2.5 V to 7.5 V power supply. The
outputs of each amplifier swing to within one volt of either
supply rail to easily accommodate video signals. The AD8023
is unique among current feedback op amps by virtue of its large
capacitive load drive with a small series resistor, while still
achieving rapid settling time. For instance, it can settle to 0.1% in
35 ns while driving 300 pF capacitance.
APPLICATIONS
LCD Displays
Video Line Driver
Broadcast and Professional Video
Computer Video Plug-In Boards
Consumer Video
The bandwidth of 250 MHz along with a 1200 V/µs slew rate
make the AD8023 useful in high speed applications requiring
a single +5 V or dual power supplies up to 7.5 V. Further-
more, the AD8023 contains a high speed disable function for
each amplifier in order to power down the amplifier or high
impedance the output. This can then be used in video multi-
plexing applications. The AD8023 is available in the indus-
trial temperature range of –40°C to +85°C.
RGB Amplifier in Component Systems
PRODUCT DESCRIPTION
The AD8023 is a high current output drive, high voltage output
drive, triple video amplifier. Each amplifier has 70 mA of output
current and is optimized for driving large capacitive loads. The
amplifiers are current feedback amplifiers and feature gain
flatness of 0.1 dB to 10 MHz while offering differential gain and
phase error of 0.06% and 0.02°.
V
V
IN
IN
V
O
V
O
Figure 2. Output Swing Voltage,
RL = 150 Ω; VS = 7.5 V, G = +10
Figure 1. Pulse Response Driving a Large Load Capacitor,
CL = 300 pF, G = +3, RF = 750 Ω, RS = 16.9 Ω, RL = 10 kΩ
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(@ T = +25ꢁC, V = ꢂ7.5, CLOAD = 10 pF, RLOAD = 150 ꢀ, unless otherwise noted)
AD8023–SPECIFICATIONS
A
S
Model
AD8023A
Typ
Conditions
VS
Min
Max
Units
DYNAMIC PERFORMANCE
Bandwidth (3 dB)
Bandwidth (0.1 dB)
Slew Rate
Settling Time to 0.1%
RFB = 750 Ω No Peaking, G = +3
No Peaking, G = +3
5 V Step
125
7
1200
MHz
MHz
V/µs
0 V to 6 V (6 V Step)
C
LOAD = 300 pF
RLOAD > 1 kΩ, RFB = 750 Ω
TA = +25°C to +70°C, RS = 16.9 Ω
30
ns
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, RL = 150 Ω, VO = 2 p-p
f = 10 kHz
–72
2.0
dBc
Input Voltage Noise
Input Current Noise
Differential Gain (RL = 150 Ω)
Differential Phase (RL = 150 Ω)
nV/√Hz
pA/√Hz
%
f = 10 kHz (–IIN)
14
f = 3.58 MHz, G = +2, RFB = 750 Ω
f = 3.58 MHz, G = +2, RFB = 750 Ω
0.06
0.02
Degrees
DC PERFORMANCE
Input Offset Voltage
Offset Drift
Input Bias Current (–)
Input Bias Current (+)
Open-Loop Transresistance
T
MIN to TMAX
MIN to TMAX
–5
2
2
15
5
111
111
5
mV
µV/°C
µA
T
–45
–25
67
45
25
TMIN to TMAX
µA
kΩ
kΩ
TMIN to TMAX
50
INPUT CHARACTERISTICS
Input Resistance
+Input
–Input
TMIN to TMAX
TMIN to TMAX
100
75
2
kΩ
Ω
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Input Offset Voltage
–Input Current
pF
V
6.0
50
56
0.2
5
dB
µA/V
+Input Current
µA/V
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 1 kΩ
VOL–VEE
0.8
0.8
1.0
1.0
70
300
1000
1.0
1.0
1.3
1.3
V
V
CC–VOH
V
RL = 150 Ω
VOL–VEE
CC–VOH
V
V
mA
mA
pF
V
Output Current
Short-Circuit Current
Capacitive Load Drive
50
MATCHING CHARACTERISTICS
Dynamic
Crosstalk
G = +2, f = 5 MHz
70
dB
DC
Input Offset Voltage
–Input Bias Current
–5
–10
0.3
3
5
10
mV
µA
POWER SUPPLY
Operating Range
Single Supply
Dual Supply
+4.2
2.1
+15
7.5
V
V
mA
mA
Quiescent Current/Amplifier
6.2
7.0
10.0
4.0
TMIN to TMAX
Power-Down
1.3
mA
–2–
REV. A
AD8023
Model
AD8023A
Typ
Conditions
VS
Min
Max
Units
POWER SUPPLY (Continued)
Power Supply Rejection Ratio
Input Offset Voltage
VS = 2.5 V to 7.5 V
dB
54
76
0.03
0.07
dB
–Input Current
+Input Current
µA/V
µA/V
DISABLE CHARACTERISTICS
Off Isolation
Off Output Capacitance
Turn-On Time
Turn-Off Time
f = 6 MHz
G = +1
–70
12
50
30
dB
pF
ns
ns
V
RL = 150 Ω
Switching Threshold
VTH – VEE
1.6
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Maximum Power Dissipation
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5 V Total
Internal Power Dissipation
Small Outline (R) . . . . 1.0 Watts (Observe Derating Curves)
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS
Differential Input Voltage . . . . . . . . . . . . . . . . 3 V (Clamped)
Output Voltage Limit
Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+VS
Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Output Short Circuit Duration
The maximum power that can be safely dissipated by the AD8023
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for the plastic encapsulated
parts is determined by the glass transition temperature of the
plastic, about 150°C. Temporarily exceeding this limit may
cause a shift in parametric performance due to a change in the
stresses exerted on the die by the package. Exceeding a junction
temperature of 175°C for an extended period can result in
device failure.
. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range
R Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD8023A . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
While the AD8023 is internally short circuit protected, this may
not be enough to guarantee that the maximum junction temper-
ature is not exceeded under all conditions. To ensure proper
operation, it is important to observe the derating curves.
It must also be noted that in (noninverting) gain configurations
(with low values of gain resistor), a high level of input overdrive
can result in a large input error current, which may result in a
significant power dissipation in the input stage. This power
must be included when computing the junction temperature rise
due to total internal power.
ORDERING GUIDE
2.5
T
= +150ꢁC
J
Temperature
Range
Package
Description
Package
Option
Model
2.0
1.5
1.0
0.5
AD8023AR
AD8023AR-
REEL
AD8023AR-
REEL7
–40°C to +85°C 14-Lead Plastic SOIC R-14
–40°C to +85°C 13" Tape and Reel
R-14
–40°C to +85°C 7" Tape and Reel
R-14
14-LEAD SOIC
AD8023ACHIPS –40°C to +85°C Die
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ꢁC
Figure 3. Maximum Power Dissipation vs. Ambient
Temperature
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8023 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–3–
REV. A
AD8023
METALIZATION PHOTO
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
+IN
5
–IN1
6
DISABLE 3
3
+VS
4
DISABLE 2
2
DISABLE 1
1
7
OUT 1
0.0634
(1.61)
14
OUT 2
8
OUT 3
–IN 2
13
–VS
11
+IN 2
12
–IN3
9
+IN 3
10
0.0713
(1.81)
Typical Performance Characteristics
8
7
6
5
4
3
2
1
0
14
13
12
11
10
9
V
= ꢂ7.5V
S
8
7
6
2
3
4
5
6
7
8
10
100
1k
10k
LOAD RESISTANCE – ꢀ
SUPPLY VOLTAGE – ꢂVolts
Figure 4. Input Common-Mode Voltage Range vs.
Supply Voltage
Figure 5. Output Voltage Swing vs. Load Resistance
REV. A
–4–
AD8023
35
30
25
20
T
= +25ꢁC
A
25
20
15
10
5
–I
B
15
10
+I
B
5
0
0
100
–50–40 –30–20–10
0
10 20 30 40 50 60 70 80 90
1
2
4
6
8
3
5
7
9
TEMPERATURE – ꢁC
SUPPLY VOLTAGE – ꢂVolts
Figure 9. Input Bias Current vs. Temperature
Figure 6. Total Supply Current vs. Supply Voltage
1
16
T
= +25ꢁC
A
14
12
10
8
0
V = ꢂ2.5V
S
SWING
NO LOAD
V
= ꢂ7.5V
S
SWING
= 150ꢀ
R
L
–1
–2
6
4
2
2
3
4
5
6
7
8
–20
70
–40 –30
–10
0
10 20 30 40 50 60
TEMPERATURE – ꢁC
80 90
SUPPLY VOLTAGE – ꢂVolts
Figure 10. Input Offset Voltage vs. Temperature
Figure 7. Output Voltage Swing vs. Supply Voltage
24
G = +2
100
V
= ꢂ7.5V
S
22
31
V
= ꢂ2.5V
20
18
16
S
10
3.1
1
V
= ꢂ7.5V
S
V
= ꢂ2.5V
S
14
0.31
0.1
12
10
–40–30–20
0
20
40 50 60 70 80
100
90
–50
–10
10
30
10
FREQUENCY – MHz
1
100
300
TEMPERATURE – ꢁC
Figure 11. Closed-Loop Output Resistance vs. Frequency
Figure 8. Total Supply Current vs. Temperature
REV. A
–5–
AD8023
200
90
80
70
200
100
R
R
R
100
V
CM
– I NOISE
V
= ꢂ7.5V
S
+I NOISE
60
50
40
R
V
= ꢂ2.5V
S
10
10
30
20
10
0
V NOISE
1
100
200
10
FREQUENCY – MHz
1
0.1
0
100
1
10
FREQUENCY – kHz
Figure 12. Input Current and Voltage Noise vs. Frequency
Figure 15. Common-Mode Rejection vs. Frequency
70
450
V
= ꢂ7.5V
S
60
V = ꢂ7.5V (+PSRR)
S
V
= ꢂ2.5V (+PSRR)
S
400
350
50
40
30
SOURCE
SINK
V
= ꢂ2.5V (–PSRR)
S
20
10
300
250
V
= ꢂ7.5V (–PSRR)
S
0
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100
1
10
100
TEMPERATURE – ꢁC
FREQUENCY – MHz
Figure 13. Short Circuit Current vs. Temperature
Figure 16. Power Supply Rejection Ratio vs. Frequency
10k
0
G = +1
V
V
= ꢂ7.5V
= 2V p-p
S
–10
–20
–30
–40
–50
–60
–70
–80
–90
O
G = +1
S
1k
V
= ꢂ7.5V
100
10
2ND
3RD
10
FREQUENCY – Hz
1
10
100
1
100
200
FREQUENCY – MHz
Figure 14. Output Resistance vs. Frequency,
Disabled State
Figure 17. Harmonic Distortion vs. Frequency, RL = 150 Ω
REV. A
–6–
AD8023
100k
10k
1k
V
IN
100
10
V
O
1k
10k
100k
1M
10M
100M
1G
FREQUENCY – Hz
Figure 18. Open-Loop Transimpedance vs. Frequency
Figure 21. Small Signal Pulse Response, Gain = +1,
(RF = 2 kΩ, RL = 150 Ω, VS = 7.5 V)
1600
1600
G = –1
G = +2
1400
1400
G = –1
G = +2
1200
1200
G = +1
1000
1000
G = +10
800
600
400
200
0
G = +1
G = +10
800
600
400
200
0
2
3
4
5
6
7
8
1
3
4
5
6
0
2
SUPPLY VOLTAGE – V
OUTPUT VOLTAGE STEP – V p-p
Figure 22. Maximum Slew Rate vs. Supply Voltage
Figure 19. Slew Rate vs. Output Step Size
V
V
IN
IN
V
O
V
O
Figure 20. Large Signal Pulse Response,
Gain = +1, (RF = 2 kΩ, RL = 150 Ω, VS = 7.5 V)
Figure 23. Large Signal Pulse Response,
Gain = +10, (RF = 274 Ω, RL = 150 Ω, VS = 7.5 V)
REV. A
–7–
AD8023
+2
+1
GAIN
+1
0
0
V
= ꢂ7.5V
GAIN
S
V
= ꢂ7.5V
S
–1
–1
–2
–2
V
= ꢂ2.5V
V = ꢂ2.5V
S
S
–3
–4
–5
V
= ꢂ7.5V
PHASE
G = +1
S
V
= ꢂ7.5V
S
PHASE
G = +10
–3
–4
0
0
V
= ꢂ2.5V
S
–5
–6
–7
–90
–180
V
= ꢂ2.5V
S
–90
–6
–7
–8
R
= 150ꢀ
L
R
= 150ꢀ
L
–8
–9
–180
1
10
FREQUENCY – MHz
100
1
10
FREQUENCY – MHz
100
500
500
Figure 24. Closed-Loop Gain and Phase vs. Frequency,
Figure 27. Closed-Loop Gain and Phase vs. Frequency,
G = +10, RL = 150 Ω
G = –1, RL = 150 Ω
+1
0
GAIN
–1
–2
V
= ꢂ2.5V
S
–3
V
IN
V
= ꢂ7.5V
0
S
–4
–5
PHASE
–90
–180
–6
–7
V
O
–8
–9
400
1
10
FREQUENCY – MHz
100
Figure 25. Closed-Loop Gain and Phase vs. Frequency,
Figure 28. Small Signal Pulse Response,
G = +1, RL = 150 Ω
Gain = +10, (RF = 274 Ω, RL = 150 Ω, VS = 7.5 V)
V
V
IN
IN
V
O
V
O
Figure 26. Large Signal Pulse Response,
Figure 29. Small Signal Pulse Response,
Gain = –1, (RF = 750 Ω, RL = 150 Ω, VS = 7.5 V)
Gain = –1, (RF = 750 Ω, RL = 150 Ω, VS = 7.5 V)
REV. A
–8–
AD8023
+1
G
GAIN
ACL ꢁ
0
1+ SCT (RF + Gn rin)
–1
where:
CT = transcapacitance ꢂ 1 pF
V
= ꢂ7.5V
RF = feedback resistor
S
–2
–3
–4
–5
G = ideal closed loop gain
V
= ꢂ2.5V
S
R
R
G
PHASE
1+
0
Gn =
F = noise gain
rin = inverting input resistance ꢂ 150 Ω
ACL = closed loop gain
–6
–7
–90
–180
G = –10
R
= 150ꢀ
V
= ꢂ2.5V
The –3 dB bandwidth is determined from this model as:
L
S
–8
–9
1
f3 ꢁ
2 π CT (RF + Gn rin)
1
10
FREQUENCY – MHz
100
500
This model will predict –3 dB bandwidth to within about
10% to 15% of the correct value when the load is 150 Ω and
VS = 7.5 V. For lower supply voltages there will be a slight
decrease in bandwidth. The model is not accurate enough to
predict either the phase behavior or the frequency response
peaking of the AD8023.
Figure 30. Closed-Loop Gain and Phase vs. Frequency,
G = –10, RL = 150 Ω
General
The AD8023 is a wide bandwidth, triple video amplifier that
offers a high level of performance on less than 9.0 mA per
amplifier of quiescent supply current. The AD8023 achieves
bandwidth in excess of 200 MHz, with low differential gain and
phase errors and high output current making it an efficient video
amplifier.
It should be noted that the bandwidth is affected by attenuation
due to the finite input resistance. Also, the open-loop output
resistance of about 6 Ω reduces the bandwidth somewhat when
driving load resistors less than about 150 Ω. (Bandwidths will
be about 10% greater for load resistances above a couple
hundred ohms.)
The AD8023’s wide phase margin coupled with a high output
short circuit current make it an excellent choice when driving
any capacitive load up to 300 pF.
Table I. –3 dB Bandwidth vs. Closed-Loop Gain and Feedback
Resistor, RL = 150 ꢀ (SOIC)
It is designed to offer outstanding functionality and performance
at closed-loop inverting or noninverting gains of one or greater.
VS – Volts
Gain
RF – Ohms
BW – MHz
7.5
+1
+2
+10
–1
–10
+1
+2
+10
–1
–10
2000
750
300
750
250
2000
1000
300
460
240
50
150
60
250
90
30
Choice of Feedback and Gain Resistors
Because it is a current feedback amplifier, the closed-loop band-
width of the AD8023 may be customized using different values
of the feedback resistor. Table I shows typical bandwidths at
different supply voltages for some useful closed-loop gains when
driving a load of 150 Ω.
2.5
The choice of feedback resistor is not critical unless it is desired
to maintain the widest, flattest frequency response. The resistors
recommended in the table (chip resistors) are those that will
result in the widest 0.1 dB bandwidth without peaking. In
applications requiring the best control of bandwidth, 1%
resistors are adequate. Resistor values and widest bandwidth
figures are shown. Wider bandwidths than those in the table can
be attained by reducing the magnitude of the feedback resistor
(at the expense of increased peaking), while peaking can be
reduced by increasing the magnitude of the feedback resistor.
750
250
95
50
Driving Capacitive Loads
When used in combination with the appropriate feedback
resistor, the AD8023 will drive any load capacitance without
oscillation. The general rule for current feedback amplifiers is
that the higher the load capacitance, the higher the feedback
resistor required for stable operation. Due to the high open-loop
transresistance and low inverting input current of the AD8023,
the use of a large feedback resistor does not result in large closed-
loop gain errors. Additionally, its high output short circuit current
makes possible rapid voltage slewing on large load capacitors.
Increasing the feedback resistor is especially useful when driving
large capacitive loads as it will increase the phase margin of the
closed-loop circuit. (Refer to the Driving Capacitive Loads
section for more information.)
For the best combination of wide bandwidth and clean pulse
response, a small output series resistor is also recommended.
Table II contains values of feedback and series resistors which
result in the best pulse responses. Figure 28 shows the AD8023
driving a 300 pF capacitor through a large voltage step with
virtually no overshoot. (In this case, the large and small signal
pulse responses are quite similar in appearance.)
To estimate the –3 dB bandwidth for closed-loop gains of 2 or
greater, for feedback resistors not listed in the following table,
the following single pole model for the AD8023 may be used:
REV. A
–9–
AD8023
R
F
1.0ꢃF
0.1ꢃF
+V
4
S
R
V
IN
G
15ꢀ
AD8023
V
O
1.0ꢃF
0.1ꢃF
R
S
C
11
V
L
IN
R
T
–V
S
V
O
Figure 31. Circuit for Driving a Capacitive Load
Table II. Recommended Feedback and Series Resistors vs.
Capacitive Load and Gain
Figure 33. 50% Overload Recovery, Gain = +10,
(RF = 300 Ω, RL = 1 kΩ, VS = 7.5 V)
RS – Ohms
G = 2
As noted in the warning under Maximum Power Dissipation, a
high level of input overdrive in a high noninverting gain circuit
can result in a large current flow in the input stage. Though this
current is internally limited to about 30 mA, its effect on the
total power dissipation may be significant.
CL – pF
RF – Ohms
G ≥ 3
20
50
100
200
300
≥500
2k
2k
2k
3k
3k
3k
0
0
10
15
10
10
10
10
15
10
10
10
Disable Mode Operation
Pulling the voltage on any one of the Disable pins about 1.6 V up
from the negative supply will put the corresponding amplifier
into a disabled, powered down, state. In this condition, the
amplifier’s quiescent current drops to about 1.3 mA, its output
becomes a high impedance, and there is a high level of isolation
from input to output. In the case of a gain of two line driver for
example, the impedance at the output node will be about the
same as for a 1.5 kΩ resistor (the feedback plus gain resistors)
in parallel with a 12 pF capacitor.
V
IN
Leaving the Disable pin disconnected (floating) will leave the
corresponding amplifier operational, in the enabled state. The
input impedance of the disable pin is about 25 kΩ in parallel
with a few picofarads. When driven to 0 V, with the negative
supply at –7.5 V, about 100 µA flows into the disable pin.
V
O
When the disable pins are driven by complementary output
CMOS logic, on a single 5 V supply, the disable and enable
times are about 50 ns. When operated on dual supplies, level
shifting will be required from standard logic outputs to the
Disable pins. Figure 33 shows one possible method, which
results in a negligible increase in switching time.
Figure 32. Pulse Response Driving a Large Load Capacitor.
CL = 300 pF, G = +3, RF = 750 Ω, RS = 16.9 Ω, RL = 10 kΩ
Overload Recovery
The three important overload conditions are: input common-
mode voltage overdrive, output voltage overdrive, and input
current overdrive. When configured for a low closed-loop gain,
this amplifier will quickly recover from an input common-mode
voltage overdrive; typically in under 25 ns. When configured for
a higher gain, and overloaded at the output, the recovery time
will also be short. For example, in a gain of +10, with 50%
overdrive, the recovery time of the AD8023 is about 20 ns (see
Figure 31). For higher overdrive, the response is somewhat
slower. For 100% overdrive, (in a gain of +10), the recovery
time is about 80 ns.
+5
V
+7.5V
I
15kꢀ
4kꢀ
TO DISABLE PIN
10kꢀ
–7.5V
V
V
HIGH => AMPLIFIER ENABLED
LOW => AMPLIFIER DISABLED
I
I
Figure 34. Level Shifting to Drive Disable Pins on Dual
Supplies
The AD8023’s input stages include protection from the large
differential input voltages that may be applied when disabled.
Internal clamps limit this voltage to about 3 V. The high input to
output isolation will be maintained for voltages below this limit.
REV. A
–10–
AD8023
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Plastic SOIC
(R-14)
0.3444 (8.75)
0.3367 (8.55)
14
1
8
7
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0098 (0.25)
0.0040 (0.10)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
0.0138 (0.35)
REV. A
–11–
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