AD8024 [ADI]
Quad 350 MHz 24 V Amplifier; 四核350 MHz的24 V放大器
| 型号： | AD8024 |
| 厂家： | 
ADI |
| 描述： | Quad 350 MHz 24 V Amplifier |
| 文件： | 总12页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad 350 MHz
24 V Amplifier
a
AD8024
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Quad High-Speed Current Feedback Amplifier
with Disable
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–3 dB Bandwidth 350 MHz @ G = 1
Slew Rate 2400 V/ꢀs, VS = ꢁ12 V
Drives High Capacitive Loads
Settling Time to 0.1% in 35 ns; 300 pF Load, 6 V Step
Settling Time to 0.1% in 18 ns; 5 pF Load, 2 V Step
Low Power
Operates on +5 V to ꢁ12 V (+24 V)
4 mA/Amplifier Supply Current
Excellent Video Specs (RL = 150 ꢂ, G = 2)
Gain Flatness 0.1 dB to 70 MHz
0.04% Differential Gain
V
CC
V
EE
AD8024AR
DIS
DGND
0.09ꢃ Differential Phase
Crosstalk –58 dB @ 5 MHz
THD –72 dBc @ 5 MHz
Outstanding DC Accuracy
VOFFSET is 2 mV (Typ)
IBIAS is 3 ꢀA (Max)
16-Lead SOIC Package
APPLICATIONS
LCD Column Drivers
High-Performance Test Equipment
Video Line Driver
ATE
1V
20ns
V
IN
PRODUCT DESCRIPTION
The AD8024 is a low settling time, high-speed, high output
voltage quad current feedback operational amplifier. Manu-
factured on ADI’s proprietary XFHV high-speed bipolar process,
the AD8024 is capable of driving to within 1.3 V of its 24 V
supply rail. Each amplifier has high-output current capability
and can drive high capacitive loads.
V
OUT
2V
The AD8024 outputs settle to 0.1% within 35 ns into a 300 pF
load (6 V swing). The AD8024 can run on both +5 V as well as
12 V rails. Slew rate on 12 V supplies is 2400 V/µs. DC
Characteristics are outstanding with typical 2 mV offset, and
3 µA maximum input bias current. High-speed disable pin
allows the AD8024 to be shut down when not in use. Low-power
operation is assured with the 4 mA/Amplifier supply current draw.
Figure 1. Pulse Response Driving a Large Load Capaci-
tance, CL = 300 pF, G = 3, RFB = 2.32 kΩ, RS = 10.5 Ω,
RL = 1 kΩ, VS = 7.5 V
The high voltage drive capability, low settling time, high slew
rate, low offset, and high bandwidth make the AD8024 ideally
suited as an LCD column driver, a video line driver, and for
use in high-performance test equipment.
The AD8024 is available in a 16-lead SOIC package.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(@ T = 25ꢃC, V = ꢁ7.5 V, CLOAD = 10 pF, RL = 150 ꢂ, unless otherwise noted)
AD8024–SPECIFICATIONS
A
S
Model
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Bandwidth (3 dB)
Bandwidth (0.1 dB)
Slew Rate
Settling Time to 0.1%
R
FB = 800 Ω, No Peaking, G = 3
160
370
200
25
390
30
MHz
MHz
V/µs
ns
No Peaking, G = 3
6 V Step, G = 3, CLOAD = 300 pF
TA = 25°C to 85°C, 3 V (6 V Step)
CLOAD = 300 pF, RS = 10.5 Ω, RLOAD > 1 kΩ,
R
FB = 2.32 kΩ
1 V (2 V Step), CLOAD = 5 pF,
18
ns
RS = 0 Ω, RLOAD > 1 kΩ, RFB = 750 kΩ
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, RL = 1 kΩ
fC = 5 MHz, RL = 150 Ω
f = 10 kHz
–72
–67
3
dBc
dBc
Input Voltage Noise
Input Current Noise
Differential Gain (RL = 150 Ω)
Differential Phase (RL = 150 Ω)
nV/√Hz
pA/√Hz
%
f = 10 kHz (–IIN)
8
f = 3.58 MHz, G = 2
f = 3.58 MHz, G = 2
0.04
0.09
Degrees
DC PERFORMANCE
Input Offset Voltage
Offset Drift
+Input Bias Current
–Input Bias Current
Open-Loop Transresistance
T
MIN to TMAX
2
5
mV
µV/°C
µA
1.5
1
7.5
3
1
µA
0.850
1.2
0.840
MΩ
MΩ
TMIN to TMAX
INPUT CHARACTERISTICS
Input Resistance
+Input
–Input
T
T
MIN to TMAX
MIN to TMAX
1
135
2
MΩ
Ω
Input Capacitance
Input Common-Mode Voltage
Common-Mode Rejection Ratio
Input Offset Voltage
–Input Current
pF
V
–VS + 1.2
62
+VS – 2
66
0.2
1
dB
µA/V
µA/V
+Input Current
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 1 kΩ
VOL – VEE
VCC – VOH
VOL – VEE
VCC – VOH
Error <3%, R1 = 50 Ω
0.8
1.1
1.0
1.3
50
300
1000
1.0
1.3
1.35
1.55
V
V
V
RL = 150 Ω
V
Linear Output Current
Max Dynamic Output Current
Capacitive Load Drive
35
mA
mA
pF
MATCHING CHARACTERISTICS
Dynamic
Crosstalk (Worst Between Any 2)
DC
G = 2, f = 5 MHz
–58
dB
Input Offset Voltage Match
Input Current Match
0.4
0.1
1.5
2.0
mV
µA
POWER SUPPLY
Operating Range
Single Supply
Dual Supply
5
24
12
17
V
V
mA
mA
mA
2.5
Total Quiescent Current
16
19.5
0.5
TMIN to TMAX
Disable = HIGH
1
Power Supply Rejection Ratio
Input Offset Voltage
–Input Current
VS = 6.5 V to 8.5 V
64
70
0.03
0.07
dB
µA/V
µA/V
+Input Current
REV. B
–2–
AD8024
Model
Conditions
Min
Typ
Max
Unit
DISABLE CHARACTERISTICS
Off Isolation
Off Output Impedance
Turn-On Time
Turn-Off Time
f = 6 MHz
49
20
25
20
1.6
dB
pF
ns
ns
V
Switching Threshold
VTH – DGND
1.3
1.9
OPERATING TEMPERATURE RANGE
–40
+85
°C
Specifications subject to change without notice.
Output Short Circuit Limit
ABSOLUTE MAXIMUM RATINGS*
The AD8024’s internal short circuit limitation is not sufficient
to protect the device in the event of a direct short circuit be-
tween a video output and a power supply voltage rail (VCC or
VEE). Temporary short circuits can reduce an output’s ability to
source or sink current and therefore impact the device’s ability
to drive a load. Short circuits of extended duration can cause
metal lines to fuse open, rendering the device nonfunctional.
Supply Voltage VCC – VEE . . . . . . . . . . . . . . . . . . . 26 V Total
Internal Power Dissipation
Small Outline (R) . . . . . 1.0 Watts (Observe Derating Curve)
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . VS
Differential Input Voltage . . . . . . . . . . . . . . . 3 V (Clamped)
Output Voltage Limit
Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS
Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curve
Storage Temperature Range
R Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range
To prevent these problems, it is recommended that a series
resistor be placed as close as possible to the outputs. This will
serve to substantially reduce the magnitude of the fault currents
and protect the outputs from damage caused by intermittent
short circuits. This may not be enough to guarantee that the
maximum junction temperature (150°C) is not exceeded under
all conditions. To ensure proper operation, it is necessary to
observe the maximum power derating curve in Figure 2.
AD8024A . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
It must also be noted that in (noninverting) gain configurations
(with low values of gain resistor), a high level of input overdrive
can result in a large input error current, which may then result
in a significant power dissipation in the input stage. This power
must be included when computing the junction temperature rise
due to total internal power.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
2.5
Model
T
= 150ꢃC
J
AD8024AR-16
–40°C to +85°C 16-Lead Narrow-Body R-16A
SOIC
2.0
1.5
1.0
0.5
Maximum Power Dissipation
The maximum power that can be safely dissipated by the AD8024
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for the plastic encapsulated
parts is determined by the glass transition temperature of the
plastic, about 150°C. Temporarily exceeding this limit may
cause a shift in parametric performance due to a change in the
stresses exerted on the die by the package. Exceeding a junction
temperature of 175°C for an extended period can result in
device failure.
16-LEAD SOIC
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ꢃC
Figure 2. Maximum Power Dissipation vs. Ambient
Temperature
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8024 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD8024
–Typical Performance Characteristics
25
20
15
10
5
12
T
= 25ꢃC
A
T
= 25ꢃC
A
10
8
–V
CM
6
+V
CM
4
2
0
0
0
2
4
6
8
10
12
14
2
4
6
8
10
12
SUPPLY VOLTAGE – ꢁVolts
SUPPLY VOLTAGE – ꢁVolts
Figure 6. Total Supply Current vs. Supply Voltage
Figure 3. Input Common-Mode Voltage Range vs.
Supply Voltage
24
22
20
7.0
–SWING
V
= ꢁ7.5V
S
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
+SWING
V
= ꢁ12V
S
18
16
14
12
V
= ꢁ7.5V
S
10
–60
–40
–20
0
20
40
60
80
100
10
100
1k
10k
TEMPERATURE – ꢃC
LOAD RESISTANCE – ꢂ
Figure 7. Total Supply Current vs. Temperature
Figure 4. Output Voltage Swing vs. Load Resistance
25
3
T
= 25ꢃC
A
V
= ꢁ7.5V
SWING
S
(NO LOAD)
20
15
10
5
2
–I
B
SWING
(R = 150ꢂ)
L
1
0
+I
B
–1
–60
0
2
3
4
5
6
7
8
9
10 11
12
13
–40
–20
0
20
40
60
80
100
SUPPLY VOLTAGE – ꢁVolts
TEMPERATURE – ꢃC
Figure 5. Output Voltage Swing vs. Supply Voltage
Figure 8. Input Bias Current vs. Temperature
REV. B
–4–
AD8024
10M
1M
2.5
2.0
1.5
1.0
0.5
V
= ꢁ7.5V
S
V
= ꢁ7.5V
S
100k
10k
1k
V
= ꢁ12V
S
100
10
1
0.01
0.1
1
10
100
1000
–60
–40
–20
0
20
40
60
80
100
FREQUENCY – MHz
TEMPERATURE – ꢃC
Figure 12. Open-Loop Transimpedance vs. Frequency,
RL = 150 Ω
Figure 9. Input Offset Voltage vs. Temperature
100
100
90
V
= ꢁ7.5V
S
80
70
60
50
40
30
20
10
0
V
= ꢁ12V
S
V
= ꢁ7.5V
S
+I
NOISE
10
10
R
–I
NOISE
R
R
V
CM
V
NOISE
R
1
0.01
1
100
1
10
FREQUENCY – MHz
100
0.1
1
FREQUENCY – kHz
10
Figure 13. Common-Mode Rejection vs. Frequency
Figure 10. Input Current and Voltage Noise vs. Frequency
60
10000
V
= ꢁ7.5V
S
G = +1
S
V
= ꢁ7.5V
50
40
30
20
10
0
1000
100
10
+PSRR
–PSRR
0
1
10
100
1000
1
10
FREQUENCY – MHz
100
200
FREQUENCY – MHz
Figure 14. Power Supply Rejection vs. Frequency
Figure 11. Output Impedance vs. Frequency, Disabled State
REV. B
–5–
AD8024
3000
2500
2000
1500
–30
G = 2
R
= 150ꢂ
L
V
V
= ꢁ7.5V
S
–40
–50
–60
–70
= 2V p-p
O
G = +2
G = +1
2ND
G = +10
3RD
G = –1
1000
500
0
–80
–90
2
4
6
8
10
12
1
10
FREQUENCY – MHz
100
SUPPLY VOLTAGE – ꢁV
Figure 15. Harmonic Distortion vs. Frequency, RL = 150 Ω
Figure 18. Maximum Slew Rate vs. Supply Voltage
3
2
180
0
ꢄ10
ꢄ20
ꢄ30
ꢄ40
1
GAIN
90
0
0
–1
–2
–3
–4
–5
PHASE
V
= ꢁ12V
S
V
= ꢁ2.5V
S
–90
ꢄ50
ꢄ60
ꢄ70
ꢄ80
V
= ꢁ7.5V
S
V
= ꢁ7.5V
S
–6
–7
–8
–9
–180
–270
1
10
FREQUENCY – MHz
100
1000
1
10
FREQUENCY – MHz
100
Figure 19. Closed-Loop Gain and Phase vs. Frequency,
G = 1, RL = 150 Ω
Figure 16. Crosstalk vs. Frequency, G = 2, RL = 150 Ω
2
1
1200
180
V
R
= ꢁ7.5V
= 150ꢂ
S
GAIN
L
0
–1
–2
–3
1000
90
0
V
= ꢁ2.5V
800
600
400
200
0
PHASE
S
–4
–5
–6
G = +10
G = +2
G = –1
–90
–7
–8
V
= ꢁ7.5V
S
G = +1
–9
–180
–270
–10
–11
–12
0
1
2
3
4
5
6
1
10
FREQUENCY – MHz
100
1000
OUTPUT VOLTAGE STEP – V p-p
Figure 17. Slew Rate vs. Output Step Size
Figure 20. Closed-Loop Gain and Phase vs. Frequency,
G = 2, RL = 150 Ω
REV. B
–6–
AD8024
1
0
180
90
GAIN
2V
20ns
–1
–2
V
= ꢁ12V
S
–3
V
IN
PHASE
–4
–5
0
–6
V
= ꢁ7.5V
–7
S
–90
–8
–9
V
OUT
–10
–11
–12
–13
–180
–270
2V
1
10
FREQUENCY – MHz
100
1000
Figure 21. Closed-Loop Gain and Phase vs. Frequency,
Figure 24. Large Signal Pulse Response, Gain = 1
G = 10, RL = 150 Ω
(RFB = 5 kΩ, RL = 150 Ω, VS = 7.5 V)
1
180
90
GAIN
0
250mV
20ns
–1
V
IN
–2
–3
–4
–5
–6
–7
–8
–9
V
= ꢁ12V
= ꢁ7.5V
PHASE
S
0
–90
V
S
V
OUT
–180
–270
500mV
1
10
FREQUENCY – MHz
100
1000
Figure 22. Closed-Loop Gain and Phase vs. Frequency,
Figure 25. Small Signal Pulse Response, Gain = 2
G = –1, RL = 150 Ω
(RFB = 750 Ω, RL = 150 Ω, VS = 7.5 V)
500mV
20ns
1V
20ns
V
V
IN
IN
V
V
OUT
OUT
500mV
2V
Figure 23. Small Signal Pulse Response, Gain = 1
Figure 26. Large Signal Pulse Response, Gain = 2
(RFB = 5 kΩ, RL = 150 Ω, VS = 7.5 V)
(RFB = 750 Ω, RL = 150 Ω, VS = 7.5 V)
REV. B
–7–
AD8024
50mV
20ns
500mV
20ns
V
V
IN
IN
V
V
OUT
OUT
500mV
500mV
Figure 29. Small Signal Pulse Response, Gain = –1
(RFB = 909 Ω, RL = 150 Ω, VS = 7.5 V)
Figure 27. Small Signal Pulse Response, Gain = 10
(RFB = 400 Ω, RL = 150 Ω, VS = 7.5 V)
2V
20ns
20ns
200mV
V
IN
V
IN
V
OUT
V
OUT
2V
2V
Figure 30. Large Signal Pulse Response, Gain = –1
(RFB = 909 Ω, RL = 150 Ω, VS = 7.5 V)
Figure 28. Large Signal Pulse Response, Gain = 10
(RFB = 400 Ω, RL = 150 Ω, VS = 7.5 V)
REV. B
–8–
AD8024
General
Driving Capacitive Loads
The AD8024 is a wide bandwidth, quad video amplifier. It offers a
high level of performance on 16 mA total quiescent supply cur-
rent for closed-loop gains of 1 or greater.
When used in combination with the appropriate feedback resistor,
the AD8024 will drive any load capacitance without oscillation.
In accordance with the general rule for current feedback ampli-
fiers, increased load capacitance requires the use of a higher
feedback resistor for stable operation.
Bandwidth up to 380 MHz, low differential gain and phase errors,
and high output current make the AD8024 an efficient video
amplifier.
Due to the high open-loop transresistance and low inverting
input current of the AD8024, large feedback resistors do not
create large closed-loop gain errors. In addition, the high output
current allows rapid voltage slewing on large load capacitors.
The AD8024’s wide phase margin and high output current make it
an excellent choice when driving any capacitive load.
Choice of Feedback Resistor
For wide bandwidth and clean pulse response, an additional
small series output resistor of about 10 Ω is recommended.
Because it is a current feedback amplifier, the closed-loop
bandwidth of the AD8024 may be customized with the feed-
back resistor.
R
F
A larger feedback resistor reduces peaking and increases the
phase margin at the expense of reduced bandwidth. A smaller
feedback resistor increases bandwidth at the expense of increased
peaking and reduced phase margin.
1.0ꢀF
0.1ꢀF
+V
S
R
G
–
R
S
V
AD8024
+
O
1.0ꢀF
0.1ꢀF
C
V
L
The closed-loop bandwidth is affected by attenuation due to the
finite output resistance. The open-loop output resistance of ≈6 Ω
reduces the bandwidth somewhat when driving load resistors less
than ≈150 Ω. The bandwidth will be ≈10% greater for load resis-
tance above a few hundred ohms.
IN
R
T
–V
S
Figure 31. Circuit for Driving a Capacitive Load
The value of the feedback resistor is not critical unless maintaining
the widest or flattest frequency response is desired. Table I shows
the bandwidth at different supply voltages for some useful closed-
loop gains when driving a 150 Ω load. The recommended resistors
are for the widest bandwidth with less than 2 dB peaking.
1V
20nS
V
IN
Table I. –3 dB Bandwidth vs. Closed-Loop Gain Resistor,
RL = 150 ꢂ
V
OUT
VS – Volts
Gain
RF – ꢂ
BW – MHz
7.5
+1
+2
+10
–1
5000
750
400
750
350
275
105
165
2V
Figure 32. Pulse Response Driving a Large Load
Capacitance, CL = 300 pF, G = 3, RFB = 2.32 kΩ,
RS = 10.5 Ω, RL = 1 kΩ, VS = 7.5 V
12
+1
+10
–1
8000
215
750
380
150
95
2.5
+2
1125
125
REV. B
–9–
AD8024
Disable Mode Operation
Overload Recovery
When the Disable pin is tied to DGND, all amplifiers are opera-
tional, in the enabled state.
The most important overload conditions are:
Input Common-Mode Voltage Overdrive
Output Voltage Overdrive
Input Current Overdrive.
When the voltage on the Disable pin is raised to 1.6 V or more
above DGND, all amplifiers are in the disabled, powered-down
state. In this condition, the DISABLE pin sources approximately
0.1 µA, the total quiescent current is reduced to approximately
500 µA, all outputs are in a high impedance state, and there is a
high level of isolation from inputs to outputs.
When configured for a low closed-loop gain, the AD8024
recovers quickly from an input common-mode voltage over-
drive; typically in <25 ns.
When configured for a higher gain and overloaded at the output,
recovery from an output voltage overdrive is also short; approxi-
mately 55 ns (see Figure 33). For higher overdrive, the response
is somewhat slower. For 100% overdrive, the recovery time is
substantially longer.
The output impedance in the disabled mode is the equivalent of all
external resistors, seen from the output pin, in parallel with the
total disabled output impedance of the amplifier, typically 20 pF.
The input stages of the AD8024 include protection from large
differential input voltages that may be present in the disabled
mode. Internal clamps limit this voltage to 1.5 V. The high input-
to-output isolation is maintained for voltages below this limit.
When configured for a high noninverting gain, a high input over-
drive can result in a large current into the input stage. Although
this current is internally limited to approximately 30 mA, its
effect on the total power dissipation may be significant. See also
the warning under Maximum Power Dissipation.
50ns
1V
V
IN
V
OUT
5V
Figure 33. 15% Overload Recovery, Gain = 10
(RFB = 400 Ω, RL = 1 kΩ, VS = 7.5 V)
REV. B
–10–
AD8024
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic SOIC
(R-16A)
0.3937 (10.00)
0.3859 (9.80)
9
16
1
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
8
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.050 (1.27)
BSC
0.0196 (0.50)
0.0099 (0.25)
ꢅ 45ꢃ
8ꢃ
0ꢃ
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
REV. B
–11–
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