AD7989-1 [ADI]
PulSAR ADCs in MSOP/LFCSP;
ADI 
18-Bit, 100 kSPS/500 kSPS
PulSAR ADCs in MSOP/LFCSP
Data Sheet
AD7989-1/AD7989-5
FEATURES
GENERAL DESCRIPTION
Low power dissipation
AD7989-1
The AD7989-1/AD7989-5 are 18-bit, successive approximation,
analog-to-digital converters (ADCs) that operate from a single
power supply, VDD. The AD7989-1/AD7989-5 contain a low
power, high speed, 18-bit sampling ADC and a versatile serial
interface port. On the CNV rising edge, the AD7989-1/AD7989-5
sample the voltage difference between the IN+ and IN− pins.
The voltages on these pins typically swing in opposite phases
between 0 V and VREF. The reference voltage, VREF, is applied
externally and can be set independent of the supply voltage,
VDD. Its power scales linearly with throughput.
400 μW at 100 kSPS typical (VDD only)
700 μW at 100 kSPS typical (total)
AD7989-5
2 mW at 500 kSPS typical (VDD only)
3.5 mW at 500 kSPS typical (total)
18-bit resolution with no missing codes
Throughput
AD7989-1
100 kSPS
AD7989-5
500 kSPS
INL: 1 LSB typical, 2 LSB maximum
SNR: 98 dB at 1 kHz, VREF = 5 V typical
SINAD: 97 dB at 1 kHz typical
THD: −120 dB at 10 kHz typical
Dynamic range: 99 dB at VREF = 5 V typical
True differential analog input voltage range: VREF
0 V to VREF with VREF between 2.4 V and 5.1 V
No pipeline delay
The AD7989-1/AD7989-5 are serial peripheral interface (SPI)-
CS
compatible, which features the ability, using the SDI/ input,
to daisy-chain several ADCs on a single 3-wire bus. The
AD7989-1/AD7989-5 are compatible with 1.8 V, 2.5 V, 3 V, and
5 V logic, using the separate VIO supply.
The AD7989-1/AD7989-5 are available in a 10-lead MSOP or a
10-lead LFCSP with operation specified from −40°C to +85°C.
Table 1. MSOP and LFCSP 14-/16-/18-Bit PulSAR® ADCs
Bits 100 kSPS
250 kSPS
AD76912
400 kSPS to 500 kSPS
AD76902
≥1000 kSPS
AD79822
181
AD7989-12
AD7989-52
AD76882
AD76932
AD79162
AD76862
AD79842
AD79152
Single-supply 2.5 V operation with 1.8 V, 2.5 V, 3 V, and 5 V
logic interface
Proprietary serial interface SPI-/QSPI™-/MICROWIRE™-/
DSP-compatible1
Ability to daisy-chain multiple ADCs
10-lead MSOP and 3 mm × 3 mm 10-Lead LFCSP
161
AD7684
AD76872
163
143
AD7680
AD7683
AD7988-12
AD7940
AD76852
AD7694
AD79802
AD79832
AD7988-52
AD79422
AD79462
APPLICATIONS
Battery-powered equipment
Data acquisition systems
Medical instruments
1 True differential.
2 Pin for pin compatible.
3 Pseudo differential.
Seismic data acquisition systems
TYPICAL APPLICATIONS CIRCUIT
2.5V TO 5V 2.5V
VIO
1.8V TO 5.5V
REF VDD
SDI/CS
AD7989-1/
AD7989-5
IN+
3- OR 4-WIRE
INTERFACE
(SPI, CS,
SCK
SDO
CNV
±10V, ±5V, ..
IN–
DAISY CHAIN)
GND
ADA4941-1
Figure 1.
1 Protected by U.S. Patent 6,703,961.
Rev. B
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AD7989-1/AD7989-5
Data Sheet
TABLE OF CONTENTS
Features.....................................................................................1
Analog Inputs......................................................................15
Driver Amplifier Choice......................................................15
Single-Ended to Differential Driver.....................................16
Voltage Reference Input.......................................................16
Power Supply.......................................................................16
Digital Interface...................................................................16
CS Mode, 3-Wire.................................................................17
CS Mode, 4-Wire.................................................................18
Chain Mode.........................................................................19
Applications Information........................................................20
Interfacing to Blackfin® DSP................................................20
Layout..................................................................................20
Evaluating AD7989-1/AD7989-5 Performance.......................21
Outline Dimensions ................................................................22
Ordering Guide ...................................................................23
Applications...............................................................................1
General Description ..................................................................1
Typical Applications Circuit ......................................................1
Revision History........................................................................2
Specifications.............................................................................3
Timing Specifications ............................................................5
Absolute Maximum Ratings......................................................7
ESD Caution..........................................................................7
Pin Configurations and Function Descriptions.........................8
Typical Performance Characteristics.........................................9
Terminology ............................................................................12
Theory of Operation................................................................13
Circuit Information .............................................................13
Converter Operation............................................................13
Typical Connection Diagram...............................................14
REVISION HISTORY
1/2017—Rev. A to Rev. B
Change to Single-Ended to Differential Driver Section Title...16
Changes to Figure 32...............................................................17
Changes to Figure 34...............................................................18
Changes to Ordering Guide.....................................................23
Change to Table 1 ......................................................................1
Changed VIO = 2.3 V to 5.5 V to VIO = 1.71 V to 5.5 V...........3
Changes to Table 2.....................................................................3
Changed VIO = 2.3 V to 5.5 V to VIO = 1.71 V to 5.5 V...........4
Deleted VIO Range Parameter, Table 3......................................4
Changes to Table 4.....................................................................5
Added Table 5; Renumbered Sequentially .................................6
Changes to Figure 9...................................................................9
Change to Terminology Section ..............................................12
Changes to Figure 26...............................................................14
Changes to Table 9...................................................................15
7/2014—Rev. 0 to Rev. A
Changes to Features Section......................................................1
Changes to Table 1.....................................................................1
Changes to Table 8...................................................................15
1/2014—Revision0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
AD7989-1/AD7989-5
SPECIFICATIONS
VDD = 2.5 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, TA = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION
18
Bits
ANALOG INPUT
Voltage Range
IN+ − IN−
−VREF
+VREF
V
Absolute Input Voltage
Common-Mode Input Range
Analog Input Common Mode Rejection
Ratio (CMRR)
IN+ and IN−
IN+ and IN−
fIN = 450 kHz
−0.1
VREF × 0.475
VREF + 0.1
VREF × 0.525
V
V
dB
VREF × 0.5
67
Leakage Current at 25°C
Input Impedance
Acquisition phase
200
nA
See the Analog Inputs section
ACCURACY
No Missing Codes
18
Bits
Differential Nonlinearity Error (DNL)
Integral Nonlinearity Error (INL)
Transition Noise
−0.85
−2
0.5
1
1.05
+0.004
1
100
0.5
90
+1.5
+2
LSB
LSB
VREF = 5 V
LSB1
% of FS
ppm/°C
μV
ppm/°C
dB
2
Gain Error, TMIN to TMAX
−0.023
+0.023
+700
Gain Error Temperature Drift
2
Zero Error, TMIN to TMAX
Zero Temperature Drift
Power Supply Rejection Ratio (PSRR)
THROUGHPUT
AD7989-1 Conversion Rate
AD7989-5 Conversion Rate
Transient Response
VDD = 2.5 V 5%
Full-scale step
0
0
100
500
400
kSPS
kSPS
ns
AC ACCURACY
Dynamic Range
VREF = 5 V
VREF = 2.5 V
fO = 1 kSPS
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 2.5 V
fIN = 10 kHz
fIN = 10 kHz
fIN = 1 kHz, VREF = 5 V
97
99
93
dB3
dB3
dB3
dB3
dB3
dB3
dB3
dB3
Oversampled Dynamic Range4
Signal-to-Noise Ratio (SNR)
126
98
92.5
−115
−120
97
95.5
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion5 (THD)
Signal-to-Noise-and-Distortion Ratio (SINAD)
1 LSB means least significant bit. With the 5 V input range, 1 LSB is 38.15 μV.
2 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
3 All specifications expressed in decibels are referred to a full-scale input range (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4 Dynamic range is obtained by oversampling the ADC running at a throughput, fS, of 500 kSPS followed by postdigital filtering with an output word rate of fO.
5 Tested fully in production at fIN = 1 kHz.
Rev. B | Page 3 of 24
AD7989-1/AD7989-5
Data Sheet
VDD = 2.5 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, TA = −40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
VREF = 5 V
Min
Typ
Max
Unit
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
2.4
5.1
V
μA
250
10
2
MHz
ns
VDD = 2.5 V
VIL
VIO > 3 V
VIO ≤ 3 V
VIO > 3 V
VIO ≤ 3 V
–0.3
–0.3
0.7 × VIO
0.9 × VIO
−1
+0.3 × VIO
+0.1 × VIO
VIO + 0.3
VIO + 0.3
+1
V
V
V
V
μA
μA
VIH
IIL
IIH
−1
+1
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Serial, 18 bits, twos complement
Conversion results available immediately
after completed conversion
VOL
VOH
ISINK = +500 μA
ISOURCE = −500 μA
0.4
V
V
VIO − 0.3
POWER SUPPLIES
VDD
VIO
2.375
1.71
2.5
2.625
5.5
V
V
Standby Current1, 2
AD7989-1 Power Dissipation
Total
VDD and VIO = 2.5 V, 25°C
VDD = 2.625 V, VREF = 5 V, VIO = 3 V
10 kSPS throughput
0.35
μA
70
86
860
μW
μW
μW
μW
μW
100 kSPS throughput
700
400
170
130
VDD Only
REF Only
VIO Only
AD7989-5 Power Dissipation
Total
VDD = 2.625 V, VREF = 5 V, VIO = 3 V
500 kSPS throughput
3.5
2
4.3
mW
mW
VDD Only
REF Only
VIO Only
Energy per Conversion
TEMPERATURE RANGE
Specified Performance
0.85
0.65
7.0
mW
mW
nJ/sample
TMIN to TMAX
−40
+85
°C
1 With all digital inputs forced to VIO or ground as required.
2 During acquisition phase.
Rev. B | Page 4 of 24
Data Sheet
AD7989-1/AD7989-5
TIMING SPECIFICATIONS
VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, TA = −40°C to +85°C, unless otherwise noted.1
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
THROUGHPUT RATE
AD7989-1
AD7989-5
100
500
kSPS
kSPS
CONVERSION AND ACQUISITION TIMES
Conversion Time: CNV Rising Edge to Data Available
AD7989-1
AD7989-5
Acquisition Time
AD7989-1
AD7989-5
tCONV
tACQ
tCYC
9500
1600
ns
ns
500
400
ns
ns
Time Between Conversions
AD7989-1
10
2
μs
ꢀs
ns
AD7989-5
CNV PULSE WIDTH (CS MODE)
tCNVH
tSCK
500
SCK
SCK Period (CS Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
10.5
12
13
ns
ns
ns
ns
15
SCK Period (Chain Mode)
tSCK
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
11.5
13
14
16
4.5
4.5
3
ns
ns
ns
ns
ns
ns
ns
tSCKL
tSCKH
tHSDO
tDSDO
9.5
11
12
14
ns
ns
ns
ns
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CS MODE
CNV or SDI Low to SDO D17 MSB Valid
VIO Above 3 V
VIO Above 2.3V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
tEN
10
15
20
ns
ns
ns
ns
ns
tDIS
tSSDICNV
tHSDICNV
5
2
CHAIN MODE
SCK Valid Setup Time from CNV Rising Edge
SCK Valid Hold Time from CNV Rising Edge
SDI Valid Setup Time from SCK Falling Edge
SDI Valid Hold Time from SCK Falling Edge
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
5
5
2
3
ns
ns
ns
ns
1 See Figure 2 and Figure 3 for load conditions.
Rev. B | Page 5 of 24
AD7989-1/AD7989-5
Data Sheet
1
VDD = 2.37 V to 2.63 V, VIO = 1.71 V to 2.3 V, −40°C to +85°C, unless otherwise stated.
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
THROUGHPUT RATE
AD7989-1
AD7989-5
100
500
kSPS
kSPS
CONVERSION AND ACQUISTION TIMES
Conversion Time: CNV Rising Edge to Data Available
tCONV
AD7989-1
AD7989-5
9500
1500
ns
ns
Acquisition Time
AD7989-1
AD7989-5
tACQ
500
400
ns
ns
Time Between Conversions
AD7989-1
AD7989-5
tCYC
10
2
μs
μs
ns
CNV PULSE WIDTH (CS MODE)
tCNVH
500
SCK
SCK Period (CS Mode)
tSCK
22
23
6
6
3
ns
ns
ns
ns
ns
ns
SCK Period (Chain Mode)
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CS MODE
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
14
18
21
CNV or SDI Low to SDO D17 MSB Valid
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge
CHAIN MODE
tEN
tDIS
tSSDICNV
tHSDICNV
40
20
ns
ns
ns
ns
5
10
SCK Valid Setup Time from CNV Rising Edge
SCK Valid Hold Time from CNV Rising Edge
SDI Valid Setup Time from SCK Falling Edge
SDI Valid Hold Time from SCK Falling Edge
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
5
5
2
3
ns
ns
ns
ns
1 See Figure 2 and Figure 3 for load conditions.
1
Y% VIO
500µA
I
OL
1
X% VIO
tDELAY
tDELAY
2
2
V
V
V
IH
IH
1.4V
TO SDO
2
2
V
IL
IL
C
L
20pF
1
2
FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V, X = 70 AND Y = 30.
MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS
500µA
I
IH
IL
OH
SPECIFICATIONS IN TABLE 3.
Figure 2. Load Circuit for Digital Interface Timing
Figure 3. Voltage Levels for Timing
Rev. B | Page 6 of 24
Data Sheet
AD7989-1/AD7989-5
ABSOLUTE MAXIMUM RATINGS
Table 6.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
Analog Inputs
IN+, IN− to GND1
−0.3 V to VREF + 0.3 V or 130 ꢀA
Supply Voltage
REF, VIO to GND
VDD to GND
VDD to VIO
−0.3 V to +6.0 V
−0.3 V to +3.0 V
+3 V to −6 V
Digital Inputs to GND
Digital Output to GND
Storage Teꢀperature Range
Junction Teꢀperature
θJA Therꢀal Iꢀpedance
10-Lead MSOP
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
ESD CAUTION
200°C/W
48.7°C/W
10-Lead LFCSP
θJC Therꢀal Iꢀpedance
10-Lead MSOP
44°C/W
10-Lead LFCSP
2.96°C/W
Reflow Soldering
JEDEC Standard (J-STD-020)
1 See the Analog Inputs section for an explanation of IN+ and IN−.
Rev. B | Page 7 of 24
AD7989-1/AD7989-5
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
VDD
IN+
1
2
3
4
5
10 VIO
AD7989-1/
AD7989-5
TOP VIEW
(Not to Scale)
9
8
7
6
SDI/CS
SCK
SDO
CNV
IN–
REF
VDD
IN+
1
2
3
4
5
10 VIO
GND
AD7989-1/
AD7989-5
TOP VIEW
(Not to Scale)
9
8
7
6
SDI/CS
SCK
SDO
CNV
NOTES
1. EXPOSED PAD. FOR THE LFCSP, THE
EXPOSED PAD CAN BE CONNECTED TO GND.
THIS CONNECTION IS NOT REQUIRED TO
MEET THE ELECTRICAL PERFORMANCES.
IN–
GND
Figure 4. 10-Lead MSOP Pin Configuration
Figure 5. 10-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1
REF
AI
Reference Input Voltage. The REF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be
decoupled closely to the GND pin with a 10 μF capacitor.
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
Power Supply.
AI
AI
P
Differential Positive Analog Input.
Differential Negative Analog Input.
Power Supply Ground.
Conversion Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the device: chain mode or chip select (CS) mode. In CS mode, the SDO pin is
enabled when CNV is low. In chain mode, the data is read when CNV is high.
DI
7
8
9
SDO
SCK
SDI/CS
DO
DI
DI
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.
Serial Data Input/Chip Select. This input has multiple functions. It selects the interface mode of the ADC as
follows:
Chain mode is selected if this pin is low during the CNV rising edge. In this mode, SDI/CS is a data input
that daisy-chains the conversion results of two or more ADCs onto a single SDO line. The digital data level
on SDI/CS is the output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI/CS is high during the CNV rising edge. In this mode, either SDI/CS or CNV can
enable the serial output signals when low.
10
VIO
P
Input/Output Interface Digital Power. This pin is nominally at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V).
EPAD
Exposed Pad. For the LFCSP, the exposed pad can be connected to GND. This connection is not required to
meet the electrical performances.
1AI means analog input, DI means digital input, DO means digital output, and P means power.
Rev. B | Page 8 of 24
Data Sheet
AD7989-1/AD7989-5
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V.
2.0
1.5
1.0
2.0
POSITIVE INL: +0.79 LSB
NEGATIVE INL: –0.68 LSB
1.5
1.0
0.5
0.5
0
0
–0.5
–1.0
–0.5
–1.0
–1.5
–2.0
–1.5
–2.0
0
65536
131072
CODE
196608
262144
0
65536
131072
CODE
196608
262144
Figure 6. INL vs. Code
Figure 9. DNL vs. Code
60k
50k
40k
30k
20k
10k
0
50k
45k
44806
43239
50975
40k
35k
30k
25k
20k
15k
10k
5k
32476
29064
20013
16682
9064
7795
3158
2793
4
745
881
43
3FFFA
145
7
222
29
0
0
0
0
0
0
0
1
7
0
0
0
3FFF0
3FFF2
3FFF4
3FFF6
3FFF8
3FFFC
2
3
5
6
7
8
9
A
B
C
D
CODE IN HEX
CODE IN HEX
Figure 7. Histogram of a DC Input at the Code Center
Figure 10. Histogram of a DC Input at the Code Transition
0
–20
0
fS = 500kSPS
fIN = 1kHz
SNR = 97.4361dB
SINAD = 97.3577dB
THD = –114.42dB
f
f
= 100kSPS
= 1kHz
S
IN
–20
–40
SNR = 97.2634dB
SINAD = 97.145dB
THD = –112.7dB
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
0
50
100
150
200
250
0
10
20
30
40
50
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 8. AD7989-5 Fast Fourier Transform (FFT) Plot
Figure 11. AD7989-1 FFT Plot
Rev. B | Page 9 of 24
AD7989-1/AD7989-5
Data Sheet
100
100
95
99
98
97
96
95
94
93
92
91
90
90
85
80
0.1
1
10
100
1k
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
FREQUENCY (kHz)
INPUT LEVEL (dB)
Figure 15. SINAD vs. Frequency
Figure 12. SNR vs. Input Level
–100
130
125
100
95
18
17
16
–105
–110
SNR, SINAD
120
115
110
105
100
SFDR
THD
–115
–120
–125
–130
90
ENOB
85
80
15
14
2.25
2.75
3.25
3.75
4.25
4.75
5.25
2.25
2.75
3.25
3.75
4.25
4.75
5.25
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 16. THD and SFDR vs. Reference Voltage
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
–115
100
98
96
94
92
–117
–119
–121
–123
90
–55
–125
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. SNR vs. Temperature
Figure 17. THD vs. Temperature
Rev. B | Page 10 of 24
Data Sheet
AD7989-1/AD7989-5
0.7
0.6
0.5
0.4
0.3
0.2
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
I
VDD
I
VDD
I
REF
I
REF
I
VIO
I
VIO
0.1
0
2.375
2.425
2.475
2.525
2.575
2.625
2.375
2.425
2.475
2.525
2.575
2.625
VDD VOLTAGE (V)
VDD VOLTAGE (V)
Figure 18. Operating Currents vs. VDD Voltage (AD7989-5)
Figure 21. Operating Currents vs. VDD Voltage (AD7989-1)
–80
8
7
6
5
4
3
2
1
–85
–90
–95
–100
–105
–110
–115
–120
–125
I
+ I
VIO
VDD
0
–55
0.1
1
10
100
1k
–35
–15
5
25
45
65
85
105
125
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 19. THD vs. Frequency
Figure 22. Power-Down Currents vs. Temperature
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.14
0.12
0.10
008
I
I
VDD
VDD
0.06
I
I
REF
REF
0.04
0.02
0
I
I
VIO
VIO
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 20. Operating Currents vs. Temperature (AD7989-5)
Figure 23. Operating Currents vs. Temperature (AD7989-1)
Rev. B | Page 11 of 24
AD7989-1/AD7989-5
TERMINOLOGY
Data Sheet
Integral Nonlinearity Error (INL)
Effective Resolution
Effective resolution is calculated as
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 25).
Effective Resolution = log2(2N/RMS Input Noise)
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Differential Nonlinearity Error (DNL)
Dynamic Range
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels. It is
measured with a signal at −60 dB so it includes all noise sources
and DNL artifacts.
Zero Error
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, and the actual voltage producing the midscale
output code, that is, 0 LSB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Gain Error
The first code transition (from 100 … 00 to 100 …01) occurs at
a level ½ LSB above nominal negative full scale (−4.999981 V
for the 5 V range). The last transition (from 011 … 10 to
011 … 11) occurs for an analog voltage 1½ LSB below the
nominal full scale (+4.999943 V for the 5 V range). The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the firsttransitionfrom
the difference between the ideal levels.
Signal-to-Noise-and-Distortion (SINAD) Ratio
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value of SINAD is expressed in decibels.
Aperture Delay
Spurious-Free Dynamic Range (SFDR)
Aperture delay is the measure of the acquisition performance
and is the time between the rising edge of the CNV input and
when the input signal is held for a conversion.
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD as follows:
Transient Response
Transient response isthe time required forthe ADC to accurately
acquire its input after a full-scale step function is applied.
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Noise Free Code Resolution
Noise free code resolution is the number of bits beyond which it is
impossible to distinctly resolve individual codes. It is calculated as
Noise Free Code Resolution = log2(2N/Peak-to-Peak Noise)
and is expressed in bits.
Rev. B | Page 12 of 24
Data Sheet
AD7989-1/AD7989-5
THEORY OF OPERATION
IN+
SWITCHES CONTROL
SW+
MSB
LSB
LSB
131,072C 65,536C
4C
4C
2C
2C
C
C
C
C
BUSY
REF
CONTROL
LOGIC
COMP
GND
131,072C 65,536C
MSB
OUTPUT CODE
SW–
CNV
IN–
Figure 24. ADC Simplified Schematic
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via Switch SW+
and Switch SW−. All independent switches are connected to the
analog inputs. Therefore, the capacitor arrays are used as sampling
capacitorsand acquire the analog signal on the IN+ input and IN−
input. When the acquisition phase completesand the CNV input
goes high, a conversion phase initiates. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor arrays
then disconnectfrom the inputs and connect to the GND input.
Therefore, the differential voltage between the IN+ and IN− inputs
captured at the end of the acquisition phase is applied to the
comparator inputs, causing the comparator to become unbalanced.
By switching each element of the capacitor array between GND
a n d R E F, t h e comparator input varies by binary weighted voltage
steps (VREF/2, VREF/4 ... VREF/262,144). The control logic toggles
these switches, starting with the MSB, to bring the comparatorback
into a balanced condition. Afterthe completion of this process, the
device returns tothe acquisition phase, and the control logic
generates the ADC output code.
CIRCUIT INFORMATION
The AD7989-1/AD7989-5 are high speed, low power, single-
supply, precise, 18-bit ADCs using a successive approximation
architecture.
The AD7989-1 is capable of converting 100,000 samples per second
(100 kSPS), whereas the AD7989-5 is capable of converting 500,000
samples per second (500 kSPS), and they power down between
conversions. When operating at 100 kSPS, the ADC typically
consumes 700 µW, making the AD7989-1 ideal for battery-
powered applications.
The AD7989-1/AD7989-5 provide the user with an on-chip
track-and-hold amplifier and do not exhibit any pipeline delay
or latency, making these devices ideal for multiple multiplexed
channel applications.
The AD7989-1/AD7989-5 can be interfaced to any 1.8 V to 5 V
digital logic family. It is available in a 10-lead MSOP or a tiny
10 lead LFCSP that allows space savingsand flexible configurations.
CONVERTER OPERATION
Because the AD7989-1/AD7989-5 have an on-board conversion
clock, the serial clock, SCK, is not required for the conversion
process.
The AD7989-1/AD7989-5 are a successive approximation ADCs
based on a charge redistribution digital-to-analog converter (DAC).
Figure 24 shows the simplified schematic of the ADC. The
capacitive DAC consists of two identical arrays of 18 binary
weighted capacitors, which are connected to the two comparator
inputs.
Rev. B | Page 13 of 24
AD7989-1/AD7989-5
Data Sheet
Transfer Functions
Table 8. Output Codes and Ideal Input Voltages
Analog Input
VREF = 5 V
Digital Output
Code (Hex)
The ideal transfer characteristic for the AD7989-1/AD7989-5 is
shown in Figure 25 and Table 8.
Description
+FSR – 1 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
+4.999962 V
+38.15 μV
0 V
−38.15 μV
−4.999962 V
−5 V
0x1FFFF1
0x00001
0x00000
0x3FFFF
0x20001
0x200002
011...111
011...110
011...101
1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
TYPICAL CONNECTION DIAGRAM
100...010
100...001
100...000
Figure 26 shows an example of the recommended connection
diagram for the AD7989-1/AD7989-5 when multiple supplies
are available.
–FSR
–FSR + 1 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
–FSR + 0.5 LSB
Figure 25. ADC Ideal Transfer Function
1
2.5V
REF
V+
V+
2
100nF
10µF
1.8V TO 5.5V
100nF
20Ω
0V TO V
REF
REF
VDD
VIO
2.7nF
SDI/CS
IN+
IN–
V–
V+
SCK
SDO
CNV
AD7989-1/
AD7989-5
4
3-WIRE INTERFACE
20Ω
GND
V
TO 0V
REF
2.7nF
ADA4807-12, 3
V–
4
1
2
SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
C
REF
SEE THE RECOMMENDED LAYOUT IN FIGURE 39 AND FIGURE 40.
SEE THE DRIVER AMPLIFIER CHOICE SECTION.
OPTIONAL FILTER. SEE THE ANALOG INPUTS SECTION.
3
4
Figure 26. Typical Application Diagram with Multiple Supplies
Rev. B | Page 14 of 24
Data Sheet
AD7989-1/AD7989-5
Large source impedances significantly affect the ac
ANALOG INPUTS
performance, especially THD. The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency.
Figure 27 shows an equivalent circuit of the input structure of
the AD7989-1/AD7989-5.
The two diodes, D1 and D2, provide electrostatic discharge (ESD)
protection for the IN+ analog input and IN− analog input.
Ensure the analog input signal does not exceed the reference input
voltage (REF) by more than 0.3 V. If the analog input signal
exceeds this level, the diodes become forward-biased and begin
conducting current. These diodes can handle a forward-biased
current of 130 mA maximum. However, if the supplies of the input
buffer (for example, the supplies of the ADA4807-1 in Figure 26)
are different from those of REF, the analog input signal can
eventually exceed the supply rails by more than 0.3 V. In such a case
(for example, an input buffer with a short circuit), the current
limitation can protect the device.
DRIVER AMPLIFIER CHOICE
Although the AD7989-1/AD7989-5 is easy to drive, the driver
amplifier must meet the following requirements:
The noise generated by the driver amplifier must be kept
as low as possible to preserve the SNR and transition noise
performance of the AD7989-1/AD7989-5. The noise from
the driver is filtered by the one-pole, low-pass filter of the
AD7989-1/AD7989-5 analog input circuit made by RIN and
CIN or by the external filter, if one is used. Because the
typical noise of the AD7989-1/AD7989-5 is 40 μV rms, the
SNR degradation due to the amplifier is
REF
D1
D2
C
IN
R
IN
IN+ OR IN–
GND
C
PIN
40
SNRLOSS 20 log
π
2
402 f3dB (NeN )2
Figure 27. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
90
where:
–3dB is the input bandwidth, in megahertz, of the AD7989-1/
AD7989-5 (10 MHz) or the cutoff frequency of the input
filter, if one is used.
f
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp in
85
80
75
70
nV/√Hz.
For ac applications, use a driver with a THD performance
commensurate with the AD7989-1/AD7989-5.
For multichannel, multiplexed applications, the driver
amplifier and the AD7989-1/AD7989-5 analog input circuit
must settle for a full-scale step onto the capacitor array at an
18-bit level (0.0004%, 4 ppm). In the data sheet of the
amplifier, settling at 0.1% to 0.01% is more commonly
specified. This settling can differ significantly from the settling
time at an 18-bit level and must be verified prior to driver
selection.
65
60
1
10
100
1k
10k
FREQUENCY (kHz)
Figure 28. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of Capacitor CPIN and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component composed of serial resistors
and the on resistance of the switches. CIN is typically 30 pF and
is mainly the ADC sampling capacitor.
1
Table 9. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4941-1 Very low noise, low power, single to differential
ADA4940-1 Very low noise, low power, single to differential
ADA4807-2 Very low noise and low power
ADA4627-1 Precision, low noise and low input bias
ADA4522-2 Precision, zero drift and electromagnetic interference
(EMI) enhanced
During the sampling phase when the switches are closed, the input
impedance is limited to CPIN. RIN and CIN make a one-pole, low-
pass filter that reduces undesirable aliasing effects and limits noise.
ADA4500-2 Precision, rail-to-rail input and output (RRIO) and
zero input crossover distortion
1 For the latest recommended drivers, see the product recommendations
listed on the product webpage.
When the source impedance of the driving circuit is low, the
AD7989-1/AD7989-5 can be driven directly.
Rev. B | Page 15 of 24
AD7989-1/AD7989-5
Data Sheet
SINGLE-ENDED TO DIFFERENTIAL DRIVER
POWER SUPPLY
For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941-1 single-ended to differential
driver allows a differential input to the device. The schematic is
shown in Figure 29.
The AD7989-1/AD7989-5 use two power supply pins: a core
supply (VDD) and a digital input/output interface supply (VIO).
VIO allows direct interface with any logic between 1.8 V and 5.5 V.
To reduce the number of supplies needed, tie VIO and VDD
together. The AD7989-1/AD7989-5 are independent of power
supply sequencing between VIO and VDD. Additionally, they are
insensitive to power supply variations over a wide frequency
range, as shown in Figure 3ꢀ.
R1 and R2 set the attenuation ratio between the input range and
the ADC voltage range (VREF). R1, R2, and CF are chosen
depending on the desired input resistance, signal bandwidth,
antialiasing, and noise contribution. For example, for the 1ꢀ V
range with a 4 kΩ impedance, R2 = 1 kΩ and R1 = 4 kΩ.
95
90
85
80
75
70
65
60
R3 and R4 set the common mode on the IN− input, and R5 and R6
set the common mode on the IN+ input of the ADC. Ensure the
common mode is close to VREF/2. For example, for the 1ꢀ V
range with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 =
1ꢀ.5 kΩ, and R6 = 9.76 kΩ.
R5
R6
R3
R4
+5V REF
+2.5V
10µF
+5.2V
100nF
100nF
REF
20Ω
20Ω
OUTN
OUTP
REF
VDD
IN+
IN–
2.7nF
2.7nF
AD7989-1/
AD7989-5
1
10
100
FREQUENCY (kHz)
1k
IN
GND
Figure 30. PSRR vs. Frequency
FB
ADA4941
–0.2V
R2
The AD7989-1/AD7989-5 power down automatically at the end
of each conversion phase.
R1
±10V,
±5V, ..
DIGITAL INTERFACE
C
F
Although the AD7989-1/AD7989-5 have a reduced number of
pins, they offer flexibility in their serial interface modes.
Figure 29. Single-Ended to Differential Driver Circuit
CS
When in
mode, the AD7989-1/AD7989-5 are compatible
VOLTAGE REFERENCE INPUT
with SPI, queued serial peripheral interface (QSPI), digital hosts,
and digital signal processors (DSPs). In this mode, the AD7989-1/
AD7989-5 can use either a 3-wire or 4-wire interface. A 3-wire
interface using the CNV, SCK, and SDO signals minimizes
wiring connections, which is useful, for instance, in isolated
The AD7989-1/AD7989-5 voltage reference input, REF, has a
dynamic input impedance and must, therefore, be driven by a
low impedance source with efficient decoupling between the
REF and GND pins, as explained in the Layout section.
When REF is driven by a very low impedance source (for example,
a reference buffer using the AD8ꢀ31 or the ADA48ꢀ7-1), a 1ꢀ μF
(X5R, ꢀ8ꢀ5 size) ceramic chip capacitor is appropriate for optimum
performance.
CS
applications. A 4-wire interface using the SDI/ , CNV, SCK,
and SDO signals allows CNV, which initiates the conversions, to be
independent of the readback timing (SDI). This is useful in low
jitter sampling or simultaneous sampling applications.
If using an unbuffered reference voltage, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
12ꢀ6 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR435 reference.
When in chain mode, the AD7989-1/AD7989-5 provide a daisy-
chain feature using the SDI input for cascading multiple ADCs
on a single data line, similar to a shift register.
CS
The mode in which the device operates depends on the SDI/
If desired, use a reference decoupling capacitor with values as
small as 2.2 μF with a minimal impact on performance,
especially DNL.
CS
level when the CNV rising edge occurs. mode is selected if
CS CS
SDI/ is high, and chain mode is selected if SDI/ is low. The
CS
CS
SDI/ hold time is such that when SDI/ and CNV are
connected together, chain mode is always selected. The user
must timeout the maximum conversion time prior to readback.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 1ꢀꢀ nF) between the REF
and GND pins.
Rev. B | Page 16 of 24
Data Sheet
AD7989-1/AD7989-5
When the conversion is complete, the AD7989-1/AD7989-5 enter
the acquisition phase and power down. When CNV goes low, the
MSB is output onto SDO. The remaining data bits are clocked by
subsequent SCK falling edges. The data is valid on both SCK edges.
Although the rising edge can capture the data, a digital host using
the SCK falling edge allows a faster reading rate, provided that it
has an acceptable hold time. After the 18th SCK falling edge or
when CNV goes high (whichever occurs first), SDO returns to
high impedance.
CS MODE, 3-WIRE
This mode is usually used when a single AD7989-1/AD7989-5
is connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 31, and the corresponding timing is
given in Figure 32.
CS
With SDI/ tied to VIO, a rising edge on CNV initiates a
conversion, selects the
impedance.
CS
mode, and forces SDO to high
CONVERT
DIGITAL HOST
CNV
VIO
AD7989-1/
AD7989-5
SDI/CS
SDO
DATA IN
SCK
CLK
CS
Figure 31. Mode, 3-Wire Connection Diagram (SDI High)
SDI/CS = 1
tCYC
CNV
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
SDO
1
2
3
16
17
18
tHSDO
tSCKH
tDSDO
tEN
tDIS
D17
D16
D15
D1
D0
CS
Figure 32. Mode, 3-Wire Serial Interface Timing (SDI High)
Rev. B | Page 17 of 24
AD7989-1/AD7989-5
Data Sheet
CS
Prior to the minimum conversion time, SDI/ can select other
CS MODE, 4-WIRE
CS
SPI devices, such as analog multiplexers, but SDI/ must be
This mode is usually used when multiple AD7989-1/AD7989-5
devices are connected to an SPI-compatible digital host.
returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time.
A connection diagram example using two AD7989-1/AD7989-5
devices is shown in Figure 33, and the corresponding timing is
given in Figure 34.
When the conversion is complete, the AD7989-1/AD7989-5
enter the acquisition phase and power down. Each ADC result
can be read by bringing its SDI/ input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 18th SCK
CS
With SDI high, a rising edge on CNV initiates a conversion,
CS
selects SDI/ mode, and forces SDO to high impedance. In
this mode, CNV must be held high during the conversion phase
CS
and the subsequent data readback. If SDI/ and CNV are low,
SDO is driven low.
CS
falling edge or when SDI/ goes high (whichever occurs first),
SDO returns to high impedance and another AD7989-1/AD7989-5
can be read.
CS2
CS1
CONVERT
CNV
CNV
DIGITAL HOST
AD7989-1/
AD7989-5
AD7989-1/
AD7989-5
SDI/CS
SDO
SDI/CS
SDO
SCK
SCK
DATA IN
CLK
CS
Figure 33. Mode, 4-Wire Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
tSSDICNV
CONVERSION
ACQUISITION
SDI/CS (CS1)
tHSDICNV
SDI/CS (CS2)
tSCK
tSCKL
SCK
SDO
1
2
3
16
17
18
19
20
34
35
36
tHSDO
tSCKH
tDSDO
tDIS
tEN
D17
D16
D15
D1
D0
D17
D16
D1
D0
CS
Figure 34. Mode, 4-Wire Serial Interface Timing
Rev. B | Page 18 of 24
Data Sheet
AD7989-1/AD7989-5
In this mode, CNV is held high during the conversion phase
and the subsequent data readback. When the conversion is
complete, the MSB is output onto SDO and the AD7989-1/
AD7989-5 enter the acquisition phase and power down. The
remaining data bits stored in the internal shift register are
clocked by subsequent SCK falling edges. For each ADC, SDI
feeds the input of the internal shift register and is clocked by the
SCK falling edge. Each ADC in the chain outputs its data MSB
first, and 18 × N clocks are required to read back the N ADCs.
The data is valid on both SCK edges. Although the rising edge
can capture the data, a digital host using the SCK falling edge
allows a faster reading rate and, consequently, more AD7989-1/
AD7989-5 devices in the chain, provided that the digital host has
an acceptable hold time. The maximum conversion rate may be
reduced due to the total readback time.
CHAIN MODE
This mode can daisy-chain multiple AD7989-1/AD7989-5
devices on a 3-wire serial interface. This feature reduces
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7989-1/AD7989-5
devices is shown in Figure 35, and the corresponding timing is
given in Figure 36.
CS
When SDI/ and CNV are low, SDO is driven low. With SCK
low, a rising edge on CNV initiates a conversion, and selects the
chain mode.
CONVERT
CNV
CNV
DIGITAL HOST
DATA IN
AD7989-1/
AD7989-5
AD7989-1/
AD7989-5
SDI/CS
SDO
SDI/CS
SDO
A
SCK
B
SCK
CLK
Figure 35. Chain Mode Connection Diagram
SDI/CS = 0
A
tCYC
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
2
3
A
B
16
17
18
19
20
34
35
36
tHSCKCNV
tSSDISCK
tSCKH
tHSDISCK
tEN
D
D
17
D
16
D
D
15
15
D
1
1
D
0
SDO = SDI/CS
A
A
B
A
A
A
B
tHSDO
tDSDO
17
D
16
D
D
0
D
17
D
16
D 1
A
D 0
A
SDO
B
B
B
B
A
A
Figure 36. Chain Mode Serial Interface Timing
Rev. B | Page 19 of 24
AD7989-1/AD7989-5
Data Sheet
APPLICATIONS INFORMATION
INTERFACING TO BLACKFIN® DSP
LAYOUT
The AD7989-1/AD7989-5 can easily connect to a DSP, SPI, or
SPORT. The SPI configuration is straightforward using the
standard SPI interface, as shown in Figure 37.
The printed circuit board (PCB) that houses the AD7989-1/
AD7989-5 must be designed so the analog and digital sections
are separated and confined to certain areas of the PCB. The pinout
of the AD7989-1/AD7989-5, with its analog signals on the left
side and its digital signals on the right side, eases this task.
SPI_CLK
SPI_MISO
SPI_MOSI
SCK
SDO
CNV
AD7989-1/
AD7989-5
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7989-1/AD7989-5 is used as a shield. Do not run fast
switching signals, such as CNV or clocks, near analog signal
paths. Avoid crossover of digital and analog signals.
DSP
Figure 37. Typical Connection to Blackfin SPI Interface
Similarly, the SPORT interface can interface to this ADC. The
SPORT interface has some benefits in that it can use direct
memory access (DMA) and provides a lower jitter CNV signal
generated from a hardware counter.
Using at least one ground plane is recommended. It can be
common or split between the digital and analog sections. In the
latter case, join the planes underneath the AD7989-1/AD7989-5
devices.
Some glue logic may be required between SPORT and the
AD7989-1/AD7989-5 interface. The EVAL-AD7989-5SDZ
evaluation board for the AD7989-1/AD7989-5 interfaces
directly to the SPORT of the Blackfin-based (ADSP-BF527)
SDP board. The configuration used for the SPORT interface
requires the addition of some glue logic as shown in Figure 38.
The SCK input to the ADC was gated off when CNV was high
to keep the SCK line static while converting the data, thereby
ensuring the best integrity of the result. This approach uses an
AND gate and a NOT gate for the SCK path. The other logic
gates used on the RSCLK and RFS paths are for delay matching
purposes and may not be necessary when path lengths are
short.
The AD7989-1/AD7989-5 voltage reference input, REF, has a
dynamic input impedance. Decouple REF with minimal parasitic
inductances by placing the reference decoupling ceramic capacitor
close to, but ideally right up against, the REF and GND pins and
connecting them with wide, low impedance traces.
Finally, decouple the power supplies of the AD7989-1/AD7989-5,
VDD and VIO, with ceramic capacitors, typically 100 nF, placed
close to the AD7989-1/AD7989-5 and connected using short,
wide traces to provide low impedance paths and to reduce the
effect of glitches on the power supply lines.
An example of a layout following these rules is shown in Figure 39
and Figure 40.
This is one approach to using the SPORT interface for the
AD7989-1/AD7989-5 ADC; there can be other solutions similar
to this approach.
VDRIVE
DR
SDO
SCK
RSCLK
TSCLK
BLACKFIN
DSP
AD7989-1/
AD7989-5
RFS
TFS
CNV
Figure 38. The EVAL-AD7989-5SDZ Evaluation Board Connection to Blackfin
SPORT Interface
Rev. B | Page 20 of 24
Data Sheet
AD7989-1/AD7989-5
EVALUATING AD7989-1/AD7989-5 PERFORMANCE
Other recommended layouts for the AD7989-1/AD7989-5 are
outlined in UG-340 user guide for the EVAL -AD7989-5SDZ.
The evaluation board package includes a fully assembled and
tested evaluation board, the user guide, and software for controlling
the evaluation board from a PC via the EVAL -SDP-CB1Z.
AD7989-1/
AD7989-5
Figure 40. Recommended Layout of the AD7989-1/AD7989-5 (Bottom Layer)
Figure 39. Recommended Layout of the AD7989-1/AD7989-5 (Top Layer)
Rev. B | Page 21 of 24
AD7989-1/AD7989-5
OUTLINE DIMENSIONS
Data Sheet
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 41. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
0.50 BSC
2.90
10
6
PIN 1 INDEX
EXPOSED
PAD
1.74
1.64
1.49
AREA
0.50
0.40
0.30
0.20 MIN
1
5
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 42. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9)
Dimensions shown in millimeters
Rev. B | Page 22 of 24
Data Sheet
AD7989-1/AD7989-5
ORDERING GUIDE
Temperature
Range
Package
Option
Ordering
Quantity
Model1, 2, 3
Package Description
Branding
C76
C76
C80
C80
AD7989-1BRMZ
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
10-Lead MSOP, Tube
RM-10
RM-10
CP-10-9
CP-10-9
RM-10
RM-10
CP-10-9
CP-10-9
50
AD7989-1BRMZ-RL7
AD7989-1BCPZ-RL7
AD7989-1BCPZ-R2
AD7989-5BRMZ
AD7989-5BRMZ-RL7
AD7989-5BCPZ-RL7
AD7989-5BCPZ-R2
EVAL-AD7989-5SDZ
10-Lead MSOP, 7”Tape and Reel
10-Lead LFCSP, 7”Tape and Reel
10-Lead LFCSP
1,000
1,500
250
10-Lead MSOP, Tube
C7N
C7N
C7Y
50
10-Lead MSOP, 7”Tape and Reel
10-Lead LFCSP, 7”Tape and Reel
10-Lead LFCSP
1,000
1,500
250
C7Y
Evaluation Board with AD7989-5 Populated; Use
for Evaluation of Both AD7989-1 and AD7989-5
EVAL-SDP-CB1Z
System Demonstration Board, Used as a
Controller Board for Data Transfer via USB
Interface to PC
1 Z = RoHS Compliant Part.
2 The EVAL-AD7989-5SDZ board can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes.
3 The EVAL-SDP-CB1Z board allows a PC to control and communicate with all Analog Devices, Inc., evaluation boards ending in the SD designator.
Rev. B | Page 23 of 24
AD7989-1/AD7989-5
NOTES
Data Sheet
©2014–2017 Analog Devices, Inc. All rights reserved. Trademarksand
registered trademarks are the property of their respective owners.
D10232-0-1/17(B)
Rev. B | Page 24 of 24
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