AD7793B [ADI]
Low Power, 16/24-Bit Sigma-Delta ADC with Low-Noise In-Amp and Embedded Reference; 低功耗，16位/ 24位Σ-Δ型ADC，具有低噪声仪表放大器和嵌入式参考
| 型号： | AD7793B |
| 厂家： | 
ADI |
| 描述： | Low Power, 16/24-Bit Sigma-Delta ADC with Low-Noise In-Amp and Embedded Reference |
| 文件： | 总18页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power, 16/24-Bit Sigma-Delta ADC with
Low-Noise In-Amp and Embedded Reference
Preliminary Technical Data
AD7792/AD7793
REFIN(+)/AIN3(+)
GND
AV
DD
REFIN(-)/AIN3(-)
FEATURES
Resolution:
V
BIAS
AD7792: 16-Bit
AD7793: 24-Bit
V
DD
BANDGAP
REFERENCE
GND
SERIAL
INTERFACE
AND
DOUT/RDY
DIN
AIN1(+)
Low Noise Programmable Gain Instrumentation-Amp
RMS noise: 80 nV (Gain = 64)
Bandgap Reference with 5ppm/ C Drift typ
Power
Supply: 2.7 V to 5.25 V operation
Normal: 400 µA typ
SIGMA DELTA
ADC
IN-AMP
MUX
AIN1(-)
AIN2(+)
SCLK
CS
CONTROL
LOGIC
AIN2(-)
V
GND
DD
INTERNAL
CLOCK
DVDD
IOUT1
IOUT2
AD7792/AD7793
CLK
Power-down: 1 µA max
Update Rate: 4 Hz to 500 Hz
Figure 1.
Simultaneous 50 Hz/60 Hz Rejection
Internal Clock Oscillator
GENERAL DESCRIPTION
Programmable Current Sources (10 µA/200 µA/1 mA)
On-Chip Bias Voltage Generator
100 nA Burnout Currents
Independent Interface Power Supply
16-Lead TSSOP Package
The AD7792/AD7793 is a low power, complete analog front end
for low frequency measurement applications. The
AD7792/AD7793 contains a low noise 16/24-bit ∑-∆ ADC with
three differential analog inputs. The on-chip low noise
instrumentation amplifier means that signals of small
amplitude can be interfaced directly to the ADC. With a gain
setting of 64, the rms noise is 80 nV when the update rate equals
16.6 Hz.
INTERFACE
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
The device contains a precision low noise, low drift internal
bandgap reference for absolute measurements. An external
reference can also be used if ratiometric measurements are re-
quired. On-chip programmable excitation current sources can
be used to supply a constant current to RTDs and thermistors
while the 100 nA burnout currents can be used to ensure that
the sensors connected to the ADC are not burnt out. For ther-
mocouple applications, the on-chip bias voltage generator steps
up the common mode voltage from the thermocouple so that it
is within the ADC’s allowable range.
APPLICATIONS
Thermocouple Measurements
RTD Measurements
Thermistor Measurements
FUNCTIONAL BLOCK DIAGRAM
The device can be operated with the internal clock or, alterna-
tively, an external clock can be used if synchronizing several
devices. The output data rate from the part is software pro-
grammable and can be varied from 4 Hz to 500 Hz.
The part operates with a power supply from 2.7 V to 5.25 V. It
consumes a current of 450 uA maximum and is housed in a 16-
lead TSSOP package.
REV.PrF
6/04.
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD7792/AD7793
Preliminary Technical Data
TABLE OF CONTENTS
on/Reset = 0x5xx5(AD7792)/ 0x5xXXx5(AD7793))............ 17
ADC Circuit Information.............................................................. 19
Overview ..................................................................................... 19
Noise Performance..................................................................... 19
Digital Interface.......................................................................... 20
Single Conversion Mode ....................................................... 21
Continuous Conversion Mode............................................. 21
Continuous Read Mode ........................................................ 22
Circuit Description......................................................................... 23
Analog Input Channel ............................................................... 23
Bipolar/Unipolar Configuration .............................................. 23
Data Output Coding .................................................................. 23
Reference ..................................................................................... 23
VDD Monitor................................................................................ 24
Grounding and Layout .............................................................. 24
Outline Dimensions....................................................................... 26
ESD Caution................................................................................ 26
AD7792/AD7793—Specifications.................................................. 3
Timing Characteristics, .................................................................... 6
Absolute Maximum Ratings............................................................ 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
On-chip Registers ........................................................................... 12
Communications Register (RS2, RS1, RS0 = 0, 0, 0).............. 12
Status Register (RS2, RS1, RS0 = 0, 0, 0; Power-on/Reset =
0x80 (AD7792) / 0x88 (AD7793)) ........................................... 13
Mode Register (RS2, RS1, RS0 = 0, 0, 1; Power-on/Reset =
0x000A)........................................................................................ 13
Configuration Register (rs2, RS1, RS0 = 0, 1, 0; Power-
on/Reset = 0x0710) .................................................................... 15
Data Register (RS2, RS1, RS0 = 0, 1, 1; Power-on/Reset =
0x0000(00)) ................................................................................. 16
ID Register (RS2, RS1, RS0 = 1, 0, 0; Power-on/Reset = 0xXA
(ad7792) / 0xXB (ad7793))........................................................ 16
IO Register (RS2, RS1, RS0 = 1, 0, 1; Power-on/Reset = 0x00)
....................................................................................................... 16
OFFSET Register (RS2, RS1, RS0 = 1, 1, 0; Power-on/Reset =
0x8000(AD7792)/ 0x800000(AD7793)).................................. 17
FULL-SCALE Register (RS2, RS1, RS0 = 1, 1, 1; Power-
REVISION HISTORY
REV.PrF, June 2004: Initial Version
REV.PrF 6/04 | Page 2
Preliminary Technical Data
AD7792/AD7793
AD7792/AD7793—SPECIFICATIONS1
Table 1. (AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.)
Parameter
AD7792/AD7793B Unit
Test Conditions/Comments
ADC CHANNEL SPECIFICATION
Output Update Rate
4
Hz min nom
500
Hz max nom
ADC CHANNEL
No Missing Codes2
24
16
16
19
16
Bits min
Bits min
Bits p-p
Bits p-p
Bits p-p
fADC < 125 Hz. AD7793
Resolution (pk – pk)
Gain = 128, 16.6 Hz Update Rate, VREF = 2.5V
Gain = 1, 16.6 Hz Update Rate, VREF = 2.5V, AD7793
Gain = 1, 16.6 Hz Update Rate, VREF = 2.5V, AD7792
Output Noise and Update Rates
Integral Nonlinearity
See Tables in ADC
Description
15
25
3
ppm of FSR max 3.5 ppm of FSR typ, Gain = 1 to 32
ppm of FSR max 5 ppm of FSR typ, Gain = 64 and 128
µV typ
Offset Error3
Offset Error Drift vs. Temperature4
Full-Scale Error3, 5
10
10
0.5
3
nV/°C typ
µV typ
ppm/°C typ
ppm/°C typ
dB min
Gain Drift vs. Temperature4
Gain = 1 or 2
Gain = 4 to 128
100 dB typ, AIN = FS/2
Power Supply Rejection
ANALOG INPUTS
90
Differential Input Voltage Ranges
REFIN/Gain
V nom
REFIN = REFIN(+) – REFIN(–) or Internal Reference,
Gain = 1 to 128
Absolute AIN Voltage Limits2
Unbuffered Mode
GND – 30 mV
AVDD + 30 mV
GND + 100 mV
AVDD – 100 mV
GND + 300 mV
AVDD – 1.1
V min
V max
V min
V max
V min
V max
V min
Gain = 1 or 2
Gain = 1 or 2
Gain = 4 to 128
Gain = 4 to 128
Buffered Mode
In-Amp Enabled
Common Mode Voltage
Analog Input Current
0.5
Buffered Mode or In-Amp Enabled
Average Input Current2
Average Input Current Drift
Unbuffered Mode
200
2
pA max
pA/°C typ
Gain = 1 or 2. Input current varies with input
voltage.
Average Input Current
Average Input Current Drift
Normal Mode Rejection2
Internal Clock
400
50
nA/V typ
pA/V/°C typ
@ 50 Hz, 60 Hz
@ 50 Hz
@ 60 Hz
70
84
90
dB min
dB min
dB min
80 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 10106
100 dB typ, 50 1 Hz, FS[3:0] = 10016
100 dB typ, 60 1 Hz, FS[3:0] = 10006
External Clock
@ 50 Hz, 60 Hz
@ 50 Hz
@ 60 Hz
Common Mode Rejection
80
94
90
dB min
dB min
dB min
90 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 10106
100 dB typ, 50 1 Hz, FS[3:0] = 10016
100 dB typ, 60 1 Hz, FS[3:0] = 10006
AIN = +FS/2
@DC
@ 50 Hz, 60 Hz2
90
100
dB min
dB min
100 dB typ, FS[3:0] = 10106
50 1 Hz, 60 1 Hz, FS[3:0] = 10106
REV.PrF 6/04 | Page 3
AD7792/AD7793
Preliminary Technical Data
Parameter
AD7792/AD7793B Unit
Test Conditions/Comments
@ 50 Hz, 60 Hz2
100
dB min
50 1 Hz (FS[3:0] = 10016), 60 1 Hz (FS[3:0] =
10006)
REFERENCE
Internal Reference Initial Accuracy
Internal Reference Drift
1.17 0.01ꢀ
5
15
2
V min/max
ppm/°C typ
ppm/°C max
µV RMS
Internal Reference Noise
Gain = 1, Update Rate = 16.6 Hz. Includes ADC
Noise.
External REFIN Voltage
Reference Voltage Range2
2.5
0.1
V nom
V min
REFIN = REFIN(+) – REFIN(–)
V DD
V max
V min
V max
nA/V typ
nA/V/°C typ
Absolute REFIN Voltage Limits2
GND – 30 mV
AVDD + 30 mV
400
Average Reference Input Current
Average Reference Input Current Drift
Normal Mode Rejection2
0.03
Same as for Analog
Inputs
Common Mode Rejection
Same as for Analog
Inputs
EXCITATION CURRENT SOURCES
(IEXC1 and IEXC2)
Output Current
Initial Tolerance at 25°C
Drift
Initial Current Matching at 25°C
Drift Matching
Line Regulation (VDD)
Load Regulation
10/200/1000
5
200
1
20
2.1
0.3
AVDD – 0.6
AVDD – 1
GND – 30 mV
µA nom
ꢀ typ
ppm/°C typ
ꢀ typ
ppm/°C typ
ppm/V max
ppm/V typ
V max
Matching between IEXC1 and EXC2. VOUT = 0 V
AVDD = 5 V 5ꢀ. Typically 1.25 ppm/V
Output Compliance
10 µA or 200 µA Currents Selected
1 mA Currents Selected
V max
V min
TEMP SENSOR
Accuracy
TBD
°C typ
BIAS VOLTAGE GENERATOR
VBIAS
VBIAS Generator Start-Up Time
INTERNAL/EXTERNAL CLOCK
Internal Clock
AVDD/2
TBD
V nom
ms/nF typ
Dependent on the Capacitance on the AIN pin
Frequency
Duty Cycle
Drift
64 2ꢀ
50:50
0.01
KHz nom
ꢀ typ
ꢀ/°C typ
External Clock
Frequency
Duty Cycle
64
45:55
KHz nom
ꢀ typ
LOGIC INPUTS
All Inputs Except SCLK, DIN and CLK2
VINL, Input Low Voltage
0.8
0.4
2.0
V max
V max
V min
DVDD = 5 V
DVDD = 3 V
DVDD = 3 V or 5 V
VINH, Input High Voltage
SCLK and DIN (Schmitt-Triggered Input)2
VT(+)
VT(–)
VT(+) – VT(–)
1.4/2
0.8/1.4
0.3/0.85
V min/V max
V min/V max
V min/V max
DVDD = 5 V
DVDD = 5 V
DVDD = 5 V
REV.PrF 6/04 | Page 4
Preliminary Technical Data
AD7792/AD7793
Parameter
VT(+)
VT(–)
VT(+) - VT(–)
CLK2
AD7792/AD7793B Unit
Test Conditions/Comments
0.9/2
V min/V max
DVDD = 3 V
DVDD = 3 V
DVDD = 3 V
0.4/1.1
0.3/0.85
V min/V max
V min/V max
V
V
V
V
INL, Input Low Voltage
INL, Input Low Voltage
INH, Input High Voltage
INH, Input High Voltage
0.8
0.4
3.5
2.5
1
V max
V max
V min
V min
µA max
pF typ
DVDD = 5 V
DVDD = 3 V
DVDD = 5 V
DVDD = 3 V
VIN = DVDD or GND
All Digital Inputs
Input Currents
Input Capacitance
10
LOGIC OUTPUTS (Including CLK)
VOH, Output High Voltage2
VOL, Output Low Voltage2
VOH, Output High Voltage2
VOL, Output Low Voltage2
DVDD – 0.6
0.4
4
V min
V max
V min
V max
DVDD = 3 V, ISOURCE = 100 µA
DVDD = 3 V, ISINK = 100 µA
DVDD = 5 V, ISOURCE = 200 µA
0.4
RDY
DVDD = 5 V, ISINK = 1.6 mA (DOUT/
(CLK)
)/800 µA
Floating-State Leakage Current
Floating-State Output Capacitance
Data Output Coding
1
10
µA max
pF typ
Offset Binary
SYSTEM CALIBRATION2
Full-Scale Calibration Limit
Zero-Scale Calibration Limit
Input Span
1.05 x FS
-1.05 x FS
0.8 x FS
V max
V min
V min
V max
2.1 x FS
POWER REQUIREMENTS7
Power Supply Voltage
AVDD – GND
2.7/5.25
2.7/5.25
V min/max
V min/max
DVDD – GND
Power Supply Currents
IDD Current
150
175
µA max
µA max
125 µA typ, Unbuffered Mode, Ext. Reference
150 µA typ, Buffered Mode, In-Amp Bypassed, Ext
Ref
380
450
1
µA max
µA max
µA max
330 µA typ, In-Amp used, Ext. Ref
400 µA typ, In-Amp used, Int Ref
IDD (Power-Down Mode)
1 Temperature Range –40°C to +105°C.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Following a self-calibration, this error will be in the order of the noise for the programmed gain and update rate selected. A system calibration will completely remove
this error.
4 Recalibration at any temperature will remove these errors.
5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 4 V).
6 FS[3:0] are the four bits used in the mode register to select the output word rate.
7 Digital inputs equal to DVDD or GND.
REV.PrF 6/04 | Page 5
AD7792/AD7793
Preliminary Technical Data
TIMING CHARACTERISTICS4, 5
Table 2. (AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise
noted.)
Limit at TMIN, TMAX
(B Version)
Parameter
Unit
Conditions/Comments
SCLK High Pulsewidth
SCLK Low Pulsewidth
t3
t4
100
100
ns min
ns min
Read Operation
t1
0
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns max
ns min
CS Falling Edge to DOUT/RDY Active Time
DVDD = 4.75 V to 5.25 V
DVDD = 2.7 V to 3.6 V
SCLK Active Edge to Data Valid Delay7
DVDD = 4.75 V to 5.25 V
DVDD = 2.7 V to 3.6 V
Bus Relinquish Time after CS Inactive Edge
60
80
0
60
80
10
80
100
10
6
t2
8, 9
t5
t6
SCLK Inactive Edge to CS Inactive Edge
SCLK Inactive Edge to DOUT/RDY High
t7
Write Operation
t8
0
ns min
ns min
ns min
ns min
CS Falling Edge to SCLK Active Edge Setup Time7
Data Valid to SCLK Edge Setup Time
Data Valid to SCLK Edge Hold Time
CS Rising Edge to SCLK Edge Hold Time
t9
t10
t11
30
25
0
4 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10ꢀ to 90ꢀ of DVDD) and timed from a voltage level of 1.6 V.
5 See Figure 3 and Figure 4.
6 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
7 SCLK active edge is falling edge of SCLK.
8 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
9 RDY
RDY
returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while
is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
REV.PrF 6/04 | Page 6
Preliminary Technical Data
AD7792/AD7793
+1.6 V
50 pF
Figure 2. Load Circuit for Timing Characterization
CS (I)
t6
t1
t5
MSB
LSB
t7
DOUT/RDY (O)
t2
t3
SCLK (I)
t4
04227-0-003
I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram
CS (I)
t11
t8
SCLK (I)
DIN (I)
t9
t10
MSB
LSB
04227-0-004
I = INPUT, O = OUTPUT
Figure 4. Write Cycle Timing Diagram
REV.PrF 6/04 | Page 7
AD7792/AD7793
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 3. (TA= 25°C, unless otherwise noted.)
Parameter
Rating
AVDD to GND
DVDD to GND
–0.3 V to +7 V
–0.3 V to +7 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
10 mA
–40°C to +105°C
–65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Analog Input Voltage to GND
Reference Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
AIN/Digital Input Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
TSSOP
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
128°C/W
14°C/W
215°C
220°C
InfraRed (15 sec(
REV.PrF 6/04 | Page 8
Preliminary Technical Data
AD7792/AD7793
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
16
15
14
13
12
SCLK
CLK
DIN
DOUT/RDY
DVDD
AVDD
GND
CS
AD7792/
AD7793
TOP VIEW
IOUT1
AIN1(+)
(Not To Scale)
6
7
8
11
10
9
AIN1(-)
AIN2(+)
AIN2(-)
IOUT2
REFIN(-)/AIN3(-)
REFIN(+)/AIN3(+)
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No. Mnemonic
Function
1
SCLK
Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the
interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in
a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being trans-
mitted to or from the ADC in smaller batches of data.
2
3
CLK
CS
Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can
be disabled and the ADC can be driven by an external clock. This allows several ADCs to be driven from a
common clock, allowing simultaneous conversions to be performed.
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in
systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and
DOUT used to interface with the device.
4
IOUT1
Output of Internal Excitation Current Source.
The internal excitation current source can be made available at this pin. The excitation current source is
programmable so that the current can be 10 uA, 200 uA or 1 mA. Either IEXC1 or IEXC2 can be switched to this
output.
5
6
7
8
9
AIN1(+)
Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(-).
Analog Input. AIN1(–) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(-).
Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(-).
Analog Input. AIN2(–) is the negative terminal of the differential analog input pair AIN2(+)/AIN2(-).
Positive Reference Input/Analog Input.
AIN1(-)
AIN2(+)
AIN2(-)
REFIN(+)/AIN3(+)
An external reference can be applied between REFIN(+) and REFIN(-). REFIN(+) can lie anywhere between AVDD
and GND + 0.1 V. The nominal reference voltage (REFIN(+) – REFIN(–)) is 2.5 V, but the part functions with a
reference from 0.1 V to AVDD.
Alernatively, this pin can function as AIN3(+) where AIN3(+) is the positive terminal of the differential analog
input pair AIN3(+)/AIN3(-).
10
11
REFIN(-)/AIN3(-)
IOUT2
Negative Reference Input/Analog Input.
REFIN(-) is the negative reference input for REFIN. This reference input can lie anywhere between GND and
AVDD – 0.1 V.
This pin also functions as AIN3(-) which is the negative terminal of the differential analog input pair
AIN3(+)/AIN3(-).
Output of Internal Excitation Current Source.
The internal excitation current source can be made available at this pin. The excitation current source is
programmable so that the current can be 10 uA, 200 uA or 1 mA. Either IEXC1 or IEXC2 can be switched to this
output
12
13
14
GND
AVDD
DVDD
Ground Reference Point.
Supply Voltage, 2.7 V to 5.25 V.
Digital Interface Supply Voltage. The logic levels for the serial interface pins are related to this supply, which is
between 2.7 V and 5.25 V. The D VDD voltage in independent of the voltage on AVDD so, AVDD can equal 3V with
REV.PrF 6/04 | Page 9
AD7792/AD7793
Preliminary Technical Data
Pin
No. Mnemonic
Function
D VDD at 5V or vice versa.
15
DOUT/RDY
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose . It functions as a serial data output pin
to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip
data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the
completion of a conversion. If the data is not read after the conversion, the pin will go high before the next
update occurs.
The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available.
With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word
informa-tion is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge.
The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the DOUT/RDY
pin is three-stated but the RDY bit remains active.
16
DIN
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control
registers within the ADC, the register selection bits of the communications register identifying the appropriate
register.
REV.PrF 6/04 | Page 10
Preliminary Technical Data
AD7792/AD7793
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
REV.PrF 6/04 | Page 11
AD7792/AD7793
Preliminary Technical Data
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following
descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.
COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0)
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the com-
munications register. The data written to the communications register determines whether the next operation is a read or write operation,
and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected
register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of
the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications regis-
ter. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to
this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indi-
cate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit.
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
WEN(0)
R/W(0)
RS2(0)
RS1(0)
RS0(0)
CREAD(0)
0(0)
0(0)
Table 5. Communications Register Bit Designations
Bit Location
Bit Name
Description
CR7
WEN
Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually
occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay
at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits
will be loaded to the communications register.
CR6
R/W
A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this
position indicates that the next operation will be a read from the designated register.
CR5–CR3
CR2
RS2–RS0
CREAD
Register Address Bits. These address bits are used to select which of the ADC’s registers are being
selected during this serial interface communication. See Table 6.
Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the
serial interface is configured so that the data register can be continuously read, i.e., the contents of the
data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The commu-
nications register does not have to be written to for data reads. To enable continuous read mode, the
instruction 01011100 must be written to the communications register. To exit the continuous read
mode, the instruction 01011000 must be written to the communications register while the RDY pin is
low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the
instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on
DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to
the device.
CR1–CR0
0
These bits must be programmed to logic 0 for correct operation.
Table 6. Register Selection
RS2
RS1
RS0
Register
Register Size
0
0
0
0
0
0
0
0
1
Communications Register during a Write Operation
Status Register during a Read Operation
Mode Register
8-Bit
8-Bit
16-Bit
0
0
1
1
0
1
Configuration Register
Data Register
16-Bit
16 / 24-Bit
1
0
0
ID Register
8-Bit
1
0
1
IO Register
8-Bit
1
1
1
1
0
1
Offset Register
Full-Scale Register
16-Bit (AD7792)/24-Bit (AD7793)
16-Bit (AD7792)/24-Bit (AD7793)
REV.PrF 6/04 | Page 12
Preliminary Technical Data
AD7792/AD7793
STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; POWER-ON/RESET = 0x80 (AD7792) / 0x88 (AD7793))
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load bits RS2, RS1 and RS0 with 0. Table 7 outlines the bit designations for the status register.
SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The
number in brackets indicates the power-on/reset default status of that bit.
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RDY(1)
ERR(0)
0(0)
0(0)
0/1
CH2(0)
CH1(0)
CH0(0)
Table 7. Status Register Bit Designations
Bit Location
Bit Name
Description
SR7
RDY
Ready bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically
after the ADC data register has been read or a period of time before the data register is updated with a
new conversion result to indicate to the user not to read the conversion data. It is also set when the part
is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin
can be used as an alternative to the status register for monitoring the ADC for conversion data.
SR6
ERR
ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written
to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange,
underrange. Cleared by a write operation to start a conversion.
SR5-SR4
SR3
0
These bits are automatically cleared.
0/1
This bit is automatically cleared on the AD7792 and is automatically set on the AD7793.
These bits indicate which channel is being converted by the ADC.
SR2–SR0
CH2–CH0
MODE REGISTER (RS2, RS1, RS0 = 0, 0, 1; POWER-ON/RESET = 0x000A)
The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the oper-
ating mode, update rate and clock source. Table 8 outlines the bit designations for the mode register. MR0 through MR15 indicate the bit
locations, MR denoting the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in brackets indicates
the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the
bit.
RDY
MR15
MD2(0)
MR7
MR14
MD1(0)
MR6
MR13
MD0(0)
MR5
MR12
0(0)
MR11
0(0)
MR10
0(0)
MR9
0(0)
MR8
0(0)
MR4
0(0)
MR3
FS3(1)
MR2
FS2(0)
MR1
FS1(1)
MR0
FS0(0)
CLK1(0)
CLK0(0)
0(0)
Table 8. Mode Register Bit Designations
Bit Location
Bit Name
Description
MR15–MR13
MD2–MD0
Mode Select Bits. These bits select the operational mode of the AD7792/AD7793 (See
Table 9).
MR12-MR8
MR7-MR6
0
These bits must be programmed with a Logic 0 for correct operation.
CLK1-CLK0
These bits are used to select the clock source for the AD7792/AD7793. Either on on-chip 64 kHz clock
can be used or an external clock can be used. The ability to override use an external clock is useful as it
allows several AD7792/AD7793 devices to be synchronised. Also, 50 Hz/60 Hz is improved when an
accurate external clock drives the AD7792/AD7793.
CLK1 CLK0 ADC Clock Source
0
0
1
0
1
0
Internal 64 kHz Clock, Internal Clock is not available at the CLK pin
Internal 64 kHz Clock. This clock is made available at the CLK pin
External 64 kHz Clock used. An Exernal clock gives better 50 Hz/60 Hz rejection. The
external clock can have a 45:55 duty cycle.
1
1
External Clock used. This external clock is divided by 2 within the AD7792/AD7793.
This allows the user to supply a clock which has a duty cycle worse than a 45:55 duty
cycle to the AD7792/AD7793, for example, a 128 kHz clock.
MR5-MR4
0
These bits must be programmed with a Logic 0 for correct operation.
REV.PrF 6/04 | Page 13
AD7792/AD7793
Preliminary Technical Data
Bit Location
Bit Name
FS3-FS0
Description
MR3-MR0
Filter Update Rate Select Bits (see Table 10).
Table 9. Operating Modes
MD2
MD1
MD0
Mode
Continuous Conversion Mode (Default).
0
0
0
In continuous conversion mode, the ADC continuously performs conversions and places the result in the data
register. RDY goes low when a conversion is complete. The user can read these conversions by placing the
device in continuous read mode whereby the conversions are automatically placed on the DOUT line when
SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to
the communications register. After power-on, a channel change or a write to the Mode, Configuration or IO
Registers, the first conversion is available after a period 2/ fADC while subsequent conversions are available at a
frequency of fADC
.
0
0
1
Single Conversion Mode.
In single conversion mode, the ADC is placed in power-down mode when conversions are not being
performed. When single conversion mode is selected, the ADC powers up and performs a single conversion,
which occurs after a period 2/fADC. The conversion result in placed in the data register, RDY goes low, and the
ADC returns to power-down mode. The conversion remains in the data register and RDY remains active (low)
until the data is read or another conversion is performed.
0
0
1
1
1
0
0
1
0
Idle Mode.
In Idle Mode, the ADC Filter and Modulator are held in a reset state although the modulator clocks are still
provided
Power-Down Mode.
In power down mode, all the AD7792/AD7793 circuitry is powered down including the current sources,
burnout currents, bias voltage generator and CLKOUT circuitry.
Internal Zero-Scale Calibration.
An internal short is automatically connected to the enabled channel. A calibration takes 2 conversion cycles
to complete. RDY goes high when the calibration is initiated and returns low when the calibration is
complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed
in the offset register of the selected channel.
1
0
1
Internal Full-Scale Calibration.
The fullscale input voltage is automatically connected to the selected analog input for this calibration.
The full-scale error of the AD7792/AD7793 is calbrated at a gain of 1 using the internal reference in the
factory. When a channel is operated with a gain of 1 and the internal reference is selected, this factory-
calibrated value is loaded into the full-scale register when a full-scale calibration is initiated. When the gain
equals 1 and the external reference is selected, a calibration takes 2 conversion cycles to complete.
Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a
system full-scale calibration can be performed.
For other gains, 4 conversion cycles are required to perform the fullscale calibration.
RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is
placed in idle mode following a calibration. The measured fullscale coefficient is placed in the fullscale
register of the selected channel.
A fullscale calibration is required each time the gain of a channel is changed.
System Offset Calibration.
User should connect the system zero-scale input to the .channel input pins as selected by the CH2-CH0 bits.
A system offset calibration takes 2 conversion cycles to complete. RDY goes high when the calibration is
initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a
calibration. The measured offset coefficient is placed in the offset register of the selected channel.
1
1
1
1
0
1
System Full-Scale Calibration.
User should connect the system full-scale input to the .channel input pins as selected by the CH2-CH0 bits.
A calibration takes 2 conversion cycles to complete.. RDY goes high when the calibration is initiated and
returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The
measured fullscale coefficient is placed in the fullscale register of the selected channel.
A fullscale calibration is required each time the gain of a channel is changed.
REV.PrF 6/04 | Page 14
Preliminary Technical Data
AD7792/AD7793
Table 10. Update Rates Available
Tsettle
(ms)
x
FS3
0
FS2
0
FS1
0
FS0
0
fADC (Hz)
x
Rejection@ 50 Hz / 60 Hz (Internal Clock)
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
500
250
125
62.5
50
5
8
16
32
0
1
0
1
40
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
41.6
33.3
19.6
16.6
16.6
12.5
10
8.33
6.25
4.17
48
60
101
120
120
160
200
240
320
480
90 dB (60 Hz only)
84 dB (50 Hz only)
70 dB (50 Hz and 60 Hz)
67 dB (50 Hz and 60 Hz)
69 dB (50 Hz and 60 Hz)
73 dB (50 Hz and 60 Hz)
74 dB (50 Hz and 60 Hz)
79 dB (50 Hz and 60 Hz)
1
1
1
1
CONFIGURATION REGISTER (RS2, RS1, RS0 = 0, 1, 0; POWER-ON/RESET = 0x0710)
The configuration register is a 16-bit register from which data can be read or to which data can be written. This register is used to configure
the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain and select the ana-
log input channel. Table 11 outlines the bit designations for the filter register. CON0 through CON15 indicate the bit locations, CON
denoting the bits are in the configuration register. CON15 denotes the first bit of the data stream. The number in brackets indicates the
power-on/reset default status of that bit.
CON15
CON14
VBIAS0(0)
CON6
CON13
BO(0)
CON5
0(0)
CON12
U/B (0)
CON4
CON11
0(0)
CON10
G2(1)
CON9
G1(1)
CON8
G0(1)
VBIAS1(0)
CON7
CON3
0(0)
CON2
CH2(0)
CON1
CH1(0)
CON0
CH0(0)
REFSEL(0)
0(0)
BUF(1)
Table 11. Configuration Register Bit Designations
Bit Location
Bit Name
Description
CON15–CON14
VBIAS1-VBIAS0
Bias Voltage Enable. The bias voltage generator applies a bias voltage of VDD/2 to the selected
negative analog input terminals.
VBIAS1
VBIAS0
Bias Voltage
0
0
1
1
0
1
0
1
Bias Voltage Generator Disabled
Bias Voltage connected to AIN1(-)
Bias Voltage connected to AIN2(-)
Reserved
CON13
CON12
BO
Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the
signal path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents
can be enabled only when the buffer or In-Amp is active.
Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in
0x000000 output and a full-scale differential input will result in 0xFFFFFF output. Cleared by the
user to enable bipolar coding. Negative full-scale differential input will result in an output code of
0x000000, zero differential input will result in an output code of 0x800000, and a positive full-
scale differential input will result in an output code of 0xFFFFFF.
U/B
CON11
CON10-CON8
0
This bit must be programmed with a Logic 0 for correct operation.
Gain Select Bits.
G2-G0
REV.PrF 6/04 | Page 15
AD7792/AD7793
Preliminary Technical Data
Bit Location
Bit Name
Description
Written by the user to select the ADC input range as follows
G2 G1
G0
0
Gain
ADC Input Range (2.5V Reference)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1 (In-Amp not used)
2.5 V
1
2 (In-Amp not used)
1.25 V
0
4
625 mV
312.5 mV
156.2 mV
78.125 mV
39.06 mV
19.53 mV
1
8
0
16
32
64
128
1
0
1
CON7
REFSEL
Reference Select Bit. The reference source for the ADC is selected using this bit.
REFSEL
Reference Source
0
1
External Reference applied between REFIN(+) and REFIN(-)
Internal Reference Selected
CON6 - CON5
CON4
0
BUF
These bits must be programmed with a Logic 0 for correct operation.
Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in
unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in
buffered mode, allowing the user to place source impedances on the front end without
contributing gain errors to the system.
The buffer can be disabled when the gain equals 1 or 2. For higher gains, the buffer is
automaticallyenabled.
CON3
CON2-CON0
0
This bit must be programmed with a Logic 0 for correct operation.
Channel Select bits.
CH2-CH0
Written by the user to select the active analog input channel to the ADC.
CH2
0
CH1
0
CH0
0
Channel
Calibration Pair
AIN1(+) – AIN1(-)
AIN2(+) – AIN2(-)
AIN3(+) – AIN3(-)
AIN1(-) – AIN1(-)
Reserved
0
1
2
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
Reserved
1
1
0
Temp Sensor
Automatically Selects Gain = 1 and Internal
Reference
1
1
1
VDD Monitor
Automatically Selects Gain = 1/6 and 1.17 V
Reference
DATA REGISTER (RS2, RS1, RS0 = 0, 1, 1; POWER-ON/RESET = 0x0000(00))
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from
this register, the bit/pin is set.
RDY
ID REGISTER (RS2, RS1, RS0 = 1, 0, 0; POWER-ON/RESET = 0xXA (AD7792) / 0xXB (AD7793))
The Identification Number for the AD7792/AD7793 is stored in the ID register. This is a read-only register.
IO REGISTER (RS2, RS1, RS0 = 1, 0, 1; POWER-ON/RESET = 0x00)
The I/O register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the excitation
currents and select the value of the excitation currents. Table 12 outlines the bit designations for the IO register. IO0 through IO7 indicate
the bit locations, IO denoting the bits are in the IO register. IO7 denotes the first bit of the data stream. The number in brackets indicates the
power-on/reset default status of that bit.
REV.PrF 6/04 | Page 16
Preliminary Technical Data
AD7792/AD7793
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IEXCEN1(0)
IO0
0(0)
0(0)
0(0)
0(0)
IEXCDIR1(0)
IEXCDIR0(0)
IEXCEN0(0)
Table 12 Filter Register Bit Designations
Bit Location Bit Name Description
IO7-IO4
IO3-IO2
0
These bits must be programmed with a Logic 0 for correct operation.
Direction of Current Sources Select bits.
IEXCDIR1–
IEXCDIR0
IEXCDIR1 IEXCDIR0
Current Source Direction
0
0
1
1
0
1
0
1
Current Source IEXC1 connected to pin IOUT1, Current Source IEXC2
connected to pin IOUT2
Current Source IEXC1 connected to pin IOUT2, Current Source IEXC2
connected to pin IOUT1
Both Current Sources connected to pin IOUT1. Permitted when the
current sources are set to 10 uA or 200 uA only.
Both Current Sources connected to pin IOUT2. Permitted when the
current sources are set to 10 uA or 200 uA only.
IO1-IO0
IEXCEN1–
IEXCEN0
Direction of Current Sources Select bits.
IEXCEN1
IEXCEN0
Current Source Value
0
0
1
1
0
1
0
1
Excitation Currents Disabled
10 uA
200 uA
1 mA
OFFSET REGISTER (RS2, RS1, RS0 = 1, 1, 0; POWER-ON/RESET = 0x8000(AD7792)/ 0x800000(AD7793))
Each analog input channel has a dedicated offset register that holds the offset calibration coefficient for the channel. This register is 16
bits wide on the AD7792 and 24 bits wide on the AD7793 and, its power-on/reset value is 8000(00) hex. The offset register is used in con-
junction with its associated full-scale register to form a register pair. The power-on-reset value is automatically overwritten if an internal
or system zero-scale calibration is initiated by the user. The offset register is a read/write register. However, the AD7792/AD7793 must be
in idle mode or power down mode when writing to the offset register.
FULL-SCALE REGISTER (RS2, RS1, RS0 = 1, 1, 1; POWER-ON/RESET = 0x5XX5(AD7792)/ 0x5XXXX5(AD7793))
The full-scale registers is a 16-bit register on the AD7792 and a 24-bit register on the AD7793. The full-scale register holds the full-scale
calibration coefficient for the ADC. The AD7792/AD7793 has 3 full-scale registers, each channel having a dedicated full-scale register.
The full-scale registers are read/write registers, However, when writing to the full-scale registers, the ADC must be placed in power
down mode or idle mode. These registers are configured on power-on with factory-calibrated internal full-scale calibration coefficients,
the factory calibration being performed with the gain set to 1 and using the internal reference. Therefore, every device will have different
default coefficients. These default values are used when the device is operated with a gain of 1 and when the internal reference is selected.
For other gains or when the external reference is used at a gain of 1, these default coefficients will be automatically overwritten if an
internal or system full-scale calibration is initiated by the user. A full-scale calibration should be performed when the gain is changed.
REV.PrF 6/04 | Page 17
AD7792/AD7793
Preliminary Technical Data
GND
AV
DD
AD7792/AD7793
BANDGAP
REFERENCE
V
REFIN(+)
GND
REFIN(-)
BIAS
AV
DD
THERMOCOUPLE
JUNCTION
R
AIN1(+)
AIN1(-)
SERIAL
INTERFACE
AND
CONTROL
LOGIC
R
C
DOUT/RDY
DIN
SIGMA DELTA
ADC
IN-AMP
MUX
AIN2(+)
AIN2(-)
SCLK
CS
GND
AV
REFIN(+)
DVDD
R
REF
DD
INTERNAL
CLOCK
REFIN(-)
IOUT2
CLK
Figure 12. Thermocouple Application using the AD7792/AD7793
GND
AV
DD
IOUT1
BANDGAP
REFERENCE
AD7792/AD7793
REFIN(+)
REFIN(-)
AV
DD
RL1
RL2
AIN1(+)
GND
SERIAL
INTERFACE
AND
CONTROL
LOGIC
DOUT/RDY
RTD
DIN
AIN1(-)
IOUT2
S I G M A D E LTA
ADC
IN-AMP
SCLK
CS
RL3
GND
INTERNAL
DVDD
CLOCK
REFIN(+)
REFIN(-)
R
REF
CLK
Figure 13. RTD Application using the AD7792/AD7793
REV.PrF 6/04 | Page 18
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