AD7687BRMZRL7 [ADI]
16-Bit, 1.5 LSB INL, 250 kSPS PulSAR™ Differential ADC in MSOP/QFN;
| 型号： | AD7687BRMZRL7 |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 1.5 LSB INL, 250 kSPS PulSAR™ Differential ADC in MSOP/QFN 光电二极管 转换器 |
| 文件： | 总27页 (文件大小：612K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 1.5 LSB INL, 250 kSPS PulSAR
Differential ADC in MSOP
Data Sheet
AD7687
FEATURES
TYPICAL APPLICATION CIRCUIT
0.5V TO 5V
2.5 TO 5V
16-bit resolution with no missing codes
Throughput: 250 kSPS
INL: ±0.4 LSB typ, ±1.5 LSB max (±23 ppm of FSR)
Dynamic range: 96.5 dB
SNR: 95.5 dB at 20 kHz
THD: −118 dB at 20 kHz
True differential analog input range
±±REF
VREF
0
VIO
1.8V TO VDD
REF VDD
SDI
SCK
SDO
CNV
IN+
AD7687
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
IN–
VREF
0
GND
0 ± to ±REF with ±REF up to ±DD on both inputs
No pipeline delay
Figure 1.
Single-supply 2.3 ± to 5.5 ± operation with
1.8 ±/2.5 ±/3 ±/5 ± logic interface
Proprietary serial interface: SPI/QSPI™/MICROWIRE/DSP
compatible
Daisy-chain multiple ADCs and BUSY indicator
Power dissipation
1.35 mW at 2.5 ±/100 kSPS, 4 mW at 5 ±/100 kSPS, and
1.4 μW at 2.5 ±/100 SPS
Standby current: 1 nA
10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP
Pin-for-pin compatible with AD7685, AD7686, and AD7688
APPLICATIONS
Battery-powered equipment
Data acquisitions
Instrumentation
Medical instruments
Process controls
GENERAL DESCRIPTION
The AD76871 is a 16-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single power supply, VDD, between 2.3 V to 5.5 V. It
contains a low power, high speed, 16-bit sampling ADC with no
missing codes, an internal conversion clock, and a versatile
serial interface port. The device also contains a low noise, wide
bandwidth, short aperture delay track-and-hold circuit. On the
CNV rising edge, the AD7687 the samples the voltage difference
The SPI-compatible serial interface also features the ability to
daisy-chain several ADCs on a single 3-wire bus and provides
an optional BUSY indicator by means of the SDI pin. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate
supply VIO.
The AD7687 comes in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +85°C.
between IN+ and IN− pins, which can range from −VREF to +VREF
.
Table 1. MSOP, LFCSP/SOT-23 16-Bit PulSAR® ADC
The reference voltage, VREF, is applied externally and can be set
up to the supply voltage.
Type
100 kSPS
AD7684
AD7683
250 kSPS
AD7687
AD7685
AD7694
500 kSPS
AD7688
AD7686
True Differential
Pseudo
Differential/Unipolar
Unipolar
The power consumption of the device scales linearly with
throughput.
AD7680
1 Protected by U.S. Patent 6,703,961.
Rev. E
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AD7687* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
TOOLS AND SIMULATIONS
• AD7685 IBIS Models
EVALUATION KITS
• AD7687 Evaluation Kit
REFERENCE DESIGNS
• CN0225
• Precision ADC PMOD Compatible Boards
REFERENCE MATERIALS
DOCUMENTATION
Technical Articles
Application Notes
• MS-1779: Nine Often Overlooked ADC Specifications
• MS-2210: Designing Power Supplies for High Speed ADC
Tutorials
• AN-931: Understanding PulSAR ADC Support Circuitry
• AN-932: Power Supply Sequencing
Data Sheet
• MT-074: Differential Drivers for Precision ADCs
• AD7687: 16-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential
ADC in MSOP Data Sheet
DESIGN RESOURCES
• AD7687 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Product Highlight
• [NO TITLE FOUND] Product Highlight
• 8- to 18-Bit SAR ADCs ... From the Leader in High
Performance Analog
• Lowest-Power 16-Bit ADC Optimizes Portable Designs
(eeProductCenter, 10/4/2006)
DISCUSSIONS
View all AD7687 EngineerZone Discussions.
User Guides
• UG-340: Evaluation Board for the 10-Lead Family 14-/16-/
18-Bit PulSAR ADCs
SAMPLE AND BUY
• UG-682: 6-Lead SOT-23 ADC Driver for the 8-/10-Lead
Visit the product page to see pricing options.
Family of 14-/16-/18-Bit PulSAR ADC Evaluation Boards
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
SOFTWARE AND SYSTEMS REQUIREMENTS
• AD7687 FMC-SDP Interposer & Evaluation Board / Xilinx
KC705 Reference Design
• BeMicro FPGA Project for AD7687 with Nios driver
DOCUMENT FEEDBACK
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AD7687
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver Amplifier Choice ........................................................... 17
Single-to-Differential Driver .................................................... 17
Voltage Reference Input ............................................................ 17
Power Supply............................................................................... 17
Supplying the ADC from the Reference.................................. 18
Digital Interface.......................................................................... 18
Applications....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Timing Specifications .................................................................. 6
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Terminology .................................................................................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 14
Circuit Information.................................................................... 14
Converter Operation.................................................................. 14
Typical Connection Diagram ................................................... 15
Analog Input ............................................................................... 16
CS
CS
CS
CS
Mode, 3-Wire Without BUSY Indicator ........................... 19
Mode, 3-Wire with BUSY Indicator .................................. 20
Mode, 4-Wire Without BUSY Indicator ........................... 21
Mode, 4-Wire with BUSY Indicator .................................. 22
Chain Mode Without BUSY Indicator.................................... 23
Chain Mode with BUSY Indicator........................................... 24
Applications Information.............................................................. 25
Layout .......................................................................................... 25
Evaluating the Performance of the AD7687............................... 25
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Rev. E | Page 2 of 26
Data Sheet
AD7687
REVISION HISTORY
12/15—Rev. D to Rev. E
4/15—Rev. C to Rev. D
Deleted Figure 1; Renumbered Sequentially .................................1
Changes to Features Section and General Description Section.......1
Change to Signal-to-(Noise + Distortion) Parameter, Table 2 .........4
Added Timing Diagrams Section....................................................7
Moved Figure 2 and Figure 3...........................................................7
Changes to Table 8 ............................................................................9
Changes to Figure 7 Caption, Figure 8 Caption, Figure 10
Caption, and Figure 11 Caption....................................................11
Added Theory of Operation Section ............................................14
Changes to Analog Input Section .................................................16
Changes to Drive Amplifier Choice Section, Table 10, Figure 30,
Voltage Reference Input Section, and Power Supply Section.........17
Changes to Supplying the ADC from the Reference Section
and Digital Interface Section .........................................................18
Added Patent Note, Note 1 ..............................................................1
Changes to SNR Degradation Equation, Driver Amplifier
Choice Section.................................................................................16
Changes to Ordering Guide...........................................................26
7/14—Rev. B to Rev. C
Deleted QFN...................................................................Throughout
Changed Application Diagram Section to Typical Application
Circuit Section...................................................................................1
Change to Features Section..............................................................1
Added Note 1.....................................................................................1
Changes to Figure 27 ......................................................................14
Changes to Evaluating the Performance of the AD7687
Section ..............................................................................................24
Updated Outline Dimensions........................................................25
Changes to Ordering Guide...........................................................26
CS
CS
Changed Mode, 3-Wire, No BUSY Indicator Section to
Mode, 3-Wire Without BUSY Indicator Section ........................19
CS
Changes to Mode, 3-Wire Without BUSY Indicator Section...19
8/11—Rev. A to Rev. B
Changes to Table 7 ............................................................................7
Changes to Ordering Guide...........................................................26
CS
Changes to Mode, 3-Wire with BUSY Indicator Section......20
CS CS
Changed Mode, 4-Wire, No BUSY Indicator Section to
Mode, 4-Wire Without BUSY Indicator Section ........................21
CS
Changes to Mode, 4-Wire Without BUSY Indicator Section ...21
2/11—Rev. 0 to Rev. A
CS
Changes to Mode, 4-Wire with BUSY Indicator Section..........22
Deleted QFN in Development Note ............................Throughout
Changes to Table 6 ............................................................................7
Added Thermal Resistance Section and Table 7...........................7
Changes to Figure 6 and Table 8 .....................................................8
Updated Outline Dimensions........................................................25
Changes to Ordering Guide...........................................................26
Changed Chain Mode, No BUSY Indicator Section to Chain
Mode Without BUSY Indicator Section.......................................23
Changes to Chain Mode Without BUSY Indicator Section,
Figure 42 Caption, and Figure 43 Caption...................................23
Changes to Chain Mode with BUSY Indicator Section .............24
Changes to Layout Section.............................................................25
Changed Application Hints Section to Application
4/05—Revision 0: Initial Version
Recommendations Section ............................................................25
Changes to Ordering Guide...........................................................26
Rev. E | Page 3 of 26
AD7687
Data Sheet
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range
IN+ − IN−
IN+ and IN−
IN+ and IN−
fIN = 250 kHz
Acquisition phase
−VREF
−0.1
0
+VREF
VREF + 0.1
VREF/2 + 0.1
V
V
V
dB
nA
Absolute Input Voltage
Common-Mode Input Range
Analog Input CMRR
Leakage Current at 25°C
Input Impedance
VREF/2
65
1
See the Analog Input section
ACCURACY
No Missing Codes
16
−1
−1.5
Bits
Differential Linearity Error
Integral Linearity Error
Transition Noise
Gain Error2, TMIN to TMAX
Gain Error Temperature Drift
Offset Error2, TMIN to TMAX
0.4
0.4
0.35
2
0.3
0.1
0.7
0.3
+1
+1.5
LSB1
LSB
LSB
LSB
ppm/°C
mV
mV
ppm/°C
LSB
REF = VDD = 5 V
6
VDD = 4.5 V to 5.5 V
VDD = 2.3 V to 4.5 V
1.6
3.5
Offset Temperature Drift
Power Supply Sensitivity
0.05
VDD = 5 V ± 5%
THROUGHPUT
Conversion Rate
VDD = 4.5 V to 5.5 V
VDD = 2.3 V to 4.5 V
Full-scale step
0
0
250
200
1.8
kSPS
kSPS
µs
Transient Response
AC ACCURACY
Dynamic Range
Signal-to-Noise Ratio
VREF = 5 V
95.8
94
92
96.5
95.5
92.5
−118
−118
95
36.5
92.5
115
dB3
dB
dB
dB
dB
dB
dB
dB
dB
fIN = 20 kHz, VREF = 5 V
fIN = 20 kHz, VREF = 2.5 V
fIN = 20 kHz
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion) Ratio
fIN = 20 kHz
fIN = 20 kHz, VREF = 5 V
fIN = 20 kHz, VREF = 5 V, −60 dB input
fIN = 20 kHz, VREF = 2.5 V
94
92
Intermodulation Distortion4
1 LSB means least significant bit. With the 5 V input range, one LSB is 152.6 µV.
2 See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
3 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full-scale.
Rev. E | Page 4 of 26
Data Sheet
AD7687
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = −40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
Test Conditions/Comments
250 kSPS, REF = 5 V
VDD = 5 V
Min
Typ
Max
Unit
0.5
VDD + 0.3
V
µA
50
2
2.5
MHz
ns
−0.3
0.7 × VIO
−1
+0.3 × VIO
VIO + 0.3
+1
V
V
µA
µA
VIH
IIL
IIH
−1
+1
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Serial 16-bits twos complement
Conversion results available immediately
after completed conversion
VOL
VOH
ISINK = 500 µA
ISOURCE = −500 µA
0.4
V
V
VIO − 0.3
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current1, 2
Power Dissipation
Specified performance
Specified performance
2.3
2.3
1.8
5.5
V
V
V
nA
µW
mW
mW
mW
mW
VDD + 0.3
VDD + 0.3
50
VDD and VIO = 5 V, 25°C
1
VDD = 2.5 V, 100 SPS throughput
VDD = 2.5 V, 100 kSPS throughput
VDD = 2.5 V, 200 kSPS throughput
VDD = 5 V, 100 kSPS throughput
VDD = 5 V, 250 kSPS throughput
1.4
1.35
2.7
4
5.5
12.5
TEMPERATURE RANGE3
Specified Performance
TMIN to TMAX
−40
+85
°C
1 With all digital inputs forced to VIO or GND as required.
2 During acquisition phase.
3 Contact sales for extended temperature range.
Rev. E | Page 5 of 26
AD7687
Data Sheet
TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter
Symbol
tCONV
tACQ
Min
0.5
1.8
4
Typ
Max
Unit
µs
CONVERSION TIME: CNV RISING EDGE TO DATA AVAILABLE
ACQUISITION TIME
2.2
µs
TIME BETWEEN CONVERSIONS
CNV PULSE WIDTH (CS MODE)
tCYC
µs
tCNVH
tSCK
10
ns
SCK PERIOD
CS Mode
15
ns
Chain Mode
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
17
18
19
20
ns
ns
ns
ns
SCK TIME
Low
High
tSCKL
tSCKH
7
7
ns
ns
SCK FALLING EDGE
To Data Remains Valid
To Data Valid Delay
tHSDO
tDSDO
5
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
14
15
16
17
ns
ns
ns
ns
CNV OR SDI
Low to SDO D15 MSB Valid (CS Mode)
VIO Above 4.5 V
tEN
15
18
22
25
ns
ns
ns
ns
VIO Above 2.7 V
VIO Above 2.3 V
High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
tDIS
SDI
Valid Setup Time from CNV Rising Edge (CS Mode)
Valid Hold Time from CNV Rising Edge (CS Mode)
Valid Setup Time from SCK Falling Edge (Chain Mode)
Valid Hold Time from SCK Falling Edge (Chain Mode)
High to SDO High (Chain Mode with BUSY indicator)
VIO Above 4.5 V
tSSDICNV
tHSDICNV
tSSDISCK
tHSDISCK
tDSDOSDI
15
0
ns
ns
ns
ns
3
4
15
26
ns
ns
VIO Above 2.3 V
SCK
Valid Setup Time from CNV Rising Edge (Chain Mode)
Valid Hold Time from CNV Rising Edge (Chain Mode)
tSSCKCNV
tHSCKCNV
5
5
ns
ns
Rev. E | Page 6 of 26
Data Sheet
AD7687
−40°C to +85°C, VDD = 2.3 V to 4.5 V, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 2 and Figure 3 for load conditions.
Table 5.
Parameter
Symbol
tCONV
tACQ
Min
0.7
1.8
5
Typ
Max
Unit
µs
CONVERSION TIME: CNV RISING EDGE TO DATA AVAILABLE
ACQUISITION TIME
3.2
µs
TIME BETWEEN CONVERSIONS
CNV PULSE WIDTH (CS MODE)
tCYC
µs
tCNVH
tSCK
10
ns
SCK PERIOD
CS Mode
25
ns
Chain Mode
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
29
35
40
ns
ns
ns
SCK TIME
Low
High
tSCKL
tSCKH
12
12
ns
ns
SCK FALLING EDGE
To Data Remains Valid
To Data Valid Delay
tHSDO
tDSDO
5
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
24
30
35
ns
ns
ns
CNV OR SDI
Low to SDO D15 MSB Valid (CS Mode)
VIO Above 2.7 V
tEN
18
22
25
ns
ns
ns
VIO Above 2.3 V
High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
tDIS
SDI
Valid Setup Time from CNV Rising Edge (CS Mode)
Valid Hold Time from CNV Rising Edge (CS Mode)
Valid Setup Time from SCK Falling Edge (Chain Mode)
Valid Hold Time from SCK Falling Edge (Chain Mode)
High to SDO High (Chain Mode with BUSY indicator)
SCK
tSSDICNV
tHSDICNV
tSSDISCK
tHSDISCK
tDSDOSDI
30
0
ns
ns
ns
ns
ns
5
4
36
Valid Setup Time from CNV Rising Edge (Chain Mode)
Valid Hold Time from CNV Rising Edge (Chain Mode)
tSSCKCNV
tHSCKCNV
5
8
ns
ns
Timing Diagrams
70% VIO
500µA
I
OL
30% VIO
tDELAY
tDELAY
1
1
2V OR VIO – 0.5V
2V OR VIO – 0.5V
1.4V
TO SDO
2
2
0.8V OR 0.5V
0.8V OR 0.5V
C
L
50pF
1
2V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
2
500µA
I
OH
Figure 2. Load Circuit for Digital Interface Timing
Figure 3. Voltage Levels for Timing
Rev. E | Page 7 of 26
AD7687
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Analog Inputs
IN+1, IN−1
Rating
GND − 0.3 V to VDD + 0.3 V
or 130 mA
GND − 0.3 V to VDD + 0.3 V
Table 7. Thermal Resistance
Package Type
10-Lead LFCSP
10-Lead MSOP
θJA
84
200
θJC
Unit
°C/W
°C/W
REF
2.96
44
Supply Voltages
VDD, VIO to GND
VDD to VIO
−0.3 V to +7 V
7 V
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
Lead Temperature Range
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
ESD CAUTION
JEDEC J-STD-20
1 See the Analog Input section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. E | Page 8 of 26
Data Sheet
AD7687
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
VDD
IN+
1
2
3
4
5
10 VIO
REF
VDD
1
2
10 VIO
9
8
7
6
SDI
AD7687
TOP VIEW
(Not to Scale)
9
8
7
6
SDI
AD7687
TOP VIEW
(Not to Scale)
SCK
SDO
CNV
IN+ 3
IN– 4
SCK
SDO
CNV
IN–
GND
GND 5
NOTES
1. FOR THE LFCSP ONLY, THE EXPOSED
PADDLE MUST BE CONNECTED TO GND.
Figure 4. 10-Lead MSOP Pin Configuration
Figure 5. 10-Lead LFCSP Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic Type1 Function
1
REF
AI
Reference Input Voltage. The REF range is from 0.5 V to VDD, referred to the GND pin. Place a 10 μF
decoupling capacitor as close to the pin as possible.
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
Power Supply.
AI
AI
P
Differential Positive Analog Input.
Differential Negative Analog Input.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates a conversion and selects
the interface mode: chain or CS (depending on the state of SDI). In CS mode, CNV enables the SDO pin
when low. In chain mode, the data is read while CNV is high.
DI
7
8
SDO
SCK
DO
DI
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. SDO also acts as
the BUSY indicator if the feature is enabled.
Serial Data Clock Input. This input primarily shifts data out on SDO when data is valid. In chain mode, the
state of SCK determines if the BUSY indicator feature is enabled. If SCK is low during the CNV rising edge,
the BUSY feature is disabled. If it is high during the CNV rising edge, the BUSY feature is enabled.
9
SDI
DI
Serial Data Input. This input serves multiple functions. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI
is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY
indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
EPAD
N/A
For the LFCSP only, the exposed paddle must be connected to GND.
1AI means analog input, DI means digital input, DO means digital output, P means power, and N/A means not applicable.
Rev. E | Page 9 of 26
AD7687
Data Sheet
TERMINOLOGY
Integral Nonlinearity Error (INL)
Effective Number of Bits (ENOB)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. Measure the deviation from the
middle of each code to the true straight line (see Figure 25).
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. The DNL is
the maximum deviation from this ideal value. It is often specified
in terms of resolution for which no missing codes are guaranteed.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in dB.
Zero Error
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Gain Error
The first transition (from 100…00 to 100…01) should occur at
a level ½ LSB above nominal negative full scale (−4.999924 V
for the 5 V range). The last transition (from 011…10 to
011…11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.999771 V for the 5 V range.) The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition
from the difference between the ideal levels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Spurious-Free Dynamic Range (SFDR)
Aperture Delay
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to acquire its
input accurately after a full-scale step function is applied.
Rev. E | Page 10 of 26
Data Sheet
AD7687
TYPICAL PERFORMANCE CHARACTERISTICS
1.5
1.5
1.0
POSITIVE INL = +0.32LSB
NEGATIVE INL = –0.41LSB
POSITIVE DNL = +0.27LSB
NEGATIVE DNL = –0.24LSB
1.0
0.5
0
0.5
0
–0.5
–0.5
–1.0
–1.5
–1.0
–1.5
0
16384
32768
CODE
49152
65535
0
16384
32768
CODE
49152
65535
Figure 6. Integral Nonlinearity vs. Code
Figure 9. Differential Nonlinearity vs. Code
300000
250000
200000
VDD = REF = 5V
VDD = REF = 2.5V
258680
200403
250000
200000
150000
100000
150000
100000
50000
0
50000
0
30721
47
29918
49
0
0
1049
43
1391
45
0
0
0
0
60
46
18
0
0
41
42
44
46
47
44
45
48
4A
4B
4C
CODE IN HEX
CODE IN HEX
Figure 7. Histogram of a DC Input at the Code Center, VDD = REF = 5 V
Figure 10. Histogram of a DC Input at the Code Center, VDD = REF = 2.5 V
0
0
8192 POINT FFT
32768 POINT FFT
VDD = REF = 2.5V
VDD = REF = 5V
–20
–20
fS = 250kSPS
fIN = 2.1kHz
SNR = 95.5dB
fS = 250kSPS
fIN = 2kHz
–40
–40
SNR = 92.8dB
THD = –118.3dB
2nd HARMONIC = –130dB
3rd HARMONIC = –122.7dB
THD = –115.9dB
2nd HARMONIC = –124dB
3rd HARMONIC = –119dB
–80
–60
–80
–60
–100
–100
–120
–140
–160
–180
–120
–140
–160
–180
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 8. FFT Plot, VDD = REF = 5 V
Figure 11. FFT Plot, VDD = REF = 2.5 V
Rev. E | Page 11 of 26
AD7687
Data Sheet
100
17.0
16.0
–100
–105
–110
–115
–120
–125
–130
SNR
SINAD
ENOB
95
90
85
15.0
14.0
13.0
THD
SFDR
70
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
200
125
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 15. THD, SFDR vs. Reference Voltage
100
–60
–70
VREF = 5V, –10dB
VREF = 2.5V, –10dB
95
90
85
80
75
70
VREF = 5V, –1dB
–80
VREF = 2.5V, –1dB
VREF = 5V, –1dB
VREF = 2.5V, –1dB
–90
–100
–110
–120
VREF = 2.5V, –10dB
VREF = 5V, –10dB
0
50
100
150
200
0
50
100
FREQUENCY (kHz)
150
FREQUENCY (kHz)
Figure 13. SINAD vs. Frequency
Figure 16. THD vs. Frequency
100
95
90
85
80
–90
–100
–110
–120
–130
VREF = 5V
VREF = 2.5V
VREF = 5V
VREF = 2.5V
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. SNR vs. Temperature
Figure 17. THD vs. Temperature
Rev. E | Page 12 of 26
Data Sheet
AD7687
100
1000
750
500
250
0
fS = 100kSPS
99
VDD = 5V
98
97
VREF = 5V
VDD = 2.5V
96
95
94
93
92
91
VREF = 2.5V
VIO
90
–10
–55
–35
–15
5
25
45
65
85
105
125
–8
–6
–4
–2
0
TEMPERATURE (°C)
INPUT LEVEL (dB)
Figure 21. Operating Current vs. Temperature
Figure 18. SNR vs. Input Level
6
4
1000
fS = 100kSPS
VDD
750
500
250
0
GAIN ERROR
2
0
–2
–4
–6
OFFSET ERROR
VIO
–55
–35
–15
5
25
45
65
85
105
125
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
TEMPERATURE (°C)
SUPPLY (V)
Figure 22. Offset Error and Gain Error vs. Temperature
Figure 19. Operating Current vs. Supply
25
1000
750
500
250
0
VDD = 2.5V, 85°C
20
15
10
5
VDD = 2.5V, 25°C
VDD = 5V, 85°C
VDD = 5V, 25°C
VDD = 3.3V, 85°C
VDD = 3.3V, 25°C
VDD + VIO
0
0
20
40
60
80
100
120
–55
–35
–15
5
25
45
65
85
105
125
SDO CAPACITIVE LOAD (pF)
TEMPERATURE (°C)
Figure 23. tDSDO Delay vs. Capacitance Load and Supply
Figure 20. Power-Down Current vs. Temperature
Rev. E | Page 13 of 26
AD7687
Data Sheet
THEORY OF OPERATION
IN+
SWITCHES CONTROL
CONTROL
MSB
LSB
LSB
SW+
SW–
32,768C 16,384C
4C
4C
2C
2C
C
C
C
C
BUSY
REF
COMP
LOGIC
GND
OUTPUT CODE
32,768C 16,384C
MSB
CNV
IN–
Figure 24. ADC Simplified Schematic
CONVERTER OPERATION
CIRCUIT INFORMATION
The AD7687 is a successive approximation ADC based on a
charge redistribution DAC. Figure 24 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
The AD7687 is a fast, low power, single-supply, precise 16-bit
ADC using a successive approximation architecture.
The AD7687 is capable of converting 250,000 samples per
second (250 kSPS) and powers down between conversions.
When operating at 100 SPS, for example, it typically consumes
1.35 µW, which is ideal for battery-powered applications.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Thus, the capacitor arrays function as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW− open first. The two
capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the inputs IN+ and IN− captured at the end of the
acquisition phase is applied to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and REF, the
comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4…VREF/65536). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the device returns to the acquisition phase and the control logic
generates the ADC output code and a BUSY signal indicator.
The AD7687 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7687 is specified for use from 2.3 V to 5.5 V and can be
interfaced to any of the 1.8 V to 5 V digital logic family. It is
housed in a 10-lead MSOP or in a tiny 10-lead LFCSP that saves
space and allows flexible configurations.
It is pin-for-pin-compatible with the AD7685, AD7686, and
AD7688.
Because the AD7687 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev. E | Page 14 of 26
Data Sheet
AD7687
Table 9. Output Codes and Ideal Input Voltages
Analog Input Digital Output Code
Transfer Functions
Figure 25 and Table 9 show the ideal transfer characteristic for
the AD7687.
Description
VREF = 5 V
Hexadecimal
7FFF1
FSR − 1 LSB
+4.999847 V
Midscale + 1 LSB +152.6 µV
Midscale 0 V
Midscale − 1 LSB −152.6 µV
0001
0000
FFFF
8001
80002
011...111
011...110
011...101
−FSR + 1 LSB
−FSR
−4.999847 V
−5 V
1 This is also the code for an overranged analog input (VIN+ − VIN− above
VREF − VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below
−VREF + VGND).
TYPICAL CONNECTION DIAGRAM
100...010
100...001
100...000
Figure 26 shows an example of the recommended connection
diagram for the AD7687 when multiple supplies are available.
–FSR
–FSR + 1 LSB
+
FSR – 1 LSB
–FSR + 0.5 LSB
+FSR – 1.5 LSB
ANALOG INPUT
Figure 25. ADC Ideal Transfer Function
1
≥7V
≥7V
REF
5V
2
10µF
100nF
1.8V TO VDD
100nF
33Ω
REF
VDD
VIO
SDI
0 TO VREF
IN+
IN–
3
2.7nF
4
SCK
≤–2V
5
3- OR 4-WIRE INTERFACE
AD7687
SDO
CNV
≥7V
GND
33Ω
VREF TO 0
3
2.7nF
4
≤–2V
1
2
3
4
5
SEE VOLTAGE INPUT REFERENCE SECTION FOR REFERENCE SELECTION.
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
SEE DRIVER AMPLIFIER CHOICE SECTION.
OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.
C
REF
Figure 26. Typical Connection Diagram with Multiple Supplies
Rev. E | Page 15 of 26
AD7687
Data Sheet
During the acquisition phase, the impedance of the analog
ANALOG INPUT
inputs (IN+ or IN−) can be modeled as a parallel combination
of capacitor, CPIN, and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is
typically 3 kΩ and is a lumped component made up of some
serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. RIN and CIN make a
1-pole, low-pass filter that reduces undesirable aliasing effects
and limits the noise.
Figure 27 shows an equivalent circuit of the input structure of
the AD7687.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN+ and IN−. Take care to ensure that the analog
input signal never exceeds the supply rails by more than 0.3 V
because this causes these diodes to begin to forward-bias and
start conducting current. These diodes can handle a forward-
biased current of 130 mA maximum. These overvoltage
conditions can occur if the supplies of the input buffer (U1)
differ from VDD. In such a case, use an input buffer with a
short-circuit current limitation to protect the device.
VDD
If the source impedance of the driving circuit is sufficiently low,
the AD7687 can be driven directly. Large source impedances
significantly affect the ac performance, especially the total
harmonic distortion (THD). The maximum source impedance
depends on the amount of THD that can be tolerated by the
AD7687. The THD degrades as a function of the source
impedance and the maximum input frequency, as shown in
Figure 29.
D1
C
IN
R
IN
IN+
OR IN–
C
PIN
D2
GND
Figure 27. Equivalent Analog Input Circuit
–60
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. This differential input
scheme allows for rejection of common-mode signals. Figure 28
shows the typical CMRR over frequency.
–70
–80
–90
90
VDD = 5V
R
R
= 250Ω
= 100Ω
S
80
–100
VDD = 2.5V
S
70
60
–110
–120
R
R
= 50Ω
= 33Ω
S
S
0
25
50
75
100
FREQUENCY (kHz)
Figure 29. THD vs. Analog Input Frequency and Source Resistance
50
40
1
10
100
FREQUENCY (kHz)
1000
Figure 28. Analog Input CMRR vs. Frequency
Rev. E | Page 16 of 26
Data Sheet
AD7687
DRIVER AMPLIFIER CHOICE
SINGLE-TO-DIFFERENTIAL DRIVER
Although the AD7687 is easy to drive, consider the following
when selecting a driver amplifier.
For applications using a single-ended analog signal, either bipolar
or unipolar, a single-ended-to-differential driver (like the one
shown in Figure 30) allows for a differential input into the part.
When provided a single-ended input signal, this configuration
The noise generated by the driver amplifier needs to be kept as low
as possible in order to preserve the SNR and transition noise
performance of the AD7687. The AD7687 has a noise much lower
than most of the other 16-bit ADCs and, therefore, can be driven
by a noisier op amp while preserving the same or better system
performance. The noise coming from the driver is filtered by the
AD7687 analog input circuit 1-pole, low-pass filter made by RIN
and CIN or by an external filter. Because the typical noise of the
AD7687 is 53 µV rms, the SNR degradation due to the amplifier is
produces a differential
VREF with midscale at VREF/2.
590Ω
10kΩ
ANALOG INPUT
(±10V, ±5V, ..)
U1
10kΩ
VREF
VREF
10µF
100nF
590Ω
590Ω
REF
IN+
AD7687
53
IN–
U2
10kΩ
10kΩ
SNRLOSS = 20log
VREF
π
2
)
532 + f−3dB
(
2NeN
100nF
2
Figure 30. Single-Ended-to-Differential Driver Circuit
where:
VOLTAGE REFERENCE INPUT
f
–3dB is either the input bandwidth in MHz of the AD7687 (2 MHz)
or the cutoff frequency of an external filter, if one is used.
N is the noise gain of the amplifier (for example, +1 in buffer
configuration).
The AD7687 voltage reference input, REF, has a dynamic input
impedance and must therefore be driven by a low impedance
source with sufficient decoupling between the REF and GND
pins (as explained in the Layout section).
eN is the equivalent input noise voltage of the op amp, in nV/√Hz.
For ac applications, ensure that the THD performance of the driver
is commensurate with the AD7687 and that the driver exceeds
the THD vs. frequency shown in Figure 16.
For optimum performance, drive the REF pin with a low output
impedance amplifier (such as the AD8031 or the AD8605) as a
reference buffer with a 10 µF (X5R, 0805 size) ceramic chip
decoupling capacitor.
For multichannel multiplexed applications, the driver amplifier
and the AD7687 analog input circuit must settle a full-scale step
onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). Settling
at 0.1% to 0.01% is more commonly specified in the amplifier
data sheet. This can differ significantly from the settling time at
a 16-bit level and must be verified prior to driver selection.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR431, ADR433,
ADR434, or ADR435 reference.
If desired, smaller reference decoupling capacitor values down
to 2.2 µF can be used with a minimal impact on performance,
especially DNL.
Table 10. Recommended Driver Amplifiers.
Amplifier
AD8021
AD8022
AD8031
AD8519
Typical Application
Very low noise and high frequency
Low noise and high frequency
High frequency and low power
Small, low power and low frequency
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
AD8605, AD8615 5 V single-supply, low power
POWER SUPPLY
AD8655
5 V single-supply, low noise
The AD7687 is specified for use over a wide operating range of
2.3 V to 5.5 V. Unlike other low voltage converters, it has a low
enough noise to design a 16-bit resolution system with low
voltage supplies while maintaining respectable performance. It
uses two power supply pins: a core supply, VDD, and a digital
input/output interface supply, VIO. VIO allows direct interface
with any logic between 1.8 V and VDD. VIO and VDD can be
powered by the same source, reducing the number of supplies
required in the overall design. The AD7687 is independent of
power supply sequencing between VIO and VDD.
ADA4841-2
ADA4941-1
Very low noise, small, and low power
Very low noise, low power single-ended-to-
differential
OP184
Low power, low noise, and low frequency
Rev. E | Page 17 of 26
AD7687
Data Sheet
Additionally, it is resistant to power supply variations over a wide
frequency range. Figure 31 shows the power supply rejection
ration (PSRR) of the device over frequency.
5V
5V
10
5V 10k
1F
AD8031 10F
1F
100
95
1
VDD = 5V
90
REF
VDD
VIO
85
80
75
AD7687
1
OPTIONAL REFERENCE BUFFER AND FILTER.
VDD = 2.5V
70
Figure 33. Example of Application Circuit
65
60
DIGITAL INTERFACE
Though the AD7687 has a reduced number of pins, it offers
flexibility in its serial interface modes.
55
50
1
10
100
1000
10000
CS
When in mode, the AD7687 is compatible with SPI, QSPI,
FREQUENCY (kHz)
digital hosts, and DSPs, such as the Blackfin® processors or the
high performance, mixed-signal DSP family. In this mode, the
AD7687 uses either a 3-wire or a 4-wire interface. A 3-wire
interface using the CNV, SCK, and SDO signals minimizes
wiring connections and is useful, for instance, in isolated
applications. A 4-wire interface using the SDI, CNV, SCK, and
SDO signals allows CNV, which initiates the conversions, to be
independent of the readback timing (SDI). This is useful in low
jitter sampling or simultaneous sampling applications.
Figure 31. PSRR vs. Frequency
The AD7687 powers down automatically at the end of each
conversion phase, and consequentially its power consumption
scales linearly with the sampling rate, as shown in Figure 32.
This makes the device ideal for low sampling rate (even a few
SPS) and low battery-powered applications.
1000
VDD = 5V
When in chain mode, the AD7687 provides a daisy chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
VDD = 2.5V
10
The mode in which the device operates depends on the SDI
VIO
CS
level when the CNV rising edge occurs. The
mode is
selected if SDI is high, and the chain mode is selected if SDI is
low. The SDI hold time is such that when SDI and CNV are
connected together, the chain mode is always selected.
0.1
The initial state of SDO on power up is indeterminate. Therefore,
to put SDO in a known state, initiate a conversion and clock out
all data bits.
0.001
10
100
1000
10000
100000
1000000
SAMPLING RATE (SPS)
Figure 32. Operating Currents vs. Sampling Rate
In either mode, the AD7687 offers the option of forcing a start
bit in front of the data bits. Use this start bit as a BUSY signal
indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a BUSY indicator, the user must
time out the maximum conversion time prior to readback.
SUPPLYING THE ADC FROM THE REFERENCE
With its low operating current, the AD7687 can be supplied
directly by the reference circuitry (see Figure 33). The reference
line is driven by one of the following:
The BUSY indicator feature is enabled
The system power supply directly.
A reference voltage with enough current output capability,
such as the ADR435.
A reference buffer, such as the AD8031, which can also
filter the system power supply (see Figure 33).
CS
mode if CNV or SDI is low when the ADC
In the
conversion ends (see Figure 37 and Figure 41).
In the chain mode if SCK is high during the CNV rising
edge (see Figure 45).
Rev. E | Page 18 of 26
Data Sheet
AD7687
both SCK edges. Although the rising edge can capture the data,
a digital host using the SCK falling edge allows a faster reading
rate (provided it has an acceptable hold time). After the 16th
SCK falling edge, or when CNV goes high, whichever is earlier,
SDO returns to high impedance.
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7687 is connected
to an SPI-compatible digital host. Figure 34 shows the connection
diagram and Figure 35 gives the corresponding timing.
With SDI tied to VIO, a rising edge on CNV initiates a conversion,
CS
CONVERT
selects the
mode, and forces SDO to high impedance. Once
a conversion is initiated, it continues to completion irrespective
of the state of CNV. For instance, it can be useful to bring CNV
low to select other SPI devices, such as analog multiplexers, but
CNV must be returned high before the minimum conversion
time and held high until the maximum conversion time to
avoid the generation of the BUSY signal indicator (see tCONV in
Table 5). When the conversion is complete, the AD7687 enters
the acquisition phase and powers down. When CNV goes low,
the MSB is output onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
DIGITAL HOST
CNV
VIO
DATA IN
SDI
SDO
AD7687
SCK
CLK
CS
Figure 34. Mode, 3-Wire Without BUSY Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
14
15
16
D0
tHSDO
tSCKH
tDSDO
tEN
tDIS
SDO
D15
D14
D13
D1
CS
Figure 35. Mode, 3-Wire Without BUSY Indicator Serial Interface Timing (SDI High)
Rev. E | Page 19 of 26
AD7687
Data Sheet
bits are then clocked out, MSB first, by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the rising
edge can capture the data, a digital host using the SCK falling
edge allows a faster reading rate (provided it has an acceptable
hold time). After the optional 17th SCK falling edge, or when
CNV goes high, whichever is earlier, SDO returns to high
impedance.
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7687 is connected
to an SPI-compatible digital host having an interrupt input.
Figure 36 shows the connection diagram and Figure 37 gives
the corresponding timing.
With SDI tied to VIO, a rising edge on CNV initiates a conversion,
CS
selects the
mode, and forces SDO to high impedance. SDO
If multiple AD7687 devices are selected at the same time, the
SDO output pin handles this contention without damage or
induced latch-up. Keep this contention as short as possible to
limit extra power dissipation.
is maintained in high impedance until the completion of the
conversion irrespective of the state of CNV. Prior to the minimum
conversion time, CNV can be used to select other SPI devices,
such as analog multiplexers, but CNV must be returned low
before the minimum conversion time and held low until the
maximum conversion time to guarantee the generation of the
BUSY signal indicator (see tCONV in Table 5). When the conversion
is complete, SDO goes from high to low impedance. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. When using this option, select the value of the pull-
up resistor such that it maintains an appropriate rise time on the
SDO line for the application. This is a function of the resistance
of the pull-up and the capacitance of the SDO line. The AD7687
then enters the acquisition phase and powers down. The data
CONVERT
VIO
DIGITAL HOST
CNV
VIO
47kΩ
DATA IN
IRQ
SDI
SDO
AD7687
SCK
CLK
CS
Figure 36. Mode, 3-Wire with BUSY Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
15
16
17
tHSDO
tDSDO
tSCKH
tDIS
SDO
D15
D14
D1
D0
CS
Figure 37. Mode, 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
Rev. E | Page 20 of 26
Data Sheet
AD7687
time and held high until the maximum conversion time to
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7687 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing low its SDI input, which consequently outputs the
MSB onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can capture the data, a digital
host using the SCK falling edge allows a faster reading rate
(provided it has an acceptable hold time). After the 16th SCK
falling edge, or when SDI goes high, whichever is earlier, SDO
returns to high impedance and another AD7687 can be read.
This mode is usually used when multiple AD7687 devices are
connected to an SPI-compatible digital host.
Figure 38 shows a connection diagram example using two
AD7687 devices and Figure 39 gives the corresponding timing.
With SDI high, a rising edge on CNV initiates a conversion,
CS
selects the
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
CS2
CS1
CONVERT
DIGITAL HOST
CNV
CNV
SDI
SDO
SDI
SDO
AD7687
AD7687
SCK
SCK
DATA IN
CLK
CS
Figure 38. Mode, 4-Wire Without BUSY Indicator Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
tSSDICNV
CONVERSION
ACQUISITION
SDI(CS1)
tHSDICNV
SDI(CS2)
SCK
tSCK
tSCKL
1
2
3
14
15
16
17
18
30
31
32
tHSDO
tSCKH
tDSDO
D13
tDIS
tEN
SDO
D15
D14
D1
D0
D15
D14
D1
D0
CS
Figure 39. Mode, 4-Wire Without BUSY Indicator Serial Interface Timing
Rev. E | Page 21 of 26
AD7687
Data Sheet
When using this option, select the value of the pull-up resistor
such that it maintains an appropriate rise time on the SDO line
for the application. This is a function of the resistance of the
pull-up and the capacitance of the SDO line. The AD7687 then
enters the acquisition phase and powers down. The data bits are
then clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can capture the data, a digital host using the SCK falling edge
allows a faster reading rate (provided it has an acceptable hold
time). After the optional 17th SCK falling edge, or SDI going
high, whichever is earlier, the SDO returns to high impedance.
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7687 is connected to
an SPI-compatible digital host, which has an interrupt input, and it
is desired to keep CNV, which is used to sample the analog input,
independent of the signal used to select the data reading. This
requirement is particularly important in applications where low
jitter on CNV is desired.
Figure 40 shows the connection diagram and Figure 41 gives
the corresponding timing.
With SDI high, a rising edge on CNV initiates a conversion,
CS
selects the
mode, and forces SDO to high impedance. In this
CS1
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can
select other SPI devices, such as analog multiplexers, but SDI
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high to low impedance. With a
pull-up on the SDO line, this transition can act as an interrupt
signal to initiate the data readback controlled by the digital host.
CONVERT
VIO
DIGITAL HOST
CNV
47k
DATA IN
IRQ
SDI
SDO
AD7687
SCK
CLK
CS
Figure 40. Mode, 4-Wire with BUSY Indicator Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
SCK
SDO
1
2
3
15
16
17
tHSDO
tDSDO
tSCKH
tDIS
tEN
D15
D14
D1
D0
CS
Figure 41. Mode, 4-Wire with BUSY Indicator Serial Interface Timing
Rev. E | Page 22 of 26
Data Sheet
AD7687
and powers down. The remaining data bits stored in the
CHAIN MODE WITHOUT BUSY INDICATOR
internal shift register are then shifted out by subsequent SCK
falling edges. For each ADC, SDI feeds the input of the internal
shift register; these data bits are also shifted in by the SCK
falling edge. Each of the N ADCs in the chain outputs its data
MSB first. The data is valid on both SCK edges. Although the
rising edge can capture the data, a digital host using the SCK
falling edge allows a faster reading rate and, consequently, more
AD7687 devices in the chain (provided the digital host has an
acceptable hold time). After the 16 × Nth SCK falling edge or
CNV rising edge, whichever is earlier, SDO is driven low again.
The maximum conversion rate can be reduced due to the total
readback time. For example, using a digital host with a 3 ns set-
up time and 3 V interface, up to eight AD7687 devices daisy-
chained on a 3-wire port can be run at a maximum effective
conversion rate of 220 kSPS.
Use this mode to daisy-chain multiple AD7687 devices on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for isolated
multiconverter applications, or for systems with a limited
interfacing capacity (for example). Data readback is analogous
to clocking a shift register.
Figure 42 shows a connection diagram example using two
AD7687 devices and Figure 43 gives the corresponding timing.
When SDI and CNV are low, SDO is driven low. With SDI and
SCK low, a rising edge on CNV initiates a conversion, selects
the chain mode, and disables the BUSY indicator. In this mode,
CNV is held high during the conversion phase and the subsequent
data readback. When the conversion is complete, the MSB is
output onto SDO and the AD7687 enters the acquisition phase
CONVERT
CNV
CNV
DIGITAL HOST
SDI
SDO
SDI
SDO
AD7687
AD7687
DATA IN
A
B
SCK
SCK
CLK
Figure 42. Chain Mode Without BUSY Indicator Connection Diagram
SDI = 0
A
tCYC
CNV
tACQ
t
CONV
ACQUISITION
CONVERSION
tSSCKCNV
ACQUISITION
tSCK
tSCKL
SCK
1
A
B
2
3
A
B
14
15
16
17
18
30
31
32
tHSCKCNV
tSSDISCK
tSCKH
tHSDISC
tEN
D
D
15
D
14
D
D
13
13
D
1
1
D
0
SDO = SDI
A
A
A
A
B
tHSDO
tDSDO
15
D
14
D
B
D
0
D
15
D
14
D
A
1
D 0
A
SDO
B
B
A
A
B
Figure 43. Chain Mode Without BUSY Indicator Serial Interface Timing
Rev. E | Page 23 of 26
AD7687
Data Sheet
trigger the data readback controlled by the digital host. The
CHAIN MODE WITH BUSY INDICATOR
AD7687 then enters the acquisition phase and powers down.
The data bits stored in the internal shift register are then
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register;
these data bits are also shifted in by the SCK falling edge. Each
of the N ADCs in the chain outputs its data MSB first. The data
is valid on both SCK edges. Although the rising edge can capture
the data, a digital host using the SCK falling edge allows a faster
reading rate and, consequently, more AD7687 devices in the
chain (provided the digital host has an acceptable hold time).
After the optional (16 × N) + 1th SCK falling edge or CNV
rising edge, whichever is earlier, SDO is driven low again. The
maximum conversion rate may be reduced due to the total
readback time. For example, using a digital host with a 3 ns set-
up time and 3 V interface, up to eight AD7687 devices daisy-
chained on a 3-wire port can be run at a maximum effective
conversion rate of 220 kSPS.
This mode can also be used to daisy-chain multiple AD7687
devices on a 3-wire serial interface while providing a BUSY
indicator. This feature is useful for reducing component count
and wiring connections, for isolated multiconverter applications
or for systems with a limited interfacing capacity (for example).
Data readback is analogous to clocking a shift register.
Figure 44 shows a connection diagram example using three
AD7687 devices, and Figure 45 gives the corresponding timing.
When SDI and CNV are low, SDO is driven low. With SDI low
and SCK high, a rising edge on CNV initiates a conversion,
selects the chain mode, and enables the BUSY indicator feature.
In this mode, CNV is held high during the conversion phase
and the subsequent data readback. When all ADCs in the chain
have completed their conversions, the SDO pin of the ADC
closest to the digital host (see the AD7687 C in Figure 44) is driven
high. This transition on SDO can act as a BUSY indicator to
CONVERT
DIGITAL HOST
DATA IN
CNV
CNV
CNV
SDI
SDO
SDI
SDO
SDI
SDO
AD7687
AD7687
AD7687
A
B
C
SCK
SCK
SCK
IRQ
CLK
Figure 44. Chain Mode with BUSY Indicator Connection Diagram
tCYC
CNV = SDI
A
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSSCKCNV
tSCKH
SCK
1
2
3
A
4
15
16
17
18
19
31
32
33
34
35
47
48
49
tHSCKCNV
tSSDISCK
tSCKL
tDSDOSDI
tHSDISC
tEN
SDO = SDI
D
15
D
14
D
13
D
1
D
D
0
A
A
B
A
A
A
tHSDO
tDSDO
tDSDOSDI
tDSDOSDI
tDSDOSDI
SDO = SDI
B
D
15
D
D
14
D
13
B
D
D
1
0
D
15
D
14
D 1
A
D 0
A
C
B
B
B
B
A
A
tDSDOSDI
SDO
D
15
14
D
13
1
D
0
D
15
D
14
D
1
D
0
D
15
D
14
D
1
D 0
A
C
C
C
C
C
C
B
B
B
B
A
A
A
Figure 45. Chain Mode with BUSY Indicator Serial Interface Timing
Rev. E | Page 24 of 26
Data Sheet
AD7687
APPLICATIONS INFORMATION
LAYOUT
Providing a steady and stable reference voltage to the AD7687 is
critical for device operation. Prioritize design tasks aimed at
preventing voltage fluctuations at this node. Decouple the REF
pin, which has a dynamic input impedance, with minimal parasitic
inductances (see the Converter Operation Section). Achieve this
by placing the reference decoupling ceramic capacitor as close as
physically possible the REF and GND pins and connecting it
with wide, low impedance traces.
Limiting sources of noise on the analog signal nodes is
imperative in high precision ADC systems. The digital lines
controlling the AD7687 have the potential to radiate noise that
can couple into the analog signals; therefore, ensure that these
two types of signals are separated and confined to different
areas of boards housing the AD7687. Never allow fast switching
signals (such as CNV or clocks) to run near analog signal paths,
and avoid physical crossover of digital and analog signals. Do
not route digital lines under the AD7687 without a ground
plane providing adequate isolation between the two. To
facilitate these design tasks, the analog and digital pins are
located on separate sides of the device (see Figure 46).
Figure 46. Example of Layout of the AD7687 (Top Layer)
Printed circuit boards (PCBs) housing the AD7687 must contain
at least one ground plane. Connecting analog and digital ground
on the board is not required; however, connecting these planes
underneath the AD7687 is recommended.
Finally, decouple the power supply pins of the AD7687 (VDD
and VIO) with ceramic capacitors (typically 100 nF) placed
close to the AD7687 and connected using short and wide traces
to provide low impedance paths and reduce the effect of glitches
on the power supply lines.
Figure 47. Example of Layout of the AD7687 (Bottom Layer)
EVALUATING THE PERFORMANCE OF THE AD7687
Figure 46 and Figure 47 show an example of a layout following
these rules.
The EVAL-AD7687SDZ evaluation board documentation
outlines other recommended layouts for the AD7687. The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-SDP-CB1Z.
Rev. E | Page 25 of 26
AD7687
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 48. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
0.50 BSC
2.90
10
6
PIN 1 INDEX
EXPOSED
PAD
1.74
1.64
1.49
AREA
0.50
0.40
0.30
0.20 MIN
1
5
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 49. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Package Ordering
Model1, 2, 3
Integral Nonlinearity
1.5 LSB
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
10-Lead MSOP, Tube
10-Lead MSOP, Reel
10-Lead LFCSP_WD, Reel
10-Lead LFCSP_WD, Reel
Evaluation Board
Option
Quantity
Branding
C3Q
C3Q
C3Q
#C03
AD7687BRMZ
RM-10
50
AD7687BRMZRL7
AD7687BCPZ-R2
AD7687BCPZRL7
EVAL-AD7687SDZ
EVAL-SDP-CB1Z
1.5 LSB
1.5 LSB
1.5 LSB
RM-10
CP-10-9
CP-10-9
1,000
250
1,500
Controller Board
1 Z = RoHS Compliant Part, # denotes RoHS compliant product, may be top or bottom marked.
2 The EVAL-AD7687SDZ can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation and/or demonstration purposes.
3 The EVAL-SDP-CB1Z allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the SDZ designator.
©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02972-0-12/15(E)
Rev. E | Page 26 of 26
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