AD7688 [ADI]
16-Bit, +/-0.65 LSB INL, 500 kSPS PulSAR Differential ADC in MSOP/QFN; 16位+/- 0.65 LSB INL ， 500 kSPS时的PulSAR差分ADC ，采用MSOP / QFN
| 型号： | AD7688 |
| 厂家： | 
ADI |
| 描述： | 16-Bit, +/-0.65 LSB INL, 500 kSPS PulSAR Differential ADC in MSOP/QFN |
| 文件： | 总24页 (文件大小：527K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, +/-0.65 LSB INL, 500 kSPS PulSAR®
Differential ADC in MSOP/QFN
Preliminary Technical Data
AD7693
FEATURES
APPLICATION DIAGRAM
+2.5V TO +5V
+5V
16-bit resolution with no missing codes
Throughput: 500 kSPS
INL: +/-0.25 LSB typical, 0.65 LSB max ( 10 ppm of FSR)
Dynamic range: 96.5 dB typical @ 500 kSPS
SINAD: 96 dB typical @ 1 kHz, REF = 5V
THD: −120 dB typical @ 1 kHz. REF = 5V
True differential analog input range: VREF
0 V to VREF with VREF up to VDD on both inputs
No pipeline delay
VIO
SDI
+1.8V TO VDD
REF VDD
GND
IN+
IN–
3- OR 4-WIRE
SCK
SDO
CNV
INTERFACE
±10V, ±5V, ...
(SPI, DAISY CHAIN, CS)
ADA4941-1
AD7693
Figure 2.
Single-supply 5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible
Daisy-chain multiple ADCs and busy indicator
Power dissipation
4 mW @ 5 V/100 kSPS
40 μW @ 5 V/1 kSPS
Standby current: 1 nA
10-lead package: MSOP (MSOP-8 size) and
3 mm × 3 mm QFN1 (LFCSP) (SOT-23 size)
Table 1. MSOP, QFN1 (LFCSP)/SOT-23
14-/16-/18-Bit PulSAR ADC
400 kSPS
to
500 kSPS Driver
100
kSPS
250
kSPS
ADC
Type
18-Bit
AD7691
AD7690
ADA4941-1
ADA4841-x
ADA4941-1
ADA4841-x
16-Bit True
Differential
AD7684 AD7687
AD7688
AD7693
AD7686
16-Bit Pseudo AD7683 AD7685
ADA4841-x
Pin-for-pin compatible with the AD7687, AD7688 and 18-bit
AD7690 and AD7691
Differential/
Unipolar
AD7680 AD7694
14-Bit
AD7940 AD7942
AD7946
ADA4841-x
APPLICATIONS
1 QFN package in development. Contact sales for samples and availability.
Battery-powered equipment
Data acquisitions
GENERAL DESCRIPTION
Seismic data acquisition systems
DVMs
The AD7693 is a 16-bit, successive approximation, analog-to-
digital converter (ADC) that operates from a single power supply,
VDD. It contains a low power, high speed, 16-bit sampling ADC
with no missing codes, an internal conversion clock, and a
versatile serial interface port. On the CNV rising edge, it
samples the voltage difference between the IN+ and IN− pins.
The voltages on these pins swing in opposite phase between 0 V
and REF. The reference voltage, REF, is applied externally and
can be set up to the supply voltage, VDD.
Instrumentation
Medical instruments
Its power scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply.
The AD7693 is housed in a 10-lead MSOP or a 10-lead QFN1
(LFCSP) with operation specified from −40°C to +85°C.
Figure 1. Integral Nonlinearity vs. Code
1 QFN package in development. Contact sales for samples and availability.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD7693
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver Amplifier Choice ........................................................... 14
Single-to-Differential Driver .................................................... 15
Voltage Reference Input ............................................................ 15
Power Supply............................................................................... 15
Supplying the ADC from the Reference.................................. 16
Digital Interface.......................................................................... 16
Applications....................................................................................... 1
Application Diagram........................................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 12
Circuit Information.................................................................... 12
Converter Operation.................................................................. 12
Typical Connection Diagram ................................................... 13
Analog Inputs.............................................................................. 14
CS
CS
CS
CS
Mode 3-Wire, No BUSY Indicator..................................... 17
Mode 3-Wire with BUSY Indicator ................................... 18
Mode 4-Wire, No BUSY Indicator..................................... 19
Mode 4-Wire with BUSY Indicator ................................... 20
Chain Mode, NO BUSY Indicator ........................................... 21
Chain Mode with BUSY Indicator........................................... 22
Application Hints ........................................................................... 23
Layout .......................................................................................... 23
Evaluating the AD7693’s Performance.................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
Rev. PrB | Page 2 of 24
Preliminary Technical Data
AD7693
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION
18
Bits
ANALOG INPUT
Voltage Range
IN+ − (IN−)
IN+, IN−
IN+, IN−
fIN = 250 kHz
Acquisition phase
−VREF
−0.1
0
+VREF
VREF + 0.1
VREF/2 + 0.1
V
V
V
dB
nA
Absolute Input Voltage
Common-Mode Input Range
Analog Input CMRR
Leakage Current at 25°C
Input Impedance1
THROUGHPUT
VREF/2
65
1
Conversion Rate
Transient Response
ACCURACY
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Transition Noise
Gain Error3
Gain Error Temperature Drift
Zero Error3
Zero Temperature Drift
Power Supply Sensitivity
0
500
400
kSPS
ns
Full-scale step
REF = VDD = 5 V
VDD = 5 V ± 5%
16
−0.65
−0.5
Bits
LSB
LSB2
LSB
LSB
ppm/°C
LSB
ppm/°C
ppm
0.25
0.2
0.16
1.5
+0.65
+0.5
-30
+30
+10
0.5
−10
1
1
AC ACCURACY
Dynamic Range
Signal-to-Noise
VREF = 5 V
96
95.5
96.5
96
93
−120
−120
96
dB4
dB
dB
dB
dB
dB
dB
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 2.5 V
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 5 V
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Intermodulation Distortion5
95.5
TBD
1 See the Analog Inputs section.
2 LSB means least significant bit. With the 5 V input range, one LSB is 152.6 μV.
3 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
4 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
5 fIN1 = 21.4 kHz and fIN2 = 18.9 kHz, with each tone at −7 dB below full scale.
Rev. PrB | Page 3 of 24
AD7693
Preliminary Technical Data
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
Conditions/Comments
500 kSPS, REF = 5 V
VDD = 5V
Min
Typ
Max
Unit
0.5
VDD + 0.3
V
μA
100
9
2.5
MHz
ns
−0.3
0.7 × VIO
−1
+0.3 × VIO
VIO + 0.3
+1
V
V
μA
μA
VIH
IIL
IIH
−1
+1
DIGITAL OUTPUTS
Data Format
Serial 16 bits twos
complement
Pipeline Delay1
VOL
VOH
ISINK = +500 μA
ISOURCE = −500 μA
0.4
V
V
VIO − 0.3
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current2, 3
Power Dissipation
Specified performance
Specified performance
4. 5
2.3
1.8
5.5
V
V
V
nA
μW
mW
mW
nJ/sample
VDD + 0.3
VDD + 0.3
50
VDD and VIO = 5V, 25°C
100 SPS throughput
100 kSPS throughput
500 kSPS throughput
1
5
5
15
50
Energy per Conversion
TEMPERATURE RANGE4
Specified Performance
TMIN to TMAX
−40
+85
°C
1 Conversion results available immediately after completed conversion.
2 With all digital inputs forced to VIO or GND as required.
3 During acquisition phase.
4 Contact an Analog Devices sales representative for extended temperature range.
Rev. PrB | Page 4 of 24
Preliminary Technical Data
AD7693
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 4. 1
Parameter
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
Min
0.5
400
2.0
10
Typ
Max
Unit
μs
ns
μs
ns
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
1.6
15
ns
SCK Period (Chain Mode)
tSCK
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
17
18
19
20
7
ns
ns
ns
ns
ns
ns
ns
tSCKL
tSCKH
tHSDO
tDSDO
7
4
14
15
16
17
ns
ns
ns
ns
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 4.5 V
tEN
15
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with BUSY Indicator)
VIO Above 4.5 V
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
15
0
5
10
3
4
15
26
ns
ns
VIO Above 2.3 V
1 See Figure 3 and Figure 4 for load conditions.
Rev. PrB | Page 5 of 24
AD7693
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Analog Inputs
IN+,1 IN−1
Rating
GND − 0.3 V to VDD + 0.3 V
or 130 mA
GND − 0.3 V to VDD + 0.3 V
REF
Supply Voltages
VDD, VIO to GND
VDD to VIO
−0.3 V to +7 V
7 V
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
θJA Thermal Impedance (MSOP-10) 200°C/W
θJC Thermal Impedance (MSOP-10) 44°C/W
Lead Temperature Range
JEDEC J-STD-20
1 See the Analog Inputs section.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
500µA
I
OL
1.4V
TO SDO
C
L
50pF
500µA
I
OH
Figure 3. Load Circuit for Digital Interface Timing
70% VIO
30% VIO
tDELAY
tDELAY
1
1
2V OR VIO – 0.5V
2V OR VIO – 0.5V
2
2
0.8V OR 0.5V
0.8V OR 0.5V
1
2V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
2
Figure 4. Voltage Levels for Timing
Rev. PrB | Page 6 of 24
Preliminary Technical Data
AD7693
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
VDD
IN+
1
2
3
4
5
10 VIO
REF
VDD
IN+
1
2
3
4
5
10 VIO
9
8
7
6
SDI
AD7693
TOP VIEW
(Not to Scale)
9
8
7
6
SDI
SCK
SDO
CNV
AD7693
TOP VIEW
(Not to Scale)
SCK
SDO
CNV
IN–
IN–
GND
GND
NOTES
1. QFN PACKAGE IN DEVELOPMENT. CONTACT
SALES FOR SAMPLES AND AVAILABILITY.
Figure 5. 10-Lead MSOP Pin Configuration
Figure 6. 10-Lead QFN (LFCSP) Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
REF
AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This
pin should be decoupled closely to the pin with a 10 μF capacitor.
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
Power Supply.
AI
AI
P
Differential Positive Analog Input.
Differential Negative Analog Input.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions
and selects the interface mode of the part; chain or CS mode. In chain mode, the data should be
read when CNV is high. In CS mode, it enables the SDO pin when low.
DI
7
8
SDO
SCK
DO
DI
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this
clock.
9
SDI
DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC
as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a
data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line.
The digital data level on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV
can enable the serial output signals when low, and if SDI or CNV is low when the conversion is
complete, the BUSY indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V).
1AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. PrB | Page 7 of 24
AD7693
Preliminary Technical Data
TERMINOLOGY
Least Significant Bit (LSB)
Effective Number of Bits (ENOB)
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For an analog-to-digital con-
verter with N bits of resolution, the LSB expressed in volts is
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
VINp-p
LSB(V) =
2N
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 25).
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
Differential Nonlinearity Error (DNL)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Signal-to-(Noise + Distortion) Ratio (SINAD)
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Gain Error
The first transition (from 100 . . . 00 to 100 . . . 01) should occur
at a level ½ LSB above nominal negative full scale (−4.999847 V
for the 5 V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.999771 V for the 5 V range.) The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition
from the difference between the ideal levels.
Aperture Delay
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.
Rev. PrB | Page 8 of 24
Preliminary Technical Data
AD7693
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. Integral Nonlinearity vs. Code
Figure 10. Differential Nonlinearity vs. Code
Figure 11. Histogram of a DC Input at the Code Transition
Figure 8. Histogram of a DC Input at the Code Center
Figure 9. FFT Plot
Figure 12. SNR vs. Input Level
Rev. PrB | Page 9 of 24
AD7693
Preliminary Technical Data
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 16. THD, SFDR vs. Reference Voltage
Figure 17. THD vs. Temperature
Figure 18. THD vs. Frequency
Figure 14. SNR vs. Temperature
Figure 15. SINAD vs. Frequency
Rev. PrB | Page 10 of 24
Preliminary Technical Data
AD7693
1000
fS = 100kSPS
VDD
750
500
250
VIO
0
4.50
4.75
5.00
5.25
5.50
SUPPLY (V)
Figure 22. Offset and Gain Error vs. Temperature
Figure 19. Operating Currents vs. Supply
25
20
15
10
5
1000
750
500
250
0
VDD = 5V, 85°C
VDD = 5V, 25°C
VDD + VIO
0
0
20
40
60
80
100
120
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
SDO CAPACITIVE LOAD (pF)
Figure 20. Power-Down Currents vs. Temperature
Figure 23. tDSDO Delay vs. Capacitance Load and Supply
1000
750
500
250
–6
fS = 100kSPS
VDD
VIO
–55
–35
–15
5
25
45
65
85
105
125
SUPPLY (V)
Figure 21. Operating Currents vs. Temperature
Rev. PrB | Page 11 of 24
AD7693
Preliminary Technical Data
THEORY OF OPERATION
IN+
SWITCHES CONTROL
MSB
LSB
LSB
SW+
32,768C 16,384C
4C
4C
2C
2C
C
C
C
C
BUSY
REF
CONTROL
LOGIC
COMP
GND
OUTPUT CODE
32,768C 16,384C
MSB
SW–
CNV
IN–
Figure 24. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7693 is a fast, low power, single-supply, precise, 16-bit
ADC using a successive approximation architecture.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
The AD7693 is capable of converting 500,000 samples per
second (500 kSPS) and powers down between conversions.
When operating at 1 kSPS, for example, it consumes 40 μW
typically, ideal for battery-powered applications.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/32,768).
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the part returns to the
The AD7693 provides the user with an on-chip track-and-hold
and does not exhibit pipeline delay or latency, making it ideal
for multiple multiplexed channel applications.
The AD7693 is specified from 4.5 V to 5.5 V and can be
interfaced to any 1.8 V to 5 V digital logic family. It is housed in
a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines
space savings and allows flexible configurations.
It is pin-for-pin compatible with the 16-bit AD7687 and
AD7688 and with the 18-bit AD7690 and AD7691.
CONVERTER OPERATION
acquisition phase, and the control logic generates the ADC
output code and a busy signal indicator.
The AD7693 is a successive approximation ADC based on a
charge redistribution DAC. Figure 24 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors, which are
connected to the two comparator inputs.
Because the AD7693 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev. PrB | Page 12 of 24
Preliminary Technical Data
AD7693
TYPICAL CONNECTION DIAGRAM
Transfer Functions
Figure 26 shows an example of the recommended connection
diagram for the AD7693 when multiple supplies are available.
The ideal transfer characteristic for the AD7693 is shown in
Figure 25 and Table 7.
011...111
011...110
011...101
100...010
100...001
100...000
–FSR
–FSR + 1LSB
+FSR – 1LSB
+FSR – 1.5LSB
–FSR + 0.5LSB
ANALOG INPUT
Figure 25. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Analog Input
VREF = 5 V
Digital Output
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Code (Hex)
0x7FFF1
0x0001
+4.999847 V
+152.6 μV
0 V
0x0000
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
−152.6 μV
−4.999847 V
−5 V
0xFFFF
0x8001
0x80002
1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
1
V+
V+
REF
5V
2
10µF
100nF
1.8V TO VDD
100nF
15Ω
REF
VDD
VIO
SDI
0 TO V
REF
IN+
IN–
2.7nF
4
3
ADA4841-2
SCK
V–
V+
5
AD7693
3- OR 4-WIRE INTERFACE
SDO
CNV
GND
15Ω
V
TO 0
REF
2.7nF
4
3
ADA4841-2
V–
1
SEE REFERENCE SECTION FOR REFERENCE SELECTION.
2
3
4
5
C
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
REF
SEE TABLE 8 FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
SEE THE DIGITAL INTERFACE SECTION FOR MOST CONVENIENT INTERFACE MODE.
Figure 26. Typical Application Diagram with Multiple Supplies
Rev. PrB | Page 13 of 24
AD7693
Preliminary Technical Data
When the source impedance of the driving circuit is low, the
AD7693 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency.
ANALOG INPUTS
Figure 27 shows an equivalent circuit of the input structure of
the AD7693.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal does not exceed the supply rails by more
than 0.3 V because this causes the diodes to become forward
biased and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur when the input buffer’s
(U1) supplies are different from VDD. In such a case, for
example, an input buffer with a short-circuit, the current
limitation can be used to protect the part.
DRIVER AMPLIFIER CHOICE
Although the AD7693 is easy to drive, the driver amplifier must
meet the following requirements:
•
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7693. The noise coming from
the driver is filtered by the AD7693 analog input circuit’s
1-pole, low-pass filter made by RIN and CIN or by the
external filter, if one is used. Because the typical noise of
the AD7693 is 56 μV rms, the SNR degradation due to the
amplifier is
VDD
D1
D2
C
IN
R
IN
IN+
OR IN–
C
PIN
GND
Figure 27. Equivalent Analog Input Circuit
⎛
⎜
⎞
⎟
56
562 + f−3 dB (NeN )2 + f−3 dB (NeN )2
⎜
⎜
⎟
⎟
SNRLOSS = 20 log
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
π
π
⎜
⎜
⎟
⎟
2
2
⎝
⎠
where:
f
90
−3 dB is the input bandwidth in megahertz of the AD7693
V
= VDD = 5V
REF
(9 MHz) or the cutoff frequency of the input filter, if one is
used.
N is the noise gain of the amplifier (for example, 1 in
buffer configuration).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
85
80
75
70
65
60
55
50
45
40
•
•
For ac applications, the driver should have a THD
performance commensurate with the AD7693.
For multichannel multiplexed applications, the driver
amplifier and the AD7693 analog input circuit must settle
for a full-scale step onto the capacitor array at an 16-bit
level (0.0015%, 15 ppm). In the amplifier’s data sheet,
settling at 0.1% to 0.01% is more commonly specified. This
could differ significantly from the settling time at an 16-bit
level and should be verified prior to driver selection.
1
10
100
1000
10000
FREQUENCY (kHz)
Figure 28. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs (IN+ and IN−) can be modeled as a parallel combination
of the capacitor, CPIN, and the network formed by the series
connection of RIN and CIN. CPIN is primarily the pin capacitance.
IN is typically 600 Ω and is a lumped component made up of
serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
Table 8. Recommended Driver Amplifiers
Amplifier
ADA4941-1
ADA4841-x
AD8655
Typical Application
R
Very low noise, low power single to differential
Very low noise, small, and low power
5 V single supply, low noise
AD8021
AD8022
OP184
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. RIN and CIN make a 1-
pole, low-pass filter that reduces undesirable aliasing effects and
limits the noise.
AD8605, AD8615 5 V single supply, low power
Rev. PrB | Page 14 of 24
Preliminary Technical Data
AD7693
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially DNL.
SINGLE-TO-DIFFERENTIAL DRIVER
For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941-1 single-ended-to-differential
driver allows for a differential input into the part. The
schematic is shown in Figure 29.
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
R1 and R2 set the attenuation ratio between the input range and
the ADC range (VREF). R1, R2, and CF will be chosen depending
on the desired input resistance, signal bandwidth, antialiasing
and noise contribution. For example, for the 10 V range with a
4 kΩ impedance, R2 = 1 kΩ and R1 = 4 kΩ.
POWER SUPPLY
The AD7693 uses two power supply pins: a core supply, VDD,
and a digital input/output interface supply, VIO. VIO allows
direct interface with any logic between 1.8 V and VDD. To
reduce the supplies needed, the VIO and VDD pins can be tied
together. The AD7693 is independent of power supply sequencing
between VIO and VDD. Additionally, it is very insensitive to
power supply variations over a wide frequency range, as shown
in Figure 30.
R3 and R4 set the common mode on the IN− input, and R5 and
R6 set the common mode on the IN+ input of the ADC. The
common mode should be set close to VREF/2; however, if single
supply is desired, it can be set slightly above VREF/2 to provide
some headroom for the ADA4941-1 output stage. For example,
for the 10 V range with a single supply, R3 = 8.45 kΩ, R4 =
11.8 kΩ, R5 = 10.5 kΩ, and R6 = 9.76 kΩ.
90
V
= VDD = 5V
REF
85
80
75
70
65
60
55
50
45
40
R5
R6
R3
R4
+5V REF
+5.2V
10µF
+5.2V
100nF
100nF
15Ω
15Ω
REF
VDD
IN+
2.7nF
2.7nF
AD7693
IN–
GND
ADA4941
1
10
100
1000
10000
FREQUENCY (kHz)
±10V, ±5V, ...
Figure 30. PSRR vs. Frequency
R1
R2
C
F
The AD7693 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate. This makes the part ideal for low sampling
rate (even a few hertz) and low battery-powered applications.
Figure 29. Single-Ended-to-Differential Driver Circuit
VOLTAGE REFERENCE INPUT
The AD7693 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
10000
1000
VDD = 5V
100
When REF is driven by a very low impedance source, for
example, a reference buffer using the AD8031 or the AD8605, a
10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
10
VIO
1
0.1
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using low temperature drift ADR43x and ADR44x
references.
0.01
0.001
10
100
1k
10k
100k
1M
SAMPLING RATE (SPS)
Figure 31. Operating Currents vs. Sample Rate
Rev. PrB | Page 15 of 24
AD7693
Preliminary Technical Data
ADSP-219x. In this mode, the AD7693 can use either a 3-wire
or 4-wire interface. A 3-wire interface using the CNV, SCK, and
SDO signals minimizes wiring connections useful, for instance,
in isolated applications. A 4-wire interface using the SDI, CNV,
SCK, and SDO signals allows CNV, which initiates the
conversions, to be independent of the readback timing (SDI).
This is useful in low jitter sampling or simultaneous sampling
applications.
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7693, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 32. The reference line can be driven by
•
•
The system power supply directly.
A reference voltage with enough current output capability,
such as the ADR43x.
When in chain mode, the AD7693 provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
•
A reference buffer, such as the AD8031, which can also
filter the system power supply, as shown in Figure 32.
5V
The mode in which the part operates depends on the SDI level
5V
CS
when the CNV rising edge occurs. The
mode is selected if
10
5V 10k
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is selected.
10µF
1µF
AD8031
1µF
1
REF
VDD
VIO
In either mode, the AD7693 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must
timeout the maximum conversion time prior to readback.
AD7693
1
OPTIONAL REFERENCE BUFFER AND FILTER.
Figure 32. Example of Application Circuit
DIGITAL INTERFACE
The busy indicator feature is enabled
Though the AD7693 has a reduced number of pins, it offers
flexibility in its serial interface modes.
CS
mode if CNV or SDI is low when the ADC
•
In the
conversion ends (see Figure 36 and Figure 40).
In the chain mode if SCK is high during the CNV rising
edge (see Figure 44).
CS
When in
mode, the AD7693 is compatible with SPI, QSPI,
•
digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or
Rev. PrB | Page 16 of 24
Preliminary Technical Data
AD7693
subsequent SCK falling edges. The data is valid on both SCK
CS MODE 3-WIRE, NO BUSY INDICATOR
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16th SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 33, and the corresponding timing is given in
Figure 34.
With SDI tied to VIO, a rising edge on CNV initiates a
CONVERT
conversion, selects the
mode, and forces SDO to high
CS
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This could be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers; however, CNV must be
returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time to
avoid the generation of the busy signal indicator. When the
conversion is complete, the AD7693 enters the acquisition
phase and powers down. When CNV goes low, the MSB is
output onto SDO. The remaining data bits are clocked by
DIGITAL HOST
CNV
VIO
DATA IN
SDI
SDO
AD7693
SCK
CLK
CS
Figure 33. 3-Wire Mode Without Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
14
15
16
tHSDO
tSCKH
tDSDO
D13
tEN
tDIS
SDO
D15
D14
D1
D0
CS
Figure 34. 3-Wire Mode Without Busy Indicator Serial Interface Timing (SDI High)
Rev. PrB | Page 17 of 24
AD7693
Preliminary Technical Data
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge will allow a faster reading rate, provided it has an
acceptable hold time. After the optional 17th SCK falling edge,
or when CNV goes high, whichever is earlier, SDO returns to
high impedance.
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 35, and the
corresponding timing is given in Figure 36.
If multiple AD7693s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
With SDI tied to VIO, a rising edge on CNV initiates a
CS
conversion, selects the
mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high
CONVERT
VIO
DIGITAL HOST
CNV
VIO
SDI
SDO
DATA IN
IRQ
AD7693
SCK
impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7693 then
enters the acquisition phase and powers down. The data bits are
clocked out, MSB first, by subsequent SCK falling edges. The
CLK
CS
Figure 35. 3-Wire Mode with Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
15
16
17
tHSDO
tSCKH
tDSDO
D14
tDIS
SDO
D15
D1
D0
CS
Figure 36. 3-Wire Mode with Busy Indicator Serial Interface Timing (SDI High)
Rev. PrB | Page 18 of 24
Preliminary Technical Data
AD7693
time elapses and then held high for the maximum possible
CS MODE 4-WIRE, NO BUSY INDICATOR
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7693 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16th SCK falling edge, or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7693
can be read.
This mode is usually used when multiple AD7693s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7693s is shown in
Figure 37, and the corresponding timing is given in Figure 38.
With SDI high, a rising edge on CNV initiates a conversion,
selects the
mode, and forces SDO to high impedance. In this
CS
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
CS2
CS1
CONVERT
DIGITAL HOST
CNV
CNV
SDI
SDO
SDI
SDO
AD7693
AD7693
SCK
SCK
DATA IN
CLK
CS
Figure 37. 4-Wire Mode Without Busy Indicator Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
tSSDICNV
CONVERSION
ACQUISITION
SDI(CS1)
tHSDICNV
SDI(CS2)
SCK
tSCK
tSCKL
1
2
3
14
15
16
17
18
30
31
32
tHSDO
tSCKH
tDSDO
tDIS
tEN
SDO
D15
D14
D13
D1
D0
D16
D15
D1
D0
CS
Figure 38. 4-Wire Mode Without Busy Indicator Serial Interface Timing
Rev. PrB | Page 19 of 24
AD7693
Preliminary Technical Data
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7693
then enters the acquisition phase and powers down. The data
bits are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge will allow a faster reading rate, provided it has an
acceptable hold time. After the optional 17th SCK falling edge,
or SDI going high, whichever is earlier, SDO returns to high
impedance.
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 39, and the
corresponding timing is given in Figure 40.
CS1
CONVERT
With SDI high, a rising edge on CNV initiates a conversion,
CS
selects the
mode, and forces SDO to high impedance. In this
VIO
DIGITAL HOST
CNV
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
DATA IN
IRQ
SDI
SDO
AD7693
SCK
CLK
CS
Figure 39. 4-Wire Mode with Busy Indicator Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
SCK
SDO
1
2
3
15
16
17
tHSDO
tDSDO
tSCKH
tDIS
tEN
D15
D14
D1
D0
CS
Figure 40. 4-Wire Mode with Busy Indicator Serial Interface Timing
Rev. PrB | Page 20 of 24
Preliminary Technical Data
AD7693
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7693 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge will allow a faster
reading rate and consequently more AD7693s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate can be reduced due to the total
readback time.
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7693s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7693s is shown in
Figure 41, and the corresponding timing is given in Figure 42.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
CONVERT
CNV
CNV
DIGITAL HOST
AD7693
AD7693
SDI
SDO
SDI
SDO
DATA IN
A
B
SCK
SCK
CLK
Figure 41. Chain Mode Without Busy Indicator Connection Diagram
SDI = 0
A
tCYC
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
A
B
2
3
A
B
14
15
16
17
18
30
31
32
tHSCKCNV
tSSDISCK
tSCKH
tHSDISC
tEN
D
D
15
D
14
D
D
13
13
D
A
1
1
D
0
SDO = SDI
A
A
A
B
tHSDO
tDSDO
15
D
14
D
B
D
0
D
15
D
14
D
A
1
D 0
A
SDO
B
B
A
A
B
Figure 42. Chain Mode Without Busy Indicator Serial Interface Timing
Rev. PrB | Page 21 of 24
AD7693
Preliminary Technical Data
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7693 ADC labeled C in Figure 43) is
driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7693 then enters the acquisition phase and powers
down. The data bits stored in the internal shift register are
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N + 1 clocks are required to
readback the N ADCs. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate and consequently more AD7693s in the
chain, provided the digital host has an acceptable hold time.
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy chain multiple AD7693s
on a 3-wire serial interface while providing a BUSY indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications
or for systems with a limited interfacing capacity. Data readback
is analogous to clocking a shift register.
A connection diagram example using three AD7693s is shown
in Figure 43, and the corresponding timing is given in Figure 44.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
CONVERT
DIGITAL HOST
DATA IN
CNV
CNV
CNV
AD7693
AD7693
AD7693
SDI
SDO
SDI
SDO
SDI
SDO
A
B
C
SCK
SCK
SCK
IRQ
CLK
Figure 43. Chain Mode with Busy Indicator Connection Diagram
tCYC
CNV = SDI
A
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSSCKCNV
tSCKH
SCK
1
2
3
4
15
16
17
18
19
31
32
33
34
35
47
48
49
tHSCKCNV
tSSDISCK
tSCKL
tDSDOSDI
tHSDISC
tEN
SDO = SDI
D
15
15
D
14
14
D
13
D
A
1
D
0
A
A
B
A
A
A
tHSDO
tDSDO
tDSDOSDI
tDSDOSDI
tDSDOSDI
SDO = SDI
B
D
D
D
D
D
13
B
D
D
1
D
0
D
15
D
14
D 1
A
D 0
A
C
C
B
B
B
B
A
A
tDSDOSDI
SDO
D
15
14
13
1
D
0
D
15
D
14
D
1
D
0
D
15
D
14
D
1
D 0
A
C
C
C
C
C
B
B
B
B
A
A
A
Figure 44. Chain Mode with Busy Indicator Serial Interface Timing
Rev. PrB | Page 22 of 24
Preliminary Technical Data
AD7693
APPLICATION HINTS
LAYOUT
The printed circuit board that houses the AD7693 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7693, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
Avoid running digital lines under the device because these
couple noise onto the die unless a ground plane under the
AD7693 is used as a shield. Fast switching signals, such as CNV
or clocks, should not run near analog signal paths. Crossover of
digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the latter
case, the planes should be joined underneath the AD7693s.
Figure 45. Example Layout of the AD7693 (Top Layer)
The AD7693 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.
Finally, the power supplies VDD and VIO of the AD7693
should be decoupled with ceramic capacitors, typically 100 nF,
placed close to the AD7693 and connected using short and wide
traces to provide low impedance paths and reduce the effect of
glitches on the power supply lines.
An example of a layout following these rules is shown in
Figure 45 and Figure 46.
EVALUATING THE AD7693’S PERFORMANCE
Figure 46. Example Layout of the AD7693 (Bottom Layer)
Other recommended layouts for the AD7693 are outlined
in the documentation of the evaluation board for the AD7693
(EVAL-AD7693-CB). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-CONTROL BRD3.
Rev. PrB | Page 23 of 24
AD7693
Preliminary Technical Data
OUTLINE DIMENSIONS
3.10
3.00
2.90
6
10
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 47.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
INDEX
AREA
PIN
1
3.00
BSC SQ
INDICATOR
10
1
1.50
BCS SQ
0.50
BSC
2.48
2.38
2.23
EXPOSED
PAD
TOP VIEW
(BOT TOM VIEW)
6
5
0.50
0.40
0.30
1.74
1.64
1.49
0.80 MAX
0.55 TYP
PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SIDE VIEW
ELECTRICAL PERFORMANCES
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
QFN Package in development. Contact sales for samples and availability.
Figure 48. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model
EVAL-AD7693CB1
EVAL-CONTROL BRD22
EVAL-CONTROL BRD32
Temperature Range
Ordering Quantity
Package Description
Evaluation Board
Controller Board
Controller Board
Package Option
Branding
1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.
2 These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR05793-9/06(PrB)
Rev. PrB | Page 24 of 24
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