AD7625 [ADI]
16-Bit, 6MSPS PulSAR Differential ADC; 16位， 6MSPS的PulSAR差分ADC
| 型号： | AD7625 |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 6MSPS PulSAR Differential ADC |
| 文件： | 总11页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 6MSPS PulSAR
Differential ADC
Preliminary Technical Data
AD7625
FEATURES
FUNCTIONAL BLOCK DIAGRAM
REFIN REF VCM
Throughput: 6 MSPS
SAR architecture
16-bit resolution with no missing codes
SNR: 92 dB Typ, 90dB Min @ 1MHz
INL: 1 LSB Typ, 2 LSB Max
DNL: 0.3 LSB Typ, 1 LSB Max
Differential input range: 4.096V
No latency/no pipeline delay (SAR architecture)
Serial LVDS interface:
1.2V
BANDGAP
VIO
2
CLOCK
LOGIC
IN+
IN-
CNV
CAP DAC
D
SERIAL
LVDS
SAR
DCO
CLK
AD7626
Self-clocked mode
Echoed-clock mode
Figure 1.
Reference:
Internal 4.096 V
External (1.2V) buffered to 4.096 V
External 4.096 V
Power dissipation 150 mW
32-Lead LFCSP package (5 mm x 5 mm)
GENERAL DESCRIPTION
The AD7625 is a 16-bit, 6MSPS, charge redistribution successive
approximation register (SAR) architecture, analog-to-digital
converter (ADC). SAR architecture allows unmatched
performance both in noise – 92dB SNR - and in linearity –
1LSB. The AD7625 contains a high speed 16-bit sampling ADC,
an internal conversion clock, and an internal buffered reference.
On the CNV edge, it samples the voltage difference between
IN+ and IN− pins. The voltages on these pins swing in opposite
phase between 0 V and REF. The 4.096V reference voltage, REF,
can be generated internally or applied externally.
APPLICATIONS
High dynamic range telecommunications
Receivers
Digital imaging systems
High-speed data acquisition
Spectrum analysis
All converted results are available on a single LVDS self-clocked
or echoed-clock serial interface reducing external hardware
connections.
Test equipment
Table 1. Fast PulSAR ADC Selection
The AD7625 is housed in a 32-lead LFCSP (5mm by 5mm) with
operation specified from −40°C to +85°C.
≥1 MSPS
to
< 2MSPS
Res
(Bit
s)
≥ 2 MSPS
to
≤ 3 MSPS
10
MSPS
Input Type
6 MSPS
Differential
(ground
sense)
16
AD7653
AD7667
AD7980
AD7983
AD7985
True Bipolar
16
16
AD7671
Differential
(anti-phase)
AD7677
AD7623
AD7621
AD7622
AD7625 AD7626
Differential
(anti-phase)
18
AD7643
AD7982
AD7984
AD7641
AD7986
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD7625
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Resistance.......................................................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Terminology.......................................................................................8
Theory of Operation.........................................................................9
Outline Dimensions....................................................................... 11
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
Rev. PrB | Page 2 of 11
Preliminary Technical Data
AD7625
SPECIFICATIONS
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.5 V; VREF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range
VIN+ − VIN−
−VREF
+VREF
V
Operating Input Voltage
Common Mode Input Range
Analog Input CMRR
Input Current
VIN+, VIN− to AGND
−0.1
VREF/2 – 0.1
+VREF + 0.1
VREF/2 + 0.1
V
V
dB
μA
VREF/2
60
350
fIN = 1 MHz
6 MSPS throughput
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
DC ACCURACY
166
6
ns
MSPS
0.001
Integral Linearity Error
No Missing Codes
Differential Linearity Error
Transition Noise
Zero Error, TMIN to TMAX
Zero Error Drift
Gain Error, TMIN to TMAX
Gain Error Drift
Power Supply Sensitivity
-2
16
-1
1
+2
+1
LSB
Bits
LSB
LSB
0.3
0.6
100
1
μV
ppm/°C
ppm of FS
ppm/°C
LSB
50
1
VDD1 = 5 V 5%
VDD2 = 2.5 V 5%
TBD
TBD
LSB
AC ACCURACY
Dynamic Range
Signal-to-Noise
Spurious-Free Dynamic Range
90
90
92
92
110
90
dB
dB
dB
dB
fIN = 250 kHz
fIN = 250 kHz
fIN = TBD
Total Harmonic Distortion
fIN = 250 kHz
fIN = TBD
fIN = 250 kHz
-110
-90
92
dB
dB
dB
MHz
ns
Signal-to-(Noise + Distortion)
−3 dB Input Bandwidth
Aperture Delay
100
Aperture jitter
5
50
ps rms
ns
Transient Response
INTERNAL REFERENCE
Output Voltage
Temperature Drift
REFERENCE BUFFER
REFIN Input Voltage Range
REF Output Voltage range
EXTERNAL REFERENCE
Voltage Range
Full-Scale Step
REFIN @ 25°C
−40°C to +85°C
1.2
7
V
ppm/°C
1.2
4.096
V
V
REF
4.096
V
VCM
@ 25°C
Output Voltage
Output Impedance
VREF/2
5
VREF/2
kΩ
4
6
Rev. PrB | Page 3 of 11
AD7625
Preliminary Technical Data
Parameter
Conditions
Min
Typ
Max
Unit
LVDS I/O, (ANSI-644)
Data Format
Serial LVDS Two’s complement
VOD
Differential Output Voltage,
RL=100 Ω
Common mode Output Voltage,
RL=100Ω
247
350
454
mV
mV
VOCM
1125
1250
1375
VID
VICM
Differential Input Voltage
Common mode Input Voltage
100
800
650
1575
mV
mV
POWER SUPPLIES
Specified Performance
VDD1
4.75V
2.37
2.3
5
2.5
2.5
5.25V
2.63
2.7
V
V
V
VDD2
VIO
Operating Currents
VDD1
VDD2
VIO
VIO
10
25
14
18
mA
mA
mA
mA
Self-clocked mode
Echoed-clock mode
Power Dissipation1
With Internal Reference
Without Internal Reference
Energy per conversion
TEMPERATURE RANGE
Specified Performance
6 MSPS throughput
6 MSPS throughput
6 MSPS throughput
140
120
10
mW
mW
nJ/sample
TMIN to TMAX
−40
+85
°C
1 Power dissipation is for the AD7626 only. In self-clocked interface, 9mW is dissipated in the 100 ohm terminator. In echoed-clock interface, 18mW is dissipated in (2)
100 ohm terminators.
TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.3V to 2.7 V; VREF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Symbol
tCYC
Min
100
40
Typ
Max
Unit
ns
ns
ns
ns
Time between conversion
Acquisition time
CNV high time
CNV to D (MSB) delay
CNV to last CLK (LSB) delay
CLK period
tACQ
tCNVH
tMSB
tCLKL
tCLK
10000
40
166
120
10
ns
ns
TBD
4
CLK frequency
fCLK
tDCO
tD
250
4
0
400
7
1
MHz
ns
ns
CLK to DCO delay (echoed-clock mode)
DCO to D delay (echoed-clock mode)
CLK to D delay
0
-1
0
tCLKD
4
7
ns
Rev. PrB | Page 4 of 11
Preliminary Technical Data
AD7625
maximum rating conditions for extended periods may affect
device reliability.
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
THERMAL RESISTANCE
With
Respect to
Rating
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Analog Inputs/Outputs
CAP1, REFIN
IN+, IN-, REF, REF/2,
CAP2
GND
GND
-0.3V to 2.7V
-0.3V to 6V
Table 5. Thermal Resistance
Package Type
θJA
θJC
Unit
Digital Inputs/Outputs
Supply Voltage
VDD1
GND
-0.3V to 2.7V
GND
GND
-0.3V to 6V
-0.3V to 2.7V
ESD CAUTION
VDD2, VIO
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
Rev. PrB | Page 5 of 11
AD7625
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD1
VDD2
CAP1
REFIN
EN0
EN1
VDD2
CNV-
1
2
3
4
5
6
7
8
24 GND
23 IN+
22 IN-
21 REF/2
20 VDD1
19 VDD1
18 VDD2
17 CLK+
PIN 1
INDICATOR
TOP VIEW
Figure 2.
Table 6. Pin Function Descriptions
Pin No. Mnemonic
Type1 Description
1
VDD1
P
Analog 5V Supply.
Decouple with 10uF and 100nF capacitors.
Analog 2.5V Supply.
2
VDD2
P
The system 2.5V supply should supply this pin first, decoupled with 10uF and 100nF capacitors, then
starred off to other VDD2 pins.
3
4
CAP1
REFIN
AO
AI/O
Connect to a 10nF capacitor.
Pre-Buffer Reference Voltage.
When using the internal reference, this pin outputs the band-gap voltage and is nominally at 1.2V. It can
be overdriven with an external reference voltage like the ADR280.
In either mode, a 10uF capacitor is required. If using an external 4.096V reference (connected to REF), this
pin is a no connect and does not require any capacitor.
5, 6
EN0, EN1
DI
Enable Pins.
EN1
0
EN0
0
Operation
Power down all; ADC, internal reference and reference buffer.
0
1
Enable internal buffer, disable internal reference. An external 1.2V reference
connected to REFIN pin is required.
1
0
Disable internal reference and buffer. An external reference connected to the REF
pin is required.
1
1
Enable all; ADC, internal reference and reference buffer.
7
VDD2
P
Digital 2.5V supply.
8, 9
CNV-, CNV+
DI
Convert Input.
This input has multiple functions. On its rising edge, it samples the analog inputs and initiates a
conversion cycle. CNV+ works as a CMOS input when CNV- is grounded otherwise CNV+, CNV- are LVDS
inputs.
10, 11
D-, D+
D0
LVDS Data Outputs.
The conversion data is output serially on these pins.
Input/Output Interface Supply. Nominally 2.5V.
Ground.
12
13
VIO
GND
P
P
14, 15
DCO-, DCO+
DI/O
LVDS Buffered Clock Outputs.
When DCO+ is grounded, the self-clock interface mode is selected. In this mode, the 16 bit results on D
is preceded by a three bit header (010) to allow synchronization of the data by the digital host with
simple logic.
When DCO+ is not grounded, the echoed clock interface mode is selected. In this mode, DCO is a copy
of CLK . The data bits are output on the falling edge of DCO+ and can be latched in the digital host on
the next rising edge of DCO+.
16, 17
CLK-, CLK+
DI
LVDS Clock Inputs.
This clock shifts out the conversion results on the negative edge of CLK+.
Rev. PrB | Page 6 of 11
Preliminary Technical Data
AD7625
Pin No. Mnemonic
Type1 Description
18
19, 20
21
VDD2
VDD1
VCM
P
P
AO
Analog 2.5V Supply.
Analog 5V supply. Isolate from Pin 1 with a ferrite bead.
Common Mode Output.
When using any reference scheme, this pin produces ½ of the voltage present on the REF pin which can
be useful for driving the common mode of the input amplifiers.
22
23
24
IN-
AI
AI
Differential Negative Analog Input.
Referenced to and must be driven 180° out of phase with IN+.
Differential Positive Analog Input.
IN+
Referenced to and must be driven 180° out of phase with IN-.
GND
P
Ground.
25, 26,
28
CAP2
AO
Connect all three pins to a single 10uF X5R capacitor with the shortest distance. The other side of the
capacitor must be placed close to pin 27 (GND).
27
GND
REF
P
Ground.
Return path for 10uF capacitor connected to pins 25, 26, and 28.
Buffered Reference Voltage.
When using the internal reference or 1.2V external reference (REFIN input), the 4.096V system reference
is produced at this pin.
29, 30,
32
AI/O
When using an external reference, like the ADR434 or ADR444, the internal reference buffer must be
disabled.
In either case, connect all three pins to a single 10uF X5R capacitor with the shortest distance. The other
side of the capacitor must be placed close to pin 31 (GND)
31
GND
P
Ground.
Return path for 10uF capacitor connected to pins 29, 30, and 32.
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
Rev. PrB | Page 7 of 11
AD7625
Preliminary Technical Data
TERMINOLOGY
Total Harmonic Distortion (THD)
Least Significant Bit (LSB)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and
is expressed in decibels.
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For a fully differential input
ADC with N bits of resolution, the LSB expressed in volts is
Signal-to-(Noise + Distortion) Ratio (SINAD)
VINp-p
LSB (V) =
2N
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full-
scale. The point used as negative full scale occurs a ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSBs beyond the last code transition. The deviation is meas-
ured from the middle of each code to the true straight line.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
Differential Nonlinearity Error (DNL)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
ENOB = [(SINADdB − 1.76)/6.02]
Aperture Delay
Aperture delay is a measure of the acquisition performance
Zero Error
CNVST
measured from the falling edge of the
input to when
The difference between the ideal midscale input voltage (0 V)
and the actual voltage producing the midscale output code.
the input signal is held for a conversion.
Transient Response
Gain Error
The time required for the AD7634 to achieve its rated accuracy
after a full-scale step function is applied to its input.
The first transition (from 100 ... 00 to 100 ... 01) should occur at
a level ½ LSB above nominal negative full scale (−4.095938 V
for the 4.096V V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.095813 V for the 4.096V range). The
gain error is the deviation of the difference between the actual
level of the last transition and the actual level of the first
transition from the difference between the ideal levels.
Reference Voltage Temperature Coefficient
Reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at
the maximum and minimum reference output voltage (VREF
)
measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as
VREF (Max)–VREF (Min)
TCVREF (ppm/°C) =
×106
Dynamic Range
VREF (25°C) × (TMAX –TMIN
)
Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured for an input typically at −60 dB. The
value for dynamic range is expressed in decibels.
where:
V
V
V
REF (Max) = maximum VREF at TMIN, T(25°C), or TMAX.
REF (Min) = minimum VREF at TMIN, T(25°C), or TMAX
REF (25°C) = VREF at 25°C.
.
Signal-to-Noise Ratio (SNR)
T
T
MAX = +85°C.
MIN = –40°C.
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Rev. PrB | Page 8 of 11
Preliminary Technical Data
AD7625
THEORY OF OPERATION
Echoed-Clock Interface Mode
Conversions are initiated by a CNV pulse. The CNV must be
returned low ≤ tCNVH(max) for valid operation. Once a
The AD7626 digital operation in “echoed-clock interface mode”
is shown in Figure 3. This interface mode, requiring just a shift
register on the digital host, can be used with many digital hosts
(FPGA, shift register, microprocessor, etc.). It requires 3 LVDS
pairs (D , CLK , and DCO ) between each AD7626 and the
digital host.
conversion has begun, it continues until completion. Additional
CNV pulses are ignored during the conversion phase. After the
time tMSB elapses, the host should begin to burst the CLK. Note
that tMSB is the maximum time for the MSB of the new
conversion result and should be used as the gating device for
CLK. The echoed clock, DCO, and data, D, will be driven in
phase with D being updated on the DCO+ falling edge and the
host should use the DCO+ rising edge to capture D. The only
requirement is that the 16 CLK pulses finish before the time
The clock DCO is a buffered copy of CLK and synchronous to
the data, D, which is updated on DCO+ falling edge (tD). By
keeping good propagation delay matching between D and DCO
through the board and the digital host, DCO can be can be used
to latch D with good timing margin for the shift register.
t
CLKL elapses of the next conversion phase or the data will be lost.
From the time tCLKL to tMSB, D and DCO will be driven to 0’s.
SAMPLE N
SAMPLE N+1
T
CYC
T
CNVH
CNV-
CNV+
T
ACQ
ACQUISITION
CLK
ACQUISITION
ACQUISITION
T
CLKL
15
T
1
15
15
16
1
2
16
2
3
CLK-
CLK+
T
DCO
1
16
1
2
15
16
2
3
DCO-
DCO+
T
MSB
T
D
T
CLKD
D+
D-
D13
N+1
D0
N
D15
N+1
D14
N+1
D1
N-1
D0
N-1
D15
N
D14
N
D1
N
0
0
Figure 3. Echoed-Clock Interface Mode Timing Diagram
Rev. PrB | Page 9 of 11
AD7625
Preliminary Technical Data
Self Clocked Mode
between the state machine clock and D including any board
propagation time allowing to use the best clock signal to latch
the following bits of the conversion result.
The AD7626 digital operation in “self-clocked interface mode”
is shown in Figure 4. This interface mode reduces the number
of wires between ADCs and the digital host to 2 LVDS pairs per
AD7626, CLK and D or a single pair if sharing a common
CLK using multiple AD7626’s. This considerably eases the
design of a system using multiple AD7626’s since the interface
can tolerate several CLK cycles of propagation delay mismatch
between the different AD7626 devices and the digital host.
Conversions are initiated by a CNV pulse. The CNV must be
returned low ≤ tCNVH(max) for valid operation. Once a
conversion has begun, it continues until completion. Additional
CNV pulses are ignored during the conversion phase. After the
time tMSB elapses, the host should begin to burst the CLK. Note
that tMSB is the maximum time for the first bit of the header and
should be used as the gating device for CLK. CLK is also used
internally on the host to begin the internal synchronization
state machine. The next header bit and conversion results are
output on subsequent falling edges of CLK. The only
The “self-clocked interface mode” consists of preceding each
ADC word results by a header of 2 bits on the data, D This
header is used to synchronize D of each conversion in the
digital host. Synchronization is accomplished by one simple
state machine per AD7626 device. The state machine is running,
for instance, at the same speed as CLK with 3 phases. The state
machine measures when the first “one” of the header occurs.
This provides the value of the actual propagation delay delta
requirement is that the 18 CLK pulses finish before the time
tCLKL elapses of the next conversion phase or the data will be
lost.
SAMPLE N
SAMPLE N+1
T
CYC
T
CNVH
CNV-
CNV+
T
ACQ
ACQUISITION
ACQUISITION
ACQUISITION
T
T
CLKL
CLK
1
17
18
1
2
3
4
17
18
2
3
CLK-
CLK+
T
MSB
T
CLKD
D+
*1
1
0
0
0
D0
N
0
D15
N+1
D1
N-1
D0
N-1
D15
N
D14
N
D1
N
1
D-
Figure 4. Self-Clocked Interface Mode Timing Diagram1
1 This timing is for silicon rev 1 or above. For silicon rev 0, there is an extra bit (a zero) in front on the bit with value 1. Therefore, silicon rev 0 needs 19 clock pulses.
Rev. PrB | Page 10 of 11
Preliminary Technical Data
OUTLINE DIMENSIONS
AD7625
5.00
0.60 MAX
BSC SQ
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
EXPOSED
PAD
(BOTTOM VIEW)
3.45
3.30 SQ
3.15
TOP
VIEW
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 5.32-Lead Lead Frame Chip Scale package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-3)
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07652-0-6/08(PrB)
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