AD7625BCPZ [ADI]
16-Bit, 6 MSPS, PulSAR Differential ADC;
| 型号： | AD7625BCPZ |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 6 MSPS, PulSAR Differential ADC 转换器 |
| 文件： | 总25页 (文件大小：1008K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 6 MSPS, PulSAR
Differential ADC
AD7625
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
REFIN REF VCM
Throughput: 6 MSPS
SNR: 93 dB
1.2V
BAND GAP
VIO
÷2
CLOCK
INL: 0.45 LSB typical, 1 LSB maximum
DNL: 0.3 LSB typical, 0.5 LSB maximum
Power dissipation: 135 mW
32-lead LFCSP (5 mm × 5 mm)
SAR architecture
No latency/no pipeline delay
16-bit resolution with no missing codes
Zero error: 1.5 LSB
LOGIC
IN+
IN–
CAP
DAC
CNV+, CNV–
D+, D–
SERIAL
LVDS
SAR
DCO+, DCO–
CLK+, CLK–
AD7625
Figure 1.
GENERAL DESCRIPTION
Differential input voltage: 4.096 V
Serial LVDS interface
The AD7625 is a 16-bit, 6 MSPS, charge redistribution successive
approximation register (SAR) based architecture analog-to-digital
converter (ADC). SAR architecture allows unmatched perfor-
mance both in noise (93 dB SNR) and in linearity (1 LSB). The
AD7625 contains a high speed, 16-bit sampling ADC, an internal
conversion clock, and an internal buffered reference. On the
CNV rising edge, it samples the voltage difference between the
IN+ and IN− pins. The voltages on these pins swing in opposite
phase between 0 V and REF. The 4.096 V reference voltage, REF,
can be generated internally or applied externally.
Self-clocked mode
Echoed-clock mode
Can use LVDS or CMOS for conversion control (CNV signal)
Reference options
Internal: 4.096 V
External (1.2 V) buffered to 4.096 V
External: 4.096 V
APPLICATIONS
High dynamic range telecommunications
Receivers
Digital imaging systems
High speed data acquisition
Spectrum analysis
All converted results are available on a single LVDS self-clocked
or echoed-clock serial interface, reducing external hardware
connections.
The AD7625 is housed in a 32-lead, 5 mm × 5 mm LFCSP with
operation specified from −40°C to +85°C.
Test equipment
Table 1. Fast PulSAR® ADC Selection
Input Type
Resolution (Bits)
1 MSPS to <2 MSPS
AD7653
2 MSPS to 3 MSPS
5 MSPS
6 MSPS
10 MSPS
Differential (Ground Sense)
16
AD7985
AD7667
AD7980
AD7983
True Bipolar
Differential (Antiphase)
16
16
AD7671
AD7677
AD7621
AD7622
AD7641
AD7986
AD7625
AD7626
AD7623
AD7643
AD7982
AD7961
AD7960
18
AD7984
Rev. B
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AD7625* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DESIGN RESOURCES
• AD7625 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
EVALUATION KITS
• AD7625 Evaluation Kit
DOCUMENTATION
Data Sheet
DISCUSSIONS
View all AD7625 EngineerZone Discussions.
• AD7625: 16-Bit, 6MSPS, PulSAR Differential ADC Data
Sheet
SAMPLE AND BUY
Visit the product page to see pricing options.
User Guides
• UG-745: Evaluating the AD7625/AD7626 16-Bit, 6 MSPS/
10 MSPS PulSAR Differential ADC
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
REFERENCE DESIGNS
• CN0080
• CN0307
DOCUMENT FEEDBACK
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REFERENCE MATERIALS
Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
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AD7625
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Information.................................................................... 13
Converter Information .............................................................. 13
Transfer Functions ..................................................................... 14
Analog Inputs ............................................................................. 14
Typical Connection Diagram ................................................... 15
Driving the AD7625................................................................... 16
Voltage Reference Options........................................................ 17
Power Supply............................................................................... 18
Digital Interface.......................................................................... 19
Applications Information.............................................................. 21
Layout, Decoupling, and Grounding....................................... 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
REVISION HISTORY
10/15—Rev. A to Rev. B
7/12—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 1
Added Aperture Delay Parameter and Current Drain Parameter,
Table 2 ................................................................................................ 3
Changes to CLK Period Parameter and Endnote 2, Table 3 ... 5
Changes to Figure 32 Caption and Ordering Guide.................. 22
Change to Table 5 ..............................................................................6
Changes to Figure 2...........................................................................7
Updated Outline Dimensions (Changed CP-32-2 to CP-32-7) .... 22
Changes to Ordering Guide.......................................................... 22
1/09—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
AD7625
SPECIFICATIONS
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.5 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range
VIN+ − VIN−
−VREF
+VREF
V
Operating Input Voltage
Common-Mode Input Range
Common-Mode Rejection Ratio
Input Current
VIN+, VIN− to GND
−0.1
VREF/2 − 0.05
VREF + 0.1
VREF/2 + 0.05
V
V
dB
μA
VREF/2
60
77
fIN = 1 MHz
Midscale input
THROUGHPUT
Complete Cycle
Throughput Rate
DC ACCURACY
166
6
ns
MSPS
0.1
Integral Linearity Error
No Missing Codes
Differential Linearity Error
Transition Noise
Zero Error
Zero Error Drift
−1
16
−0.5
0.45
+1
LSB
Bits
LSB
LSB
LSB
ppm/°C
LSB
0.3
0.6
1.5
0.5
8
+0.5
+4
TMIN to TMAX
TMIN to TMAX
−4
Gain Error
20
Gain Error Drift
Power Supply Sensitivity1
0.4
0.4
0.2
ppm/°C
LSB
LSB
VDD1 = 5 V 5%
VDD2 = 2.5 V 5%
AC ACCURACY
External Reference
fIN = 20 kHz
Dynamic Range
92.5
92
93.2
93
106
−105.5
92
dB
dB
dB
dB
dB
Signal-to-Noise Ratio
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Internal Reference
91.5
fIN = 20 kHz
Dynamic Range
92.5
91.5
93.2
92.9
106
−105.5
92.5
100
dB
dB
dB
dB
dB
MHz
ns
Signal-to-Noise Ratio
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
−3 dB Input Bandwidth
Aperture Delay
91
1.5
Aperture Jitter
0.25
ps rms
INTERNAL REFERENCE
Output Voltage
Temperature Drift
REFIN @ 25°C
−40°C to +85°C
1.2
15
V
ppm/°C
REFERENCE BUFFER
REFIN Input Voltage Range
REF Output Voltage Range
Line Regulation
1.2
4.096
5
V
V
mV
4.076
4.116
VDD1 5%, VDD2 5%
EXTERNAL REFERENCE
Voltage Range
Current Drain
REF
6 MSPS
4.096
590
V
μA
Rev. B | Page 3 of 24
AD7625
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VCM PIN
@ 25°C
Output Voltage
Output Impedance
LVDS I/O (ANSI-644)
Data Format
REF/2
5
V
kΩ
4
6
Serial LVDS twos complement
Differential Output Voltage, VOD
Common-Mode Output Voltage, VOCM
Differential Input Voltage, VID
Common-Mode Input Voltage, VICM
POWER SUPPLIES
Specified Performance
VDD1
RL = 100 Ω
RL = 100 Ω
200
850
100
800
350
1250
454
1375
650
mV
mV
mV
mV
2
1575
4.75
2.37
2.37
5
2.5
2.5
5.25
2.63
2.63
V
V
V
VDD2
VIO
Operating Currents
Static—Not Converting
VDD1
4.5
17
11
7.8
22.7
13
mA
mA
mA
VDD2
VIO
Self-clocked mode and echoed-
clock mode
With Internal Reference
6 MSPS throughput
VDD1
VDD2
VIO
11
21.5
13.5
15.4
28.3
16
mA
mA
mA
Self-clocked mode and echoed-
clock mode
Without Internal Reference
6 MSPS throughput
VDD1
VDD2
VIO
9
21
13.5
12.1
26
16
mA
mA
mA
Self-clocked mode and echoed-
clock mode
Power Dissipation3
Static—Not Converting
With Internal Reference
Without Internal Reference
Energy per Conversion
TEMPERATURE RANGE
Specified Performance
95
130
190
165
mW
mW
mW
nJ/sample
6 MSPS throughput
6 MSPS throughput
6 MSPS throughput
145
135
22
TMIN to TMAX
−40
+85
°C
1 Using an external reference.
2 The ANSI-644 LVDS specification has a minimum output common mode (VOCM) of 1125 mV.
3 Power dissipation is for the AD7625 device only. In self-clocked interface mode, 9 mW is dissipated in the 100 Ω terminator. In echoed-clock interface mode, 18 mW is
dissipated in two 100 Ω terminators.
Rev. B | Page 4 of 24
Data Sheet
AD7625
TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Symbol
tCYC
Min
166
40
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
MHz
ns
ns
Time Between Conversions1
10,000
Acquisition Time
CNV High Time
CNV to D (MSB) Delay
CNV to Last CLK (LSB) Delay
CLK Period2
tACQ
tCNVH
tMSB
tCLKL
tCLK
fCLK
tDCO
tD
10
40
145
110
3.33
300
7
(tCYC − tMSB + tCLKL)/n
4
250
4
0
4
CLK Frequency
CLK to DCO Delay (Echoed-Clock Mode)
DCO to D Delay (Echoed-Clock Mode)
CLK to D Delay
0
0
1
7
tCLKD
ns
1 The maximum time between conversions is 10,000 ns. If CNV is left idle for a time greater than the maximum value of tCYC, the subsequent conversion result is invalid.
2 For the minimum CLK period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) that are read. In echoed-clock interface
mode, n = 16; in self-clocked interface mode, n = 18.
Rev. B | Page 5 of 24
AD7625
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
Analog Inputs/Outputs
IN+, IN− to GND1
−0.3 V to REF + 0.3 V
or 130 mA
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +2.7 V
Table 5. Thermal Resistance
REF2 to GND
Package Type
θJA
θJC
Unit
32-Lead LFCSP_WQ
40
4
°C/W
VCM, CAP2 to GND
CAP1, REFIN to GND
Supply Voltage
VDD1
VDD2, VIO
Digital Inputs to GND
Digital Outputs to GND
Input Current to Any Pin Except Supplies3
ESD CAUTION
−0.3 V to +6 V
−0.3 V to +3 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
10 mA
Operating Temperature Range
(Commercial)
−40°C to +85°C
Storage Temperature Range
Junction Temperature
ESD
−65°C to +150°C
150°C
1 kV
1 See the Analog Inputs section.
2 Keep CNV+/CNV− low for any external REF voltage > 4.3 V applied
to the REF pin.
3 Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 6 of 24
Data Sheet
AD7625
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD1 1
24 GND
23
2
VDD2
IN+
CAP1 3
REFIN 4
22 IN–
21 VCM
AD7625
TOP VIEW
5
6
20
19
EN0
EN1
VDD1
VDD1
(Not to Scale)
VDD2 7
CNV– 8
18 VDD2
17 CLK+
NOTES
1. CONNECT THE EXPOSED PAD TO THE GROUND
PLANE OF THE PCB USING MULTIPLE VIAS.
Figure 2.
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
Analog 5 V Supply. Decouple the 5 V supply with a 100 nF capacitor.
Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor. The 2.5 V supply source should
supply this pin first and then be traced to the other VDD2 pins (Pin 7 and Pin 18).
1
2
VDD1
VDD2
P
P
3
4
CAP1
REFIN
AO
AI/O
Connect this pin to a 10 nF capacitor.
Prebuffer Reference Voltage. When using the internal reference, this pin outputs the band gap voltage
and is nominally at 1.2 V. It can be overdriven with an external reference voltage such as the ADR280.
In either internal or external reference mode, a 10 ꢀF capacitor is required. If using an external 4.096 V
reference (connected to REF), this pin is a no connect and does not require any capacitor.
5, 6
EN0, EN1
DI
Enable Pins. The logic levels of these pins set the operation of the device as follows:
EN1 = 0, EN0 = 0: Illegal state.
EN1 = 0, EN0 = 1: Enable internal buffer, disable internal reference. An external 1.2 V reference
connected to the REFIN pin is required.
EN1 = 1, EN0 = 0: Disable internal reference and reference buffer. An external 4.096 V reference
connected to the REF pin is required.
EN1 = 1, EN0 = 1: Enable internal reference and reference buffer.
7
VDD2
P
Digital 2.5 V Supply. Decouple this pin with a 100 nF capacitor.
8, 9
CNV−, CNV+
DI
Convert Input. These pins act as the conversion control pin. On the rising edge of these pins, the
analog inputs are sampled and a conversion cycle is initiated. CNV+ works as a CMOS input when
CNV− is grounded; otherwise, CNV+ and CNV− are differential LVDS inputs.
10, 11
12
13
D−, D+
VIO
GND
DO
P
P
LVDS Data Outputs. The conversion data is output serially on these pins.
Input/Output Interface Supply. Use a 2.5 V supply and decouple this pin with a 100 nF capacitor.
Ground. Return path for the 100 nF capacitor connected to Pin 12.
14, 15
DCO−, DCO+ DO
LVDS Buffered Clock Outputs. When DCO+ is grounded, the self-clocked interface mode is selected.
In this mode, the 16-bit results on D are preceded by a 2-bit header (10) to allow synchronization of
the data by the digital host with simple logic. When DCO+ is not grounded, the echoed-clock inter-
face mode is selected. In this mode, DCO is a copy of CLK . The data bits are output on the falling
edge of DCO+ and can be latched in the digital host on the next rising edge of DCO+.
16, 17
18
CLK−, CLK+
VDD2
DI
P
LVDS Clock Inputs. This clock shifts out the conversion results on the falling edge of CLK+.
Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor.
19, 20
VDD1
P
Analog 5 V Supply. Isolate these pins from Pin 1 with a ferrite bead and decouple them with a 100 nF
capacitor.
21
VCM
AO
Common-Mode Output. When using any reference scheme, this pin produces one-half the voltage
present on the REF pin, which can be useful for driving the common mode of the input amplifiers.
22
23
24
IN−
IN+
GND
AI
AI
P
Differential Negative Analog Input. Referenced to and must be driven 180° out of phase with IN+.
Differential Positive Analog Input. Referenced to and must be driven 180° out of phase with IN−.
Ground.
Rev. B | Page 7 of 24
AD7625
Data Sheet
Pin No.
Mnemonic
Type1
Description
25, 26, 28 CAP2
AO
Connect all three CAP2 pins together and decouple them with the shortest trace possible to a single
10 ꢀF, low ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 27 (GND).
27
GND
P
Ground. Return path for the 10 ꢀF capacitor connected to Pin 25, Pin 26, and Pin 28.
29, 30, 32 REF
AI/O
Buffered Reference Voltage. When using the internal reference or the 1.2 V external reference (REFIN
input), the 4.096 V system reference is produced at this pin. When using an external reference, such
as the ADR434 or the ADR444, the internal reference buffer must be disabled. In either case, connect
all three REF pins together and decouple them with the shortest trace possible to a single 10 ꢀF, low
ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 31 (GND).
31
EP
GND
Exposed Pad
P
Ground. Return path for the 10 ꢀF capacitor connected to Pin 29, Pin 30, and Pin 32.
The exposed pad is located on the underside of the package. Connect the exposed pad to the
ground plane of the PCB using multiple vias. See the Exposed Pad section for more information.
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DO = digital output; P = power.
Rev. B | Page 8 of 24
Data Sheet
AD7625
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–20
INPUT TONE = 2kHz
SNR = 93.16dB
SINAD = 92.09dB
THD = –110.45dB
SFDR = 111.37dB
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
0.5
1.0
1.5
2.0
2.5
3.0
0
5
10
15
20
25
30
35
40
45
FREQUENCY (MHz)
FREQUENCY (kHz)
Figure 3. FFT 2 kHz Input Tone, Full View
Figure 6. FFT 2 kHz Input Tone, Zoom In on Input Tone and Harmonics
0
0
–20
INPUT TONE = 100kHz
SNR = 92.91dB
INPUT TONE = 50kHz
SNR = 93.04dB
SINAD = 92.63dB
THD = –103.57dB
SFDR = –102.69dB
–20
SINAD = 92.55dB
THD = –103.11dB
SFDR = –103.41dB
–40
–40
–60
–80
–60
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4. FFT 50 kHz Input Tone
Figure 7. FFT 100 kHz Input Tone
1.0
0.8
0.5
0.4
0.6
0.3
0.4
0.2
0.2
0.1
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
16,384
32,768
CODE
49,152
65,536
0
16,384
32,768
CODE
49,152
65,536
Figure 5. Differential Nonlinearity vs. Code
Figure 8. Integral Nonlinearity vs. Code
Rev. B | Page 9 of 24
AD7625
Data Sheet
–94
–96
–100.5
–101.0
–101.5
–102.0
–102.5
–103.0
–103.5
–0.5dBFS
–98
–100
–102
–104
–106
–108
–110
–112
–114
INTERNAL REF
–3dBFS
–1dBFS
–10dBFS
EXTERNAL REF
–5dBFS
–116
0
20
40
60
80
100
120
–60
–40
–20
0
20
40
60
80
100
120
INPUT FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 9. THD at Input Amplitudes of −0.5 dBFS to −10 dBFS vs. Frequency
Figure 12. THD vs. Temperature (−0.5 dB, 20 kHz Input Tone)
93.8
93.2
93.6
93.0
92.8
92.6
92.4
92.2
92.0
91.8
91.6
DYNR vs. TEMP INTERNAL REF
DYNR vs. TEMP EXTERNAL REF
93.4
SINAD vs. TEMP EXTERNAL REF
93.2
93.0
92.8
SINAD vs. TEMP INTERNAL REF
SNR vs. TEMP EXTERNAL REF
SNR vs. TEMP INTERNAL REF
92.6
92.4
92.2
–60
–40
–20
0
20
40
60
80
100
120
–60
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. Dynamic Range and SNR vs. Temperature
(−0.5 dB, 20 kHz Input Tone)
Figure 13. SINAD vs. Temperature
(−0.5 dB, 20 kHz Input Tone)
120
100
80
12
10
8
IN+
60
40
GAIN ERROR
6
20
IN–
0
4
–20
–40
–60
2
ZERO ERROR
0
–60
–6
–4
–2
0
2
4
6
–40
–20
0
20
40
60
80
100
120
DIFFERENTIAL INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 11. Input Current (IN+, IN−) vs. Differential Input Voltage (6 MSPS)
Figure 14. Zero Error and Gain Error vs. Temperature
Rev. B | Page 10 of 24
Data Sheet
AD7625
250,000
140,000
120,000
100,000
80,000
60,000
40,000
20,000
0
262,144 SAMPLES
STD DEVIATION = 0.4829
129,601
262,144 SAMPLES
STD DEVIATION = 0.5329
128,084
201,320
200,000
150,000
100,000
50,000
0
30,651
30,073
FECB
2329
0
2130
54
46
0
0
0
FEC6
FEC7
FEC8
FEC9
FECA
FECB
FEC7
FEC8
FEC9
FECA
FECC
FECD
CODE (HEX)
CODE (HEX)
Figure 15. Histogram of 262,144 Conversions of a DC Input
at the Code Center (Internal Reference)
Figure 17. Histogram of 262,144 Conversions of a DC Input
at the Code Transition (Internal Reference)
250,000
262,144 SAMPLES
STD DEVIATION = 0.4814
201,614
200,000
150,000
100,000
50,000
0
30,250
30,206
FECA
41
33
0
0
FEC8
FEC9
FECB
FECC
FECD
FECE
CODE (HEX)
Figure 16. Histogram of 262,144 Conversions of a DC Input
at the Code Center (External Reference)
Rev. B | Page 11 of 24
AD7625
Data Sheet
TERMINOLOGY
Power Supply Rejection Ratio (PSRR)
Common-Mode Rejection Ratio (CMRR)
Variations in power supply affect the full-scale transition but not
the linearity of the converter. PSRR is the maximum change in
the full-scale transition point due to a change in power supply
voltage from the nominal value.
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of an 80 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN− at
frequency fS.
Reference Voltage Temperature Coefficient
CMRR (dB) = 10log(Pf/PfS)
The reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (VREF) meas-
ured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as
where:
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Differential Nonlinearity (DNL) Error
V
REF (Max)–VREF (Min)
TCVREF (ppm/C)
106
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
VREF (25C) (TMAX –TMIN
)
where:
V
V
V
REF (Max) = maximum VREF at TMIN, T(25°C), or TMAX.
REF (Min) = minimum VREF at TMIN, T(25°C), or TMAX
.
Integral Nonlinearity (INL) Error
REF (25°C) = VREF at 25°C.
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is meas-
ured from the middle of each code to the true straight line.
T
MAX = +85°C.
TMIN = −40°C.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured for an input typically at −60 dB. The
value for dynamic range is expressed in decibels.
Signal-to-(Noise + Distortion) (SINAD) Ratio
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by
Spurious-Free Dynamic Range (SFDR)
ENOB = [(SINADdB − 1.76)/6.02]
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.
Gain Error
The first transition (from 100 … 000 to 100 …001) should occur
at a level ½ LSB above nominal negative full scale (−4.0959375 V
for the 4.096 V range). The last transition (from 011 … 110 to
011 … 111) should occur for an analog voltage 1½ LSB below
the nominal full scale (+4.0959375 V for the 4.096 V range).
The gain error is the deviation of the difference between the
actual level of the last transition and the actual level of the first
transition from the difference between the ideal levels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and
is expressed in decibels.
Zero Error
Zero error is the difference between the ideal midscale input
voltage (0 V) and the actual voltage producing the midscale
output code.
Least Significant Bit (LSB)
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For a fully differential input
ADC with N bits of resolution, the LSB expressed in volts is
VIN p-p
LSB (V)
2N
Rev. B | Page 12 of 24
Data Sheet
AD7625
THEORY OF OPERATION
IN+
GND
LSB
SWITCHES
CONTROL
SW+
MSB
32,768C 16,384C
4C
4C
2C
2C
C
C
C
C
REF
(4.096V)
CLK+, CLK–
DCO+, DCO–
D+, D–
DATA TRANSFER
CONTROL
LOGIC
COMP
GND
OUTPUT CODE
32,768C 16,384C
MSB
SW–
LSB
CNV+, CNV–
LVDS INTERFACE
GND
CONVERSION
CONTROL
IN–
Figure 18. ADC Simplified Schematic
When the conversion phase begins, SW+ and SW− are opened
first. The two capacitor arrays are then disconnected from the
inputs and connected to the GND input. Therefore, the differential
voltage between the inputs (IN+ and IN−) captured at the end
of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between GND and 4.096 V
(the reference voltage), the comparator input varies by binary
weighted voltage steps (VREF/2, VREF/4 … VREF/65,536). The
control logic toggles these switches, MSB first, to bring the
comparator back into a balanced condition. At the completion
of this process, the control logic generates the ADC output code.
CIRCUIT INFORMATION
The AD7625 is a 6 MSPS, high precision, power efficient, 16-bit
ADC that uses SAR based architecture to provide performance
of 93 dB SNR, 0.45 LSB INL, and 0.3 LSB DNL.
The AD7625 is capable of converting 6,000,000 samples per
second (6 MSPS). The device typically consumes 135 mW. The
AD7625 offers the added functionality of a high performance
on-chip reference and on-chip reference buffer.
The AD7625 is specified for use with 5 V and 2.5 V supplies
(VDD1, VDD2). The interface from the digital host to the AD7625
uses 2.5 V logic only. The AD7625 uses an LVDS interface to
transfer data conversions. The CNV+ and CNV− inputs to the
device activate the conversion of the analog input. The CNV+
and CNV− pins can be applied using a CMOS or LVDS source.
The AD7625 digital interface uses low voltage differential
signaling (LVDS) to enable high data transfer rates.
The AD7625 conversion result is available for reading after tMSB
(time from the conversion start until MSB is available) has
elapsed. The user must apply a burst LVDS CLK signal to the
AD7625 to transfer data to the digital host.
The AD7625 is housed in a space-saving, 32-lead, 5 mm ×
5 mm LFCSP.
CONVERTER INFORMATION
The CLK signal outputs the ADC conversion result onto the
data output D . The bursting of the CLK signal is illustrated
in Figure 29 and Figure 30 and is characterized as follows: The
differential voltage on CLK should be held to create logic low
The AD7625 is a 6 MSPS ADC that uses SAR based architecture
incorporating a charge redistribution DAC. Figure 18 shows a
simplified schematic of the ADC. The capacitive DAC consists
of two identical arrays of 16 binary weighted capacitors that are
connected to the two comparator inputs.
in the time between tCLKL and tMSB
.
The AD7625 has two data read modes. For more information
about the echoed-clock and self-clocked interface modes, see
the Digital Interface section.
During the acquisition phase, the terminals of the array tied
to the input of the comparator are connected to GND via SW+
and SW−. All independent switches are connected to the analog
inputs. In this way, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. A conversion phase is initiated when the acquisition
phase is complete and the CNV input goes logic high. Note
that the AD7625 can receive a CMOS (CNV+) or LVDS format
(CNV ) signal.
Rev. B | Page 13 of 24
AD7625
Data Sheet
TRANSFER FUNCTIONS
ANALOG INPUTS
The AD7625 uses a 4.096 V reference. The AD7625 converts the
differential voltage of the antiphase analog inputs (IN+ and
IN−) into a digital output. The analog inputs, IN+ and IN−,
require a 2.048 V common-mode voltage (REF/2).
The analog inputs, IN+ and IN−, applied to the AD7625 must be
180° out of phase with each other. Figure 20 shows an equivalent
circuit of the input structure of the AD7625.
The two diodes provide ESD protection for the analog inputs,
IN+ and IN−. Care must be taken to ensure that the analog input
signal does not exceed the reference voltage by more than 0.3 V.
If the analog input signal exceeds this level, the diodes become
forward-biased and start conducting current. These diodes can
handle a forward-biased current of 130 mA maximum. However,
if the supplies of the input buffer (for example, the supplies of
the ADA4899-1 in Figure 24) are different from those of the
reference, the analog input signal may eventually exceed the
supply rails by more than 0.3 V. In such a case (for example, an
input buffer with a short circuit), the current limitation can be
used to protect the device.
The 16-bit conversion result is in MSB first, twos complement
format.
The ideal transfer functions for the AD7625 are shown in Figure 19
and Table 7.
011 ... 111
011 ... 110
011 ... 101
VDD1
CNV
25pF
IN+
OR
IN–
250Ω
100 ... 010
100 ... 001
100 ... 000
–FSR
–FSR + 1LSB
+FSR – 1LSB
+FSR – 1.5LSB
–FSR + 0.5LSB
Figure 20. Equivalent Analog Input Circuit
ANALOG INPUT
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these differ-
ential inputs, signals common to both inputs are rejected. The
AD7625 shows some degradation in THD with higher analog
input frequencies.
Figure 19. ADC Ideal Transfer Functions (FSR = Full-Scale Range)
Table 7. Output Codes and Ideal Input Voltages
Analog Input
(IN+ − IN−)
Digital Output Code
Description
REF = 4.096 V
Twos Complement (Hex)
85
FSR − 1 LSB
+4.0959375 V
0x1FFF
0x0001
0x0000
0xFFFF
0x1001
0x1000
80
75
70
65
60
55
50
45
40
Midscale + 1 LSB +62.5 ꢀV
Midscale 0 V
Midscale − 1 LSB −62.5 ꢀV
−FSR + 1 LSB
−FSR
−4.0959375 V
−4.096 V
1
10
100
1k
10k
100k
1M
10M
INPUT COMMON-MODE FREQUENCY (Hz)
Figure 21. Analog Input CMRR vs. Frequency
Rev. B | Page 14 of 24
Data Sheet
AD7625
TYPICAL CONNECTION DIAGRAM
8
V+
ADR434
ADR444
CAPACITOR ON OUTPUT
FOR STABILITY
C
10µF
REF
1, 2
1
10µF
VDD1
(5V)
100nF
VDD2
(2.5V)
32
31
30
29
28
27
26
25
100nF
24
GND
1
2
VDD1
VDD2
CAP1
REFIN
EN0
10nF
23
22
IN+
IN–
IN+
IN–
8
ADR280
PADDLE
SEE THE DRIVING
THE AD7625 SECTION
7
3
4
10µF
VCM
21
20
VCM
VIO
AD7625
3
10kΩ
10kΩ
5
6
VDD1
(5V)
CONTROL FOR
ENABLE
VDD1
FERRITE
BEAD
PINS
100nF
6
EN1
19
18
VDD1
VDD2
VDD2
(2.5V)
7
VDD2
VDD2
(2.5V)
100nF
100nF
4
CONVERSION
CONTROL
CMOS (CNV+ ONLY)
OR
8
9
10
11
12
13
14
15
16
100Ω
17
LVDS CNV+ AND CNV–
USING 100Ω
5
TERMINATION RESISTOR
100Ω
VIO
(2.5V)
100Ω
100Ω
DIGITAL INTERFACE SIGNALS
DIGITAL HOST
LVDS TRANSMIT AND RECEIVE
1
SEE THE LAYOUT, DECOUPLING, AND GROUNDING SECTION.
2
3
C
IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESR AND ESL.
REF
USE PULL-UP OR PULL-DOWN RESISTORS TO CONTROL EN0, EN1 DURING POWER-UP. EN0 AND EN1 INPUTS CAN BE
FIXED IN HARDWARE OR CONTROLLED USING A DIGITAL HOST (EN0 = 0 AND EN1 = 0 IS AN ILLEGAL STATE).
OPTION TO USE A CMOS (CNV+) OR LVDS (CNV±) INPUT TO CONTROL CONVERSIONS.
4
5
6
7
8
TO ENABLE SELF-CLOCKED MODE, TIE DCO+ TO GND USING A PULL-DOWN RESISTOR.
CONNECT PIN 19 AND PIN 20 TO VDD1 SUPPLY; ISOLATE FROM PIN 1 USING A FERRITE BEAD SIMILAR TO WURTH 74279266.
SEE THE DRIVING THE AD7625 SECTION FOR DETAILS ON AMPLIFIER CONFIGURATIONS.
SEE THE VOLTAGE REFERENCE OPTIONS SECTION FOR DETAILS.
Figure 22. Typical Application Diagram
Rev. B | Page 15 of 24
AD7625
Data Sheet
DRIVING THE AD7625
Differential Analog Input Source
ADA4899-1
U1
ANALOG INPUT
(UNIPOLAR 0V TO 4.096V)
Figure 24 shows an ADA4899-1 driving each differential input
to the AD7625.
590Ω
590Ω
33Ω
Single-Ended-to-Differential Driver
56pF
For applications using unipolar analog signals, a single-ended-
to-differential driver, as shown in Figure 23, allows for a differ-
ential input into the device. This configuration, when provided
with an input signal of 0 V to 4.096 V, produces a differential
4.096 V with midscale at 2.048 V. The one-pole filter using
R = 33 Ω and C = 56 pF provides a corner frequency of 86 MHz.
The VCM output of the AD7625 can be buffered and then used
to provide the required 2.048 V common-mode voltage.
IN+
AD7625
IN–
VCM
33Ω
ADA4899-1
U2
56pF
100nF
100nF
V+
V–
50Ω
AD8031, AD8032
Figure 23. Single-Ended-to-Differential Driver Circuit
1
1
REF
REF
C
10µF
C
10µF
REF
REF
2
2
+V
S
33Ω
0V TO V
REF
REF
REFIN
56pF
IN+
IN–
ADA4899-1
–V
S
AD7625
+V
S
VCM
2.048V
33Ω
GND
V
TO 0V
REF
56pF
–V
ADA4899-1
S
+V
–V
S
VCM
BUFFERED VCM PIN OUTPUT
GIVES THE REQUIRED 2.048V
COMMON-MODE SUPPLY FOR
ANALOG INPUTS.
0.1µF
AD8031, AD8032
S
1
2
SEE THE VOLTAGE REFERENCE OPTIONS SECTION. CONNECTION TO EXTERNAL REFERENCE SIGNALS
IS DEPENDENT ON THE EN1 AND EN0 SETTINGS.
C
IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESL AND ESR.
REF
THE REF AND REFIN PINS ARE DECOUPLED REGARDLESS OF EN1 AND EN0 SETTINGS.
Figure 24. Driving the AD7625 from a Differential Analog Source
Rev. B | Page 16 of 24
Data Sheet
AD7625
Table 8. Voltage Reference Options1
VOLTAGE REFERENCE OPTIONS
Option EN1
EN0
Reference Mode
The AD7625 allows flexible options for creating and buffering
the reference voltage. The AD7625 conversions refer to 4.096 V
only. The various options creating this 4.096 V reference are
controlled by the EN1 and EN0 pins (see Table 8).
A
1
1
Use internal reference and internal
reference buffer (both are enabled).
Use external 1.2 V reference with
internal reference buffer enabled.
The internal reference is disabled.
Use external 4.096 V reference with
an external reference buffer. The
internal reference and reference
buffer are disabled.
B
0
1
0
C
1
1 EN1 = 0 and EN0 = 0 is an illegal state.
A
SETTING EN1 = 1 AND EN0 = 1 ENABLES THE INTERNAL
REFERENCE AND REFERENCE BUFFER. DECOUPLE
THE REF AND REFIN PINS EXTERNALLY.
V+
V+
ADR280
ADR434
V+
ADR444
10µF
10µF
V–
C
B
SETTING EN1 = 1 AND EN0 = 0
DISABLES THE INTERNAL REFERENCE
AND REFERENCE BUFFER. CONNECT THE
BUFFERED 4.096V SIGNAL TO
SETTING EN1 = 0 AND EN0 = 1
DISABLES THE INTERNAL REFERENCE
AND ENABLES THE INTERNAL REFERENCE BUFFER.
CONNECT A 1.2V REFERENCE TO THE REFIN PIN. THE 1.2V
APPLIED TO THE REFIN PIN IS BUFFERED INTERNALLY
TO CREATE A 4.096V REFERENCE FOR THE ADC.
REF REFIN
IN+
IN–
THE REF PIN.
AD7625
Figure 25. Voltage Reference Options
Rev. B | Page 17 of 24
AD7625
Data Sheet
After VIO is established, apply the 2.5 V VDD2 supply to the
device followed by the 5 V VDD1 supply and then an external
reference (depending on the reference setting being used).
Finally, apply the analog inputs to the ADC.
25
POWER SUPPLY
The AD7625 uses both 5 V (VDD1) and 2.5 V (VDD2) power
supplies, as well as a digital input/output interface supply (VIO).
VIO allows a direct interface with 2.5 V logic only. VIO and
VDD2 can be taken from the same 2.5 V source; however, it is
best practice to isolate the VIO and VDD2 pins using separate
traces and also to decouple each pin separately.
VDD2 INTERNAL REF
20
The 5 V and 2.5 V supplies required for the AD7625 can be
VDD2 EXTERNAL REF
generated using Analog Devices, Inc., low dropout regulators
(LDOs) such as the ADP3330-2.5, ADP3330-5, ADP3334, and
15
VIO
ADP1708.
10
90
VDD1 INTERNAL REF
VDD2
85
5
VDD1 EXTERNAL REF
80
VDD1
75
0
0
1000
2000
3000
4000
5000
6000
7000
SAMPLING RATE (kSPS)
70
65
60
Figure 27. Current Consumption vs. Sampling Rate
150
140
130
120
110
100
90
55
INTERNAL REFERENCE USED
50
1
10
100
1k
10k
INTERNAL REF
SUPPLY FREQUENCY (Hz)
Figure 26. PSRR vs. Supply Frequency
(350 mV pp Ripple on VDD2, 600 mV Ripple on VDD1)
EXTERNAL REF
Power-Up
When powering up the AD7625 device, first apply the VIO
voltage to the device so that the EN1 and EN0 values can be set
for the reference option in use. Connect the EN0 and EN1 pins
to pull-up/pull-down resistors to ensure that one or both of
these pins is set to a nonzero value. EN0 = 0 and EN1 = 0 is an
illegal state that must be avoided.
80
70
60
0
1000
2000
3000
4000
5000
6000
7000
SAMPLING RATE (kSPS)
Figure 28. Power Dissipation vs. Sampling Rate
Rev. B | Page 18 of 24
Data Sheet
AD7625
The clock DCO is a buffered copy of CLK and is synchronous
to the data, D , which is updated on the falling edge of DCO+
(tD). By maintaining good propagation delay matching between
DIGITAL INTERFACE
Conversion Control
All analog-to-digital conversions are controlled by the CNV
signal. This signal can be applied in the form of a CNV+/CNV−
LVDS signal, or it can be applied in the form of a 2.5 V CMOS
logic signal to the CNV+ pin. The conversion is initiated by the
rising edge of the CNV signal.
D
and DCO through the board and the digital host, DCO
can be used to latch D with good timing margin for the shift
register.
Conversions are initiated by a CNV pulse. The CNV pulse
must be returned low (≤tCNVH maximum) for valid operation.
After a conversion begins, it continues until completion. Addi-
tional CNV pulses are ignored during the conversion phase.
After the time tMSB elapses, the host should begin to burst the
CLK . Note that tMSB is the maximum time for the MSB of the
new conversion result and should be used as the gating device
for CLK . The echoed clock, DCO , and the data, D , are
driven in phase, with D being updated on the falling edge of
DCO+; the host should use the rising edge of DCO+ to capture
D . The only requirement is that the 16 CLK pulses finish
before the time tCLKL elapses for the next conversion phase or the
data is lost. From the time tCLKL to tMSB, D and DCO are
driven to 0s. Set CLK to idle low between CLK bursts.
After the AD7625 is powered up, the first conversion result
generated is invalid. Subsequent conversion results are valid
provided that the time between conversions does not exceed
the maximum specification for tCYC
.
The two methods for acquiring the digital data output of the
AD7625 via the LVDS interface are described in the following
sections.
Echoed-Clock Interface Mode
The digital operation of the AD7625 in echoed-clock interface
mode is shown in Figure 29. This interface mode, requiring
only a shift register on the digital host, can be used with many
digital hosts (FPGA, shift register, microprocessor, and so on).
It requires three LVDS pairs (D , CLK , and DCO ) between
each AD7625 and the digital host.
SAMPLE N
SAMPLE N + 1
tCYC
tCNVH
CNV–
CNV+
tACQ
ACQUISITION
ACQUISITION
ACQUISITION
tCLKL
15
tCLK
15
16
1
2
16
1
2
3
CLK–
CLK+
tDCO
1
15
16
1
2
15
16
2
3
DCO–
DCO+
tMSB
tD
tCLKD
D+
D–
D1
N – 1
D0
N – 1
D15
N
D14
N
D1
N
D0
N
D15
N + 1
D14
D13
0
0
N + 1 N + 1
Figure 29. Echoed-Clock Interface Mode Timing Diagram
Rev. B | Page 19 of 24
AD7625
Data Sheet
Conversions are initiated by a CNV pulse. The CNV pulse
must be returned low (≤tCNVH maximum) for valid operation.
After a conversion begins, it continues until completion. Addi-
tional CNV pulses are ignored during the conversion phase.
After the time tMSB elapses, the host should begin to burst the
CLK . Note that tMSB is the maximum time for the first bit of
the header and should be used as the gating device for CLK .
CLK is also used internally on the host to begin the internal
synchronization state machine. The next header bit and conversion
results are output on subsequent falling edges of CLK . The
only requirement is that the 18 CLK pulses finish before the
time tCLKL elapses for the next conversion phase or the data is
lost. Set CLK to idle high between bursts of 18 CLK pulses.
Self-Clocked Interface Mode
The digital operation of the AD7625 in self-clocked interface
mode is shown in Figure 30. This interface mode reduces the
number of wires between ADCs and the digital host to two LVDS
pairs per AD7625 (CLK and D ) or to a single pair if sharing a
common CLK using multiple AD7625 devices. Self-clocked
interface mode facilitates the design of boards that use multiple
AD7625 devices. The digital host can adapt the interfacing
scheme to account for differing propagation delays between
each AD7625 device and the digital host.
The self-clocked interface mode consists of preceding the results
of each ADC word with a 2-bit header on the data, D . This
header is used to synchronize D of each conversion in the
digital host. Synchronization is accomplished by one simple
state machine per AD7625 device. For example, if the state
machine is running at the same speed as CLK with three
phases, the state machine measures when the Logic 1 of the
header occurs.
SAMPLE N
SAMPLE N + 1
tCYC
tCNVH
CNV–
CNV+
tACQ
ACQUISITION
tCLK
ACQUISITION
ACQUISITION
tCLKL
1
17
18
1
2
3
4
17
18
2
3
CLK–
CLK+
tMSB
tCLKD
D+
D–
D15
N + 1
D14
N
D1
N
D0
N
D1
N – 1
D0
N – 1
D15
N
0
1
0
0
1
0
Figure 30. Self-Clocked Interface Mode Timing Diagram
Rev. B | Page 20 of 24
Data Sheet
AD7625
APPLICATIONS INFORMATION
supply to Pin 19 and Pin 20 using a 100 nF capacitor to GND.
This GND connection can be placed a short distance away from
the exposed pad.
LAYOUT, DECOUPLING, AND GROUNDING
When laying out the printed circuit board (PCB) for the AD7625,
follow the practices described in this section to obtain the maxi-
mum performance from the converter.
VIO Supply Decoupling
Decouple the VIO supply applied to Pin 12 to ground at Pin 13.
Layout and Decoupling of Pin 25 to Pin 32
Exposed Pad
The AD7625 has an exposed pad on the underside of the package.
Connect the outputs of Pin 25, Pin 26, and Pin 28 together and
decouple them to Pin 27 using a 10 μF capacitor with low ESR
and low ESL.
Solder the pad directly to the PCB.
Connect the pad to the ground plane of the board using
multiple vias, as shown in Figure 31.
Decouple all supply pins except for Pin 12 (VIO) directly to
the pad, minimizing the current return path.
Pin 13 and Pin 24 can be connected directly to the pad. Use
vias to ground at the point where these pins connect to the
pad.
Reduce the inductance of the path connecting Pin 25, Pin 26,
and Pin 28 by widening the PCB traces connecting these pins.
A similar approach should be taken in the connections used for
the reference pins of the AD7625. Connect Pin 29, Pin 30, and
Pin 32 together using widened PCB traces to reduce inductance.
In internal or external reference mode, a 4.096 V reference voltage
is output on Pin 29, Pin 30, and Pin 32. Decouple these pins to
Pin 31 using a 10 μF capacitor with low ESR and low ESL.
VDD1 Supply Routing and Decoupling
The VDD1 supply is connected to Pin 1, Pin 19, and Pin 20. The
supply should be decoupled using a 100 nF capacitor at Pin 1.
The user can connect this supply trace to Pin 19 and Pin 20. Use
a series ferrite bead to connect the VDD1 supply from Pin 1 to
Pin 19 and Pin 20. The ferrite bead isolates any high frequency
noise or ringing on the VDD1 supply. Decouple the VDD1
Figure 31 shows an example of the recommended layout for
the underside of the AD7625 device. Note the extended signal
trace connections and the outline of the capacitors decoupling
the signals applied to the REF pins (Pin 29, Pin 30, and Pin 32)
and to the CAP2 pins (Pin 25, Pin 26, and Pin 28).
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
Paddle
4.096V
EXTERNAL REFERENCE
(ADR434 OR ADR444)
1
2
3
4
5
6
7
8
Figure 31. PCB Layout and Decoupling Recommendations for Pin 24 to Pin 32
Rev. B | Page 21 of 24
AD7625
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
24
32
1
0.50
BSC
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
16
8
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
Figure 32. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-32-7
CP-32-7
AD7625BCPZ
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
AD7625BCPZRL7
EVAL-AD7625FMCZ
EVAL-SDP-CH1Z
Controller Board
1 Z = RoHS Compliant Part.
2 The EVAL-SDP-CH1Z board allows the PC to control and communicate with all Analog Devices evaluation boards with model numbers ending with the FMC designator.
Rev. B | Page 22 of 24
Data Sheet
NOTES
AD7625
Rev. B | Page 23 of 24
AD7625
NOTES
Data Sheet
©2009–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07652-0-10/15(B)
Rev. B | Page 24 of 24
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