AD7628BQ [ROCHESTER]
DUAL, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, CDIP20, 0.300 INCH, CERDIP-20;
| 型号： | AD7628BQ |
| 厂家： | 
Rochester Electronics |
| 描述： | DUAL, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, CDIP20, 0.300 INCH, CERDIP-20 CD 输入元件 转换器 |
| 文件： | 总9页 (文件大小：875K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS Dual 8-Bit
Buffered Multiplying DAC
a
AD7628
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
On-Chip Latches for Both DACs
+12 V to +15 V Operation
DACs Matched to 1%
Four Quadrant Multiplication
TTL/ CMOS Com patible from +12 V to +15 V
Latch Free (Protection Schottkys not Required)
APPLICATIONS
Disk Drives
Program m able Filters
X-Y Graphics
Gain/ Attenuation
GENERAL D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he AD7628 is a monolithic dual 8-bit digital/analog converter
featuring excellent DAC-to-DAC matching. It is available in
small 0.3" wide 20-pin DIPs and in 20-terminal surface mount
packages.
1. DAC to DAC matching: since both of the AD7628 DACs
are fabricated at the same time on the same chip, precise
matching and tracking between DAC A and DAC B is inher-
ent. T he AD7628’s matched CMOS DACs make a whole
new range of applications circuits possible, particularly in the
audio, graphics and process control areas.
Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.
2. Small package size: combining the inputs to the on-chip
DAC latches into a common data bus and adding a DAC A/
DAC B select line has allowed the AD7628 to be packaged in
a small 20-pin 0.3" wide DIP, 20-pin SOIC, 20-terminal
PLCC and 20-terminal LCC.
Data is transferred into either of the two DAC data latches via a
common 8-bit T T L/CMOS compatible input port. Control in-
put DAC A/DAC B determines which DAC is to be loaded.
T he AD7628’s load cycle is similar to the write cycle of a ran-
dom access memory, and the device is bus compatible with most
8-bit microprocessors, including 6502, 6809, 8085, Z80.
3. T T L-Compatibility: All digital inputs are T T L-compatible
over a +12 V to +15 V power supply range.
T he device operates from a +12 V to +15 V power supply and is
T T L-compatible over this range. Power dissipation is a low
20 mW.
Both DACs offer excellent four quadrant multiplication charac-
teristics with a separate reference input and feedback resistor for
each DAC.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1996
(V = +10.8 V to +15.75 V, V A = V B = +10 V; OUT A = OUT B = 0 V unless
DD
REF
REF
AD7628–SPECIFICATIONS
otherwise noted)
TA = –40؇C
TA = –55؇C
to +125؇C1
P aram eter
TA = +25؇C1
to +85؇C
Units
Test Conditions/Com m ents
ST AT IC PERFORMANCE2
Resolution
Relative Accuracy
8
8
8
Bits
LSB max
LSB max
±1/2
±1
±1/2
±1
±1/2
±l
T his is an Endpoint Linearity Specification
All Grades Guaranteed Monotonic Over
Full Operating T emperature Range
Measured Using Internal RFB A and RFB B.
Both DAC Latches Loaded with 11111111.
Gain Error is Adjustable Using Circuits
of Figures 4 and 5.
Differential Nonlinearity
Gain Error
±2
±3
±3
LSB max
Gain T emperature Coefficient3
∆Gain/∆T emperature
±0.0035
±0.0035
%/°C max
Output Leakage Current
OUT A (Pin 2)
OUT B (Pin 20)
±50
±50
8
±200
±200
8
±200
±200
8
nA max
nA max
kΩ min
kΩ max
DAC Latches Loaded with 00000000
Input Resistance (VREFA, VREFB)
Input Resistance T C = –300 ppm/°C, T ypical
Input Resistance is 11 kΩ
15
15
15
V
REFA/VREFB Input Resistance
Match
±1
±1
±1
% max
DIGIT AL INPUT S4
Input High Voltage (VIH
Input Low Voltage (VIL
Input Current (IIN
Input Capacitance
DB0–DB7
)
2.4
0.8
±1
2.4
0.8
±10
2.4
0.8
±10
V min
V max
µA max
)
)
VIN = 0 or VDD
10
15
10
15
10
15
pF max
pF max
WR, CS, DACA/DACB
SWIT CHING CHARACT ERIST ICS3
See T iming Diagram
Chip Select to Write Set Up T ime (tCS
Chip Select to Write Hold T ime (tCH
DAC Select to Write Set Up T ime (tAS
DAC Select to Write Hold T ime (tAH
Data Valid to Write Set Up T ime (tDS
Data Valid to Write Hold T ime (tDH
)
160
10
160
10
160
10
150
160
10
160
10
160
10
170
210
10
210
10
210
10
210
ns min
ns min
ns min
ns min
ns min
ns min
ns min
)
)
)
)
)
Write Pulse Width (tWR
)
POWER SUPPLY
IDD, K Grade
See Figure 3
All Digital Inputs VIL or VIH
All Digital Inputs VIL or VIH
2
2
2
2.5
mA
mA
B, T Grades
2.5
All Grades
100
500
500
µA
All Digital Inputs 0 V or VDD
Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS These characteristics are included for Design Guidance only and are not
subject to test. V = +10.8 V to +15.75 V. (Measured Using Recommended PC Board Layout (Figure 7) and AD644 as Output Amplifiers)
DD
TA = –40؇C
to +85؇C1
TA = –55؇C
to +125؇πC1
P aram eter
TA = +25؇C1
Units
Test Conditions/Com m ents
DC SUPPLY REJECT ION
(∆GAIN/∆VDD
)
0.01
350
0.02
400
0.02
400
% per % max ∆VDD = ±5%
CURRENT SET T LING T IME
ns max
T o 1/2 LSB OutA/OutB Load = 100 Ω.
WR = CS = 0 V.
DB0–DB7 = 0 V to VDD or VDD to 0 V
DIGIT AL-T O-ANALOG GLIT CH
IMPULSE
330
nV sec typ
For Code T ransition 00000000 to 11111111
OUT PUT CAPACIT ANCE
COUT
COUT
A
B
25
25
60
60
25
25
60
60
25
25
60
60
pF max
pF max
pF max
pF max
DAC Latches Loaded with 00000000
DAC Latches Loaded with 11111111
C
COUT
OUT A
B
AC FEEDT HROUGH
REFA to OUT A
VREFB to OUT B
V
–70
–70
–65
–65
–65
–65
dB max
dB max
VREFA, VREFB = 20 V p-p Sine Wave
@ 10 kHz
CHANNEL-T O-CHANNEL ISOLAT ION
VREFA to OUT B
Both DAC Latches Loaded with 11111111.
VREFA = 20 V p-p Sine Wave @ 10 kHz
VREFB = 0 V See Figure 6.
VREFB = 20 V p-p Sine Wave @ 10 kHz
VREFA = 0 V See Figure 6.
–80
–80
dB typ
dB typ
VREFB to OUT A
DIGIT AL CROSST ALK
60
nV sec typ
dB typ
Measured for Code T ransition 00000000
to 11111111
HARMONIC DIST ORT ION
NOT ES
–85
VIN = 6 V rms @ 1 kHz
1T emperature Ranges are K Version; –40°C to +85°C; B Version; –40°C to +85°C; T Version; –55°C to +125°C.
2Specification applies to both DACs in AD7628.
3Guaranteed by design but not production tested.
4Logic inputs are MOS Gates. T ypical input current (+25°C) is less than 1 nA.
Specifications subject to change without notice.
–2–
REV. A
AD7628
TERMINO LO GY
Relative Accur acy:
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after ad-
justing for zero and full-scale, and is normally expressed in
LSBs or as a percentage of full-scale reading.
ABSO LUTE MAXIMUM RATINGS
(T A = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V
Digital Input Voltage to DGND . . . . . . –0.3 V, VDD + 0.3 V
VPIN2, VPIN20 to AGND . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
D iffer ential Nonlinear ity:
VREF A, VREF B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V
VRFB A, VRFB B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating T emperature Range
Commercial (K) Grades . . . . . . . . . . . . . . . –40°C to +85°C
Industrial (B) Grades . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T ) Grades . . . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
Gain Er r or :
Gain error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC latches after offset error has been adjusted out. Gain
error of both DACs is adjustable to zero with external resistance.
O utput Capacitance:
Capacitance from OUT A or OUT B to AGND.
O RD ERING GUID E
D igital-to-Analog Glitch Im pulse:
Tem perature
Range
Relative
Accuracy Error
Gain
P ackage
O ption2
Model1
T he amount of charge injected from the digital inputs to the
analog output when the inputs change state. T his is normally
specified as the area of the glitch in either pA-secs or nV-secs,
depending upon whether the glitch is measured as a current or
voltage signal. Glitch impulse is measured with VREF A, VREF
= AGND.
AD7628KN –40°C to +85°C
AD7628KP –40°C to +85°C
AD7628KR –40°C to +85°C
AD7628BQ –40°C to +85°C
AD7628T Q –55°C to +125°C ±1/2 LSB ±2 LSB Q-20
AD7628T E –55°C to +125°C ±1/2 LSB ±2 LSB E-20A
±1/2 LSB ±2 LSB N-20
±1/2 LSB ±2 LSB P-20A
±1/2 LSB ±2 LSB R-20
±1/2 LSB ±2 LSB Q-20
B
Channel-to-Channel Isolation:
T he proportion of input signal from one DAC’s reference input
that appears at the output of the other DAC, expressed as a
ratio in dB.
NOT ES
1T o order MIL-ST D-883, Class B process parts, add /883B to part number.
Contact your local sales office for military data sheet.
2E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = SOIC.
D igital Cr osstalk:
T he glitch energy transferred to the output of one converter due
to a change in digital input code to the other converter. Speci-
fied in nV secs.
P IN CO NFIGURATIO NS
LCCC
D IP , SO IC
P LCC
1
AGND
OUT A
RFB A
20 OUT B
19 RFB B
3
2
1 20 19
2
3
4
5
6
7
8
9
3
2
20 19
1
18 VREF
17 VDD
B
4
V
A
18
17
16
V
V
B
V
A
4
5
6
7
8
18
17
V
V
B
REF
REF
DD
REF
REF
VREF
A
DGND 5
DGND
DAC A/DAC B
DB7 (MSB)
DB6
AD7628
TOP VIEW
(Not to Scale)
DD
AD7628
TOP VIEW
(Not to Scale)
AD7628
TOP VIEW
(Not to Scale)
DGND
DAC A/DAC B
(MSB) DB7
DB6
16 WR
6
7
8
WR
DAC A /DAC B
DB7 (MSB)
DB6
16 WR
15 CS
15 CS
15 CS
14 DB0 (LSB)
13 DB1
12 DB2
11 DB3
14
DB0 (LSB)
14 DB0 (LSB)
9
10 11 12 13
9
10
12 13
11
DB5
DB4 10
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7628 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD7628
INTERFACE LO GIC INFO RMATIO N
D AC Selection
Both DAC latches share a common 8-bit input port. T he con-
trol input DAC A/DAC B selects which DAC can accept data
from the input port.
weighted currents are switched between the DAC output and
AGND, thus maintaining fixed currents in each ladder leg inde-
pendent of switch state.
EQ UIVALENT CIRCUIT ANALYSIS
Figure 2 shows an approximate equivalent circuit for one of
the AD7628’s D/A converters, in this case DAC A. A similar
equivalent circuit can be drawn for DAC B. Note that AGND
(Pin 1) is common for both DAC A and DAC B.
Mode Selection
Inputs CS and WR control the operating mode of the selected
DAC. See Mode Selection T able below.
Wr ite Mode
T he current source ILEAKAGE is composed of surface and junc-
tion leakages and, as with most semiconductor devices, approxi-
mately doubles every 10°C. T he resistor Ro, as shown in Fig-
ure 2, is the equivalent output resistance of the device, which
varies with input code (excluding all 0s code) from 0.8R to 2R.
R is typically 11 kΩ. COUT is the capacitance due to the N-channel
switches and varies from about 50 pF to 120 pF, depending on
the digital input. g(VREF A, N) is the T hevenin equivalent volt-
age generator due to the reference input voltage VREF A and the
transfer function of the R-2R ladder.
When CS and WR are both low, the selected DAC is in the write
mode. T he input data latches of the selected DAC are transpar-
ent and its analog output responds to activity on DB0–DB7.
H old Mode
T he selected DAC latch retains the data that was present on
DB0–DB7 just prior to CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches.
Mode Selection Table
For further information on CMOS multiplying D/A converters,
refer to “CMOS DAC Application Guide, 2ND Edition” avail-
able from Analog Devices, Publication Number G872a–15–4/86.
DAC A/
D AC B
CS
WR
D AC A
D AC B
L
L
L
H
X
L
L
X
H
WRIT E
HOLD
HOLD
HOLD
HOLD
WRIT E
HOLD
HOLD
H
X
X
L = Low State, H = High State, X = Don’t Care
WRITE CYCLE TIMING D IAGRAM
Figure 2. Equivalent Analog Output Circuit of DAC A
CIRCUIT INFO RMATIO N–D IGITAL SECTIO N
T he input buffers are simple CMOS level-shifters designed so
that when the AD7628 is operated with VDD from 10.8 V to
15.75 V, the buffer converts TTL input levels (2.4 V and 0.8 V)
into CMOS logic levels. When VIN is in the region of 1.0 volt to
2.0 volts, the input buffers operate in their linear region and
pass a quiescent current (see Figure 3). To minimize power sup-
ply currents, it is recommended that the digital input voltages be as
close to the supply rails (VDD and DGND) as practicably possible.
T he AD7628 may be operated with any supply voltage in the
range 10.8 ≤ VDD ≤ 15.75 volts.
CIRCUIT INFO RMATIO N—D /A SECTIO N
The AD7628 contains two identical 8-bit multiplying D/A con-
verters, DAC A and DAC B. Each DAC consists of a highly
stable thin film R-2R ladder and eight N-channel current steering
switches. A simplified D/A circuit for DAC A is shown in Figure
1. An inverted R-2R ladder structure is used; that is, binary
Figure 3. Typical Plot of Supply Current, IDD vs. Logic
Input Voltage VIN to VDD = +15 V
Figure 1. Sim plified Functional Circuit for DAC A
REV. A
–4–
AD7628
Figure 4. Dual DAC Unipolar Binary Operation (2 Quadrant Multiplication). See Table I.
Figure 5. Dual DAC Bipolar Operation (4 Quadrant Multiplication). See Table II.
Table II. Bipolar (O ffset Binary) Code Table
Table I. Unipolar Binary Code Table
D AC Latch Contents
MSB LSB
Analog O utput
(D AC A or D AC B)
D AC Latch Contents
MSB LSB
Analog O utput
(D AC A or D AC B)
127
255
+V IN
–V IN
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
128
256
1
129
+V IN
–V IN
128
256
128
256
V IN
–V IN
–V IN
–V IN
–V IN
= –
0
2
1
127
256
–V IN
128
127
1
–V IN
128
256
128
–V IN
0
= 0
128
256
1
NOT E: 1 LSB = (2–8)(VIN) =
1
V
(
NOT E: 1 LSB = (2–7)(VIN ) =
)
IN
V
(
)
IN
256
128
Table III. Recom m ended Trim Resistor Values
Trim
Resistor
K/B/T
R1; R3
R2; R4
500
150
REV. A
–5–
AD7628
Figure 7 shows a printed circuit layout for the AD7628 and the
AD644 dual op amp, which minimizes feedthrough and crosstalk.
AP P LICATIO NS INFO RMATIO N
Application H ints
T o ensure system performance consistent with AD7628 specifi-
cations, careful attention must be given to the following points:
SINGLE SUP P LY AP P LICATIO NS
T he AD7628 DAC R-2R ladder termination resistors are con-
nected to AGND within the device. T his arrangement is par-
ticularly convenient for single supply operation because AGND
may be biased at any voltage between DGND and VDD. Figure
8 shows a circuit that provides two +5 V to +8 V analog outputs
by biasing AGND +5 V up from DGND. T he two DAC refer-
ence inputs are tied together and a reference input voltage is ob-
tained without a buffer amplifier by making use of the constant
and matched impedances of the DAC A and DAC B reference
inputs. Current flows through the two DAC R-2R ladders into
R1, and R1 is adjusted until the VREF A and VREF B inputs are
at +2 V. T he two analog output voltages range from +5 V to
+8 V for DAC codes 00000000 to l l l l l l l l .
1. GENERAL GROUND MANAGEMENT : AC or transient
voltages between the AD7628 AGND and DGND can cause
noise injection into the analog output. T he simplest method
of ensuring that voltages at AGND and DGND are equal is
to tie AGND and DGND together at the AD7628. In more
omplex systems where the AGND–DGND intertie is on the
backplane, it is recommended that diodes be connected in
inverse parallel between the AD7628 AGND and DGND
pins (1N914 or equivalent).
2. OUT PUT AMPLIFIER OFFSET : CMOS DACs exhibit a
code-dependent output resistance which, in turn, causes a
code-dependent amplifier noise gain. T he effect is a code-
dependent differential nonlinearity term at the amplifier
output that depends on VOS (VOS is amplifier input offset
voltage). This differential nonlinearity term adds to the R/2R
differential nonlinearity. T o maintain monotonic operation, it
is recommended that amplifier VOS be no greater than 10% of
1 LSB over the temperature range of interest.
3. HIGH FREQUENCY CONSIDERAT IONS: T he output
capacitance of a CMOS DAC works in conjunction with the
amplifier feedback resistance to add a pole to the open loop
response. T his can cause ringing or oscillation. Stability can
be restored by adding a phase compensation capacitor in
parallel with the feedback resistor.
D YNAMIC P ERFO RMANCE
Figure 8. AD7628 Single Supply Operation
T he dynamic performance of the two DACs in the AD7628 will
depend on the gain and phase characteristics of the output am-
plifiers, together with the optimum choice of the PC board lay-
out and decoupling components. Figure 6 shows the relationship
between input frequency and channel-to-channel isolation.
Figure 9 shows DAC A of the AD7628 connected in a positive
reference, voltage switching mode. T his configuration is useful
because VOUT is the same polarity as VIN, allowing single supply
operation. However, to retain specified linearity, VIN must be in
the range 0 V to +2.5 V and the output buffered or loaded with
a high impedance (see Figure 10). Note that the input voltage is
connected to the DAC OUT A, and the output voltage is taken
from the DAC VREF A pin.
Figure 6. Channel-to-Channel Isolation
Figure 9. AD7628 Single Supply, Voltage Switching Mode
Figure 7. Suggested PC Board Layout for AD7628 with
AD644 Dual Op Am p
Figure 10. Typical AD7628 Perform ance in Single Supply
Voltage Switching Mode
REV. A
–6–
AD7628
MICRO P RO CESSO R INTERFACE
Figure 11. AD7628 Dual DAC to 6800 CPU Interface
Figure 12. AD7628 Dual DAC to 8085 CPU Interface
P RO GRAMMABLE WIND O W CO MP ARATO R
In the circuit of Figure 13, the AD7628 is used to implement a
programmable window comparator. DACs A and B are loaded
with the required upper and lower voltage limits for the test,
respectively. If the test input is not within the programmed lim-
its, the pass/fail output will indicate a fail (logic zero).
Figure 13. Digitally Program m able Window Com parator
(Upper and Lower Lim it Detector)
CIRCUIT EQ UATIO NS
C1 = C2, R1 = R2, R4 = R5
P RO GRAMMABLE STATE VARIABLE FILTER
1
fC
=
2π R C1
1
R3
RF
.
Q =
R4 RFBB1
RF
AO = –
RS
NOT E
DAC equivalent resistance equals
256 × DAC Ladder resistance
(
)
DAC Digital Code
Figure 14. Digitally Controlled State Variable Filter
In this state, variable or universal filter configuration (Figure
14) for DACs A1 and B1 control the gain and Q of the filter
characteristic, while DACs A2 and B2 control the cutoff fre-
quency, fC. DACs A2 and B2 must track accurately for the simple
expression for fC to hold. T his is readily accomplished by the
AD7628. Op amps are 2 × AD644. C3 compensates for the
effects of op amp gain-bandwidth limitations.
T he filter provides low pass, high pass and band pass outputs
and is ideally suited for applications where microprocessor con-
trol of filter parameters is required, e.g., equalizer, tone con-
trols, etc.
Programmable range for component values shown is fC = 0 kHz
to 15 kHz and Q = 0.3 to 4.5.
REV. A
–7–
AD7628
D IGITALLY CO NTRO LLED D UAL
MECH ANICAL INFO RMATIO N
TELEP H O NE ATTENUATO R
O UTLINE D IMENSIO NS
In this configuration, the AD7628 functions as a 2-channel
digitally controlled attenuator; ideal for stereo audio and tele-
phone signal level control applications. T able IV gives input
codes vs. attenuation for a 0 dB to 15.5 dB range.
D imensions shown in inches and (mm).
20-P in Cer dip (Q Suffix)
Attenuation, dB
−
Input Code = 256 × 10 exp
20
20-P in P lastic D IP (N Suffix)
Figure 15. Digitally Controlled Dual Telephone Attenuator
Table IV. Attenuation vs. D AC A, D AC B Code for the
Circuit of Figure 15
20-Ter m inal
Leadless Chip
Car r ier (E Suffix)
D AC Input
Attn. dB Code
Code in
D ecim al Attn. dB Code
D AC Input
Code in
D ecim al
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
1 1 1 1 1 1 1 1 255
1 1 1 1 0 0 1 0 242
1 1 1 0 0 1 0 0 228
1 1 0 1 0 1 1 1 215
1 1 0 0 1 0 1 1 203
1 1 0 0 0 0 0 0 192
1 0 1 1 0 1 0 1 181
1 0 1 0 1 0 1 1 171
1 0 1 0 0 0 1 0 162
1 0 0 1 1 0 0 0 152
1 0 0 1 0 0 0 0 144
1 0 0 0 1 0 0 0 136
1 0 0 0 0 0 0 0 128
8.0
8.5
9.0
0 1 1 0 0 1 1 0
0 1 1 0 0 0 0 0
0 1 0 1 1 0 1 1
0 1 0 1 0 1 1 0
0 1 0 1 0 0 0 1
0 1 0 0 1 1 0 0
0 1 0 0 1 0 0 0
0 1 0 0 0 1 0 0
0 1 0 0 0 0 0 0
0 0 1 1 1 1 0 1
0 0 1 1 1 0 0 1
0 0 1 1 0 1 1 0
0 0 1 1 0 0 1
102
96
91
86
81
76
72
68
64
61
57
54
51
48
46
43
9.5
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
14.5
15.0
15.5
20-Ter m inal
P lastic Leaded
Chip Car r ier (P Suffix)
0 1 1 1 0 0 1
121
0 0 1 1 0 0 0 0
0 0 1 0 1 1 1 0
0 0 1 0 1 0 1 1
0 1 1 1 0 0 1 0 114
0 1 1 0 1 1 0 0 108
REV. A
–8–
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