AD7545JP [ADI]

CMOS 12-Bit Buffered Multiplying DAC; CMOS 12位缓冲乘法DAC


型号：	AD7545JP
厂家：	ADI
描述：	CMOS 12-Bit Buffered Multiplying DAC CMOS 12位缓冲乘法DAC
文件：	总8页 (文件大小：197K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CMOS 12-Bit

Buffered Multiplying DAC

AD7545

FEATURES

FUNCTIONAL BLOCK DIAGRAM

12-Bit Resolution

Low Gain TC: 2 ppm/؇C typ

Fast TTL Compatible Data Latches

Single +5 V to +15 V Supply

Small 20-Lead 0.3" DIP and 20-Terminal Surface Mount

Packages

AD7545

OUT 1

AGND

12-BIT

MULTIPLYING DAC

REF

Latch Free (Schottky Protection Diode Not Required)

Low Cost

Ideal for Battery Operated Equipment

WR 17

INPUT DATA LATCHES

DGND

DB11–DB0

(PINS 4–15)

GENERAL DESCRIPTION

The AD7545 is particularly suitable for single supply operation

and applications with wide temperature variations.

The AD7545 is a monolithic 12-bit CMOS multiplying DAC

with onboard data latches. It is loaded by a single 12-bit wide

word and directly interfaces to most 12- and 16-bit bus systems.

Data is loaded into the input latches under the control of the CS

and WR inputs; tying these control inputs low makes the input

latches transparent, allowing direct unbuffered operation of the

DAC.

The AD7545 can be used with any supply voltage from +5 V to

+15 V. With CMOS logic levels at the inputs the device dissi-

pates less than 0.5 mW for V_DD= +5 V.

PIN CONFIGURATIONS

LCCC

DIP

PLCC

OUT 1

AGND

DGND

DB11 (MSB)

DB10

REF

20 19

1 20 19

PIN 1

IDENTIFIER

DB11 (MSB)

DB10

DB11 (MSB)

17 WR

DB10 5

DB9 6

DB8 7

DB7 8

AD7545

TOP VIEW

(Not to Scale)

AD7545

TOP VIEW

(Not to Scale)

AD7545

TOP VIEW

(Not to Scale)

DB9

DB0 (MSB)

DB1

DB9

DB0 (LSB)

DB8

15 DB0 (LSB)

14 DB1

DB8

14 DB1

DB7

DB2

DB7

10 11 12 13

DB6

DB3

DB4

DB5

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

World Wide Web Site: http://www.analog.com

(V_REF= +10 V, V_OUT1= O V, AGND = DGND unless otherwise noted)

AD7545–SPECIFICATIONS

V_DD= +5 V

Limits

T_A= + 25؇C T_MIN,T_MAX

V_DD= +15 V

Limits

T_A= + 25؇C T_MIN,T_MAX

Parameter

Version

Units

Test Conditions/Comments

STATIC PERFORMANCE

Resolution

All

J, A, S

Bits

LSB max

K, B, T

L, C, U

GL, GC, GU

J, A, S

K, B, T

L, C, U

GL, GC, GU

J, A, S

1/2

Differential Nonlinearity

10-Bit Monotonic T_MINto T_MAX

12-Bit Monotonic T_MINto T_MAX

DAC Register Loaded with

1111 1111 1111

Gain Error (Using Internal RFB)²

K, B, T

L, C, U

GL, GC, GU

Gain Error Is Adjustable Using

the Circuits of Figures 4, 5, and 6

Gain Temperature Coefficient³

∆Gain/∆Temperature

All

ppm/°C max

Typical Value is 2 ppm/°C for V_DD= +5 V

DC Supply Rejection³

∆Gain/∆V_DD

All

0.015

0.03

0.01

0.02

% per % max ∆V_DD

Output Leakage Current at OUT1

J, K, L, GL

A, B, C, GC

S, T, U, GU

nA max

DB0–DB11 = 0 V; WR, CS = 0 V

200

DYNAMIC PERFORMANCE

Current Settling Time³

All

µs max

To 1/2 LSB. OUT1 Load = 100 Ω. DAC

Output Measured from Falling Edge of

WR, CS = 0.

Propagation Delay³(from Digital

Input Change to 90%

of Final Analog Output)

Digital-to-Analog Glitch Inpulse

AC Feedthrough⁵

All

300

400

–

250

–

ns max

nV sec typ

OUT1 Load = 100 Ω, C_EXT= 13 pF⁴

V_REF= AGND

At OUT1

All

mV p-p typ

V_REF= 10 V, 10 kHz Sinewave

REFERENCE INPUT

Input Resistance

kΩ min

kΩ max

Input Resistance TC = –300 ppm/°C typ

Typical Input Resistance = 11 kΩ

(Pin 19 to GND)

ANALOG OUTPUT

Output Capacitance³

C_OUT1

All

200

pF max

DB0–DB11 = 0 V, WR, CS = 0 V

DB0–DB11 = V_DD, WR, CS = 0 V

C_OUT1

DIGITAL INPUTS

Input High Voltage

V_IH

All

2.4

0.8

2.4

0.8

13.5

1.5

13.5

1.5

V min

V max

µA max

Input Low Voltage

V_IL

Input Current⁶

I_IN

V_IN= 0 or V_DD

Input Capacitance³

DB0–DB11

WR, CS

All

pF max

V_IN= 0

SWITCHING CHARACTERISTICS⁷

Chip Select to Write Setup Time

t_CS

All

280

200

380

270

180

120

200

150

ns min

ns typ

See Timing Diagram

Chip Select to Write Hold Time

t_CH

All

ns min

Write Pulse Width

t_WR

250

175

140

100

400

280

210

150

160

100

240

170

120

ns min

ns typ

ns min

ns typ

t_CS≥ t_WR, t_CH≥ 0

Data Setup Time

t_DS

Data Hold Time

t_DH

All

ns min

POWER SUPPLY

I_DD

100

500

100

500

mA max

µA max

µA typ

All Digital Inputs V_ILor V_IH

All Digital Inputs 0 V to V_DD

NOTES

¹Temperature range as follows: J, K, L, GL versions, 0°C to +70°C; A, B, C, GC versions, –25°C to +85°C; S, T, U GU versions, –55°C to +125°C.

²This includes the effect of 5 ppm max gain TC.

³Guaranteed but not tested.

⁴DB0–DB11 = 0 V to V_DDor V_DDto 0 V.

⁵Feedthrough can be further reduced by connecting the metal lid on the ceramic package (Suffix D) to DGND.

⁶Logic inputs are MOS gates. Typical input current (+25°C) is less than 1 nA.

⁷Sample tested at +25°C to ensure compliance.

Specifications subject to change without notice.

–2–

REV. A

AD7545

t_CH

MODE SELECTION

HOLD MODE:

t_CS

WRITE MODE:

CHIP

SELECT

CS AND WR LOW, DAC RESPONDS

TO DATA BUS (DB0–DB11) INPUTS.

EITHER CS OR WR HIGH, DATA BUS

(DB0–DB11) IS LOCKED OUT; DAC

HOLDS LAST DATA PRESENT WHEN

t_WR

WR OR CS ASSUMED HIGH STATE.

WRITE

NOTES:

= +5V; t = t = 20ns

r f

t_DS

DATA VALID

t_DH

= +15V; t = t = 40ns

r f

ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO

90% OF V

DATA IN

(DB0–DB11)

TIMING MEASUREMENT REFERENCE LEVEL IS V + V /2.

IH IL

Write Cycle Timing Diagram

ABSOLUTE MAXIMUM RATINGS*

(T_A= + 25°C unless otherwise noted)

Commercial (J, K, L, GL) Grades . . . . . . . . 0°C to +70°C

Industrial (A, B, C, GC) Grades . . . . . . . . –25°C to +85°C

Extended (S, T, U, GU) Grades . . . . . . . –55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C

V_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +17 V

Digital Input Voltage to DGND . . . . . . . –0.3 V, V_DD+0.3 V

V_RFB, V_REFto DGND . . . . . . . . . . . . . . . . . . . . . . . . .

25 V

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

_PIN1to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V, V_DD+0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V, V_DD+ 0.3 V

Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW

Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

Operating Temperature

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7545 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE¹

TERMINOLOGY

RELATIVE ACCURACY

Maximum

Gain Error

The amount by which the D/A converter transfer function

differs from the ideal transfer function after the zero and full-

scale points have been adjusted. This is an endpoint linearity

Temperature

Range

Relative

Accuracy

T_A= +25؇C Package

Model²

V_DD= +5 V Options³

measurement.

AD7545JN

AD7545AQ

AD7545SQ

AD7545KN

AD7545BQ

AD7545TQ

AD7545LN

AD7545CQ

AD7545UQ

AD7545GLN 0°C to +70°C

AD7545GCQ –25°C to +85°C

AD7545GUQ –55°C to +125°C

AD7545JP

AD7545SE

AD7545KP

AD7545TE

AD7545LP

AD7545UE

AD7545GLP

0°C to +70°C

2 LSB

1 LSB

1/2 LSB

2 LSB

1 LSB

20 LSB

10 LSB

5 LSB

1 LSB

20 LSB

10 LSB

5 LSB

1 LSB

N-20

Q-20

N-20

Q-20

N-20

Q-20

N-20

Q-20

P-20A

E-20A

P-20A

E-20A

P-20A

E-20A

P-20A

E-20A

–25°C to +85°C

–55°C to +125°C

0°C to +70°C

DIFFERENTIAL NONLINEARITY

The difference between the measured change and the ideal

change between any two adjacent codes. If a device has a differ-

ential nonlinearity of less than 1 LSB it will be monotonic, i.e.,

the output will always increase for an increase in digital code

applied to the D/A converter.

–25°C to +85°C

–55°C to +125°C

0°C to +70°C

–25°C to +85°C

–55°C to +125°C

PROPAGATION DELAY

This is a measure of the internal delay of the circuit and is mea-

sured from the time a digital input changes to the point at which

0°C to +70°C

–55°C to +125°C

0°C to +70°C

the analog output at OUT1 reaches 90% of its final value.

–55°C to +125°C

0°C to +70°C

1/2 LSB

DIGITAL-TO-ANALOG GLITCH IMPULSE

–55°C to +125°C

0°C to +70°C

This is a measure of the amount of charge injected from the

digital inputs to the analog outputs when the inputs change

state. It is usually specified as the area of the glitch in nV secs

and is measured with V_REF= AGND and an ADLH0032CG as

the output op amp, C1 (phase compensation) = 33 pF.

AD7545GUE –55°C to +125°C

NOTES

¹Analog Devices reserves the right to ship either ceramic (D-20) in lieu of cerdip

packages (Q-20).

²To order MIL-STD-883, Class B process parts, add /883B to part number.

Contact local sales office for military data sheet. For U.S. Standard Military

DRAWING (SMD) see DESC drawing 5962-87702.

³E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip

Carrier; Q = Cerdip.

REV. A

–3–

AD7545

CIRCUIT INFORMATION—D/A CONVERTER SECTION

Figure 1 shows a simplified circuit of the D/A converter section

of the AD7545 and Figure 2 gives an approximate equivalent

circuit. Note that the ladder termination resistor is connected to

AGND. R is typically 11 kΩ.

power supply. To minimize power supply currents it is recom-

mended that the digital input voltages be as close as practicably

possible to the supply rails (V_DDand DGND).

The AD7545 may be operated with any supply voltage in the

range 5 ≤ V_DD≤ 15 volts. With V_DD= +15 V the input logic

levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.

REF

BASIC APPLICATIONS

Figures 4 and 5 show simple unipolar and bipolar circuits using

the AD7545. Resistor R1 is used to trim for full scale. The

“G” versions (AD7545GLN, AD7545GCQ, AD7545GUD)

have a guaranteed maximum gain error of 1 LSB at +25°C

(V_DD= +5 V), and in many applications it should be possible to

dispense with gain trim resistors altogether. Capacitor C1 provides

phase compensation and helps prevent overshoot and ringing when

using high speed op amps. Note that all the circuits of Figures 4, 5

and 6 have constant input impedance at the V_REFterminal.

OUT 1

AGND

DB11

(MSB)

DB10

DB9

DB1

DB0

(LSB)

Figure 1. Simplified D/A Circuit of AD7545

The binary weighted currents are switched between the OUT1

bus line and AGND by N-channel switches, thus maintaining a

constant current in each ladder leg independent of the switch

state.

The circuit of Figure 1 can either be used as a fixed reference

D/A converter so that it provides an analog output voltage in the

range 0 to –V_IN(note the inversion introduced by the op amp),

or V_INcan be an ac signal in which case the circuit behaves as

an attenuator (2-Quadrant Multiplier). V_INcan be any voltage

in the range –20 ≤ V_IN+ 20 volts (provided the op amp can

The capacitance at the OUT1 bus line, C_OUT1, is code depen-

dent and varies from 70 pF (all switches to AGND) to 200 pF

(all switches to OUT1).

handle such voltages) since V_REFis permitted to exceed V_DD

Table II shows the code relationship for the circuit of Figure 4.

One of the current switches is shown in Figure 2. The input

resistance at V_REF(Figure 1) is always equal to R_LDR(R_LDRis

the R/2R ladder characteristic resistance and is equal to value

“R”). Since R_INat the V_REFpin is constant, the reference termi-

nal can be driven by a reference voltage or a reference current,

ac or dc, of positive or negative polarity. (If a current source is

used, a low temperature coefficient external R_FBis recommended

to define scale factor.)

33pF

OUT1

OUT

REF

AD7545

R1*

AGND

AD544L

(SEE TEXT)

DGND

ANALOG

COMMON

TO LADDER

DB11–DB0

*REFER TO TABLE I

FROM

INTERFACE

LOGIC

Figure 4. Unipolar Binary Operation

Table I. Recommended Trim Resistor Values vs. Grades for

V_DD= +5 V

AGND

OUT 1

Figure 2. N-Channel Current Steering Switch

Trim

Resistor

J/A/S

K/B/T

L/C/U

GL/GC/GU

CIRCUIT INFORMATION—DIGITAL SECTION

Figure 3 shows the digital structure for one bit.

500 Ω

150 Ω

200 Ω

68 Ω

100 Ω

33 Ω

20 Ω

6.8 Ω

The digital signals CONTROL and CONTROL are generated

from CS and WR.

Table II. Unipolar Binary Code Table for Circuit of Figure 4

Binary Number in DAC Register Analog Output

TO AGND SWITCH

TO OUT1 SWITCH





4095

4096

INPUT BUFFERS

1 1 1 1

–V_IN









CONTROL





2048

4096

Figure 3. Digital Input Structure

1 0 0 0

0 0 0 0

= –1/2 V_IN









The input buffers are simple CMOS inverters designed so that

when the AD7545 is operated with V_DD= 5 V, the buffers con-

vert TTL input levels (2.4 V and 0.8 V) into CMOS logic levels.

When V_INis in the region of 2.0 volts to 3.5 volts, the input

buffers operate in their linear region and draw current from the





0 0 0 0

0 0 0 1

0 0 0 0





4096





0 Volts

–4–

REV. A

AD7545

Table IV. 12-Plus Sign Magnitude Code Table for Circuit of

Figure 6

Figure 5 and Table III illustrate the recommended circuit and

code relationship for bipolar operation. The D/A function itself

uses offset binary code and inverter U₁on the MSB line con-

verts twos complement input code to offset binary code. If ap-

propriate; inversion of the MSB may be done in software using

an exclusive –OR instruction and the inverter omitted. R3, R4

and R5 must be selected to match within 0.01% and they should

be the same type of resistor (preferably wire-wound or metal

foil), so their temperature coefficients match. Mismatch of R3

value to R4 causes both offset and full-scale error. Mismatch of

R5 and R4 and R3 causes full-scale error.

Sign

Bit

Binary Number in DAC

MSB LSB

Analog Output, V_OUT





4095

4096

1 1 1 1 1 1 1 1 1 1 1 1

+ V_IN×









0 0 0 0 0 0 0 0 0 0 0 0

0 Volts





4095

4096

V_DD

R2*

1 1 1 1 1 1 1 1 1 1 1 1

– V_IN×





20kΩ





33pF

Note: Sign bit of “0” connects R3 to GND.

V_DD

R_FB

20kΩ

OUT1

10kΩ

V_REF

AD544L

AD7545

V_IN

R1*

AGND

AD544J

5kΩ

APPLICATIONS HINTS

V_OUT

DB11

DB10–DB0

Output Offset: (CMOS D/A converters exhibit a code depen-

dent output resistance which, in turn, causes a code dependent

amplifier noise gain. The effect is a code dependent differential

nonlinearity term at the amplifier output that depends on V_OS

where V_OSis the amplifier input offset voltage. To maintain

monotonic operation it is recommended that V_OSbe no greater

than 25 × 10^–6) (V_REF) over the temperature range of operation.

Suitable op amps are AD517L and AD544L. The AD517L is

best suited for fixed reference applications with low bandwidth

requirements: it has extremely low offset (50 µV) and in most

applications will not require an offset trim. The AD544L has a

much wider bandwidth and higher slew rate and is recommended

for multiplying and other applications requiring fast settling. An

offset trim on the AD544L may be necessary in some circuits.

10%

U₁

(SEE TEXT)

ANALOG

COMMON

FOR VALUES OF R1 AND R2

SEE TABLE I.

DATA INPUT

Figure 5. Bipolar Operation (Twos Complement Code)

Table III. Twos Complement Code Table for Circuit of

Figure 5

Data Input

Analog Output





2047

2048

0 1 1 1

1 1 1 1

+V_IN









General Ground Management: AC or transient voltages

between AGND and DGND can cause noise injection into the

analog output. The simplest method of ensuring that voltages at

AGND and DGND are equal is to tie AGND and DGND

together at the AD7545. In more complex systems where the

AGND and DGND intertie is on the backplane, it is recom-

mended that two diodes be connected in inverse parallel

between the AD7545 AGND and DGND pins (IN914 or

equivalent).





0 0 0 0

0 0 0 1

0 0 0 0

+V_IN





2048





0 Volts





1 1 1 1

1 0 0 0

1 1 1 1

0 0 0 0

1 1 1 1

0 0 0 0

–V_IN





2048









2048









Digital Glitches: When WR and CS are both low the latches

are transparent and the D/A converter inputs follow the data

inputs. In some bus systems, data on the data bus is not always

valid for the whole period during which WR is low and as a

result invalid data can briefly occur at the D/A converter inputs

during a write cycle. Such invalid data can cause unwanted

glitches at the output of the D/A converter. The solution to this

problem, if it occurs, is to retime the write pulse WR so that it

only occurs when data is valid.

Figure 6 shows an alternative method of achieving bipolar out-

put. The circuit operates with sign plus magnitude code and has

the advantage of giving 12-bit resolution in each quadrant, com-

pared with 11-bit resolution per quadrant for the circuit of Fig-

ure 5. The AD7592 is a fully protected CMOS change-over

switch with data latches. R4 and R5 should match each other to

0.01% to maintain the accuracy of the D/A converter. Mismatch

between R4 and R5 introduces a gain error.

Another cause of digital glitches is capacitive coupling from the

digital lines to the OUT1 and AGND terminals. This should be

minimized by screening the analog pins of the AD7545 (Pins 1,

2, 19, 20) from the digital pins by a ground track run between

Pins 2 and 3 and between Pins 18 and 19 of the AD7545. Note

how the analog pins are at one end of the package and separated

from the digital pins by V_DDand DGND to aid screening at

the board level. On-chip capacitive coupling can also give rise

to crosstalk from the digital-to-analog sections of the AD7545,

particularly in circuits with high currents and fast rise and

fall times. This type of crosstalk is minimized by using

V_DD

20kΩ

33pF

V_DD

R_FB

V_OUT

OUT1

AGND

V_REF

AD544L

10kΩ

AD7545

V_IN

R1*

AD544J

10%

DB11–DB0

1/2 AD7592JN

ANALOG

COMMON

SIGN BIT

FOR VALUES OF R1 AND R2

SEE TABLE I.

Figure 6. 12-Bit Plus Sign Magnitude D/A Converter

REV. A

–5–

AD7545

V_DD= +5 volts. However, great care should be taken to ensure

that the +5 V used to power the AD7545 is free from digitally

induced noise.

Temperature Coefficients: The gain temperature coefficient

of the AD7545 has a maximum value of 5 ppm/°C and a typical

value of 2 ppm/°C. This corresponds to worst case gain shifts of

2 LSBs and 0.8 LSBs respectively over a 100°C temperature

range. When trim resistors Rl and R2 are used to adjust full-

scale range, the temperature coefficient of R1 and R2 should

also be taken into account. The reader is referred to Analog

Devices Application Note “Gain Error and Gain Temperature

Coefficient of CMOS Multiplying DACs,” Publication Number

E630–10–6/81.

–1

–2

SINGLE SUPPLY OPERATION

– Volts

The ladder termination resistor of the AD7545 (Figure 1) is

connected to AGND. This arrangement is particularly suitable

for single supply operation because OUT1 and AGND may be

biased at any voltage between DGND and V_DD. OUT1 and

AGND should never go more than 0.3 volts less than DGND or

an internal diode will be turned on and a heavy current may

flow which will damage the device. (The AD7545 is, however,

protected from the SCR latch-up phenomenon prevalent in

many CMOS devices.)

Figure 8. Differential Nonlinearity vs. V_DDfor Figure 7

Circuit. Reference Voltage = 2.5 Volts. Shaded Area Shows

Range of Values of Differential Nonlinearity that Typically

Occur for L, C and U Grades.

0.5

0.0

Figure 7 shows the AD7545 connected in a voltage switching

mode. OUT1 is connected to the reference voltage and AGND

is connected to DGND. The D/A converter output voltage is

available at the V_REFpin and has a constant output impedance

equal to R. R_FBis not used in this circuit.

–0.5

–1.0

+15V

–1.5

–2.0

REFERENCE

VOLTAGE

OUT1

REF

AD7545

AGND

DGND

DB11–DB0

– Volts

REF

Figure 9. Differential Nonlinearity vs. Reference Voltage

for Figure 7 Circuit. V_DD= 15 Volts. Shaded Area Shows

Range of Values of Differential Nonlinearity that Typically

Occur for L, C and U Grades.

15 VOLT CMOS DIGITAL INPUTS

Figure 7. Single Supply Operation Using Voltage

Switching Mode

The circuits of Figures 4, 5 and 6 can all be converted to single

supply operation by biasing AGND to some voltage between

The loading on the reference voltage source is code dependent

and the response time of the circuit is often determined by the

behavior of the reference voltage with changing load conditions.

V_DDand DGND. Figure 10 shows the twos complement bipolar

circuit of Figure 5 modified to give a range from +2 V to +8 V

about a “pseudo-analog ground” of 5 V. This voltage range

would allow operation from a single V_DDof +10 V to +15 V.

The AD584 pin-programmable reference fixes AGND at +5 V.

V_INis set at +2 V by means of the series resistors R1 and R2.

There is no need to buffer the V_REFinput to the AD7545

with an amplifier because the input impedance of the D/A con-

verter is constant. Note, however, that since the temperature

coefficient of the D/A reference input resistance is typically

–300 ppm/°C; applications that experience wide temperature

variations may require a buffer amplifier to generate the +2.0 V

at the AD7545 V_REFpin. Other output voltage ranges can be

obtained by changing R4 to shift the zero point and (R1 + R2)

to change the slope, or gain, of the D/A transfer function. V_DD

must be kept at least 5 V above OUT1 to ensure that linearity is

preserved.

To maintain linearity, the voltages at OUT1 and AGND should

remain within 2.5 volts of each other, for a V_DDof 15 volts. If

_DDis reduced from 15 V, or the differential voltage between

OUT1 and AGND is increased to more than 2.5 V, the differ-

ential nonlinearity of the DAC will increase and the linearity of

the DAC will be degraded. Figures 8 and 9 show typical curves

illustrating this effect for various values of reference voltage and

V_DD. If the output voltage is required to be offset from ground

by some value, then OUT1 and AGND may be biased up. The

effect on linearity and differential nonlinearity will be the same

as reducing V_DDby the amount of the offset.

–6–

REV. A

AD7545

= +10V TO +15V

Figure 12 shows an alternative approach for use with 8-bit

processors which have a full 16-bit wide address bus such as

6800, 8080, Z80 This technique uses the 12 lower address lines

of the processor address bus to supply data to the DAC, thus

each AD7545 connected in this way uses 4k bytes of address

locations. Data is written to the DAC using a single memory

write instruction. The address field of the instruction is orga-

nized so that the lower 12 bits contain the data for the DAC and

the upper 4 bits contain the address of the 4k block at which the

DAC resides.

20kΩ

33pF

REF

OUT1

+2V

10kΩ

AD7545

AGND

DGND

AD544L

+5V

10KΩ

MSB

DB10–DB0

AD544J

5kΩ

33.3kΩ

2kΩ

AD584J

A15

CMOS DATA BUS

= +10V TO +15V

16-BIT ADDRESS BUS

Figure 10. Single Supply “Bipolar” Twos Complement

D/A Converter

DB11

ADDRESS

DECODE

DB0

CPU

AD7545

MICROPROCESSOR INTERFACING OF THE AD7545

The AD7545 can directly interface to both 8- and 16-bit micro-

processors via its 12-bit wide data latch using standard CS and

WR control signals.

A typical interface circuit for an 8-bit processor is shown in

Figure 11. This arrangement uses two memory addresses, one

for the lower eight bits of data to the DAC and one for the up-

per four bits of data into the DAC via the latch.

DATA BUS

Figure 12. Connecting the AD7545 to 8-Bit Processors via

the Address Bus

A15

SUPPLEMENTAL APPLICATION MATERIAL

For further information on CMOS multiplying D/A converters

the reader is referred to the following texts:

ADDRESS BUS

Q *

Application Guide to CMOS Multiplying D/A converters

available from Analog Devices, Publication Number G479.

ADDRESS

DECODE

Q *

CPU

DB11

DB8

LATCH

Gain Error and Gain Temperature Coefficient of CMOS

Multiplying DACS—Application Note, Publication Number

E630–10–6/81 available from Analog Devices.

AD7545

DB7

DB0

8-BIT DATA BUS

* Q = DECODED ADDRESS FOR DAC

= DECODED ADDRESS FOR LATCH

Figure 11. 8-Bit Processor to AD7545 Interface

REV. A

–7–

AD7545

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

20-Lead Plastic DIP

(N-20)

20-Lead Cerdip

(Q-20)

20-Terminal Leadless Ceramic Chip Carrier (LCCC)

(E-20A)

20-Lead Plastic Leaded Chip Carrier (PLCC)

(P-20A)

–8–

REV. A

AD7545JP [ADI]

相关型号：

AD7545JP-REEL

AD7545JPZ

AD7545JPZ

AD7545KCWP

AD7545KD

AD7545KN

AD7545KN

AD7545KN/+

AD7545KNZ

AD7545KP

AD7545LCWP

AD7545LD