AD7545KNZ [ROCHESTER]
D/A Converter, 1 Func, Parallel, Word Input Loading, PDIP20, 0.300 INCH, PLASTIC, DIP-20;
| 型号： | AD7545KNZ |
| 厂家： | 
Rochester Electronics |
| 描述： | D/A Converter, 1 Func, Parallel, Word Input Loading, PDIP20, 0.300 INCH, PLASTIC, DIP-20 光电二极管 转换器 |
| 文件： | 总4页 (文件大小：802K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS 12-Bit
Buffered Multiplying DAC
a
AD7545
FEATURES
FUNCTIONAL BLOCK DIAGRAM
12-Bit Resolution
R
FB
20
Low Gain TC: 2 ppm/؇C typ
Fast TTL Compatible Data Latches
Single +5 V to +15 V Supply
Small 20-Lead 0.3" DIP and 20-Terminal Surface Mount
Packages
AD7545
R
1
2
OUT 1
AGND
12-BIT
MULTIPLYING DAC
V
19
REF
Latch Free (Schottky Protection Diode Not Required)
Low Cost
12
Ideal for Battery Operated Equipment
WR 17
16
18
3
V
DD
INPUT DATA LATCHES
CS
DGND
12
DB11–DB0
(PINS 4–15)
GENERAL DESCRIPTION
The AD7545 is particularly suitable for single supply operation
and applications with wide temperature variations.
The AD7545 is a monolithic 12-bit CMOS multiplying DAC
with onboard data latches. It is loaded by a single 12-bit wide
word and directly interfaces to most 12- and 16-bit bus systems.
Data is loaded into the input latches under the control of the CS
and WR inputs; tying these control inputs low makes the input
latches transparent, allowing direct unbuffered operation of the
DAC.
The AD7545 can be used with any supply voltage from +5 V to
+15 V. With CMOS logic levels at the inputs the device dissi-
pates less than 0.5 mW for VDD = +5 V.
PRELIMINARY
PIN CONFIGURATIONS
TECHNICAL
DATA
DIP
LCCC
PLCC
1
2
20
19
18
17
16
15
14
13
12
11
OUT 1
AGND
DGND
DB11 (MSB)
DB10
R
FB
V
REF
2
3
1
20 19
2
3
1 20 19
3
V
DD
PIN 1
IDENTIFIER
DB11 (MSB)
DB10
4
5
6
7
8
18
V
DD
18
17
16
15
V
4
DB11 (MSB)
DD
4
WR
17 WR
DB10 5
DB9 6
DB8 7
DB7 8
WR
AD7545
TOP VIEW
(Not to Scale)
AD7545
TOP VIEW
(Not to Scale)
5
CS
AD7545
TOP VIEW
(Not to Scale)
DB9
16
CS
CS
DB0 (MSB)
DB1
DB9
6
DB0 (LSB)
DB8
15 DB0 (LSB)
14 DB1
DB8
7
14 DB1
DB7
DB2
8
DB7
9
10 11 12 13
9
10 11 12 13
9
DB6
DB3
DB4
DB5
10
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1997
(VREF = +10 V, VOUT1 = O V, AGND = DGND unless otherwise noted)
AD7545–SPECIFICATIONS
VDD = +5 V
Limits
TA = + 25؇C TMIN, TMAX
VDD = +15 V
Limits
TA = + 25؇C TMIN, TMAX
1
1
Parameter
Version
Units
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
All
12
12
12
12
Bits
J, A, S
K, B, T
L, C, U
GL, GC, GU ±1/2
J, A, S
K, B, T
L, C, U
GL, GC, GU ±1
J, A, S
K, B, T
L, C, U
±2
±1
±1/2
±2
±1
±1/2
±1/2
±4
±1
±1
±1
±2
±1
±1/2
±1/2
±4
±1
±1
±1
±25
±15
±10
±6
±2
±1
±1/2
±1/2
±4
±1
±1
±1
±25
±15
±10
±7
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Differential Nonlinearity
±4
±1
±1
10-Bit Monotonic TMIN to TMAX
12-Bit Monotonic TMIN to TMAX
12-Bit Monotonic TMIN to TMAX
12-Bit Monotonic TMIN to TMAX
DAC Register Loaded with
1111 1111 1111
Gain Error (Using Internal RFB)2
±20
±10
±5
±20
±10
±6
Gain Error Is Adjustable Using
the Circuits of Figures 4, 5, and 6
GL, GC, GU ±1
±2
Gain Temperature Coefficient3
∆Gain/∆Temperature
All
±5
±5
±10
±10
ppm/°C max
Typical Value is 2 ppm/°C for VDD = +5 V
DC Supply Rejection3
∆Gain/∆VDD
All
0.015
10
10
0.03
50
50
0.01
10
10
0.02
50
50
% per % max ∆VDD = ±5%
Output Leakage Current at OUT1
J, K, L, GL
A, B, C, GC
S, T, U, GU
nA max
nA max
nA max
DB0–DB11 = 0 V; WR, CS = 0 V
10
200
10
200
DYNAMIC PERFORMANCE
Current Settling Time3
All
2
2
2
2
µs max
To 1/2 LSB. OUT1 Load = 100 Ω. DAC
Output Measured from Falling Edge of
WR, CS = 0.
Propagation Delay3 (from Digital
Input Change to 90%
of Final Analog Output)
Digital-to-Analog Glitch Inpulse
AC Feedthrough5
All
All
300
400
–
–
250
250
–
–
ns max
nV sec typ
OUT1 Load = 100 Ω, CEXT = 13 pF4
VREF = AGND
At OUT1
All
All
5
5
5
5
mV p-p typ
VREF = ±10 V, 10 kHz Sinewave
REFERENCE INPUT
Input Resistance
7
25
7
25
7
25
7
25
kΩ min
kΩ max
Input Resistance TC = –300 ppm/°C typ
Typical Input Resistance = 11 kΩ
(Pin 19 to GND)
ANALOG OUTPUT
Output Capacitance3
COUT1
PRELIMINARY
All
70
200
70
200
70
200
70
200
pF max
pF max
DB0–DB11 = 0 V, WR, CS = 0 V
DB0–DB11 = VDD, WR, CS = 0 V
COUT1
TECHNICAL
DIGITAL INPUTS
Input High Voltage
VIH
DATA
All
All
All
2.4
0.8
±1
2.4
0.8
±10
13.5
1.5
±1
13.5
V min
V max
µA max
Input Low Voltage
VIL
1.5
Input Current6
IIN
±10
VIN = 0 or VDD
Input Capacitance3
DB0–DB11
WR, CS
All
All
5
20
5
20
5
20
5
20
pF max
pF max
VIN = 0
VIN = 0
SWITCHING CHARACTERISTICS7
Chip Select to Write Setup Time
tCS
All
280
200
380
270
180
120
200
150
ns min
ns typ
See Timing Diagram
Chip Select to Write Hold Time
tCH
All
All
All
0
0
0
0
ns min
Write Pulse Width
tWR
250
175
140
100
400
280
210
150
160
100
90
240
170
120
80
ns min
ns typ
ns min
ns typ
tCS ≥ tWR, tCH ≥ 0
Data Setup Time
tDS
60
Data Hold Time
tDH
All
All
10
10
10
10
ns min
POWER SUPPLY
IDD
2
100
10
2
500
10
2
100
10
2
500
10
mA max
µA max
µA typ
All Digital Inputs VIL or VIH
All Digital Inputs 0 V to VDD
All Digital Inputs 0 V to VDD
NOTES
1Temperature range as follows: J, K, L, GL versions, 0°C to +70°C; A, B, C, GC versions, –25°C to +85°C; S, T, U GU versions, –55°C to +125°C.
2This includes the effect of 5 ppm max gain TC.
3Guaranteed but not tested.
4DB0–DB11 = 0 V to VDD or VDD to 0 V.
5Feedthrough can be further reduced by connecting the metal lid on the ceramic package (Suffix D) to DGND.
6Logic inputs are MOS gates. Typical input current (+25°C) is less than 1 nA.
7Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. A
AD7545
tCH
MODE SELECTION
HOLD MODE:
tCS
V
DD
WRITE MODE:
CHIP
SELECT
0
CS AND WR LOW, DAC RESPONDS
TO DATA BUS (DB0–DB11) INPUTS.
EITHER CS OR WR HIGH, DATA BUS
(DB0–DB11) IS LOCKED OUT; DAC
HOLDS LAST DATA PRESENT WHEN
tWR
V
WR OR CS ASSUMED HIGH STATE.
DD
WRITE
NOTES:
0
V
= +5V; t = t = 20ns
DD
r f
tDS
DATA VALID
tDH
V
= +15V; t = t = 40ns
r f
DD
ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO
90% OF V
V
DD
V
IH
.
DATA IN
(DB0–DB11)
DD
V
IL
TIMING MEASUREMENT REFERENCE LEVEL IS V + V /2.
IH IL
0
Write Cycle Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
(TA = + 25°C unless otherwise noted)
Commercial (J, K, L, GL) Grades . . . . . . . . 0°C to +70°C
Industrial (A, B, C, GC) Grades . . . . . . . . –25°C to +85°C
Extended (S, T, U, GU) Grades . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +17 V
Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD +0.3 V
VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
V
PIN1 to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7545 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PRELIMINARY
ORDERING GUIDE1
TERMINOLOGY
RELATIVE ACCURACY
TECHNICAL
Maximum
Gain Error
The amount by which the D/A converter transfer function DATA
differs from the ideal transfer function after the zero and full-
scale points have been adjusted. This is an endpoint linearity
Temperature
Range
Relative
Accuracy
TA = +25؇C Package
Model2
VDD = +5 V Options3
measurement.
AD7545JN
AD7545AQ
AD7545SQ
AD7545KN
AD7545BQ
AD7545TQ
AD7545LN
AD7545CQ
AD7545UQ
0°C to +70°C
–25°C to +85°C
–55°C to +125°C ±2 LSB
0°C to +70°C
–25°C to +85°C
–55°C to +125°C ±1 LSB
0°C to +70°C
–25°C to +85°C
±2 LSB
±2 LSB
±20 LSB
±20 LSB
±20 LSB
±10 LSB
±10 LSB
±10 LSB
±5 LSB
±5 LSB
±5 LSB
±1 LSB
±1 LSB
±1 LSB
±20 LSB
±20 LSB
±10 LSB
±10 LSB
±5 LSB
±5 LSB
±1 LSB
±1 LSB
N-20
Q-20
Q-20
N-20
Q-20
Q-20
N-20
Q-20
Q-20
N-20
Q-20
Q-20
P-20A
E-20A
P-20A
E-20A
P-20A
E-20A
P-20A
E-20A
DIFFERENTIAL NONLINEARITY
±1 LSB
±1 LSB
The difference between the measured change and the ideal
change between any two adjacent codes. If a device has a differ-
ential nonlinearity of less than 1 LSB it will be monotonic, i.e.,
the output will always increase for an increase in digital code
applied to the D/A converter.
±1/2 LSB
±1/2 LSB
–55°C to +125°C ±1/2 LSB
AD7545GLN 0°C to +70°C
AD7545GCQ –25°C to +85°C
±1/2 LSB
±1/2 LSB
PROPAGATION DELAY
AD7545GUQ –55°C to +125°C ±1/2 LSB
This is a measure of the internal delay of the circuit and is mea-
sured from the time a digital input changes to the point at which
AD7545JP
AD7545SE
AD7545KP
AD7545TE
AD7545LP
AD7545UE
AD7545GLP
0°C to +70°C
–55°C to +125°C ±2 LSB
0°C to +70°C ±1 LSB
–55°C to +125°C ±1 LSB
0°C to +70°C ±1/2 LSB
–55°C to +125°C ±1/2 LSB
0°C to +70°C ±1/2 LSB
±2 LSB
the analog output at OUT1 reaches 90% of its final value.
DIGITAL-TO-ANALOG GLITCH IMPULSE
This is a measure of the amount of charge injected from the
digital inputs to the analog outputs when the inputs change
state. It is usually specified as the area of the glitch in nV secs
and is measured with VREF = AGND and an ADLH0032CG as
the output op amp, C1 (phase compensation) = 33 pF.
AD7545GUE –55°C to +125°C ±1/2 LSB
NOTES
1Analog Devices reserves the right to ship either ceramic (D-20) in lieu of cerdip
packages (Q-20).
2To order MIL-STD-883, Class B process parts, add /883B to part number.
Contact local sales office for military data sheet. For U.S. Standard Military
DRAWING (SMD) see DESC drawing 5962-87702.
3E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip.
REV. A
–3–
相关型号：
AD7545LNZ
D/A Converter, 1 Func, Parallel, Word Input Loading, PDIP20, 0.300 INCH, PLASTIC, DIP-20
ROCHESTER
©2020 ICPDF网 联系我们和版权申明