AD7482ASTZ [ADI]
3 MSPS, 12-Bit SAR ADC; 3 MSPS ， 12位SAR ADC
| 型号： | AD7482ASTZ |
| 厂家： | 
ADI |
| 描述： | 3 MSPS, 12-Bit SAR ADC |
| 文件： | 总20页 (文件大小：527K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 MSPS, 12-Bit SAR ADC
AD7482
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AV
DD AGND
C
DV
DD
V
DRIVE DGND
BIAS
Fast throughput rate: 3 MSPS
Wide input bandwidth: 40 MHz
No pipeline delays with SAR ADC
Excellent dc accuracy performance
2 parallel interface modes
Low power: 90 mW (full power) and 2.5 mW (nap mode)
Standby mode: 2 µA maximum
Single 5 V supply operation
2.5V
REFOUT
REFIN
BUF
REFERENCE
REFSEL
VIN
12-BIT
ALGORITHMIC
SAR
T/H
Internal 2.5 V reference
AD7482
Full-scale overrange mode (using 13th bit)
System offset removal via user access offset register
Nominal 0 V to 2.5 V input with shifted range capability
14-bit pin compatible upgrade AD7484 available
D12
D11
D10
D9
MODE1
MODE2
CLIP
NAP
CONTROL
LOGIC AND I/O
REGISTERS
D8
STBY
RESET
CONVST
D7
D6
D5
Figure 1.
GENERAL DESCRIPTION
The AD7482 is a 12-bit, high speed, low power, successive
approximation ADC. The part features a parallel interface with
throughput rates up to 3 MSPS. The part contains a low noise,
wide bandwidth track-and-hold that can handle input frequencies
in excess of 40 MHz.
alive for a quick power-up while consuming 2.5 mW, and a
standby mode that reduces power consumption to a mere 10 μW.
The AD7482 features an on-board 2.5 V reference but can also
accommodate an externally provided 2.5 V reference source.
The nominal analog input range is 0 V to 2.5 V, but an offset
shift capability allows this nominal range to be offset by 200 mV.
This allows the user considerable flexibility in setting the bottom
end reference point of the signal range, a useful feature when
using single-supply op amps.
The conversion process is a proprietary algorithmic successive
approximation technique that results in no pipeline delays. The
input signal is sampled, and a conversion is initiated on the falling
CONVST
edge of the
signal. The conversion process is controlled
via an internally trimmed oscillator. Interfacing is via standard
parallel signal lines, making the part directly compatible with
microcontrollers and DSPs.
The AD7482 also provides an 8% overrange capability via a
13th bit. Therefore, if the analog input range strays outside the
nominal by up to 8%, the user can still accurately resolve the
signal by using the 13th bit.
The AD7482 provides excellent ac and dc performance specifica-
tions. Factory trimming ensures high dc accuracy, resulting in
very low INL, offset, and gain errors.
The AD7482 is powered by a 4.75 V to 5.25 V supply. The part
also provides a VDRIVE pin that allows the user to set the voltage
levels for the digital interface lines. The range for this VDRIVE pin
is 2.7 V to 5.25 V. The part is housed in a 48-lead LQFP package
and is specified over a −40°C to +85°C temperature range.
The part uses advanced design techniques to achieve very low
power dissipation at high throughput rates. Power consumption
in the normal mode of operation is 90 mW. There are two power
saving modes: a nap mode, which keeps the reference circuitry
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
AD7482
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Description......................................................................... 12
Converter Operation.................................................................. 12
Analog Input ............................................................................... 12
ADC Transfer Function............................................................. 13
Power Saving............................................................................... 13
Offset/Overrange........................................................................ 14
Parallel Interface......................................................................... 15
Board Layout and Grounding................................................... 17
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 11
REVISION HISTORY
12/09—Rev. A to Rev. B
Changes to Table 1, Power Requirements Section ....................... 4
Changes to Ordering Guide .......................................................... 19
9/08—Rev. 0 to Rev. A
Changes to Table 4............................................................................ 7
Changes to Offset/Overrange Section ......................................... 14
Changes to Table 5, Table 6, Table 7............................................. 15
Changes to Ordering Guide .......................................................... 19
8/02—Revision 0: Initial Version
Rev. B | Page 2 of 20
AD7482
SPECIFICATIONS
AVDD/DVDD = 5 V 5%, AGND = DGND = 0 V, VREF = external, fSAMPLE = 3 MSPS; all specifications TMIN to TMAX and valid for VDRIVE = 2.7 V
to 5.25 V, unless otherwise noted. The operating temperature range is −40°C to +85°C.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE1, 2
Signal-to-Noise + Distortion (SINAD)3
71
dB
dB
dB
dB
dB
dB
dB
fIN = 1 MHz
fIN = 1 MHz
fIN = 1 MHz, internal reference
72
71
Total Harmonic Distortion (THD)3
−86
−87
−90
−88
Internal reference
fIN1 = 95.053 kHz,
Peak Harmonic or Spurious Noise (SFDR)3
Intermodulation Distortion (IMD)3
Second Order Terms
−96
dB
f
IN2 = 105.329 kHz
Third Order Terms
Aperture Delay
−94
10
dB
ns
Full Power Bandwidth
40
3.5
MHz
MHz
@ 3 dB
@ 0.1 dB
DC ACCURACY
Resolution
12
Bits
LSB
LSB
LSB
Integral Nonlinearity3
0.5
1
0.5
B Grade
A Grade
Guaranteed no missed codes to
12 bits
0.25
0.25
Differential Nonlinearity3
Offset Error3
1.5
0.036
1.5
LSB
%FSR
LSB
Gain Error3
0.036
%FSR
ANALOG INPUT
Input Voltage
−200
mV
V
μA
μA
pF
+2.7
1
DC Leakage Current
VIN from 0 V to 2.7 V
VIN = −200 mV
2
35
Input Capacitance4
REFERENCE INPUT/OUTPUT
Input Voltage, VREFIN
+2.5
V
1% for specified performance
External reference
Input DC Leakage Current, VREFIN
1
μA
pF
μA
V
mV
mV
Ω
4
Input Capacitance, VREFIN
25
Input Current, VREFIN
Output Voltage, VREFOUT
Error @ 25°C, VREFOUT
Error TMIN to TMAX, VREFOUT
Output Impedance, VREFOUT
220
+2.5
50
100
1
Rev. B | Page 3 of 20
AD7482
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
VDRIVE − 1
V
V
μA
pF
0.4
1
10
4
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance4
Output Coding
0.7 × VDRIVE
V
V
μA
pF
0.4
10
10
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
300
ns
Track-and-Hold Acquisition Time (tACQ
)
70
70
2.5
3
ns
ns
MSPS
MSPS
Sine wave input
Full-scale step input
Parallel Mode 1
Parallel Mode 2
Throughput Rate
POWER REQUIREMENTS
AVDD
DVDD
5
5
V
V
V
5%
5%
VDRIVE
2.7
5.25
IDD
Normal Mode (Static)
Normal Mode (Operational)
Nap Mode
13
20
0.5
2
CS and RD = Logic 1
mA
mA
mA
μA
Standby Mode
Power Dissipation
Normal Mode (Operational)
Nap Mode
0.5
100
2.5
10
mW
mW
μW
Standby Mode5
1 SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB.
2 See the Typical Performance Characteristics section for analog input circuits used.
3 See the Terminology section.
4 Sample tested @ 25°C to ensure compliance.
5 Digital input levels at DGND or VDRIVE
.
Rev. B | Page 4 of 20
AD7482
TIMING CHARACTERISTICS
AVDD/DVDD = 5 V 5%, AGND = DGND = 0 V, VREF = external; all specifications TMIN to TMAX and valid for VDRIVE = 2.7 V to 5.25 V,
unless otherwise noted.
Table 2.
Parameter1
Symbol
Min
Typ
Max
Unit
DATA READ
Conversion Time
Quiet Time Before Conversion Start
CONVST Pulse width
tCONV
tQUIET
t1
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
5
100
20
CONVST Falling Edge to BUSY Falling Edge
CS Falling Edge to RD Falling Edge
Data Access Time
CONVST Falling Edge to New Data Valid
BUSY Rising Edge to New Data Valid
Bus Relinquish Time
t2
0
t3
t4
25
30
5
t5
t6
t7
10
RD Rising Edge to CS Rising Edge
CS Pulse width
0
t8
30
30
t14
t15
RD Pulse width
DATA WRITE
WRITE Pulse Width
Data Setup Time
Data Hold Time
CS Falling Edge to WRITE Falling Edge
WRITE Falling Edge to CS Rising Edge
t9
5
2
6
5
0
ns
ns
ns
ns
ns
t10
t11
t12
t13
1 All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used.
Rev. B | Page 5 of 20
AD7482
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Rating
AVDD to AGND
DVDD to DGND
VDRIVE to DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
REFIN to AGND
Input Current to Any Pin Except
Supply Pins
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to AVDD + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to AVDD + 0.3 V
10 mA
ESD CAUTION
Operating Temperature Range
Commercial
−40°C to +85°C
Storage Temperature Range
Junction Temperature
Thermal Impedance, θJA
Thermal Impedance, θJC
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
−65°C to +150°C
150°C
50°C/W
10°C/W
215°C
220°C
1 kV
ESD
Rev. B | Page 6 of 20
AD7482
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
1
AV
36
35
34
33
32
31
30
29
28
27
26
25
DD
D8
D7
D6
D5
V
PIN 1
2
C
IDENTIFIER
BIAS
3
4
AGND
AGND
5
AV
DD
DRIVE
AD7482
6
AGND
VIN
DGND
DGND
TOP VIEW
7
(Not to Scale)
8
REFOUT
REFIN
REFSEL
AGND
DV
D4
D3
D2
D1
DD
9
10
11
12
AGND
13 14 15 16 17 18 19 20 21 22 23 24
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 5, 13, 46
2
3, 4, 6, 11, 12, AGND
14, 15, 47, 48
Mnemonic Description
AVDD
CBIAS
Positive Power Supply for Analog Circuitry.
Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin and AGND.
Power Supply Ground for Analog Circuitry.
7
8
VIN
REFOUT
Analog Input. Single ended analog input channel.
Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF capacitor
must be placed between this pin and AGND.
9
REFIN
REFSEL
STBY
NAP
Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using an external
voltage reference source, the reference voltage should be applied to this pin.
Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected from this
pin to AGND. When using an external reference source, this pin should be connected directly to AGND.
Standby Logic Input. When this pin is logic high, the device is placed in standby mode. See the Power Saving
section for further details.
Nap Logic Input. When this pin is logic high, the device is placed in a very low power mode. See the Power
Saving section for further details.
Chip Select Logic Input. This pin is used in conjunction with RD to access the conversion result. The data bus
is brought out of three-state and the current contents of the output register driven onto the data lines
following the falling edge of both CS and RD. CS is also used in conjunction with WRITE to perform a write to
the offset register. CS can be hardwired permanently low.
10
16
17
18
CS
19
20
RD
Read Logic Input. Used in conjunction with CS to access the conversion result.
WRITE
Write Logic Input. Used in conjunction with CS to write data to the offset register. When the desired offset
word has been placed on the data bus, the WRITE line should be pulsed high. It is the falling edge of this
pulse that latches the word into the offset register.
21
BUSY
Busy Logic Output. This pin indicates the status of the conversion process. The BUSY signal goes low after the
falling edge of CONVST and stays low for the duration of the conversion. In Parallel Mode 1, the BUSY signal
returns high when the conversion result has been latched into the output register. In Parallel Mode 2, the
BUSY signal returns high as soon as the conversion has been completed, but the conversion result does not
get latched into the output register until the falling edge of the next CONVST pulse.
22, 23
24 to 28,
33 to 39
R1, R2
D0 to D11
No Connect. These pins should be pulled to ground via 100 kΩ resistors.
Data I/O Bits. D11 is MSB. These are three-state pins that are controlled by CS, RD, and WRITE. The operating
voltage level for these pins is determined by the VDRIVE input.
29
DVDD
Positive Power Supply for Digital Circuitry.
Rev. B | Page 7 of 20
AD7482
Pin No.
30, 31
32
Mnemonic Description
DGND
VDRIVE
Ground Reference for Digital Circuitry.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface logic of
the device operates.
40
41
42
D12
Data Output Bit for Overranging. If the overrange feature is not used, this pin should be pulled to DGND via a
100 kΩ resistor.
Convert Start Logic Input. A conversion is initiated on the falling edge of the CONVST signal. The input track-
and-hold amplifier goes from track mode to hold mode, and the conversion process commences.
Reset Logic Input. An active low reset pulse must be applied to this pin after power-up to ensure correct
operation. A falling edge on this pin resets the internal state machine and terminates a conversion that
may be in progress. The contents of the offset register are also cleared on this edge. Holding this pin low
keeps the part in a reset state.
CONVST
RESET
43
44
45
MODE2
MODE1
CLIP
Operating Mode Logic Input. See Table 8 for details.
Operating Mode Logic Input. See Table 8 for details.
Logic Input. A logic high on this pin enables output clipping. In this mode, any input voltage that is greater
than positive full scale or less than negative full scale is clipped to all 1s or all 0s, respectively. Further details
are given in the Offset/Overrange section.
Rev. B | Page 8 of 20
AD7482
TYPICAL PERFORMANCE CHARACTERISTICS
0
0.5
0.4
fIN = 10.7kHz
SNR = 72.97dB
SNR + D = 72.94dB
–20
THD = –91.5dB
0.3
0.2
–40
–60
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–80
–100
–120
0
200
400
600
800
1000
1200
1400
0
1024
2048
3072
4096
FREQUENCY (kHz)
ADC (Code)
Figure 3. 64k FFT Plot With 10 kHz Input Tone
Figure 6. Typical INL
80
75
0
–20
fIN = 1.013MHz
SNR = 72.58dB
SNR + D = 72.57dB
THD = –94.0dB
–40
–60
–80
70
65
–100
–120
0
200
400
600
800
1000
1200
1400
10
100
1000
10000
INPUT FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 4. 64k FFT Plot With 1 MHz Input Tone
Figure 7. SINAD vs. Input Tone (AD8021 Input Circuit)
0.5
0.4
0.3
0.2
0.1
0
–40
200Ω
100Ω
–50
–60
51Ω
10Ω
–70
–0.1
–80
–0.2
–0.3
–0.4
–0.5
0Ω
–90
–100
100
1000
10000
0
1024
2048
3072
4096
INPUT FREQUENCY (kHz)
ADC (Code)
Figure 5. Typical DNL
Figure 8. THD vs. Input Tone for Different Input Resistances
Rev. B | Page 9 of 20
AD7482
0
0.0004
0
100mV p-p SINE WAVE ON SUPPLY PINS
–10
–20
–30
–40
–50
–60
–70
–80
–0.0004
–0.0008
–0.0012
–0.0016
–0.0020
10
100
1000
–55
–25
5
35
65
95
125
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 9. PSRR Without Decoupling
Figure 10. Reference Out Error
Rev. B | Page 10 of 20
AD7482
TERMINOLOGY
Integral Nonlinearity
Total Harmonic Distortion (THD)
The integral nonlinearity is the maximum deviation from a
straight line passing through the endpoints of the ADC transfer
function. The endpoints of the transfer function are zero scale, a
point 1/2 LSB below the first code transition, and full scale, a
point 1/2 LSB above the last code transition.
The THD is the ratio of the rms sum of the harmonics to the
fundamental. It is defined as
2
V22 +V32 +V42 +V52 +V6
THD(dB) = 20log
V1
Differential Nonlinearity
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
The differential nonlinearity is the difference between the
measured and ideal 1 LSB change between any two adjacent
codes in the ADC.
Peak Harmonic or Spurious Noise
Offset Error
The peak harmonic or spurious noise is the ratio of the rms
value of the next largest component in the ADC output spectrum
(up to fS/2 and excluding dc) to the rms value of the fundamental.
The value of this specification is usually determined by the largest
harmonic in the spectrum, but for ADCs where the harmonics
are buried in the noise floor, it is a noise peak.
The offset error is the deviation of the first code transition
(00...000) to (00...001) from the ideal, that is, AGND + 0.5 LSB.
Gain Error
The gain error is the deviation of the last code transition
(111...110) to (111...111) from the ideal, that is, VREF − 1.5 LSB
after the offset error is adjusted out.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion products
at sum and difference frequencies of mfa nfb, where m and n = 0,
1, 2, 3, and so on. Intermodulation distortion terms are those for
which neither m nor n is equal to zero. For example, the second
order terms include (fa + fb) and (fa − fb), wehreas the third order
terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
Track-and-Hold Acquisition Time
Track-and-hold acquisition time is the time required for the
output of the track-and-hold amplifier to reach its final value,
within 1/2 LSB, after the end of conversion (the point at which
the track-and-hold returns to track mode).
Signal-to-Noise + Distortion (SINAD) Ratio
The SINAD ratio is the measured ratio of signal-to-noise +
distortion at the output of the ADC. The signal is the rms
amplitude of the fundamental. Noise is the sum of all nonfunda-
mental signals up to half the sampling frequency (fS/2), excluding
dc. The ratio is dependent on the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical SINAD ratio for an ideal N-bit
converter with a sine wave input is given by:
The AD7482 is tested using the CCIF standard, where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in frequency
from the original sine waves, whereas the third order terms are
usually at a frequency close to the input frequencies. As a result,
the second order and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification, where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
Signal-to-Noise + Distortion = (6.02N +1.76)dB
Therefore, this is 74 dB for a 12-bit converter.
Rev. B | Page 11 of 20
AD7482
CIRCUIT DESCRIPTION
At the end of conversion, the track-and-hold returns to track
mode and the acquisition time begins. The track-and-hold
acquisition time is 40 ns. Figure 13 shows the ADC during its
acquisition phase. SW2 is closed and SW1 is in Position A. The
comparator is held in a balanced condition and the sampling
capacitor acquires the signal on VIN.
CONVERTER OPERATION
The AD7482 is a 12-bit algorithmic successive approximation
ADC based around a capacitive DAC. It provides the user with
track-and-hold, reference, an ADC, and versatile interface logic
functions on a single chip. The normal analog input signal range
that the AD7482 can convert is 0 V to 2.5 V. By using the offset
and overrange features on the ADC, the AD7482 can convert
analog input signals from −200 mV to +2.7 V while operating
from a single 5 V supply. The part requires a 2.5 V reference,
which can be provided from the internal reference or an external
reference source. Figure 11 shows a simplified schematic of the
ADC. The control logic, SAR, and capacitive DAC are used to
add and subtract fixed amounts of charge from the sampling
capacitor to bring the comparator back to a balanced condition.
COMPARATOR
CAPACITIVE
DAC
A
VIN
+
SW1
CONTROL LOGIC
B
–
SW2
COMPARATOR
AGND
Figure 13. ADC Acquisition Phase
CAPACITIVE
DAC
ANALOG INPUT
+V
S
VIN
8
SWITCHES
1kΩ
100Ω
AC
V
7
REF
+
–
3
2
SIGNAL
VIN
1kΩ
6
BIAS
VOLTAGE
AD829
4
SAR
5
1
–V
S
220pF
CONTROL
LOGIC
CONTROL
INPUTS
150Ω
OUTPUT DATA
12-BIT PARALLEL
Figure 14. Analog Input Circuit Used for 10 kHz Input Tone
Figure 11. Simplified Block Diagram of the AD7482
CONVST
Conversion is initiated on the AD7482 by pulsing the
+V
S
CONVST
input. On the falling edge of
, the track-and-hold goes
from track mode to hold mode and the conversion sequence is
started. Conversion time for the part is 300 ns. Figure 12 shows
the ADC during conversion. When conversion starts, SW2
opens and SW1 moves to Position B, causing the comparator to
become unbalanced. The ADC then runs through its successive-
approximation routine and brings the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion result is available in the SAR register.
8
50Ω
AC
7
2
3
+
SIGNAL
6
VIN
AD8021
220Ω
BIAS
VOLTAGE
4
–
5
1
10pF
–V
S
220Ω
10pF
CAPACITIVE
DAC
Figure 15. Analog Input Circuit Used for 1 MHz Input Tone
Figure 14 shows the analog input circuit used to obtain the data
for the fast fourier transfer (FFT) plot shown in Figure 3. The
circuit uses an AD829 op amp as the input buffer. A bipolar analog
signal is applied and biased up with a stable, low noise dc voltage
connected to the labeled terminal, as shown in Figure 11. A 220 pF
compensation capacitor is connected between Pin 5 and the AD829
and the analog ground plane. The AD829 is supplied with +12 V
and −12 V supplies. The supply pins are decoupled as close to
the device as possible with both a 0.1 µF and a 10 µF capacitor
connected to each pin. In each case, 0.1 µF capacitor should be the
closer of the two caps to the device. More information on the
AD829 is available at www.analog.com.
A
VIN
+
SW1
CONTROL LOGIC
B
–
SW2
COMPARATOR
AGND
Figure 12. ADC Conversion Phase
Rev. B | Page 12 of 20
AD7482
For higher input bandwidth applications, the AD8021 op amp
(also available as a dual AD8022 op amp) is the recommended
choice to drive the AD7482. Figure 15 shows the analog input
circuit used to obtain the data for the FFT plot shown in Figure 4. A
bipolar analog signal is applied to the terminal and biased up with a
stable, low noise dc voltage connected, as shown in Figure 12. A
10 pF compensation capacitor is connected between Pin 5 of the
AD8021 and the negative supply. The AD8021 is supplied with
+12 V and −12 V supplies. The supply pins are decoupled as close
to the device as possible, with both a 0.1 μF anad10 μF capacitor
connected to each pin. In each case, the 0.1 μF capacitor should
be the closer of the two caps to the device. The AD8021 logic
For the remaining 700 ns of the cycle, the AD7482 dissipates
42 mW of power.
(700 ns/1 μs) × (5 V × 12 mA) = 42 mW
Therefore, the power dissipated during each cycle is
27 mW + 42 mW = 69 mW
Figure 17 shows the AD7482 conversion sequence operating in
normal mode.
1µs
CONVST
DISABLE
reference pin is tied to analog ground and the
tied to the positive supply, as shown in Figure 12. Detailed
Pin is
BUSY
300ns
700ns
information on the AD8021 is available at www.analog.com.
Figure 17. Normal Mode Power Dissipation
ADC TRANSFER FUNCTION
In nap mode, almost all the internal circuitry is powered down.
In this mode, the power dissipation is reduced to 2.5 mW. When
using an external reference, there must be a minimum of 300 ns
from exiting nap mode to initiating a conversion. This is necessary
to allow the internal circuitry to settle after power-up and for
the track-and-hold to properly acquire the analog input signal.
The internal reference cannot be used in conjunction with the
nap mode.
The output coding of the AD7482 is straight binary. The designed
code transitions occur midway between the successive integer
LSB values, that is, 1/2 LSB, 3/2 LSB, and so on. The LSB size is
VREF/4096. The nominal transfer characteristic for the AD7482 is
shown in Figure 16. This transfer characteristic may be shifted
as detailed in the Offset/Overrange section.
111...111
111...110
If the AD7482 is put into nap mode after each conversion, the
average power dissipation is reduced, but the throughput rate is
limited by the power-up time. Using the AD7482 with a through-
put rate of 500 kSPS while placing the part in nap mode after
each conversion results in average power dissipation as follows:
111...000
1LSB = V
REF
/4096
011...111
000...010
000...001
000...000
The power-up phase contributes
0.5LSB
+V
– 1.5LSB
REF
0V
(300 ns/2 μs) × (5 V × 12 mA) = 9 mW
The conversion phase contributes
(300 ns/2 μs) × (5 V × 18 mA) = 13.5 mA
ANALOG INPUT
Figure 16. AD7482 Transfer Characteristic
POWER SAVING
While in nap mode for the rest of the cycle, the AD7482
dissipates only 1.75 mW of power.
The AD7482 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. In addition, the
AD7482 features two power saving modes, nap and standby. These
modes are selected by bringing either the NAP pin or STBY pin
to a logic high, respectively.
(1400 ns/2 μs) × (5 V × 0.5 mA) = 1.75 mW
Therefore, the power dissipated during each cycle is
9 mW + 13.5 mW + 1.75 mW = 24.25 mW
When operating the AD7482 in normal fully powered mode,
the current consumption is 18 mA during conversion and the
quiescent current is 12 mA. Operating at a throughput rate of
1 MSPS, the conversion time of 300 ns contributes 27 mW to
the overall power dissipation.
(300 ns/1 μs) × (5 V × 18 mA) = 27 mW
Rev. B | Page 13 of 20
AD7482
Figure 18 shows the AD7482 conversion sequence when the
part is put into nap mode after each conversion.
reference source is used and kept powered up while the AD7482 is
in standby mode, the power-up time required is reduced to 80 µs.
600ns
1400ns
OFFSET/OVERRANGE
NAP
The AD7482 provides a 8% overrange capability as well as a
programmable offset register. The overrange capability is achieved
by the use of a 13th bit (D12) and the CLIP input. If the CLIP input
is at logic high and the contents of the offset register are 0, then the
AD7482 operates as a normal 12-bit ADC. If the input voltage is
greater than the full-scale voltage, the data output from the ADC is
all 1s. Similarly, if the input voltage is lower than the zero-scale
voltage, the data output from the ADC is all 0s. In this case, D12
acts as an overrange indicator. It is set to 1 if the analog input
voltage is outside the nominal 0 V to 2.5 V range.
300ns
CONVST
BUSY
2µs
Figure 18. Nap Mode Power Dissipation
Figure 19 and Figure 20 show a typical graphical representation
of power vs. throughput for the AD7482 when in normal mode
The default contents of the offset register are 0. If the offset register
contains any value other than 0, the contents of the register are
added to the SAR result at the end of conversion. This has the effect
of shifting the transfer function of the ADC as shown in Figure 21
and Figure 22. Note that with the CLIP input set to logic high, the
maximum and minimum codes that the AD7482 can output are
0xFFF and 0x000, respectively. Further details are given in Table 5
and Table 6.
and nap mode, respectively.
90
85
80
75
70
65
60
Figure 21 shows the effect of writing a positive value to the
offset register. For example, if the contents of the offset register
contained the value 256, then the value of the analog input
voltage for which the ADC transitions from reading all 0s to
000...001 (the bottom reference point) is
0
500
1000
1500
2000
2500
3000
0.5 LSB − (256 LSB) = −155.944 mV
THROUGHPUT (kSPS)
In this example, the analog input voltage for which the ADC
reads full-scale (0xFFF) is
Figure 19. Normal Mode, Power vs. Throughput
90
80
70
60
50
40
30
20
2.5 V − 1.5 LSB − (256 LSB) = 2.3428 V
111...111
111...110
111...000
1LSB = V
REF
/4096
011...111
+V
– 1.5LSB
REF
–OFFSET
000...010
000...001
000...000
ANALOG INPUT
0V
10
0
Figure 21. Transfer Characteristic with Positive Offset
0
250
500
750
1000
1250
1500
1750
2000
The effect of writing a negative value to the offset register is
shown in Figure 22. If a value of −128 is written to the offset
register, the bottom end reference point occurs at
THROUGHPUT (kSPS)
Figure 20. Nap Mode, Power vs. Throughput
In standby mode, all the internal circuitry is powered down and the
power consumption of the AD7482 is reduced to 10 μW. T he
power-up time necessary before a conversion can be initiated is
longer because more of the internal circuitry has been powered
down. In using the internal reference of the AD7482, the ADC
must be brought out of standby mode 500 ms before a conversion is
initiated. Initiating a conversion before the required power-up time
has elapsed results in incorrect conversion data. If an external
0.5 LSB − (−128 LSB) = 78.43 mV
Following this, the analog input voltage needed to produce a
full-scale (0xFFF) result from the ADC is
2.5 V − 1.5 LSB − (−128 LSB) = 2.5772 V
Rev. B | Page 14 of 20
AD7482
Logic 0, the ADC is outside the nominal range on the positive side
and the output code is a 13-bit straight binary code, see Table 7.
111...111
111...110
Table 7. DB14, DB13 Decoding, CLIP = 0
1LSB = V
REF
/4096
111...000
011...111
DB12 DB11
Output Coding
0
0
1
1
0
1
0
1
Straight binary – inside nominal range
Straight binary – inside nominal range
Straight binary – outside nominal range
Twos complement – outside nominal range
000...010
000...001
000...000
0.5LSB
–OFFSET
ANALOG INPUT
+V
– 1.5LSB
REF
–OFFSET
0V
Values from −327 to +327 can be written to the offset register.
These values correspond to an offset of 200 mV. A write to the
offset register is performed by writing a 13-bit word to the part
as detailed in the Parallel Interface section. The 10 LSBs of the
13-bit word contain the offset value, whereas the 3 MSBs must
be set to 0. Failure to write 0s to the 3 MSBs may result in the
incorrect operation of the device.
Figure 22. Transfer Characteristic with Negative Offset
Table 5 shows the expected ADC result for a given analog input
voltage with different offset values and with CLIP tied to logic high.
The combined advantages of the offset and overrange features of
the AD7482 are shown in Table 6. Table 6 shows the same range of
analog input and offset values as Table 5 but with the clipping
feature disabled.
PARALLEL INTERFACE
The AD7482 features two parallel interfacing modes. These
modes are selected by the mode pins (see Table 8).
Table 5. Clipping Enabled (CLIP = 1)
−128
0
+256
Offset VIN
−200 mV
−156.25 mV
0 V
+78.125 mV
+2.3431 V
+2.5 V
ADC DATA, D[0:11]
D12
1 1 1
1 1 0
1 0 0
0 0 0
0 0 0
0 0 1
0 1 1
1 1 1
Table 8. Operating Modes
Operating Mode
0
0
0
0
3711
3967
4095
4095
0
0
Mode 2
Mode 1
0
0
Do Not Use
0
0
1
1
0
1
0
1
0
256
384
4095
4095
4095
4095
Parallel Mode 1
Parallel Mode 2
Do Not Use
128
3839
4095
4095
4095
In Parallel Mode 1, the data in the output register is updated on
BUSY
+2.5775 V
+2.7 V
the rising edge of
at the end of a conversion and is available
for reading almost immediately afterward. Using this mode,
throughput rates of up to 2.5 MSPS can be achieved. This mode
is to be used if the conversion data is required immediately after
the conversion is completed. An example where this may be of use
is if the AD7482 is operating at much lower throughput rates in
conjunction with the nap mode (for power saving reasons), and
the input signal is being compared with set limits within the DSP or
other controller. If the limits are exceeded, the ADC is brought
immediately into full power operation and commences sampling at
full speed. Figure 31 shows a timing diagram for the AD7482
Table 6. Clipping Disabled (CLIP = 0)
−128
0
+256
Offset VIN
ADC DATA, D[0:12]
−200 mV
−156.25 mV
0 V
+78.125 mV
+2.3431 V
+2.5 V
−456
−384
−128
0
3711
3967
4095
4296
−328
−256
0
−72
0
256
384
4095
4351
4479
4680
128
3839
4095
4223
4424
CS
RD
operating in Parallel Mode 1 with both
In Parallel Mode 2, the data in the output register is not updated
CONVST
and
tied low.
+2.5775 V
+2.7 V
until the next falling edge of
. This mode can be used
If the CLIP input is at logic low, the overrange indicator is disabled
and the AD7482 is able to achieve output codes outside the
nominal 12-bit range of 0 to 4095 (see Figure 6). D12 acts as an
indicator that the ADC is outside this nominal range. If the ADC is
outside this nominal range on the negative side, the ADC outputs a
twos complement code and if the ADC is outside the range on the
positive side, the ADC outputs a straight binary code as normal.
If D12 is Logic 1, D11 indicates if the ADC is out of range on
the positive or negative side. If D11 is Logic 1, the ADC is outside
the nominal range on the negative side and the output code is a
13-bit twos complement number (a negative number). If D11 is
where a single sample delay is not vital to the system operation,
and conversion speeds of greater than 2.5 MSPS are desired. For
example, this may occur in a system where a large amount of
samples are taken at high speed before an FFT is performed for
frequency analysis of the input signal. Figure 32 shows a timing
diagram for the AD7482 operating in Parallel Mode 2 with both
CS
RD
tied low.
and
Rev. B | Page 15 of 20
AD7482
Data must not be read from the AD7482 while a conversion is
taking place. For this reason, if operating the AD7482 at through-
put speeds greater than 2.5 MSPS, it is necessary to tie both the
CONVST
Driving the
Pin
To achieve the specified performance from the AD7482, the
pin must be driven from a low jitter source. Because
the falling edge on the
instant, any jitter that may exist on this edge appears as noise
when the analog input signal contains high frequency components.
The relationship between the analog input frequency (fIN), timing
jitter (tj), and resulting SNR is given by
CONVST
CS
RD
pin and
pins on the AD7482 low and use a buffer on the
CONVST
pin determines the sampling
data lines. This situation may also arise in the case where a read
operation cannot be completed in the time after the end of one
conversion and the start of the quiet period before the next
conversion.
The maximum slew rate at the input of the ADC must be limited to
1
SNRJITTER dB =10log
( )
BUSY
500 V/µs while
is low to avoid corrupting the ongoing
2
2π× fIN ×t j
conversion. In any multiplexed application where the channel is
switched during conversion, this is to happen as soon as possible
For example, if the desired SNR due to jitter was 100 dB with a
maximum full-scale analog input frequency of 1.5 MHz, ignoring
all other noise sources, the result is an allowable jitter on the
BUSY
after the
falling edge.
Reading Data from the AD7482
CONVST
falling edge of 1.06 ps. For a 12-bit converter (ideal
SNR = 74 dB), the allowable jitter is greater than 1.06 ps, but
CONVST
Data is read from the part via a 13-bit parallel data bus with the
CS
RD
CS RD
signal. The signal and signal are
standard
signal and
due consideration must be given to the design of the
circuitry to achieve 12-bit performance with large analog input
frequencies.
internally gated to enable the conversion result onto the data bus.
The data lines D0 to D12 leave their high impedance state when
CS
RD
CS
both the
and
are logic low. Therefore,
may be perma-
Typical Connection
RD
nently tied logic low if required, and the
signal may be used
Figure 23 shows a typical connection diagram for the AD7482
operating in Parallel Mode 1. Conversion is initiated by a falling
to access the conversion result. Figure 29 shows a timing specifica-
tion called tQUIET. This is the amount of time that must be left
after any data bus activity before the next conversion is initiated.
CONVST
CONVST
BUSY
edge on
goes low, and at the end of conversion, the rising edge of
CS
. When
goes low, the
signal
BUSY
Writing to the AD7482
RD
and
is used to activate an interrupt service routine. The
The AD7482 features a user accessible offset register. This allows
the bottom of the transfer function to be shifted by 200 mV. This
feature is explained in more detail in the Offset/Overrange section.
lines are then activated to read the 12 data bits (13 bits if using
the overrange feature).
In Figure 23, the VDRIVE pin is tied to DVDD, which results in
logic output levels being either 0 V or DVDD. The voltage applied to
To write to the offset register, a 13-bit word is written to the
AD7482 with the 10 LSBs containing the offset value in twos
complement format. The 3 MSBs must be set to 0. The offset
value must be within the range −327 to +327, corresponding to
an offset from −200 mV to +200 mV. The value written to the
offset register is stored and used until power is removed from
the device, or the device is reset. The value stored can be updated at
any time between conversions by another write to the device.
Table 9 shows examples of offset register values and their effective
offset voltage. Figure 30 shows a timing diagram for writing to
the AD7482.
V
DRIVE controls the voltage value of the output logic signals. For
example, if DVDD is supplied by a 5 V supply and VDRIVE is supplied
by a 3 V supply, the logic output levels are either 0 V or 3 V. This
feature allows the AD7482 to interface to 3 V devices, while still
enabling the ADC to process signals at a 5 V supply.
DIGITAL
SUPPLY
4.75V TO 5.25V
ANALOG
SUPPLY
4.75V TO 5.25V
+
+
10µF
1nF
0.1µF
0.1µF
47µF
0.1µF
Table 9. Offset Register Examples
V
DV
AV
DD DD
DRIVE
Code
(Decimal)
D9 to D0 (Twos
Complement)
Offset
(mV)
C
ADM809
RESET
MODE1
MODE2
WRITE
CLIP
BIAS
D12 to D10
1nF
REFSEL
REFIN
−327
−128
+64
000
000
000
000
1010111001
1110000000
0001000000
0101000111
−200
−78.12
+39.06
+200
AD780 2.5V
REFERENCE
NAP
0.47µF
STBY
+327
AD7482
PARALLEL
INTERFACE
D0 TO D12
REFOUT
0.47µF
CS
CONVST
RD
VIN
0V TO 2.5V
BUSY
Figure 23. Typical Connection Diagram
Rev. B | Page 16 of 20
AD7482
layer where the power traces exist. The ground plane between
the top and bottom planes provides excellent shielding.
BOARD LAYOUT AND GROUNDING
For optimum performance from the AD7482, it is recommended
that a PCB with a minimum of three layers be used. One of
these layers, preferably the middle layer, should be as complete a
ground plane as possible to give the best shielding. The board
should be designed in such a way that the analog and digital
circuitry is separated and confined to certain areas of the board.
This practice, along with not running digital and analog lines close
together, helps to avoid coupling digital noise onto analog lines.
Figure 24 to Figure 28 show a sample layout of the board area
immediately surrounding the AD7482. Pin 1 is the bottom left
corner of the device. The black area in each figure indicates the
ground plane present on the middle layer Figure 24 shows the
top layer where the AD7482 is mounted with vias to the bottom
routing layer highlighted. Figure 25 shows the bottom layer
silkscreen where the decoupling components are soldered
directly beneath the device. Figure 26 shows the top and bottom
routing layers overlaid Figure 27 shows the bottom layer where
the power routing is with the same vias highlighted. Figure 28
shows the silkscreen overlaid on the solder pads for the decoupling
components, which are C1 to C6: 100 nF, C7 to C8: 470 nF, C9:
1 nF, and L1 to L4: Meggit-Sigma Chip Ferrite Beads
The power supply lines to the AD7482 should be approximately
3 mm wide to provide low impedance paths and reduce the effects
of glitches on the power supply lines. It is vital that good decoupling
also be present. A combination of ferrites and decoupling capa-
citors should be used as shown in Figure 23. The decoupling
capacitors are to be as close to the supply pins as possible. This
is made easier by the use of multilayer boards. The signal traces
from the AD7482 pins can be run on the top layer, while the
decoupling capacitors and ferrites can be mounted on the bottom
(BMB2A0600RS2).
Figure 27. Bottom Layer Routing
Figure 24. Top Layer Routing
Figure 25. Bottom Layer Silkscreen
Figure 26. Top and Bottom Routing Layers
Figure 28. Silkscreen and Bottom Layer Routing
Rev. B | Page 17 of 20
AD7482
tCONV
tACQ
tQUIET
t1
CONVST
BUSY
t2
t14
WRITE
t8
t3
t15
RD
t4
t7
DATA VALID
D[12:0]
Figure 29. Parallel Mode Read Cycle
CONVST
t12
t13
CS
RD
t9
WRITE
D[12:0]
t10
t11
OFFSET DATA
Figure 30. Parallel Mode Write Cycle
tCONV
t1
CONVST
N
N + 1
t2
BUSY
t6
DATA N – 1
DATA N
D[12:0]
Figure 31. Parallel Mode 1 Read Cycle
tCONV
t1
CONVST
BUSY
N
N + 1
t2
t5
D[12:0]
DATA N – 1
DATA N
Figure 32. Parallel Mode 2 Read Cycle
Rev. B | Page 18 of 20
AD7482
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
0.75
0.60
0.45
1.60
MAX
37
48
36
1
PIN 1
7.20
TOP VIEW
(PINS DOWN)
7.00 SQ
6.80
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
25
12
0.15
0.05
13
24
SEATING
PLANE
0.08
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
COPLANARITY
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 33. 48-Lead Plastic Quad Flatpack [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Integral
Package
Option
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Nonlinearity (INL)
1 LSB Maximum
0.5 LSB Maximum
Package Description
AD7482ASTZ
AD7482BSTZ
EVAL-AD7482CB
EVAL-CONTROLBRD2Z
48-Lead Plastic Quad Flatpack Package (LQFP)
48-Lead Plastic Quad Flatpack Package (LQFP)
ST-48
ST-48
2
Evaluation Board
Controller Board3
1 Z = RoHS Compliant Part.
2 This can be used either as a standalone evaluation board or in conjunction with the controller board for evaluation/demonstration purposes.
3 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
Rev. B | Page 19 of 20
AD7482
NOTES
©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02638-0-12/09(B)
Rev. B | Page 20 of 20
相关型号：
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1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQFP48, 7 X 7 MM, ROHS COMPLIANT, MS-026BBC, LQFP-48
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