AD7482BST [ADI]
3MSPS, 12-Bit SAR ADC; 3MSPS ， 12位SAR ADC
| 型号： | AD7482BST |
| 厂家： | 
ADI |
| 描述： | 3MSPS, 12-Bit SAR ADC |
| 文件： | 总16页 (文件大小：684K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
3 MSPS, 12-Bit SAR ADC
AD7482
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fast Throughput Rate: 3 MSPS
Wide Input Bandwidth: 40 MHz
No Pipeline Delays with SAR ADC
Excellent DC Accuracy Performance
Two Parallel Interface Modes
Low Power:
90 mW (Full Power) and 2.5 mW (NAP Mode)
Standby Mode: 2 A Max
Single 5 V Supply Operation
AV
AGND
C
DV
V
DGND
DD
BIAS
DD
DRIVE
REFOUT
REFIN
2.5V
REFERENCE
BUF
REFSEL
VIN
12-BIT
ALGORITHMIC SAR
T/H
Internal 2.5 V Reference
Full-Scale Overrange Mode (using 13th Bit)
System Offset Removal via User Access Offset Register
Nominal 0 V to 2.5 V Input with Shifted Range
Capability
AD7482
D12
D11
D10
D9
D8
D7
MODE1
MODE2
CLIP
NAP
STBY
RESET
14-Bit Pin Compatible Upgrade AD7484 Available
CONTROL
LOGIC AND I/O
REGISTERS
D6
D5
CONVST
GENERAL DESCRIPTION
The AD7482 is a 12-bit, high speed, low power, successive-
approximation ADC. The part features a parallel interface with
throughput rates up to 3 MSPS. The part contains a low noise,
wide bandwidth track-and-hold that can handle input fre-
quencies in excess of 40 MHz.
The conversion process is a proprietary algorithmic successive-
approximation technique that results in no pipeline delays. The
input signal is sampled, and a conversion is initiated on the
falling edge of the CONVST signal. The conversion process is
controlled via an internally trimmed oscillator. Interfacing is via
standard parallel signal lines, making the part directly compat-
ible with microcontrollers and DSPs.
The AD7482 features an on-board 2.5 V reference but can also
accommodate an externally provided 2.5 V reference source. The
nominal analog input range is 0 V to 2.5 V, but an offset shift
capability allows this nominal range to be offset by 200 mV.
This allows the user considerable flexibility in setting the bottom
end reference point of the signal range, a useful feature when
using single-supply op amps.
The AD7482 provides excellent ac and dc performance specifi-
cations. Factory trimming ensures high dc accuracy resulting in
very low INL, offset, and gain errors.
The AD7482 also provides the user with an 8% overrange
capability via a 13th bit. Thus, if the analog input range strays
outside the nominal by up to 8%, the user can still accurately
resolve the signal by using the 13th bit.
The part uses advanced design techniques to achieve very low
power dissipation at high throughput rates. Power consumption
in the normal mode of operation is 90 mW. There are two power-
saving modes: a NAP Mode that keeps the reference circuitry alive
for a quick power-up while consuming 2.5 mW, and a STANDBY
Mode that reduces power consumption to a mere 10 µW.
The AD7482 is powered by a 4.75 V to 5.25 V supply. The part
also provides a VDRIVE Pin that allows the user to set the voltage
levels for the digital interface lines. The range for this VDRIVE Pin
is 2.7 V to 5.25 V. The part is housed in a 48-lead LQFP package
and is specified over a –40°C to +85°C temperature range.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
(VDD = 5 V 5%, AGND = DGND = 0 V, VREF = External, fSAMPLE = 3 MSPS; all specifi-
AD7482–SPECIFICATIONS1 cations TMIN to TMAX and valid for VDRIVE = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
Specification
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE2, 3
Signal-to-Noise + Distortion (SINAD)4
71
72
71
–86
–90
–88
–87
dB min
dB typ
dB typ
dB max
dB typ
dB typ
dB max
FIN = 1 MHz
FIN = 1 MHz
FIN = 1 MHz, Internal Reference
Total Harmonic Distortion (THD)4
Internal Reference
Peak Harmonic or Spurious Noise (SFDR)4
Intermodulation Distortion (IMD)4
Second Order Terms
Third Order Terms
Aperture Delay
–96
–94
10
dB typ
dB typ
ns typ
FIN1 = 95.053 kHz, FIN2 = 105.329 kHz
Full-Power Bandwidth
40
3.5
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
DC ACCURACY
Resolution
12
0.5
1
0.25
0.5
0.25
1.5
0.036
1.5
Bits
Integral Nonlinearity4
LSB max
LSB max
LSB typ
LSB max
LSB typ
LSB max
%FSR max
LSB max
%FSR max
B Grade
A Grade
Differential Nonlinearity4
Offset Error4
Guaranteed No Missed Codes to 12 Bits
Gain Error4
0.036
ANALOG INPUT
Input Voltage
–200
+2.7
1
2
35
mV min
V max
µA max
µA typ
pF typ
DC Leakage Current
Input Capacitance5
VIN from 0 V to 2.7 V
VIN = –200 mV
REFERENCE INPUT/OUTPUT
VREFIN Input Voltage
+2.5
1
25
220
+2.5
50
100
1
V
1% for Specified Performance
External Reference
V
REFIN Input DC Leakage Current
µA max
pF typ
µA typ
V typ
mV typ
mV max
Ω typ
VREFIN Input Capacitance5
VREFIN Input Current
V
REFOUT Output Voltage
VREFOUT Error @ 25°C
VREFOUT Error TMIN to TMAX
VREFOUT Output Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
VDRIVE –1
0.4
1
V min
V max
µA max
pF max
5
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance5
Output Coding
0.7 × VDRIVE
V min
0.3 × VDRIVE
V max
µA max
pF max
10
10
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time(tACQ
300
70
70
2.5
3
ns max
ns max
ns max
MSPS max
MSPS max
)
Sine Wave Input
Full-Scale Step Input
Parallel Mode 1
Parallel Mode 2
Throughput Rate
–2–
REV. 0
AD7482
(VDD = 5 V 5%, AGND = DGND = 0 V, VREF = External, fSAMPLE = 3 MSPS; all specifications TMIN
to TMAX and valid for VDRIVE = 2.7 V to 5.25 V, unless otherwise noted.)
SPECIFICATIONS (continued)
Parameter
Specification
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
5
V
5%
VDRIVE
2.7
5.25
V min
V max
IDD
Normal Mode (Static)
Normal Mode (Operational)
NAP Mode
12
18
0.5
2
mA max
mA max
mA max
µA max
µA typ
CS and RD = Logic 1
Standby Mode
0.5
Power Dissipation
Normal Mode (Operational)
NAP Mode
90
2.5
10
mW max
mW max
µW max
Standby Mode6
NOTES
1Temperature range is as follows: –40°C to +85°C.
2SNR and SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB.
3See Typical Performance Characteristics section for analog input circuits used.
4See Terminology section.
5Sample tested @ 25°C to ensure compliance.
6Digital input levels at GND or VDRIVE
.
Specifications subject to change without notice.
(VDD = 5 V 5%, AGND = DGND = 0 V, VREF = External; all specifications TMIN to TMAX and valid for
VDRIVE = 2.7 V to 5.25 V, unless otherwise noted.)
TIMING CHARACTERISTICS*
Parameter
Symbol
Min
Typ
Max
Unit
DATA READ
Conversion Time
tCONV
tQUIET
t1
t2
t3
t4
t5
t6
t7
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Quiet Time before Conversion Start
CONVST Pulsewidth
CONVST Falling Edge to BUSY Falling Edge
CS Falling Edge to RD Falling Edge
Data Access Time
CONVST Falling Edge to New Data Valid
BUSY Rising Edge to New Data Valid
Bus Relinquish Time
RD Rising Edge to CS Rising Edge
CS Pulsewidth
100
5
20
0
25
30
5
10
t8
t14
t15
0
30
30
RD Pulsewidth
DATA WRITE
WRITE Pulsewidth
Data Setup Time
Data Hold Time
CS Falling Edge to WRITE Falling Edge
WRITE Falling Edge to CS Rising Edge
t9
5
2
6
5
0
ns
ns
ns
ns
ns
t10
t11
t12
t13
*All timing specifications given above are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used.
Specifications subject to change without notice.
REV. 0
–3–
AD7482
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 50°C/W
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 10°C/W
Lead Temperature, Soldering
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDRIVE to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to GND . . . . . –0.3 V to VDRIVE + 0.3 V
REFIN to GND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin except Supplies . . . . . . . . . 10 mA
Operating Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
1
2
AV
36
35
34
33
32
31
30
29
28
27
26
25
D8
D7
D6
D5
V
DD
PIN 1
IDENTIFIER
C
BIAS
3
AGND
4
AGND
5
AV
DD
AGND
VIN
DRIVE
AD7482
6
DGND
DGND
TOP VIEW
7
(Not to Scale)
8
REFOUT
REFIN
REFSEL
AGND
DV
D4
D3
D2
D1
DD
9
10
11
12
AGND
13 14 15 16 17 18 19 20 21 22 23 24
ORDERING GUIDE
Model
Temperature Range
Integral Nonlinearity (INL)
Package Options
AD7482AST
–40°C to +85°C
–40°C to +85°C
Evaluation Board
Controller Board
1 LSB Max
0.5 LSB Max
ST-48 (LQFP)
ST-48 (LQFP)
AD7482BST
EVAL-AD7482CB1
EVAL-CONTROL BRD22
NOTES
1This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.
2This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7482 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD7482
PIN FUNCTION DESCRIPTIONS
Pin
Number
Mnemonic
Description
Positive Power Supply for Analog Circuitry
Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin
and AGND.
1, 5, 13, 46
2
AVDD
CBIAS
3, 4, 6, 11, 12,
AGND
Power Supply Ground for Analog Circuitry
14, 15, 47, 48
7
8
VIN
REFOUT
Analog Input. Single-ended analog input channel.
Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF
capacitor must be placed between this pin and AGND.
9
REFIN
Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using an
external voltage reference source, the reference voltage should be applied to this pin.
10
REFSEL
Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected
from this pin to AGND. When using an external reference source, this pin should be connected
directly to AGND.
16
17
18
STBY
NAP
CS
Standby Logic Input. When this pin is logic high, the device will be placed in Standby Mode.
See Power Saving section for further details.
NAP Logic Input. When this pin is logic high, the device will be placed in a very low power mode.
See Power Saving section for further details.
Chip Select Logic Input. This pin is used in conjunction with RD to access the conversion result.
The databus is brought out of three-state and the current contents of the output register driven
onto the data lines following the falling edge of both CS and RD. CS is also used in conjunction
with WRITE to perform a write to the offset register. CS can be hardwired permanently low.
19
20
RD
Read Logic Input. Used in conjunction with CS to access the conversion result.
WRITE
Write Logic Input. Used in conjunction with CS to write data to the offset register. When the
desired offset word has been placed on the databus, the WRITE line should be pulsed high. It is
the falling edge of this pulse that latches the word into the offset register.
21
BUSY
Busy Logic Output. This pin indicates the status of the conversion process. The BUSY signal goes
low after the falling edge of CONVST and stays low for the duration of the conversion. In Parallel
Mode 1, the BUSY signal returns high when the conversion result has been latched into the output
register. In Parallel Mode 2, the BUSY signal returns high as soon as the conversion has been
completed, but the conversion result does not get latched into the output register until the falling
edge of the next CONVST pulse.
22, 23
R1, R2
These pins should be pulled to ground via 100 kΩ resistors.
24–28, 33–39
D0–D11
Data I/O Bits (D11 is MSB). These are three-state pins that are controlled by CS, RD, and
WRITE. The operating voltage level for these pins is determined by the VDRIVE input.
29
30, 31
32
DVDD
DGND
VDRIVE
Positive Power Supply for Digital Circuitry
Ground Reference for Digital Circuitry
Logic Power Supply Input. The voltage supplied at this pin will determine at what voltage the
interface logic of the device will operate.
40
41
D12
Data Output Bit for Overranging. If the overrange feature is not used, this pin should be pulled to
DGND via a 100 kΩ resistor.
Convert Start Logic Input. A conversion is initiated on the falling edge of the CONVST signal.
The input track-and-hold amplifier goes from track mode to hold mode and the conversion process
commences.
CONVST
42
RESET
Reset Logic Input. A falling edge on this pin resets the internal state machine and terminates a
conversion that may be in progress. The contents of the offset register will also be cleared on this
edge. Holding this pin low keeps the part in a reset state.
43
44
45
MODE2
MODE1
CLIP
Operating Mode Logic Input. See Table III for details.
Operating Mode Logic Input. See Table III for details.
Logic Input. A logic high on this pin enables output clipping. In this mode, any input voltage that
is greater than positive full scale or less than negative full scale will be clipped to all “1s” or all “0s,”
respectively. Further details are given in the Offset/Overrange section.
REV. 0
–5–
AD7482
TERMINOLOGY
Peak Harmonic or Spurious Noise
Integral Nonlinearity
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output spec-
trum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and ideal 1 LSB
change between any two adjacent codes in the ADC.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa nfb, where
m and n = 0, 1, 2, 3, and so on. Intermodulation distortion
terms are those for which neither m nor n are equal to zero.
For example, the second order terms include (fa + fb) and
(fa – fb), while the third order terms include (2fa + fb),
(2fa – fb), (fa + 2fb), and (fa – 2fb).
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 0.5 LSB.
Gain Error
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., VREF – 1.5 LSB) after the
offset error has been adjusted out.
The AD7482 is tested using the CCIF standard, where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification, where it is the ratio of the rms sum
of the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dBs.
Track-and-Hold Acquisition Time
Track-and-hold acquisition time is the time required for the
output of the track-and-hold amplifier to reach its final value,
within 1/2 LSB, after the end of conversion (the point at
which the track-and-hold returns to track mode).
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at
the output of the A/D converter. The signal is the rms amplitude
of the fundamental. Noise is the sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the quanti-
zation noise. The theoretical signal-to-(noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:
Signal−to−(Noise + Distortion) = 6.02N +1.76 dB
(
)
Thus, for a 12-bit converter this is 74 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum
of the harmonics to the fundamental. For the AD7482, it is
defined as:
2
2
2
2
2
V2 +V3 +V4 +V5 +V6
THD(dB) = 20log
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
–6–
REV. 0
Typical Performance Characteristics–AD7482
0
–20
0.5
fIN = 10.7kHz
SNR = +72.97dB
SNR + D = +72.94dB
THD = –91.5dB
0.4
0.3
0.2
–40
0.1
–60
0
–0.1
–0.2
–0.3
–0.4
–0.5
–80
–100
–120
0
200
400
600
800
1000
1200
1400
0
1024
2048
3072
4096
FREQUENCY – kHz
ADC – Code
TPC 1. 64k FFT Plot With 10kHz Input Tone
TPC 4. Typical INL
0
80
75
70
65
fIN = 1.013MHz
SNR = +72.58dB
SNR + D = +72.57dB
THD = –94.0dB
–20
–40
–60
–80
–100
–120
0
200
400
600
800
1000
1200
1400
10
100
1000
10000
INPUT FREQUENCY – kHz
FREQUENCY – kHz
TPC 5. SINAD vs. Input Tone (AD8021 Input Circuit)
TPC 2. 64k FFT Plot With 1MHz Input Tone
0.5
0.4
0.3
0.2
0.1
0
–40
200⍀
100⍀
–50
–60
51⍀
–70
10⍀
–0.1
–80
–0.2
–0.3
–0.4
–0.5
0⍀
–90
–100
100
1000
10000
0
1024
2048
3072
4096
INPUT FREQUENCY – kHz
ADC – Code
TPC 6. THD vs. Input Tone for Different Input Resistances
TPC 3. Typical DNL
REV. 0
–7–
AD7482
0
–10
–20
–30
–40
0.0004
0
100mV p-p SINEWAVE ON SUPPLY PINS
–0.0004
–0.0008
–0.0012
–0.0016
–0.0020
–50
–60
–70
–80
10
–55
–25
5
35
65
95
125
100
1000
TEMPERATURE – ؇C
FREQUENCY – kHz
TPC 8. Reference Out Error
TPC 7. PSRR without Decoupling
+V
S
Figure 1 shows the analog input circuit used to obtain the
data for the FFT plot shown in TPC 1. The circuit uses an
Analog Devices AD829 op amp as the input buffer. A bipolar
analog signal is applied as shown and biased up with a stable,
low noise dc voltage connected to the labeled terminal
shown. A 220 pF compensation capacitor is connected be-
tween Pin 5 and the AD829 and the analog ground plane.
The AD829 is supplied with +12 V and –12 V supplies. The
supply pins are decoupled as close to the device as possible
with both a 0.1 F and 10 F capacitor connected to each
pin. In each case, 0.1 F capacitor should be the closer of
the two caps to the device. More information on the AD829
is available on the Analog Devices website.
8
1k⍀
1k⍀
100⍀
AC
7
+
–
3
2
SIGNAL
V
6
IN
AD829
BIAS
VOLTAGE
4
5
1
–V
S
220pF
150⍀
Figure 1. Analog Input Circuit Used for 10 kHz Input Tone
+V
S
For higher input bandwidth applications, Analog Devices’
AD8021 op amp (also available as a dual AD8022) is the
recommended choice to drive the AD7482. Figure 2 shows
the analog input circuit used to obtain the data for the FFT
plot shown in TPC 2. A bipolar analog signal is applied to
the terminal shown and biased up with a stable, low noise dc
voltage connected as shown. A 10 pF compensation capacitor
is connected between Pin 5 of the AD8021 and the negative
supply. As with the previous circuit, the AD8021 is supplied
with +12 V and –12 V supplies. The supply pins are decoupled
as close to the device as possible, with both a 0.1 µF and 10 µF
capacitor connected to each pin. In each case, the 0.1 µF capaci-
tor should be the closer of the two caps to the device. The
AD8021 logic reference pin is tied to analog ground and the
DISABLE Pin is tied to the positive supply as shown. Detailed
information on the AD8021 is available on the Analog
Devices website.
8
50⍀
AC
7
2
3
+
SIGNAL
V
6
IN
AD8021
220⍀
BIAS
VOLTAGE
4
–
5
1
10pF
–V
S
220⍀
10pF
Figure 2. Analog Input Circuit Used for 1 MHz Input Tone
–8–
REV. 0
AD7482
CIRCUIT DESCRIPTION
CONVERTER OPERATION
CAPACITIVE
DAC
The AD7482 is a 12-bit algorithmic successive-approximation
analog-to-digital converter based around a capacitive DAC. It
provides the user with track-and-hold, reference, an A/D con-
verter, and versatile interface logic functions on a single chip.
The normal analog input signal range that the AD7482 can
convert is 0 V to 2.5 V. By using the offset and overrange fea-
tures on the ADC, the AD7482 can convert analog input signals
from –200 mV to +2.7 V while operating from a single 5 V
supply. The part requires a 2.5 V reference, which can be
provided from the part’s own internal reference or an exter-
nal reference source. Figure 3 shows a very simplified
schematic of the ADC. The control logic, SAR, and capaci-
tive DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back to a balanced condition.
A
V
IN
+
SW1
CONTROL LOGIC
B
–
SW2
COMPARATOR
AGND
Figure 5. ADC Acquisition Phase
ADC TRANSFER FUNCTION
The output coding of the AD7482 is straight binary. The designed
code transitions occur midway between the successive integer
LSB values (i.e., 1/2 LSB, 3/2 LSB, and so on). The LSB size
is VREF/4096. The nominal transfer characteristic for the AD7482
is shown in Figure 6. This transfer characteristic may be shifted
as detailed in the Offset/Overrange section.
COMPARATOR
CAPACITIVE
DAC
111...111
111...110
V
IN
SWITCHES
SAR
V
REF
111...000
1LSB =V
/4096
REF
011...111
000...010
000...001
000...000
CONTROL
LOGIC
CONTROL
INPUTS
OUTPUT DATA
12-BIT PARALLEL
0.5LSB
+V
REF
– 1.5LSB
0V
ANALOG INPUT
Figure 3. Simplified Block Diagram of AD7482
Figure 6. AD7482 Transfer Characteristic
Conversion is initiated on the AD7482 by pulsing the CONVST
input. On the falling edge of CONVST, the track-and-hold
goes from track mode to hold mode and the conversion
sequence is started. Conversion time for the part is 300 ns.
Figure 4 shows the ADC during conversion. When conversion
starts, SW2 will open and SW1 will move to Position B, causing
the comparator to become unbalanced. The ADC then runs
through its successive-approximation routine and brings the
comparator back into a balanced condition. When the compara-
tor is rebalanced, the conversion result is available in the
SAR Register.
POWER SAVING
The AD7482 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. In addition to
this, the AD7482 features two power saving modes, NAP and
Standby. These modes are selected by bringing either the NAP or
STBY Pin to a logic high, respectively.
When operating the AD7482 in normal fully powered mode, the
current consumption is 18 mA during conversion and the quies-
cent current is 12 mA. Operating at a throughput rate of 1 MSPS,
the conversion time of 300 ns contributes 27 mW to the overall
power dissipation.
CAPACITIVE
DAC
300 ns/1µs × 5V ×18 mA = 27 mW
(
)
(
)
For the remaining 700 ns of the cycle, the AD7482 dissipates
42 mW of power.
A
V
IN
+
SW1
CONTROL LOGIC
B
700 ns/1µs × 5V ×12 mA = 42 mW
(
)
(
)
–
SW2
COMPARATOR
AGND
Figure 4. ADC Conversion Phase
At the end of conversion, the track-and-hold returns to track mode
and the acquisition time begins. The track-and-hold acquisition
time is 40 ns. Figure 5 shows the ADC during its acquisition
phase. SW2 is closed and SW1 is in Position A. The comparator
is held in a balanced condition and the sampling capacitor
acquires the signal on VIN.
REV. 0
–9–
AD7482
Thus, the power dissipated during each cycle is:
90
85
80
75
70
65
60
27 mW + 42 mW = 69 mW
Figure 7 shows the AD7482 conversion sequence operating in
normal mode.
1 s
CONVST
BUSY
300 ns
700 ns
0
500
1000
1500
2000
2500
3000
Figure 7. Normal Mode Power Dissipation
THROUGHPUT – kSPS
In NAP Mode, almost all the internal circuitry is powered down.
In this mode, the power dissipation of the AD7482 is reduced
to 2.5 mW. When exiting NAP Mode, a minimum of 300 ns
when using an external reference must be waited before initiat-
ing a conversion. This is necessary to allow the internal
circuitry to settle after power-up and for the track-and-hold to
properly acquire the analog input signal. The internal reference
cannot be used in conjunction with the NAP Mode.
Figure 9. Normal Mode, Power vs. Throughput
90
80
70
60
50
40
30
20
10
0
If the AD7482 is put into NAP Mode after each conversion, the
average power dissipation will be reduced, but the throughput rate
will be limited by the power-up time. Using the AD7482 with a
throughput rate of 500 kSPS while placing the part in NAP
Mode after each conversion would result in average power dissi-
pation as follows:
The power-up phase contributes:
0
250
500
750
1000
1250
1500
1750
2000
(300 ns/2 µs)×(5 V ×12 mA) = 9 mW
The conversion phase contributes:
(300 ns/2 µs)×(5 V × 18 mA) = 13.5 mA
THROUGHPUT – kSPS
Figure 10. NAP Mode, Power vs. Throughput
In Standby Mode, all the internal circuitry is powered down and
the power consumption of the AD7482 is reduced to 10 µW. The
power-up time necessary before a conversion can be initiated is
longer because more of the internal circuitry has been powered
down. In using the internal reference of the AD7482, the ADC
must be brought out of Standby Mode 500 ms before a conver-
sion is initiated. Initiating a conversion before the required
power-up time has elapsed will result in incorrect conversion
data. If an external reference source is used and kept powered
up while the AD7482 is in Standby Mode, the power-up time
required will be reduced to 80 s.
While in NAP Mode for the rest of the cycle, the AD7482
dissipates only 1.75 mW of power.
(1400 ns/2 µs)×(5 V × 0.5 mA) = 1.75 mW
Thus, the power dissipated during each cycle is:
9 mW +13.5 mW +1.75 mW = 24.25 mW
Figure 8 shows the AD7482 conversion sequence if putting the
part into NAP Mode after each conversion.
1400ns
600ns
NAP
CONVST
BUSY
300ns
2 s
Figure 8. NAP Mode Power Dissipation
Figures 9 and 10 show a typical graphical representation of
power versus throughput for the AD7482 when in normal and
NAP Modes, respectively.
–10–
REV. 0
AD7482
OFFSET/OVERRANGE
The AD7482 provides a 8% overrange capability as well as a
programmable offset register. The overrange capability is achieved
by the use of a 13th bit (D12) and the CLIP input. If the CLIP
input is at logic high and the contents of the offset register are
zero, then the AD7482 operates as a normal 12-bit ADC. If the
input voltage is greater than the full-scale voltage, the data output
from the ADC will be all “1s.” Similarly, if the input voltage is
lower than the zero-scale voltage, the data output from the ADC
will be all “0s.” In this case, D12 acts as an overrange indicator. It
is set to “1” if the analog input voltage is outside the nominal 0 V
to 2.5 V range.
111...111
111...110
1LSB =V
/4096
REF
111...000
011...111
000...010
000...001
000...000
0.5LSB
–OFFSET
+V
– 1.5LSB
–OFFSET
REF
0V
ANALOG INPUT
Figure 12. Transfer Characteristic with Negative Offset
If the offset register contains any value other than “0,” the
contents of the register are added to the SAR result at the end
of conversion. This has the effect of shifting the transfer function
of the ADC as shown in Figure 11 and Figure 12. However,
it should be noted that with the CLIP input set to logic high,
the maximum and minimum codes that the AD7482 will output
will be 0xFFF and 0x000, respectively. Further details are given
in Table I and Table II.
Table I shows the expected ADC result for a given analog input
voltage with different offset values and with CLIP tied to logic
high. The combined advantages of the offset and overrange
features of the AD7482 are shown clearly in Table II. It shows
the same range of analog input and offset values as Table I but
with the clipping feature disabled.
Table I. Clipping Enabled (CLIP = 1)
Figure 11 shows the effect of writing a positive value to the offset
register. If, for example, the contents of the offset register
contained the value 256, then the value of the analog input
voltage for which the ADC would transition from reading all
“0s” to 000...001 (the bottom reference point) would be:
Offset
VIN
–128
0
+256
ADC DATA, D[0:11]
D12
–200 mV
–155.94 mV
0 V
+78.43 mV
+2.3428 V
+2.5 V
0
0
0
0
0
0
0
128
3838
4095
4095
4095
0
0
1 1 1
1 1 0
1 0 0
0 0 0
0 0 0
0 0 1
0 1 1
1 1 1
256
384
4095
4095
4095
4095
0.5 LSB – 256 LSB = –155.944 mV
(
)
The analog input voltage for which the ADC would read full-
scale (0xFFF) in this example would be:
3710
3967
4095
4095
+2.5772 V
+2.7 V
2.5V – 1.5 LSB – 256 LSB = 2.3428V
(
)
Table II. Clipping Disabled (CLIP = 0)
Offset –128 +256
111...111
111...110
0
111...000
011...111
VIN
ADC DATA, D[0:12]
1LSB =V
/4096
REF
–200 mV
–155.94 mV
0 V
+78.43 mV
+2.3428 V
+2.5 V
–456
–384
–128
0
3710
3968
4095
4552
–328
–256
0
–72
0
+V
REF
– 1.5LSB
000...010
000...001
000...000
256
384
4094
4352
4479
4936
–OFFSET
128
ANALOG INPUT
0V
3838
4096
4223
4680
Figure 11. Transfer Characteristic with Positive Offset
+2.5772 V
+2.7 V
The effect of writing a negative value to the offset register is
shown in Figure 12. If a value of –128 was written to the offset
register, the bottom end reference point would now occur at:
Values from –327 to +327 may be written to the offset register.
These values correspond to an offset of 200 mV. A write to the
offset register is performed by writing a 13-bit word to the part
as detailed in the Parallel Interface section. The 10 LSBs of the
13-bit word contain the offset value, while the 3 MSBs must
be set to “0.” Failure to write zeros to the 3 MSBs may result
in the incorrect operation of the device.
0.5 LSB – –128 LSB = 78.43 mV
(
)
Following this, the analog input voltage needed to produce a
full-scale (0xFFF) result from the ADC would now be:
2.5V – 1.5 LSB – –128 LSB = 2.5772V
(
)
REV. 0
–11–
AD7482
PARALLEL INTERFACE
The AD7482 features two parallel interfacing modes. These
modes are selected by the mode pins as detailed in Table III.
The data lines D0 to D12 leave their high impedance state when
both the CS and RD are logic low. Therefore, CS may be perma-
nently tied logic low if required, and the RD signal may be used to
access the conversion result. Figure 15 shows a timing specification
called tQUIET. This is the amount of time that should be left after
any databus activity before the next conversion is initiated.
Table III. Operating Modes
Mode 2
Mode 1
Writing to the AD7482
Do Not Use
0
0
1
1
0
1
0
1
The AD7482 features a user-accessible offset register. This allows
the bottom of the transfer function to be shifted by 200 mV.
This feature is explained in more detail in the Offset/Overrange
section.
Parallel Mode 1
Parallel Mode 2
Do Not Use
To write to the offset register, a 13-bit word is written to the
AD7482 with the 10 LSBs containing the offset value in two’s
complement format. The 3 MSBs must be set to “0.” The offset
value must be within the range –327 to +327, corresponding to an
offset from –200 mV to +200 mV. The value written to the offset
register is stored and used until power is removed from the device,
or the device is reset. The value stored may be updated at any
time between conversions by another write to the device. Table IV
shows some examples of offset register values and their effective
offset voltage. Figure 16 shows a timing diagram for writing to
the AD7482.
In Parallel Mode 1, the data in the output register is updated on
the rising edge of BUSY at the end of a conversion and is avail-
able for reading almost immediately afterward. Using this mode,
throughput rates of up to 2.5 MSPS can be achieved. This
mode should be used if the conversion data is required immedi-
ately after the conversion has completed. An example where this
may be of use is if the AD7482 was operating at much lower
throughput rates in conjunction with the NAP Mode (for
power-saving reasons), and the input signal was being compared
with set limits within the DSP or other controller. If the limits
were exceeded, the ADC would then be brought immediately
into full power operation and commence sampling at full speed.
Figure 17 shows a timing diagram for the AD7482 operating in
Parallel Mode 1 with both CS and RD tied low.
Table IV. Offset Register Examples
D9–D0
(Two’s
Offset
(mV)
In Parallel Mode 2, the data in the output register is not updated
until the next falling edge of CONVST. This mode could be used
where a single sample delay is not vital to the system operation
and conversion speeds of greater than 2.5 MSPS are desired.
This may occur, for example, in a system where a large amount
of samples are taken at high speed before a Fast Fourier Trans-
form is performed for frequency analysis of the input signal.
Figure 18 shows a timing diagram for the AD7482 operating in
Parallel Mode 2 with both CS and RD tied low.
Code (Dec)
D12–D10
Complement)
–327
–128
+64
000
000
000
000
1010111001
1110000000
0001000000
0101000111
–200
–78.12
+39.06
+200
+327
Driving the CONVST Pin
To achieve the specified performance from the AD7482, the
CONVST Pin must be driven from a low jitter source. Since the
falling edge on the CONVST Pin determines the sampling instant,
any jitter that may exist on this edge will appear as noise when
the analog input signal contains high frequency components. The
relationship between the analog input frequency (fIN), timing
jitter (tj), and resulting SNR is given by the equation:
Data must not be read from the AD7482 while a conversion is
taking place. For this reason, if operating the AD7482 at
throughput speeds greater than 2.5 MSPS, it will be necessary
to tie both CS and RD Pins on the AD7482 low and use a
buffer on the data lines. This situation may also arise in the case
where a read operation cannot be completed in the time after
the end of one conversion and the start of the quiet period before
the next conversion.
1
SNRJITTER (dB) = 10log
(2π × fIN × tj )2
The maximum slew rate at the input of the ADC should be
limited to 500 V/s while BUSY is low to avoid corrupting the
ongoing conversion. In any multiplexed application where the
channel is switched during conversion, this should happen as
early as possible after the BUSY falling edge.
As an example, if the desired SNR due to jitter was 100 dB with a
maximum full-scale analog input frequency of 1.5 MHz, ignor-
ing all other noise sources, the result is an allowable jitter on the
CONVST falling edge of 1.06 ps. For a 12-bit converter (ideal
SNR = 74 dB), the allowable jitter will be greater than the figure
given above, but due consideration must be given to the design
of the CONVST circuitry to achieve 12-bit performance with
large analog input frequencies.
Reading Data from the AD7482
Data is read from the part via a 13-bit parallel databus with the
standard CS and RD signals. The CS and RD signals are inter-
nally gated to enable the conversion result onto the databus.
–12–
REV. 0
AD7482
Typical Connection
Figures 14a to 14e show a sample layout of the board area
immediately surrounding the AD7482. Pin 1 is the bottom left
corner of the device. Figure 14a shows the top layer where the
AD7482 is mounted with vias to the bottom routing layer high-
lighted. Figure 14b shows the bottom layer where the power
routing is with the same vias highlighted. Figure 14c shows the
bottom layer silkscreen where the decoupling components are
soldered directly beneath the device. Figure 14d shows the
silkscreen overlaid on the solder pads for the decoupling compo-
nents, and Figure 14e shows the top and bottom routing layers
overlaid. The black area in each figure indicates the ground
plane present on the middle layer.
Figure 13 shows a typical connection diagram for the AD7482
operating in Parallel Mode 1. Conversion is initiated by a falling
edge on CONVST. Once CONVST goes low, the BUSY signal
goes low, and at the end of conversion, the rising edge of BUSY
is used to activate an interrupt service routine. The CS and RD
lines are then activated to read the 12 data bits (13 bits if using
the overrange feature).
In Figure 13, the VDRIVE Pin is tied to DVDD, which results in logic
output levels being either 0 V or DVDD. The voltage applied
to VDRIVE controls the voltage value of the output logic signals.
For example, if DVDD is supplied by a 5 V supply and VDRIVE by
a 3 V supply, the logic output levels would be either 0 V or 3 V.
This feature allows the AD7482 to interface to 3 V devices, while
still enabling the ADC to process signals at a 5 V supply.
DIGITAL
SUPPLY
4.75V–5.25V
ANALOG
SUPPLY
4.75V–5.25V
+
+
10F
1nF
0.1F
0.1F
47F
0.1F
V
DV AV
DD DD
DRIVE
C
ADM809
RESET
MODE1
MODE2
WRITE
CLIP
BIAS
Figure 14a
Figure 14b
1nF
REFSEL
REFIN
AD780 2.5V
REFERENCE
NAP
0.47F
0.47F
STBY
AD7482
PARALLEL
INTERFACE
D0–D12
REFOUT
C/P
CS
CONVST
RD
VIN
0V TO 2.5V
BUSY
Figure 13. Typical Connection Diagram
Figure 14c
Figure 14d
Board Layout and Grounding
To obtain optimum performance from the AD7482, it is recom-
mended that a printed circuit board with a minimum of three
layers be used. One of these layers, preferably the middle layer,
should be as complete a ground plane as possible to give the
best shielding. The board should be designed in such a way that
the analog and digital circuitry is separated and confined to
certain areas of the board. This practice, along with avoiding
running digital and analog lines close together, should help to
avoid coupling digital noise onto analog lines.
Figure 14e
The power supply lines to the AD7482 should be approxi-
mately 3 mm wide to provide low impedance paths and
reduce the effects of glitches on the power supply lines. It is
vital that good decoupling also be present. A combination of
ferrites and decoupling capacitors should be used as shown in
Figure 13. The decoupling capacitors should be as close to the
supply pins as possible. This is made easier by the use of multi-
layer boards. The signal traces from the AD7482 pins can be
run on the top layer, while the decoupling capacitors and
ferrites can be mounted on the bottom layer where the power
traces exist. The ground plane between the top and bottom
planes provide excellent shielding.
C1–6: 100 nF, C7–8: 470 nF, C9: 1 nF
L1–4: Meggit-Sigma Chip Ferrite Beads (BMB2A0600RS2)
REV. 0
–13–
AD7482
tCONV
tACQ
t1
tQUIET
CONVST
t2
BUSY
t14
WRITE
t15
t8
t3
RD
t7
t4
D[12:0]
DATA VALID
Figure 15. Parallel Mode READ Cycle
CONVST
t12
t13
CS
RD
t9
WRITE
D[12:0]
t10
t11
OFFSET DATA
Figure 16. Parallel Mode WRITE Cycle
–14–
REV. 0
AD7482
tCONV
t1
CONVST
BUSY
N
N+1
t2
t6
DATA N–1
DATA N
D[12:0]
Figure 17. Parallel Mode 1 READ Cycle
tCONV
t1
CONVST
BUSY
N
N+1
t2
t5
D[12:0]
DATA N–1
DATA N
Figure 18. Parallel Mode 2 READ Cycle
REV. 0
–15–
AD7482
OUTLINE DIMENSIONS
48-Lead Plastic Quad Flatpack [LQFP]
(ST-48)
Dimensions shown in millimeters
1.60 MAX
PIN 1
INDICATOR
0.75
0.60
0.45
9.00 BSC SQ
37
48
36
1
SEATING
PLANE
1.45
1.40
1.35
7.00
BSC
SQ
0.20
0.09
TOP VIEW
(PINS DOWN)
VIEW A
7؇
3.5؇
0؇
0.15
0.05
25
12
24
0.08 MAX
COPLANARITY
13
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90؇ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
–16–
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