AD624B [ADI]
Precision Instrumentation Amplifier; 精密仪表放大器器
| 型号： | AD624B |
| 厂家： | 
ADI |
| 描述： | Precision Instrumentation Amplifier |
| 文件： | 总15页 (文件大小：694K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision
Instrumentation Amplifier
a
AD624
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Low Noise: 0.2 V p-p 0.1 Hz to 10 Hz
Low Gain TC: 5 ppm max (G = 1)
50⍀
–INPUT
G = 100
Low Nonlinearity: 0.001% max (G = 1 to 200)
High CMRR: 130 dB min (G = 500 to 1000)
Low Input Offset Voltage: 25 V, max
Low Input Offset Voltage Drift: 0.25 V/؇C max
Gain Bandwidth Product: 25 MHz
Pin Programmable Gains of 1, 100, 200, 500, 1000
No External Components Required
Internally Compensated
AD624
225.3⍀
4445.7⍀
G = 200
G = 500
124⍀
V
10k⍀
B
SENSE
80.2⍀
20k⍀
20k⍀
10k⍀
10k⍀
RG
1
OUTPUT
REF
RG
2
10k⍀
50⍀
+INPUT
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD624 is a high precision, low noise, instrumentation
amplifier designed primarily for use with low level transducers,
including load cells, strain gauges and pressure transducers. An
outstanding combination of low noise, high gain accuracy, low
gain temperature coefficient and high linearity make the AD624
ideal for use in high resolution data acquisition systems.
1. The AD624 offers outstanding noise performance. Input
noise is typically less than 4 nV/√Hz at 1 kHz.
2. The AD624 is a functionally complete instrumentation am-
plifier. Pin programmable gains of 1, 100, 200, 500 and 1000
are provided on the chip. Other gains are achieved through
the use of a single external resistor.
The AD624C has an input offset voltage drift of less than
0.25 µV/°C, output offset voltage drift of less than 10 µV/°C,
CMRR above 80 dB at unity gain (130 dB at G = 500) and a
maximum nonlinearity of 0.001% at G = 1. In addition to these
outstanding dc specifications, the AD624 exhibits superior ac
performance as well. A 25 MHz gain bandwidth product, 5 V/µs
slew rate and 15 µs settling time permit the use of the AD624 in
high speed data acquisition applications.
3. The offset voltage, offset voltage drift, gain accuracy and gain
temperature coefficients are guaranteed for all pretrimmed
gains.
4. The AD624 provides totally independent input and output
offset nulling terminals for high precision applications.
This minimizes the effect of offset voltage in gain ranging
applications.
5. A sense terminal is provided to enable the user to minimize
the errors induced through long leads. A reference terminal is
also provided to permit level shifting at the output.
The AD624 does not need any external components for pre-
trimmed gains of 1, 100, 200, 500 and 1000. Additional gains
such as 250 and 333 can be programmed within one percent
accuracy with external jumpers. A single external resistor can
also be used to set the 624’s gain to any value in the range of 1
to 10,000.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(@ V = ؎15 V, R = 2 k⍀ and T = +25؇C, unless otherwise noted)
AD624–SPECIFICATIONS
S
L
A
Model
AD624A
Typ
AD624B
Typ
AD624C
Typ
AD624S
Typ
Min
Max
Min
Max
Min
Max
Min
Max
Units
GAIN
Gain Equation
(External Resistor Gain
Programming)
40,000
40,000
40,000
40,000
+ 1 ± 20%
+ 1 ± 20%
+ 1 ± 20%
+ 1 ± 20%
RG
RG
RG
RG
Gain Range (Pin Programmable)
Gain Error
1 to 1000
1 to 1000
1 to 1000
1 to 1000
G = 1
G = 100
±
±
±
0.05
0.25
0.5
±
±
±
0.03
0.15
0.35
±
±
±
0.02
0.1
0.25
±
±
±
0.05
0.25
0.5
%
%
%
G = 200, 500
Nonlinearity
G = 1
G = 100, 200
G = 500
±0.005
±0.005
±0.005
±0.003
±0.003
±0.005
±0.001
±0.001
±0.005
±0.005
±0.005
±0.005
%
%
%
Gain vs. Temperature
G = 1
G = 100, 200
G = 500
5
10
25
5
10
15
5
10
15
5
10
15
ppm/°C
ppm/°C
ppm/°C
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage
vs. Temperature
200
2
5
75
0.5
3
25
0.25
2
75
2.0
3
µV
µV/°C
mV
Output Offset Voltage
vs. Temperature
50
25
10
50
µV/°C
OOffUsTet Referred to the Input vs. Supply
G = 1
70
95
100
75
105
110
80
110
115
75
105
110
dB
dB
dB
G = 100, 200
G = 500
INPUT CURRENT
Input Bias Current
vs. Temperature
Input Offset Current
vs. Temperature
±
±
50
35
±
±
25
15
±
±
15
10
±
±
50
35
nA
pA/°C
nA
±50
±20
±50
±20
±50
±20
±50
±20
pA/°C
INPUT
Input Impedance
Differential Resistance
Differential Capacitance
Common-Mode Resistance
Common-Mode Capacitance
Input Voltage Range1
109
10
109
10
109
10
109
10
Ω
pF
Ω
109
10
109
10
109
10
109
10
pF
Max Differ. Input Linear (VDL
)
±10
±10
±10
±10
V
V
G
2
G
2
G
2
G
2
12 V −
× VD
12 V −
× VD
12 V −
× VD
12 V −
× VD
Max Common-Mode Linear (VCM
Common-Mode Rejection dc
)
to 60 Hz with 1 kΩ Source Imbalance
G = 1
G = 100, 200
G = 500
70
100
110
75
105
120
80
110
130
70
100
110
dB
dB
dB
OUTPUT RATING
V
, RL = 2 kΩ
±10
±10
±10
±10
V
DYNAMIC RESPONSE
Small Signal –3 dB
G = 1
1
1
1
1
MHz
kHz
kHz
kHz
kHz
V/µs
G = 100
G = 200
G = 500
G = 1000
150
100
50
25
5.0
150
100
50
25
5.0
150
100
50
25
5.0
150
100
50
25
5.0
Slew Rate
Settling Time to 0.01%, 20 V Step
G = 1 to 200
G = 500
15
35
75
15
35
75
15
35
75
15
35
75
µs
µs
µs
G = 1000
NOISE
Voltage Noise, 1 kHz
R.T.I.
R.T.O.
4
75
4
75
4
75
4
75
nV/√Hz
nV/√Hz
R.T.I., 0.1 Hz to 10 Hz
G = 1
G = 100
G = 200, 500, 1000
Current Noise
0.1 Hz to 10 Hz
10
0.3
0.2
10
0.3
0.2
10
0.3
0.2
10
0.3
0.2
µV p-p
µV p-p
µV p-p
60
60
60
60
pA p-p
SENSE INPUT
RIN
IIN
8
10
30
12
8
10
30
12
8
10
30
12
8
10
30
12
kΩ
µA
V
Voltage Range
±10
±10
±10
±10
Gain to Output
1
1
1
1
%
–2–
REV. C
AD624
Model
AD624A
Typ
AD624B
Typ
AD624C
Typ
AD624S
Typ
Min
Max
Min
Max
Min
Max
Min
Max
Units
REFERENCE INPUT
RIN
IIN
16
20
30
24
16
20
30
24
16
20
30
24
16
20
30
24
kΩ
µA
V
Voltage Range
±10
±10
±10
±10
Gain to Output
1
1
1
1
%
TEMPERATURE RANGE
Specified Performance
Storage
–25
–65
+85
+150
–25
–65
+85
+150
–25
–65
+85
+150
–55
–65
+125
+150
°C
°C
POWER SUPPLY
Power Supply Range
Quiescent Current
؎
6
؎
3.5
15
؎
5
18
؎
6
؎
3.5
15
؎
5
18
؎
6
؎
3.5
15
؎
5
18
؎
6
؎
3.5
15
؎
5
18
V
mA
NOTES
1VDL is the maximum differential input voltage at G = 1 for specified nonlinearity, VDL at other gains = 10 V/G. VD = actual differential input voltage.
1Example: G = 10, VD = 0.50. VCM = 12 V – (10/2 × 0.50 V) = 9.5 V.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production unit at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ABSOLUTE MAXIMUM RATINGS*
CONNECTION DIAGRAM
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 420 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD624A/B/C . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
AD624S . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature (Soldering, 60 secs) . . . . . . . . . . . . +300°C
–INPUT
+INPUT
RG
1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUTPUT NULL
OUTPUT NULL
G = 100
RG
2
AD624
TOP VIEW
(Not to Scale)
INPUT NULL
INPUT NULL
REF
SHORT TO
RG FOR
2
DESIRED
GAIN
G = 200
G = 500
SENSE
OUTPUT
–V
S
+V
S
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
FOR GAINS OF 1000 SHORT RG TO PIN 12
1
AND PINS 11 AND 13 TO RG
2
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions
Dimensions shown in inches and (mm).
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD624AD
AD624BD
AD624CD
AD624SD
–25°C to +85°C 16-Lead Ceramic DIP D-16
–25°C to +85°C 16-Lead Ceramic DIP D-16
–25°C to +85°C 16-Lead Ceramic DIP D-16
–55°C to +125°C 16-Lead Ceramic DIP D-16
AD624SD/883B* –55°C to +125°C 16-Lead Ceramic DIP D-16
AD624AChips
AD624SChips
–25°C to +85°C Die
–25°C to +85°C Die
*See Analog Devices’ military data sheet for 883B specifications.
REV. C
–3–
AD624–Typical Characteristics
20
30
20
15
10
5
15
10
5
20
10
0
+25؇C
0
0
0
10
100
1k
10k
0
5
10
15
20
5
10
15
20
SUPPLY VOLTAGE – ؎V
LOAD RESISTANCE – ⍀
SUPPLY VOLTAGE – ؎V
Figure 1. Input Voltage Range vs.
Supply Voltage, G = 1
Figure 3. Output Voltage Swing vs.
Load Resistance
Figure 2. Output Voltage Swing vs.
Supply Voltage
40
30
8.0
16
14
12
10
8
20
6.0
4.0
10
0
–10
–20
–30
–40
6
2.0
0
4
2
0
–125
–75
–25
25
75
125
0
5
10
15
20
0
5
10
15
20
SUPPLY VOLTAGE – ؎V
TEMPERATURE – ؇C
SUPPLY VOLTAGE – ؎V
Figure 4. Quiescent Current vs.
Supply Voltage
Figure 6. Input Bias Current vs.
Temperature
Figure 5. Input Bias Current vs.
Supply Voltage
16
14
–1
0
12
10
8
1
500
2
3
4
5
6
7
100
10
6
1
4
2
0
0
1
10
100
1k
10k 100k 1M 10M
0
5
10
15
20
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
WARM-UP TIME – Minutes
FREQUENCY – Hz
INPUT VOLTAGE – ؎V
Figure 9. Gain vs. Frequency
Figure 8. Offset Voltage, RTI, Turn
On Drift
Figure 7. Input Bias Current vs. CMV
REV. C
–4–
AD624
–140
–120
–100
–80
–60
–40
–20
0
30
160
140
120
100
80
G = 500
G = 100
–V = –15V dc+
S
1V p-p SINEWAVE
G = 500
20
10
0
G = 1
G = 1, 100
G = 100
G = 500
G = 100
60
-
G = 1000
40
G = 1
20
BANDWIDTH LIMITED
100k 1M
0
10
1
10
100
1k
10k 100k 1M 10M
1k
10k
100
1k
FREQUENCY – Hz
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
Figure 11. Large Signal Frequency
Response
Figure 12. Positive PSRR vs.
Frequency
Figure 10. CMRR vs. Frequency RTI,
Zero to 1k Source Imbalance
1000
160
100k
–V = –15V dc+
S
1V p-p SINEWAVE
140
120
100
80
G = 500
100
G = 1
10k
G = 10
10
1000
G = 100
G = 1
G = 100, 1000
60
G = 1000
1
40
100
10
20
0.1
0
10
1
10
100
1k
10k
100k
100
1k
10k
100k
0.1
1
10
100
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
Figure 13. Negative PSRR vs.
Frequency
Figure 14. RTI Noise Spectral
Density vs. Gain
Figure 15. Input Current Noise
–12 TO 12
–8 TO 8
1%
0.1%
0.01%
–4 TO 4
OUTPUT
STEP –V
4 TO –4
8 TO –8
1%
0.1%
0.01%
12 TO –12
0
5
10
15
20
SETTLING TIME – s
Figure 16. Low Frequency Voltage
Noise, G = 1 (System Gain = 1000)
Figure 17. Low Frequency Voltage
Noise, G = 1000 (System Gain =
100,000)
Figure 18. Settling Time, Gain = 1
REV. C
–5–
AD624
–12 TO 12
–8 TO 8
0.1%
1%
0.01%
–4 TO 4
OUTPUT
STEP –V
4 TO –4
8 TO –8
0.01%
15
1%
0.1%
10
12 TO –12
0
5
20
SETTLING TIME – s
Figure 19. Large Signal Pulse
Response and Settling Time, G = 1
Figure 20. Settling Time Gain = 100
Figure 21. Large Signal Pulse
Response and Settling Time,
G = 100
–12 TO 12
–8 TO 8
1%
0.1%
0.01%
–4 TO 4
OUTPUT
STEP –V
4 TO –4
8 TO –8
0.01%
0.1%
1%
12 TO –12
0
5
10
15
20
SETTLING TIME – s
Figure 22. Range Signal Pulse
Response and Settling Time,
G = 500
Figure 23. Settling Time Gain = 1000
Figure 24. Large Signal Pulse
Response and Settling Time,
G = 1000
REV. C
–6–
AD624
10k⍀
1%
1k⍀
10T
10k⍀
1%
V
+V
OUT
S
INPUT
20V p-p
100k⍀
1%
RG
1
G = 100
G = 200
G = 500
AD624
1k⍀
0.1%
500⍀ 200⍀
0.1% 0.1%
RG
2
–V
S
Figure 25. Settling Time Test Circuit
THEORY OF OPERATION
The AD524 should be considered in applications that require
protection from severe input overload. If this is not possible,
external protection resistors can be put in series with the inputs
of the AD624 to augment the internal (50 Ω) protection resis-
tors. This will most seriously degrade the noise performance.
For this reason the value of these resistors should be chosen to
be as low as possible and still provide 10 mA of current limiting
under maximum continuous overload conditions. In selecting
the value of these resistors, the internal gain setting resistor and
the 1.2 volt drop need to be considered. For example, to pro-
tect the device from a continuous differential overload of 20 V
at a gain of 100, 1.9 kΩ of resistance is required. The internal
gain resistor is 404 Ω; the internal protect resistor is 100 Ω.
There is a 1.2 V drop across D1 or D2 and the base-emitter
junction of either Q1 and Q3 or Q2 and Q4 as shown in Figure
27, 1400 Ω of external resistance would be required (700 Ω in
series with each input). The RTI noise in this case would be
The AD624 is a monolithic instrumentation amplifier based on
a modification of the classic three-op-amp instrumentation
amplifier. Monolithic construction and laser-wafer-trimming
allow the tight matching and tracking of circuit components and
the high level of performance that this circuit architecture is ca-
pable of.
A preamp section (Q1–Q4) develops the programmed gain by
the use of feedback concepts. Feedback from the outputs of A1
and A2 forces the collector currents of Q1–Q4 to be constant
thereby impressing the input voltage across RG.
The gain is set by choosing the value of RG from the equation,
40 k
RG
Gain =
+ 1. The value of RG also sets the transconduct-
ance of the input preamp stage increasing it asymptotically to
the transconductance of the input transistors as RG is reduced
for larger gains. This has three important advantages. First, this
approach allows the circuit to achieve a very high open loop gain
of 3 × 108 at a programmed gain of 1000 thus reducing gain
related errors to a negligible 3 ppm. Second, the gain bandwidth
product which is determined by C3 or C4 and the input trans-
conductance, reaches 25 MHz. Third, the input voltage noise
reduces to a value determined by the collector current of the
input transistors for an RTI noise of 4 nV/√Hz at G ≥ 500.
4 KTRext +(4 nV / Hz)2 = 6.2 nV / Hz
+V
S
I2
50A
I1
50A
R52
10k⍀
VB
SENSE
A1
A2
C3
C4
R53
10k⍀
+V
S
A3
V
O
R57
50⍀
–IN
20k⍀
Q2,
Q4
R54
R56
Q1, Q3
+V
S
10k⍀
20k⍀
RG
RG
1
2
R55
10k⍀
100
16.2k⍀
80.2⍀
124⍀
200
13
50A
REF
+IN
AD624
1F
500
200
100
I4
50A
1/2
AD712
500
RG
1/2
1F
G500
2
50⍀
4445⍀
AD712
9.09k⍀
225.3⍀
16.2k⍀
G1, 100, 200
1k⍀
100⍀
1F
–V
S
–V
S
–V
S
1.62M⍀
1.82k⍀
Figure 27. Simplified Circuit of Amplifier; Gain Is Defined
as (R56 + R57)/(RG) + 1. For a Gain of 1, RG Is an Open
Circuit.
Figure 26. Noise Test Circuit
INPUT CONSIDERATIONS
INPUT OFFSET AND OUTPUT OFFSET
Under input overload conditions the user will see RG + 100 Ω
and two diode drops (~1.2 V) between the plus and minus
inputs, in either direction. If safe overload current under all
conditions is assumed to be 10 mA, the maximum overload
voltage is ~ ±2.5 V. While the AD624 can withstand this con-
tinuously, momentary overloads of ±10 V will not harm the
device. On the other hand the inputs should never exceed the
supply voltage.
Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may
be adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an autozero cycle, but there are many small-
signal high-gain applications that don’t have this capability.
Voltage offset and offset drift each have two components; input
and output. Input offset is that component of offset that is
REV. C
–7–
AD624
directly proportional to gain i.e., input offset as measured at
the output at G = 100 is 100 times greater than at G = 1.
Output offset is independent of gain. At low gains, output offset
drift is dominant, while at high gains input offset drift domi-
nates. Therefore, the output offset voltage drift is normally
specified as drift at G = 1 (where input effects are insignificant),
while input offset voltage drift is given by drift specification at a
high gain (where output offset effects are negligible). All input-
related numbers are referred to the input (RTI) which is to say
that the effect on the output is “G” times larger. Voltage offset
vs. power supply is also specified at one or more gain settings
and is also RTI.
Table I.
Temperature
Gain
(Nominal)
Coefficient
(Nominal)
Pin 3
to Pin
Connect Pins
1
–0 ppm/°C
–1.5 ppm/°C
–5 ppm/°C
–5.5 ppm/°C
–6.5 ppm/°C
–3.5 ppm/°C
–5.5 ppm/°C
–15 ppm/°C
–0.5 ppm/°C
–10 ppm/°C
–5 ppm/°C
–1.5 ppm/°C
+4 ppm/°C
0 ppm/°C
–
–
–
100
125
137
186.5
200
250
333
375
500
624
688
831
1000
13
13
13
13
12
12
12
12
11
11
11
11
11
11 to 16
11 to 12
11 to 12 to 16
–
11 to 13
11 to 16
13 to 16
–
13 to 16
11 to 12; 13 to 16
16 to 12
16 to 12; 13 to 11
By separating these errors, one can evaluate the total error inde-
pendent of the gain setting used. In a given gain configura-
tion both errors can be combined to give a total error referred to
the input (R.T.I.) or output (R.T.O.) by the following formula:
Total Error R.T.I. = input error + (output error/gain)
Total Error R.T.O. = (Gain × input error) + output error
As an illustration, a typical AD624 might have a +250 µV out-
put offset and a –50 µV input offset. In a unity gain configura-
tion, the total output offset would be 200 µV or the sum of the
two. At a gain of 100, the output offset would be –4.75 mV
or: +250 µV + 100 (–50 µV) = –4.75 mV.
Pins 3 and 16 programs the gain according to the formula
40k
G −1
RG
=
(see Figure 29). For best results RG should be a precision resis-
tor with a low temperature coefficient. An external RG affects both
gain accuracy and gain drift due to the mismatch between it and
the internal thin-film resistors R56 and R57. Gain accuracy is
determined by the tolerance of the external RG and the absolute
accuracy of the internal resistors (±20%). Gain drift is determined
by the mismatch of the temperature coefficient of RG and the tem-
perature coefficient of the internal resistors (–15 ppm/°C typ),
and the temperature coefficient of the internal interconnections.
The AD624 provides for both input and output offset adjust-
ment. This optimizes nulling in very high precision applications
and minimizes offset voltage effects in switched gain applica-
tions. In such applications the input offset is adjusted first at the
highest programmed gain, then the output offset is adjusted at
G = 1.
GAIN
+V
S
The AD624 includes high accuracy pretrimmed internal
gain resistors. These allow for single connection program-
ming of gains of 1, 100, 200 and 500. Additionally, a variety
of gains including a pretrimmed gain of 1000 can be achieved
through series and parallel combinations of the internal resis-
tors. Table I shows the available gains and the appropriate
pin connections and gain temperature coefficients.
–INPUT
RG
1
1.5k⍀
1k⍀
V
AD624
OUT
2.105k⍀
OR
RG
2
REFERENCE
+INPUT
40.000
2.105
G =
+ 1 = 20 ؎20%
–V
S
The gain values achieved via the combination of internal
resistors are extremely useful. The temperature coefficient of the
gain is dependent primarily on the mismatch of the temperature
coefficients of the various internal resistors. Tracking of these
resistors is extremely tight resulting in the low gain TCs shown
in Table I.
Figure 29. Operating Connections for G = 20
The AD624 may also be configured to provide gain in the out-
put stage. Figure 30 shows an H pad attenuator connected to
the reference and sense lines of the AD624. The values of R1,
R2 and R3 should be selected to be as low as possible to mini-
mize the gain variation and reduction of CMRR. Varying R2
will precisely set the gain without affecting CMRR. CMRR is
determined by the match of R1 and R3.
If the desired value of gain is not attainable using the inter-
nal resistors, a single external resistor can be used to achieve
any gain between 1 and 10,000. This resistor connected between
+V
S
INPUT
+V
S
R1
6k⍀
OFFSET
–INPUT
10k⍀ NULL
–INPUT
RG
1
RG
1
R2
5k⍀
G = 100
G = 200
G = 100
G = 200
V
AD624
OUT
V
OUT
AD624
R
G = 500
L
G = 500
RG
OUTPUT
SIGNAL
COMMON
RG
2
2
+INPUT
R3
6k⍀
+INPUT
–V
S
–V
S
(R ||20k⍀) + R + R )
2
1
3
G =
Figure 28. Operating Connections for G = 200
(R ||20k⍀)
(R + R + R ) || R
L
2k⍀
2
1
2
3
Figure 30. Gain of 2500
REV. C
–8–
AD624
+V
S
NOISE
The AD624 is designed to provide noise performance near the
theoretical noise floor. This is an extremely important design
criteria as the front end noise of an instrumentation amplifier is
the ultimate limitation on the resolution of the data acquisition
system it is being used in. There are two sources of noise in an
instrument amplifier, the input noise, predominantly generated
by the differential input stage, and the output noise, generated
by the output amplifier. Both of these components are present
at the input (and output) of the instrumentation amplifier. At
the input, the input noise will appear unaltered; the output
noise will be attenuated by the closed loop gain (at the output,
the output noise will be unaltered; the input noise will be ampli-
fied by the closed loop gain). Those two noise sources must be
root sum squared to determine the total noise level expected at
the input (or output).
AD624
LOAD
TO
–V
S
POWER
SUPPLY
GROUND
c. AC-Coupled
Figure 31. Indirect Ground Returns for Bias Currents
Although instrumentation amplifiers have differential inputs,
there must be a return path for the bias currents. If this is not
provided, those currents will charge stray capacitances, causing
the output to drift uncontrollably or to saturate. Therefore,
when amplifying “floating” input sources such as transformers
and thermocouples, as well as ac-coupled sources, there must
still be a dc path from each input to ground, (see Figure 31).
The low frequency (0.1 Hz to 10 Hz) voltage noise due to the
output stage is 10 µV p-p, the contribution of the input stage is
0.2 µV p-p. At a gain of 10, the RTI voltage noise would be
2
2
)
10
G
+ 0.2
(
1 µV p-p,
. The RTO voltage noise would be
COMMON-MODE REJECTION
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed by equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance. “Common-Mode
Rejection Ratio” (CMRR) is a ratio expression while “Common-
Mode Rejection” (CMR) is the logarithm of that ratio. For
example, a CMRR of 10,000 corresponds to a CMR of 80 dB.
2
)
102 + 0.2 G
10.2 µV p-p,
. These calculations hold for
(
)
(
applications using either internal or external gain resistors.
INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the input
transistors of a dc amplifier. Bias currents are an additional
source of input error and must be considered in a total error
budget. The bias currents when multiplied by the source resis-
tance imbalance appear as an additional offset voltage. (What is
of concern in calculating bias current errors is the change in bias
current with respect to signal voltage and temperature.) Input
offset current is the difference between the two input bias cur-
rents. The effect of offset current is an input offset voltage whose
magnitude is the offset current times the source resistance.
In an instrumentation amplifier, ac common-mode rejection is
only as good as the differential phase shift. Degradation of ac
common-mode rejection is caused by unequal drops across
differing track resistances and a differential phase shift due to
varied stray capacitances or cable capacitances. In many appli-
cations shielded cables are used to minimize noise. This tech-
nique can create common-mode rejection errors unless the
shield is properly driven. Figures 32 and 33 shows active data
guards which are configured to improve ac common-mode
rejection by “bootstrapping” the capacitances of the input
cabling, thus minimizing differential phase shift.
+V
S
+V
S
–INPUT
G = 200
AD624
LOAD
100⍀
AD711
V
AD624
OUT
RG
2
TO
–V
S
POWER
SUPPLY
GROUND
REFERENCE
+INPUT
–V
S
a. Transformer Coupled
Figure 32. Shield Driver, G ≥ 100
+V
S
+V
S
–INPUT
RG
1
AD712
100⍀
100⍀
AD624
V
AD624
OUT
LOAD
RG
–V
S
2
REFERENCE
+INPUT
TO
–V
S
POWER
SUPPLY
GROUND
–V
S
Figure 33. Differential Shield Driver
b. Thermocouple
REV. C
–9–
AD624
GROUNDING
“inside the loop” of an instrumentation amplifier to provide the
required current without significantly degrading overall perfor-
mance. The effects of nonlinearities, offset and gain inaccuracies
of the buffer are reduced by the loop gain of the IA output
amplifier. Offset drift of the buffer is similarly reduced.
Many data-acquisition components have two or more ground
pins which are not connected together within the device. These
grounds must be tied together at one point, usually at the sys-
tem power supply ground. Ideally, a single solid ground would
be desirable. However, since current flows through the ground
wires and etch stripes of the circuit cards, and since these paths
have resistance and inductance, hundreds of millivolts can be
generated between the system ground point and the data acqui-
sition components. Separate ground returns should be provided
to minimize the current flow in the path from the most sensitive
points to the system ground point. In this way supply currents
and logic-gate return currents are not summed into the same
return path as analog signals where they would cause measure-
ment errors (see Figure 34).
REFERENCE TERMINAL
The reference terminal may be used to offset the output by up
to ±10 V. This is useful when the load is “floating” or does not
share a ground with the rest of the system. It also provides a
direct means of injecting a precise offset. It must be remem-
bered that the total output swing is ±10 volts, from ground, to
be shared between signal and reference offset.
+V
S
SENSE
V
+
IN
IN
ANALOG P.S.
+15V –15V
DIGITAL P.S.
+5V
C
C
AD624
LOAD
REF
V
–
0.1 0.1
F F
0.1 0.1
F F
1F
1F
1F
–V
S
V
OFFSET
AD711
DIG
COM
+
DIGITAL
DATA
OUTPUT
Figure 36. Use of Reference Terminal to Provide Output
Offset
AD583
SAMPLE
AND HOLD
AD624
AD574A
ANALOG
GROUND*
SIGNAL
GROUND
When the IA is of the three-amplifier configuration it is neces-
sary that nearly zero impedance be presented to the reference
terminal. Any significant resistance, including those caused by
PC layouts or other connection techniques, which appears
between the reference pin and ground will increase the gain of
the noninverting signal path, thereby upsetting the common-
mode rejection of the IA. Inadvertent thermocouple connections
created in the sense and reference lines should also be avoided
as they will directly affect the output offset voltage and output
offset voltage drift.
OUTPUT
REFERENCE
*IF INDEPENDENT, OTHERWISE RETURN AMPLIFIER REFERENCE
TO MECCA AT ANALOG P.S. COMMON
Figure 34. Basic Grounding Practice
Since the output voltage is developed with respect to the poten-
tial on the reference terminal an instrumentation amplifier can
solve many grounding problems.
SENSE TERMINAL
The sense terminal is the feedback point for the instrument
amplifier’s output amplifier. Normally it is connected to the
instrument amplifier output. If heavy load currents are to be
drawn through long leads, voltage drops due to current flowing
through lead resistance can cause errors. The sense terminal can
be wired to the instrument amplifier at the load thus putting the
IxR drops “inside the loop” and virtually eliminating this error
source.
In the AD624 a reference source resistance will unbalance the
CMR trim by the ratio of 10 kΩ/RREF. For example, if the refer-
ence source impedance is 1 Ω, CMR will be reduced to 80 dB
(10 kΩ/1 Ω = 80 dB). An operational amplifier may be used to
provide that low impedance reference point as shown in Figure
36. The input offset voltage characteristics of that amplifier will
add directly to the output offset voltage performance of the
instrumentation amplifier.
An instrumentation amplifier can be turned into a voltage-to-
current converter by taking advantage of the sense and reference
terminals as shown in Figure 37.
V+
(SENSE)
OUTPUT
CURRENT
BOOSTER
V
+
IN
IN
SENSE
X1
AD624
+INPUT
R
1
X
R
L
+V –
V
–
I
L
(REF)
AD624
V–
AD711
A2
–INPUT
REF
Figure 35. AD624 Instrumentation Amplifier with Output
Current Booster
V
V
LOAD
IN
40.000
R
G
X
1 +
I
=
=
L
Typically, IC instrumentation amplifiers are rated for a full
±10 volt output swing into 2 kΩ. In some applications, how-
ever, the need exists to drive more current into heavier loads.
Figure 35 shows how a current booster may be connected
R
R
1
1
Figure 37. Voltage-to-Current Converter
REV. C
–10–
AD624
50⍀
–IN
+IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUTPUT
OFFSET
TRIM
G = 100 G = 200 G = 500
K1 K2 K3
NC
50⍀
80.2⍀
R2
10k⍀
4445.7⍀
INPUT
OFFSET
TRIM
V
B
20k⍀
20k⍀
10k⍀
RELAY
SHIELDS
225.3⍀
124⍀
R1
10k⍀
10k⍀
10k⍀
+5V
10k⍀
–V
+V
S
K1
K2
K3
AD624
D1
D2
D3
OUT
S
C1
C2
1F
35V
K1 – K3 =
THERMOSEN DM2C
4.5V COIL
ANALOG
COMMON
A
B
INPUTS
GAIN
RANGE
D1 – D3 = IN4148
Y0
Y1
Y2
74LS138
DECODER
7407N
BUFFER
DRIVER
10F
GAIN TABLE
A
B
GAIN
0
0
1
1
0
1
0
1
100
500
200
1
+5V
LOGIC
COMMON
Figure 38. Gain Programmable Amplifier
symmetrical bipolar transmission is ideal in this application. The
multiplying DAC’s advantage is that it can handle inputs of
either polarity or zero without affecting the programmed gain.
The circuit shown uses an AD7528 to set the gain (DAC A) and
to perform a fine adjustment (DAC B).
By establishing a reference at the “low” side of a current setting
resistor, an output current may be defined as a function of input
voltage, gain and the value of that resistor. Since only a small
current is demanded at the input of the buffer amplifier A2, the
forced current IL will largely flow through the load. Offset and
drift specifications of A2 must be added to the output offset and
drift specifications of the IA.
(+INPUT)
(–INPUT)
50⍀
–IN
+IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUTPUT
OFFSET
NULL
PROGRAMMABLE GAIN
50⍀
80.2⍀
Figure 38 shows the AD624 being used as a software program-
mable gain amplifier. Gain switching can be accomplished with
mechanical switches such as DIP switches or reed relays. It
should be noted that the “on” resistance of the switch in series
with the internal gain resistor becomes part of the gain equation
and will have an effect on gain accuracy.
TO –V
10k⍀
4445.7⍀
INPUT
OFFSET
NULL
20k⍀
20k⍀
V
B
225.3⍀
124⍀
10k⍀
10k⍀
10k⍀
10k⍀
A significant advantage in using the internal gain resistors in a
programmable gain configuration is the minimization of thermo-
couple signals which are often present in multiplexed data
acquisition systems.
10k⍀
–V
+V
S
AD624
V
OUT
S
1F
35V
If the full performance of the AD624 is to be achieved, the user
must be extremely careful in designing and laying out his circuit
to minimize the remaining thermocouple signals.
10pF
V
V
DD
GND
SS
+V
S
39.2k⍀
28.7k⍀
316k⍀
1k⍀
The AD624 can also be connected for gain in the output stage.
Figure 39 shows an AD547 used as an active attenuator in the
output amplifier’s feedback loop. The active attenuation pre-
sents a very low impedance to the feedback resistors therefore
minimizing the common-mode rejection ratio degradation.
AD711
1k⍀
1k⍀
–V
S
AD7590
Another method for developing the switching scheme is to use a
DAC. The AD7528 dual DAC which acts essentially as a pair of
switched resistive attenuators having high analog linearity and
A1 A2 A3 A4 WR
Figure 39. Programmable Output Gain
REV. C
–11–
AD624
In many applications complex software algorithms for autozero
applications are not available. For these applications Figure 42
provides a hardware solution.
50⍀
+INPUT
(–INPUT)
G = 100
G = 200
G = 500
AD624
225.3⍀
+V
S
4445.7⍀
V
B
124⍀
15 16
10k⍀
RG
1
80.2⍀
14
13
20k⍀ 10k⍀
AD624
V
OUT
RG
1
9
10
V
OUT
0.1F LOW
LEAKAGE
CH
RG
2
20k⍀
10k⍀
10k⍀
RG
2
1k⍀
12 11
50⍀
–INPUT
(+INPUT)
–V
S
AD542
+V
S
1/2
AD712
DAC A
DB0
DB7
V
V
DD
AD7510DIKD
DATA
INPUTS
SS
256:1
GND
CS
AD7528
A1
A2
A3
A4
WR
200s
ZERO PULSE
DAC A/DAC B
1/2
AD712
DAC B
Figure 42. Autozero Circuit
The microprocessor controlled data acquisition system shown in
Figure 43 includes includes both autozero and autogain capabil-
ity. By dedicating two of the differential inputs, one to ground
and one to the A/D reference, the proper program calibration
cycles can eliminate both initial accuracy errors and accuracy
errors over temperature. The autozero cycle, in this application,
converts a number that appears to be ground and then writes
that same number (8 bit) to the AD624 which eliminates the
zero error since its output has an inverted scale. The autogain
cycle converts the A/D reference and compares it with full scale.
A multiplicative correction factor is then computed and applied
to subsequent readings.
Figure 40. Programmable Output Gain Using a DAC
AUTOZERO CIRCUITS
In many applications it is necessary to provide very accurate
data in high gain configurations. At room temperature the offset
effects can be nulled by the use of offset trimpots. Over the
operating temperature range, however, offset nulling becomes a
problem. The circuit of Figure 41 shows a CMOS DAC operat-
ing in the bipolar mode and connected to the reference terminal
to provide software controllable offset adjustments.
+V
S
–INPUT
RG
2
V
RG
REF
1
G = 100
G = 200
AD583
V
IN
AD624
V
OUT
AD624
AD7507
AD574A
G = 500
RG
AGND
2
RG
1
+INPUT
A2
A0
–V
S
–V
EN A1
REF
39k⍀
V
REF
–V
S
20k⍀
20k⍀
+V
AD589
S
R3
20k⍀
R5
20k⍀
R
FB
MSB
LSB
AD7524
LATCH
+V
OUT1
1/2
AD712
DATA
INPUTS
C1
10k⍀
5k⍀
S
R4
10k⍀
1/2
AD712
1/2
AD712
AD7524
DECODE
CS
1/2
AD712
OUT2
WR
R6
5k⍀
CONTROL
–V
S
GND
MICRO-
PROCESSOR
ADDRESS BUS
Figure 41. Software Controllable Offset
Figure 43. Microprocessor Controlled Data Acquisition
System
REV. C
–12–
AD624
WEIGH SCALE
Figure 45 is an example of an ac bridge system with the AD630
used as a synchronous demodulator. The oscilloscope photo-
graph shows the results of a 0.05% bridge imbalance caused by
the 1 Meg resistor in parallel with one leg of the bridge. The top
trace represents the bridge excitation, the upper middle trace is
the amplified bridge output, the lower-middle trace is the out-
put of the synchronous demodulator and the bottom trace is the
filtered dc system output.
Figure 44 shows an example of how an AD624 can be used to
condition the differential output voltage from a load cell. The
10% reference voltage adjustment range is required to accom-
modate the 10% transducer sensitivity tolerance. The high
linearity and low noise of the AD624 make it ideal for use in
applications of this type particularly where it is desirable to
measure small changes in weight as opposed to the absolute
value. The addition of an autogain/autotare cycle will enable the
system to remove offsets, gain errors, and drifts making possible
true 14-bit performance.
This system can easily resolve a 0.5 ppm change in bridge
impedance. Such a change will produce a 6.3 mV change in the
low-pass filtered dc output, well above the RTO drifts and noise.
The AC-CMRR of the AD624 decreases with the frequency of
the input signal. This is due mainly to the package-pin capaci-
tance associated with the AD624’s internal gain resistors. If
AC-CMRR is not sufficient for a given application, it can be
trimmed by using a variable capacitor connected to the amplifier’s
RG2 pin as shown in Figure 45.
+15V
+15V
R3
NOTE 2
10V ؎10%
+10V
+5V
10⍀
100⍀
2N2219
AD707
R1
30k⍀
AD584
SCALE
ERROR
ADJUST
+2.5V
VBG
R2
20k⍀
+V
R3
S
1kHz
10k⍀
BRIDGE
EXCITATION
10k⍀
RG
1
1k⍀
1k⍀
–INPUT
+10V FULL
SCALE
OUTPUT
SENSE
G500
G200
G100
AD624C
1k⍀
G = 1000
RG
A/D
CONVERTER
1k⍀
AD624
1M⍀
2
OUT
RG
2
R5
3M⍀
4–49pF
CERAMIC ac
BALANCE
REFERENCE
–V
S
+INPUT
R4
CAPACITOR
10k⍀
ZERO
ADJUST
(FINE)
GAIN = 500
R7
100k
⍀
TRANSDUCER
SEE NOTE 1
MODULATION
INPUT
R6
2.5k⍀
100k⍀
ZERO ADJUST
(COARSE)
PHASE
SHIFTER
A
NOTES
1. LOAD CELL TEDEA MODEL 1010 10kG. OUTPUT 2mV/V؎10%.
2. R1, R2 AND R3 SELECTED FOR AD584. OUTPUT 10V ؎10%.
2.5k⍀
5k⍀
B
Figure 44. AD624 Weigh Scale Application
MODULATED
OUTPUT
SIGNAL
V
10k⍀
10k⍀
AC BRIDGE
Bridge circuits which use dc excitation are often plagued by
errors caused by thermocouple effects, l/f noise, dc drifts in the
electronics, and line noise pickup. One way to get around these
problems is to excite the bridge with an ac waveform, amplify
the bridge output with an ac amplifier, and synchronously
demodulate the resulting signal. The ac phase and amplitude
information from the bridge is recovered as a dc signal at the
output of the synchronous demodulator. The low frequency
system noise, dc drifts, and demodulator noise all get mixed to
the carrier frequency and can be removed by means of a low-
pass filter. Dynamic response of the bridge must be traded off
against the amount of attenuation required to adequately sup-
press these residual carrier components in the selection of the
filter.
–V
OUT
S
–V
CARRIER
INPUT
+V
AD630
S
COMP
Figure 45. AC Bridge
BRIDGE EXCITATION
(20V/div) (A)
0V
AMPLIFIED BRIDGE
OUTPUT (5V/div) (B)
0V
0V
DEMODULATED BRIDGE
OUTPUT (5V/div) (C)
FILTER OUTPUT
2V/div) (D)
2V
0V
Figure 46. AC Bridge Waveforms
REV. C
–13–
AD624
ERROR BUDGET ANALYSIS
+V
S
To illustrate how instrumentation amplifier specifications are
applied, we will now examine a typical case where an AD624 is
required to amplify the output of an unbalanced transducer.
Figure 47 shows a differential transducer, unbalanced by ≈5 Ω,
supplying a 0 to 20 mV signal to an AD624C. The output of the
IA feeds a 14-bit A to D converter with a 0 to 2 volt input volt-
age range. The operating temperature range is –25°C to +85°C.
Therefore, the largest change in temperature ∆T within the
operating range is from ambient to +85°C (85°C – 25°C =
60°C.)
+10V
10k⍀
RG
1
350⍀
350⍀
350⍀
350⍀
14-BIT
ADC
0 TO 2V
F.S.
G = 100
AD624C
RG
2
–V
S
In many applications, differential linearity and resolution are of
prime importance. This would be so in cases where the absolute
value of a variable is less important than changes in value. In
these applications, only the irreducible errors (20 ppm =
0.002%) are significant. Furthermore, if a system has an intelli-
gent processor monitoring the A to D output, the addition of an
autogain/autozero cycle will remove all reducible errors and may
eliminate the requirement for initial calibration. This will also
reduce errors to 0.002%.
Figure 47. Typical Bridge Application
Table II. Error Budget Analysis of AD624CD in Bridge Application
Effect on
Absolute
Accuracy
Effect on
Absolute
Accuracy
Effect
on
AD624C
Error Source
Specifications Calculation
at TA = +25؇C at TA = +85؇C Resolution
Gain Error
Gain Instability
Gain Nonlinearity
Input Offset Voltage
Input Offset Voltage Drift
±0.1%
10 ppm
±0.001%
±25 µV, RTI
±0.25 µV/°C
±0.1% = 1000 ppm
(10 ppm/°C) (60°C) = 600 ppm
±0.001% = 10 ppm
±25 µV/20 mV = ±1250 ppm
(±0.25 µV/°C) (60°C)= 15 µV
15 µV/20 mV = 750 ppm
±2.0 mV/20 mV = 1000 ppm
(±10 µV/°C) (60°C) = 600 µV
600 µV/20 mV = 300 ppm
(±15 nA)(5 Ω ) = 0.075 µV
0.075 µV/20mV = 3.75 ppm
(±10 nA)(5 Ω) = 0.050 µV
0.050 µV/20 mV = 2.5 ppm
(10 nA) (175 Ω) = 1.75 µV
1.75 µV/20 mV = 87.5 ppm
(100 pA/°C) (175 Ω) (60°C) = 1 µV
1 µV/20 mV = 50 ppm
1000 ppm
_
–
1000 ppm
600 ppm
–
–
–
10 ppm
–
1250 ppm
1250 ppm
–
750 ppm
1000 ppm
–
–
Output Offset Voltage1
±2.0 mV
1000 ppm
Output Offset Voltage Drift1 ±10 µV/°C
–
300 ppm
3.75 ppm
2.5 ppm
87.5 ppm
50 ppm
–
–
–
–
–
–
Bias Current–Source
Imbalance Error
Offset Current–Source
Imbalance Error
Offset Current–Source
Resistance Error
Offset Current–Source
Resistance–Drift
Common-Mode Rejection
5 V dc
±15 nA
3.75 ppm
2.5 ppm
87.5 ppm
–
±10 nA
±10 nA
±100 pA/°C
115 dB
115 dB = 1.8 ppm × 5 V = 9 µV
9 µV/20 mV = 444 ppm
450 ppm
450 ppm
Noise, RTI
(0.1 Hz–10 Hz)
0.22 µV p-p
0.22 µV p-p/20 mV = 10 ppm
_
–
10 ppm
20 ppm
Total Error
3793.75 ppm
5493.75 ppm
NOTE
1Output offset voltage and output offset voltage drift are given as RTI figures.
For a comprehensive study of instrumentation amplifier design
and applications, refer to the Instrumentation Amplifier Application
Guide, available free from Analog Devices.
REV. C
–14–
AD624
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Side-Brazed Solder Lid Ceramic DIP
(D-16)
0.005 (0.13) MIN
16
0.080 (2.03) MAX
9
0.310 (7.87)
0.220 (5.59)
1
8
0.320 (8.13)
0.290 (7.37)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.840 (21.34) MAX
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.150
(3.81)
MAX
SEATING
PLANE
0.015 (0.38)
0.008 (0.20)
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
REV. C
–15–
相关型号：
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