AD5641ACPZ-REEL7 [ADI]
SPI Interface in LFCSP and SC70; SPI接口的LFCSP和SC70
| 型号： | AD5641ACPZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | SPI Interface in LFCSP and SC70 |
| 文件： | 总20页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.7 V to 5.5 V, <100 µA, 14-Bit nanoDAC,
SPI Interface in LFCSP and SC70
Data Sheet
AD5641
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
DD
GND
6-lead LFCSP and SC70 packages
Micropower operation: 100 µA maximum at 5 V
Power-down to typically 0.2 µA at 3 V
Single 14-bit DAC
POWER-ON
RESET
AD5641
B version: 4 LSB INL
A version: 16 LSB INL
REF(+)
14-BIT
DAC
DAC
REGISTER
OUTPUT
BUFFER
V
OUT
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation
interrupt facility
SYNC
SYNC SCLK SDIN
APPLICATIONS
Figure 1.
Voltage level setting
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Table 1. Related Devices
Part Number
Description
AD5601
2.7 V to 5.5 V, <100 µA, 8-bit nanoDAC,
SPI interface in LFCSP and SC70 packages
2.7 V to 5.5 V, <100 µA, 10-bit nanoDAC,
SPI interface in LFCSP and SC70 packages
2.7 V to 5.5 V, <100 µA, 12-bit nanoDAC,
GENERAL DESCRIPTION
AD5611
AD5621
The AD5641, a member of the nanoDAC® family, is a single,
14-bit, buffered, voltage-out DAC that operates from a single
2.7 V to 5.5 V supply, typically consuming 75 µA at 5 V. The
part comes in tiny LFCSP and SC70 packages. Its on-chip
precision output amplifier allows rail-to-rail output swing to be
achieved. The AD5641 uses a versatile 3-wire serial interface
that operates at clock rates up to 30 MHz and is compatible with
SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The
reference for AD5641 is derived from the power supply inputs
and, therefore, gives the widest dynamic output range. The part
incorporates a power-on reset circuit, which ensures that the
DAC output powers up to 0 V and remains there until a valid
write to the device takes place.
SPI interface in LFCSP and SC70 packages
PRODUCT HIGHLIGHTS
1. Available in space-saving 6-lead LFCSP and SC70
packages.
2. Low power, single-supply operation. The AD5641 operates
from a single 2.7 V to 5.5 V supply and with a maximum
current consumption of 100 µA, making it ideal for
battery-powered applications.
3. The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a typical slew rate of
0.5 V/µs.
4. Reference derived from the power supply.
5. High speed serial interface with clock speeds up to
30 MHz. Designed for very low power consumption. The
interface powers up only during a write cycle.
6. Power-down capability. When powered down, the DAC
typically consumes 0.2 µA at 3 V.
The AD5641 contains a power-down feature that reduces
current consumption typically to 0.2 µA at 3 V, and provides
software-selectable output loads while in power-down mode.
The part is put into power-down mode over the serial interface.
The low power consumption of the part in normal operation
makes it ideally suited to portable battery-operated equipment.
The combination of small package and low power makes this
nanoDAC device ideal for level-setting requirements such as
generating bias or control voltages in space-constrained and
power-sensitive applications.
7. Power-on reset with brownout detection.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2012 Analog Devices, Inc. All rights reserved.
AD5641
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Resistor String............................................................................. 13
Output Amplifier........................................................................ 13
Serial Interface ............................................................................ 13
Input Shift Register .................................................................... 13
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
Digital-to-Analog Section ......................................................... 13
SYNC
Interrupt .......................................................................... 13
Power-On Reset.......................................................................... 14
Power-Down Modes .................................................................. 14
Microprocessor Interfacing....................................................... 15
Applications..................................................................................... 16
Choosing a Reference as Power Supply for the AD5641....... 16
Bipolar Operation Using the AD5641..................................... 16
Using the AD5641 with a Galvanically Isolated Interface .... 17
Power Supply Bypassing and Grounding................................ 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
2/12—Rev. C to Rev. D
3/05—Rev. 0 to Rev. A
Added 6-Lead LFCSP.........................................................Universal
Changes to Title, Features Section, General Description Section,
Table 1, and Product Highlights Section, ...................................... 1
Changes to Table 4............................................................................ 5
Added Figure 4; Renumbered Sequentially .................................. 6
Changes to Table 5............................................................................ 6
Change to Choosing a Reference as Power Supply for the
AD5641 Section .............................................................................. 16
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide .......................................................... 19
Changes to Timing Characteristics.................................................4
Changes to Absolute Maximum Ratings........................................5
Changes to Full-Scale Error Section ...............................................7
Changes to Figures 28 and 30 ....................................................... 12
Change to Resistor String Section................................................ 13
Changes to Power-Down Mode Section ..................................... 14
1/05—Revision 0: Initial Version
10/07—Rev. B to Rev. C
Added B Grade....................................................................Universal
Changes to Offset Error and Gain Error Specifications.............. 3
Changes to Table 4............................................................................ 5
Changes to Typical Performance Characteristics......................... 7
Changes to Ordering Guide .......................................................... 18
7/05—Rev. A to Rev. B
Change to Galvanically Isolated Interface Section..................... 18
Changes to Figure 44...................................................................... 18
Rev. D | Page 2 of 20
Data Sheet
AD5641
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; −40°C < TA < +125°C; typical at +25°C; all specifications TMIN to TMAX
,
unless otherwise noted.
Table 2.
A Grade
Min Typ
B Grade
Min Typ
Parameter
Max
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
Relative Accuracy1
Differential Nonlinearity1
Zero-Code Error
Offset Error
14
14
Bits
LSB
LSB
mV
mV
mV
16
1
10
10
4
1
10
10
Guaranteed monotonic by design
All 0s loaded to DAC register
0.5
0.63
0.5
0.5
0.63
0.5
Full-Scale Error
All 1s loaded to DAC register
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
0.004
5.0
2.0
0.037
0.004
5.0
2.0
0.037 % of FSR
µV/°C
ppm of
FSR/°C
OUTPUT CHARACTERISTICS2
Output Voltage Range
Output Voltage Settling Time
Slew Rate
0
VDD
10
0
VDD
10
V
µs
V/µs
pF
pF
6
6
Code ¼ scale to ¾ scale, to 1 LSB
0.5
470
1000
120
2
0.5
470
1000
120
2
Capacitive Load Stability
RL = ∞
RL = 2 kΩ
DAC code = midscale, 1 kHz
Output Noise Spectral Density
Noise
nV/√Hz
µV
DAC code = midscale, 0.1 Hz to
10 Hz bandwidth
Digital-to-Analog Glitch
Impulse
5
5
nV-s
1 LSB change around major carry
Digital Feedthrough
DC Output Impedance
Short-Circuit Current
LOGIC INPUTS
0.2
0.5
15
0.2
0.5
15
nV-s
Ω
mA
VDD = 3 V/5 V
Input Current3
2
0.8
0.6
2
0.8
0.6
µA
V
V
V
V
VINL, Input Low Voltage
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
VINH, Input High Voltage
1.8
1.4
1.8
1.4
Pin Capacitance
POWER REQUIREMENTS
VDD
3
3
pF
2.7
5.5
2.7
5.5
V
All digital inputs at 0 V or VDD
DAC active and excluding load current
VIH = VDD and VIL = GND
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
POWER EFFICIENCY
IOUT/IDD
75
60
100
90
75
60
100
90
µA
µA
VIH = VDD and VIL = GND
0.5
0.2
0.5
0.2
µA
µA
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
96
96
%
ILOAD = 2 mA and VDD
loaded
= 5 V, full-scale
1 Linearity calculated using a reduced code range (Code 256 to Code 16,128).
2 Guaranteed by design and characterization, not production tested.
3 Total current flowing into all pins.
Rev. D | Page 3 of 20
AD5641
Data Sheet
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.
Table 3.
Parameter
Limit1
33
5
5
10
5
Unit
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
2
t1
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t2
t3
t4
t5
t6
t7
t8
t9
4.5
0
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK falling edge ignored
20
13
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 30 MHz.
t4
t2
t1
t9
SCLK
SYNC
t8
t3
t7
t6
t5
SDIN
D15
D14
D2
D1
D0
D15
D14
Figure 2. Timing Diagram
Rev. D | Page 4 of 20
Data Sheet
AD5641
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
Rating
VDD to GND
Digital Input Voltage to GND
VOUT to GND
−0.3 V to +7.0 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial
Storage Temperature Range
Maximum Junction Temperature
SC70 Package
–40°C to +125°C
–65°C to +160°C
150°C
ESD CAUTION
θJA Thermal Impedance
θJC Thermal Impedance
LFCSP Package
433.34°C/W
149.47°C/W
θJA Thermal Impedance
Reflow Soldering
95°C/W
Peak Temperature
Time at Peak Temperature
ESD
260°C
20 sec to 40 sec
2.0 kV
Rev. D | Page 5 of 20
AD5641
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
1
2
3
6
5
4
V
OUT
DD
V
1
2
3
6
5
4
AD5641
SYNC
SCLK
SDIN
OUT
SCLK
SDIN
GND
TOP VIEW
AD5641
(Not to Scale)
TOP VIEW
SYNC
GND
(Not to Scale)
V
DD
NOTES:
1. CONNECT THE EXPOSED PAD TO GND.
Figure 4. 6-Lead LFCSP Pin Configuration
Figure 3. 6-Lead SC70 Pin Configuration
Table 5. Pin Function Descriptions
SC70 LFCSP
Pin No. Pin No.
Mnemonic
Description
1
4
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input
data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling
edges of the clocks that follow. The DAC is updated following the 16th clock cycle unless SYNC is
taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write
sequence is ignored by the DAC.
2
3
4
2
3
1
SCLK
SDIN
VDD
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
Power Supply Input. The AD5641 can be operated from 2.7 V to 5.5 V. VDD should be decoupled to
GND.
5
6
5
6
GND
VOUT
EP
Ground Reference Point for All Circuitry on the AD5641.
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
Exposed Pad. Connect to GND.
Rev. D | Page 6 of 20
Data Sheet
AD5641
TYPICAL PERFORMANCE CHARACTERISTICS
8
6
4
V
T
= V
REF
= 5V
V
T
= V
= 5V
DD
= 25°C
DD
REF
= 25°C
A
A
3
2
4
1
2
0
0
–1
–2
–3
–4
–2
–4
–6
–8
256
2256
4256
6256
8256 10256 12256 14256
256
2256
4256
6256
8256 10256 12256 14256
DAC CODE
DAC CODE
Figure 5. Typical INL
Figure 8. Typical Total Unadjusted Error (TUE)
2.0
1.5
0
–2
MAX INL @ V = V
= 5V
= 3V
DD
REF
MAX TUE ERROR @ V = V
DD REF
= 5V
1.0
MAX INL @ V = V
DD
–4
REF
0.5
MAX TUE ERROR @ V = V
DD REF
= 3V
–6
0
–8
MIN TUE ERROR @ V = V
DD
= 5V
REF
–0.5
–1.0
–1.5
–2.0
–10
–12
–14
MIN INL @ V = V
= 5V
DD
REF
MIN TUE ERROR @ V = V
DD
= 3V
80
REF
MIN INL @ V = V
DD
= 3V
120
REF
–40
–20
0
20
40
60
80
100
140
–40
–20
0
20
40
60
100
120
140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. INL Error vs. Temperature (3 V/5 V Supply)
Figure 9. Total Unadjusted Error (TUE) vs. Temperature (3 V/5 V Supply)
5
4
10
T
= 25°C
T
= 25°C
A
A
3
5
0
2
MAX INL ERROR
MIN INL ERROR
1
MAX TUE ERROR
MIN TUE ERROR
0
–1
–2
–3
–4
–5
–5
–10
–15
5.2
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
4.7
SUPPLY (V)
SUPPLY (V)
Figure 7. INL Error vs. Supply at 25°C
Figure 10. Total Unadjusted Error (TUE) vs. Supply at 25°C
Rev. D | Page 7 of 20
AD5641
Data Sheet
0.0025
0.0020
0.0015
0.0010
0.0005
0
0.6
0.5
0.4
ZERO-CODE ERROR @ V = 5V
DD
MAX DNL @ V = 3V
DD
0.3
ZERO-CODE ERROR @ V = 3V
0.2
DD
MAX DNL @ V = 5V
DD
FULL-SCALE ERROR @ V = 5V
DD
0.1
–0.0005
–0.0010
–0.0015
–0.0020
0
–0.1
–0.2
–0.3
–0.4
FULL-SCALE ERROR @ V = 3V
DD
MIN DNL @ V = 3V
DD
MIN DNL @ V = 5V
DD
–0.0025
–40
–40
–20
0
20
40
60
80
100
120
140
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Zero-Code/Full-Scale Error vs. Temperature (3 V/5 V)
Figure 14. DNL Error vs. Temperature (3 V/5 V)
0.0020
1.0
0.8
T
= 25°C
A
T
= 25°C
A
0.0015
0.0010
0.0005
0
0.6
ZERO-CODE ERROR
0.4
MAX DNL ERROR
MIN DNL ERROR
0.2
0
FULL-SCALE ERROR
–0.2
–0.4
–0.6
–0.8
–1.0
–0.0005
–0.0010
–0.0015
–0.0020
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY (V)
SUPPLY (V)
Figure 12. Zero-Code/Full-Scale Error vs. Supply at 25°C
Figure 15. DNL Error vs. Supply at 25°C
0.5
12
10
8
V
= 3V
= DV
= GND
= 25°C
V
V
V
= 5V
= DV
= GND
V
= 5V
DD
IH
DD
DD
= 25°C
V
V
T
DD
IH
DD
A
0.4
0.3
IL
A
IL
A
T
T
= 25°C
0.2
0.1
6
0
–0.1
–0.2
–0.3
–0.4
–0.5
4
2
0
256 2256 4256 6256 8256 10256 12256 14256
DAC CODE
I
(mA)
DD
Figure 16. IDD Histogram (3 V/5 V)
Figure 13. Typical DNL
Rev. D | Page 8 of 20
Data Sheet
AD5641
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
–1.1
–1.2
–1.3
–1.4
–1.5
–1.6
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
T
A = 25°C
V
V
= V
= 5V
= 3V
DD
REF
= V
60
DD
REF
–40
–20
0
20
40
80
100
120
140
2.7
3.2
3.7
4.2
4.7
5.2
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 17. Offset Error vs. Temperature (3 V/5 V Supply)
Figure 20. Supply Current vs. Supply Voltage at 25°C
0.8
0.6
0
–0.002
–0.004
–0.006
–0.008
–0.010
–0.012
–0.014
–0.016
V
= 5V
= 25°C
DD
T
A
DAC LOADED WITH ZERO-SCALE CODE
0.4
V
= 5V
DD
0.2
0
V
= 3V
DD
–0.2
–0.4
–0.6
DAC LOADED WITH FULL-SCALE CODE
–40
–20
0
20
40
60
80
100
120
140
–15
–10
–5
0
5
10
15
TEMPERATURE (°C)
I (mA)
Figure 18. Gain Error vs. Temperature (3 V/5 V)
Figure 21. Sink and Source Capability
70
60
50
40
30
20
10
0
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
V
= 5V
= 3V
DD
V
V
= 5V
DD
DD
V
= 3V
DD
0
2000 4000 6000 8000 10000 12000 14000 16000
DIGITAL INPUT CODE
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
Figure 19. Supply Current vs. Temperature (3 V/5 V Supply)
Figure 22. Supply Current vs. Digital Input Code
Rev. D | Page 9 of 20
AD5641
Data Sheet
CH1
T
V
= 25°C
= 5V
A
V
DD
V
= 5V
DD
DD
T
= 25°C
A
CH1 = SCLK
CH2
V
OUT
CH2 = V
OUT
CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV
CH1 1V, CH2 5V, TIME BASE = 50µs/DIV
Figure 23. Full-Scale Settling Time
Figure 26. VDD vs. VOUT
2.458
T
= 25°C
A
V
= 5V
DD
2.456
2.454
2.452
2.450
2.448
2.446
2.444
2.442
2.440
2.438
2.436
CH1 = SCLK
CH2 = V
OUT
T
= 25°C
A
V
= 5V
DD
LOAD = 2kΩ AND 220pF
CODE 0x2000 TO 0x1FFF
10ns/SAMPLE NUMBER
CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV
0
100
200
300
400
500
SAMPLE NUMBER
Figure 24. Midscale Settling Time
Figure 27. Digital-to-Analog Glitch Energy
V
= 5V
DD
= 25°C
V
DD
V
= 5V
DD
= 25°C
T
A
T
A
MIDSCALE LOADED
CH1
CH1
V
= 70mV
OUT
CH2
CH1 5µV/DIV
CH1 1V, CH2 20mV, TIME BASE = 20µs/DIV
Figure 25. Power-On Reset to 0 V
Figure 28. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth
Rev. D | Page 10 of 20
Data Sheet
AD5641
700
V
T
= 5V
= 25°C
V
T
= 5V
DD
DD
= 25°C
CH1
A
A
600 UNLOADED OUTPUT
500
V
OUT
400
ZERO SCALE
300
MIDSCALE
200
100
0
FULL SCALE
CH2
CH1 5V, CH2 1V, TIME BASE = 2µs/DIV
100
1000
10000
100000
FREQUENCY (Hz)
Figure 29. Exiting Power-Down Mode
Figure 31. Noise Spectral Density
140
120
100
80
450
3/4 SCALE
T
= 25°C
A
SCLK/SDIN
INCREASING
FULL SCALE
400
350
300
250
200
150
100
50
SCLK/SDIN
DECREASING
= 5V
V
= 5V
DD
V
DD
MIDSCALE
1/4 SCALE
SCLK/SDIN
INCREASING
V
= 3V
DD
60
ZERO SCALE
40
20
SCLK/SDIN DECREASING V = 3V
DD
0
0
0
1
2
3
4
5
6
0
5
10
15
20
25
V
(V)
LOGIC
FREQUENCY (MHz)
Figure 32. SCLK/SDIN vs. Logic Voltage
Figure 30. IDD vs. SCLK vs. Code
Rev. D | Page 11 of 20
AD5641
Data Sheet
TERMINOLOGY
Relative Accuracy
Gain Error
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. See Figure 5 for a plot of typical INL vs. code.
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal,
expressed as a percent of the full-scale range.
Total Unadjusted Error (TUE)
Differential Nonlinearity (DNL)
Total unadjusted error is a measure of the output error taking
the various errors into account. See Figure 8 for a plot of typical
TUE vs. code.
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. See Figure 13 for a plot of typical DNL vs. code.
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in μV/°C.
Zero-Code Error
Gain Error Drift
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5641 because the output of the DAC cannot go below 0 V.
Zero-code error is due to a combination of the offset errors in
the DAC and output amplifier. Zero-code error is expressed in
mV. See Figure 11 for a plot of zero-code error vs. temperature.
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x2000 to 0x1FFF). See
Figure 27.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded to the DAC register. Ideally, the output
should be VDD − 1 LSB. Full-scale error is expressed in mV. See
Figure 11 for a plot of full-scale error vs. temperature.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated.
It is specified in nV-s and is measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice versa.
Rev. D | Page 12 of 20
Data Sheet
AD5641
THEORY OF OPERATION
DIGITAL-TO-ANALOG SECTION
OUTPUT AMPLIFIER
The AD5641 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Figure 33 is a block diagram of the DAC
architecture.
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0 V to VDD. It is
capable of driving a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in Figure 21. The slew rate is 0.5 V/μs, with a
midscale settling time of 8 μs with the output loaded.
V
DD
REF (+)
SERIAL INTERFACE
RESISTOR
NETWORK
V
DAC REGISTER
OUT
SYNC
The AD5641 has a 3-wire serial interface (
, SCLK, and
REF (–ꢀ)
OUTPUT
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence.
AMPLIFIER
GND
Figure 33. DAC Architecture
SYNC
The write sequence begins by bringing the
line low. Data
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
from the SDIN line is clocked into the 16-bit shift register on
the falling edge of SCLK. The serial clock frequency can be as
high as 30 MHz, making the AD5641 compatible with high
speed DSPs. On the 16th falling clock edge, the last data bit is
clocked in and the programmed function is executed (a change
in DAC register contents and/or a change in the mode of
D
VOUT VDD
16,384
where D is the decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 16,384.
SYNC
operation). At this stage, the
line can be kept low or
brought high. In either case, it must be brought high for a
minimum of 20 ns before the next write sequence, so that a
RESISTOR STRING
The resistor string structure is shown in Figure 34. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaran-
teed monotonic.
SYNC
falling edge of
can initiate the next write sequence.
SYNC
Because the
buffer draws more current when VIN = 1.8 V
SYNC
than it does when VIN = 0.8 V,
should be idled low between
write sequences for even lower power operation of the part, as
previously mentioned. However, it must be brought high again
just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide (see Figure 35). The first
two bits are control bits, which determine the operating mode
of the part (normal mode or any one of three power-down modes).
For a complete description of the various modes, see the Power-
Down Modes section. The next 14 bits are the data bits, which
are transferred to the DAC register on the 16th falling edge
of SCLK.
R
R
TO OUTPUT
AMPLIFIER
R
SYNC INTERRUPT
SYNC
In a normal write sequence, the
line is kept low for at
least 16 falling edges of SCLK and the DAC is updated on the
th
SYNC
16 falling edge. However, if
is brought high before the
R
R
16th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 36).
Figure 34. Resistor String Structure
Rev. D | Page 13 of 20
AD5641
Data Sheet
DB15 (MSB)
DB0 (LSB)
PD1
PD0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
NORMAL OPERATION
0
0
1
1
0
1
0
1
1 kΩ TO GND
100 kΩ TO GND
POWER-DOWN MODES
THREE-STATE
Figure 35. Input Register Contents
SCLK
SYNC
SDIN
DB15
DB0
DB16
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 16TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16TH FALLING EDGE
SYNC
Figure 36.
Interrupt Facility
Not only does the supply current fall, but the output stage is
also internally switched from the output of the amplifier to a
resistor network of known values. This has the advantage that
the output impedance of the part is known while the part is in
power-down mode. There are three different options: the
output is connected internally to GND through either a 1 kΩ
resistor or a 100 kΩ resistor, or the output is left open-circuited
(three-stated). Figure 37 shows the output stage.
POWER-ON RESET
The AD5641 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
0s and the output voltage is 0 V. It remains there until a valid
write sequence is made to the DAC. This is useful in applica-
tions in which it is important to know the state of the DAC
output while it is in the process of powering up.
POWER-DOWN MODES
The AD5641 has four separate modes of operation. These
modes are software programmable by setting two bits (DB15
and DB14) in the control register. Table 6 shows how the state
of the bits corresponds to the operating mode of the device.
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Table 6. Operating Modes for the AD5641
DB15
DB14
Operating Mode
Normal operation
Power-down mode:
1 kΩ to GND
100 kΩ to GND
Three-state
0
0
Figure 37. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are all shut down when power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The time to exit power-
down is typically 13 µs for VDD = 5 V and 16 µs for VDD = 3 V.
See Figure 29 for a plot.
0
1
1
1
0
1
When both bits are set to 0, the part has normal power
consumption of 100 µA maximum at 5 V. However, for the
three power-down modes, the supply current falls to typically
0.2 µA at 3 V.
Rev. D | Page 14 of 20
Data Sheet
AD5641
the SDIN pin of the AD5641, while TSCLK0 drives the SCLK of
MICROPROCESSOR INTERFACING
AD5641 to ADSP-2101 Interface
SYNC
the part. The
is driven from TFS0.
Figure 38 shows a serial interface between the AD5641 and the
ADSP-2101. The ADSP-2101 should be set up to operate in
SPORT transmit alternate framing mode. The ADSP-2101
SPORT is programmed through the SPORT control register and
should be configured as follows: internal clock operation, active
low framing, and 16-bit word length. Transmission is initiated
by writing a word to the Tx register after the SPORT is enabled.
AD5641*
ADSP-BF53x*
DT0PRI
TSCLK0
TFS0
SDIN
SCLK
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 40. AD5641 to Blackfin ADSP-BF53x Interface
ADSP-2101*
AD5641*
AD5641 to 80C51/80L51 Interface
TFS
DT
SYNC
SDIN
SCLK
Figure 41 shows a serial interface between the AD5641 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/80L51 drives SCLK of the AD5641,
SCLK
SYNC
while RxD drives the serial data line of the part. The
*ADDITIONAL PINS OMITTED FOR CLARITY
signal is again derived from a bit-programmable pin on the
port. In this case, Port Line P3.3 is used. When data is to be
transmitted to the AD5641, P3.3 is taken low.
Figure 38. AD5641 to ADSP-2101 Interface
AD5641 to 68HC11/68L11 Interface
Figure 39 shows a serial interface between the AD5641 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5641, while the MOSI output drives
The 80C51/80L51 transmits data only in 8-bit bytes; therefore,
only eight falling clock edges occur in the transmit cycle. To
load data to the DAC, P3.3 is left low after the first eight bits are
transmitted, and a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion
of this cycle. The 80C51/80L51 outputs the serial data LSB first.
The AD5641 requires its data with the MSB as the first bit
received. The 80C51/80L51 transmit routine should take this
into account.
SYNC
the serial data line of the DAC. The
signal is derived
from a port line (PC7). The setup conditions for correct
operation of this interface are as follows: the 68HC11/68L11
should be configured so that the CPOL bit is 0 and the CPHA
SYNC
bit is 1. When data is being transmitted to the DAC, the
line is taken low (PC7). When the 68HC11/68L11 are config-
ured as previously described, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5641, PC7 is left
low after the first eight bits are transferred and a second serial
write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.
AD5641*
80C51/80L51*
P3.3
TxD
RxD
SYNC
SCLK
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 41. AD5641 to 80C51/80L51 Interface
68HC11/
68L11*
AD5641*
AD5641 to MICROWIRE Interface
Figure 42 shows an interface between the AD5641 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5641 on the rising edge of SK.
PC7
SCK
SYNC
SCLK
SDIN
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5641*
MICROWIRE*
Figure 39. AD5641 to 68HC11/68L11 Interface
AD5641 to Blackfin® ADSP-BF53x Interface
CS
SK
SO
SYNC
SCLK
SDIN
Figure 40 shows a serial interface between the AD5641 and
the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multi-
processor communications. Using SPORT0 to connect to the
AD5641, the setup for the interface is as follows: DT0PRI drives
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 42. AD5641 to MICROWIRE Interface
Rev. D | Page 15 of 20
AD5641
Data Sheet
APPLICATIONS
CHOOSING A REFERENCE AS POWER SUPPLY FOR
THE AD5641
BIPOLAR OPERATION USING THE AD5641
The AD5641 has been designed for single-supply operation,
but a bipolar output range is also possible using the circuit in
Figure 44. The circuit in Figure 44 gives an output voltage
range of 5 V. Rail-to-rail operation at the amplifier output is
achievable using an AD820 or OP295 as the output amplifier.
R2 = 10k
The AD5641 comes in tiny LFCSP and SC70 packages with less
than 100 μA supply current. Because of this, the choice of refer-
ence depends on the application requirement. For space-saving
applications, the ADR02 is available in an SC70 package and
has excellent drift at 9 ppm/°C (3 ppm/°C in the R-8 package).
It also provides very good noise performance at 3.4 μV p-p in
the 0.1 Hz to 10 Hz range.
+5V
+5V
R1 = 10k
Because the supply current required by the AD5641 is
extremely low, the parts are ideal for low supply applications.
The ADR395 voltage reference is recommended in this case.
It requires less than 100 μA of quiescent current and can,
therefore, drive multiple DACs in one system, if required. It
also provides very good noise performance at 8 μV p-p in the
0.1 Hz to 10 Hz range.
AD820/
+5V
OP295
V
V
OUT
DD
10F
0.1F
AD5641
–5V
3-WIRE
SERIAL
INTERFACE
7V
Figure 44. Bipolar Operation with the AD5641
5V
ADR395
The output voltage for any input code can be calculated as
D
R1 R2
R2
R1
VOUT V
V
DD
DD
SYNC
3-WIRE
V
= 0V TO 5V
16,384
R1
OUT
SERIAL
INTERFACE
SCLK
SDIN
AD5641
where D represents the input code in decimal (0 – 16384).
With VDD = 5 V, R1 = R2 = 10 kΩ,
Figure 43. ADR395 as Power Supply to AD5641
10 D
VOUT
5 V
Table 7 lists some recommended precision references for use as
supplies to the AD5641.
16,384
This is an output voltage range of 5 V with 0x0000 corre-
sponding to a –5 V output, and 0x3FFF corresponding to a
+5 V output.
Table 7. Precision References for Use with AD5641
Initial
Temperature
Accuracy Drift
0.1 Hz to 10 Hz
Part No.
ADR435
ADR425
ADR02
ADR02
ADR395
(mV max) (ppm/°C max)
Noise (μV p-p typ)
2
2
3
3
5
3 (R-8)
3 (R-8)
3 (R-8)
3 (SC70)
9 (TSOT-23)
8
3.4
10
10
8
Rev. D | Page 16 of 20
Data Sheet
AD5641
USING THE AD5641 WITH A GALVANICALLY
ISOLATED INTERFACE
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5641 should
have separate analog and digital sections, each having its own
area of the board. If the AD5641 is in a system where other
devices require an AGND-to-DGND connection, the
In process control applications in industrial environments, it
is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that might occur in the area where
the DAC is functioning. iCoupler® provides isolation in excess
of 2.5 kV. The AD5641 use a 3-wire serial logic interface, so the
ADuM1300 three-channel digital isolator provides the required
isolation (see Figure 45). The power supply to the part also
needs to be isolated, which is done by using a transformer. On
the DAC side of the transformer, a 5 V regulator provides the
5 V supply required for the AD5641.
connection should be made at one point only. This ground
point should be as close as possible to the AD5641.
The power supply to the AD5641 should be bypassed with
10 µF and 0.1 µF capacitors. The capacitors should be physically
as close as possible to the device, with the 0.1 µF capacitor
ideally right up against the device. The 10 µF capacitors are
the tantalum bead type. It is important that the 0.1 µF capacitor
has low effective series resistance (ESR) and effective series
inductance (ESI), such as in common ceramic types of
capacitors. This 0.1 µF capacitor provides a low impedance
path to ground for high frequencies caused by transient
currents due to internal logic switching.
5V
REGULATOR
POWER
10µF
0.1µF
V
DD
SCLK
VIA
VOA
SCLK
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals,
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects on the board. The best board layout
technique is the microstrip technique, where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
ADuM1300
AD5641
V
OUT
SDI
VIB
VIC
VOB
VOC
SYNC
SDIN
DATA
GND
Figure 45. AD5641 with a Galvanically Isolated Interface
Rev. D | Page 17 of 20
AD5641
Data Sheet
OUTLINE DIMENSIONS
2.20
2.00
1.80
2.40
2.10
1.80
6
1
5
2
4
3
1.35
1.25
1.15
PIN 1
1.30 BSC
0.65 BSC
1.00
0.90
0.70
0.40
0.10
1.10
0.80
0.30
0.10
0.30
0.15
0.22
0.08
0.10 MAX
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 46. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
1.50
1.40
1.30
2.10
2.00
1.90
0.65 REF
0.20 MIN
4
6
3.10
3.00
2.90
EXPOSED
PAD
1.70
1.60
1.50
0.45
0.40
0.35
PIN 1 INDEX
AREA
3
1
PIN 1
INDICATOR
(R 0.15)
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.00 MIN
0.203 REF
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.35
0.30
0.25
COPLANARITY
0.08
COMPLIANT TOJEDEC STANDARDS MO-229
Figure 47. 6-Lead Lead Frame Chip Scale Package [LFCSP_WD]
2.00 × 3.00 mm Body, Very Very Thin, Dual Lead
(CP-6-5)
Dimensions shown in millimeters
Rev. D | Page 18 of 20
Data Sheet
AD5641
ORDERING GUIDE
Temperature
Range
Package
Option
Model1
Description
Package Description
Branding
AD5641AKSZ-REEL7
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
16 LSB INL
6-Lead Thin Shrink Small Outline Transistor
Package [SC70]
6-Lead Thin Shrink Small Outline Transistor
Package [SC70]
6-Lead Lead Frame Chip Scale Package
[LFCSP_WD]
KS-6
KS-6
CP-6-5
KS-6
KS-6
D3Q
AD5641AKSZ-500RL7
AD5641ACPZ-REEL7
AD5641BKSZ-REEL7
AD5641BKSZ-500RL7
16 LSB INL
16 LSB INL
4 LSB INL
4 LSB INL
D3Q
8A
6-Lead Thin Shrink Small Outline Transistor
Package [SC70]
6-Lead Thin Shrink Small Outline Transistor
Package [SC70]
D3P
D3P
1 Z = RoHS Compliant Part.
Rev. D | Page 19 of 20
AD5641
NOTES
Data Sheet
©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04611-0-2/12(D)
Rev. D | Page 20 of 20
相关型号：
AD5643RBRMZ-3
SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 14-BIT DAC, PDSO10, ROHS COMPLIANT, MO-187BA, MSOP-10
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