AD5641AKS-500RL7 [ADI]
AD5641AKS-500RL7;
| 型号： | AD5641AKS-500RL7 |
| 厂家： | 
ADI |
| 描述： | AD5641AKS-500RL7 |
| 文件： | 总20页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.7 V to 5.5 V, <100 µA, 14-Bit
nanoDAC™ D/A in SC70 Package
Preliminary Technical Data
AD5641
FUNCTIONAL BLOCK DIAGRAM
FEATURES
6-lead SC70 package
V
GND
DD
Power-down to <100 nA @ 3 V
Single 14-bit DAC:
A Version: 16 LSB INL
POWER-ON
RESET
AD5641
Micropower operation: max 100 µA @ 5 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation
SYNC interrupt facility
REF(+)
DAC
REGISTER
OUTPUT
BUFFER
V
14-BIT
DAC
OUT
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
APPLICATIONS
Voltage level setting
SYNC
SCLK DIN
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Figure 1.
Table 1. Related Devices
Part Number
Description
AD5601/AD5611/AD5621 2.7 V to 5.5 V, <100 µA, 8-/10-/12-Bit,
nanoDAC™ D/A, SPI Interface, SC70
Package
GENERAL DESCRIPTION
The AD5641, a member of the nanoDAC family, is a single,
14-bit, buffered, voltage out DAC that operates from a single
2.7 V to 5.5 V supply, consuming <100 µA at 5 V. The part
comes in a tiny SC70 package. Its on-chip precision output
amplifier allows rail-to-rail output swing to be achieved. The
AD5641 utilizes a versatile 3-wire serial interface that operates
at clock rates up to 30 MHz and is compatible with SPI®, QSPI™,
MICROWIRE™, and DSP interface standards. The reference for
AD5641 is derived from the power supply inputs and, therefore,
gives the widest dynamic output range. The part incorporates a
power-on reset circuit, which ensures that the DAC output
powers up to 0 V and remains there until a valid write to the
device takes place.
The AD5641 is designed with new technology and comes in a
space-saving SC70 package.
PRODUCT HIGHLIGHTS
1. Available in a space-saving 6-lead SC70 package.
2. Low power, single-supply operation. The AD5641 operates
from a single 2.7 V to 5.5 V supply and typically consumes
0.2 mW at 3 V and 0.5 mW at 5 V, making it ideal for
battery-powered applications.
3. The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a typical slew rate of
0.5 V/µs.
The AD5641 contains a power-down feature that reduces
current consumption to <100 nA at 3 V, and provides software-
selectable output loads while in power-down mode. The part is
put into power-down mode over the serial interface. The low
power consumption of the part in normal operation makes it
ideally suited to portable battery-operated equipment. The
combination of small package and low power makes this
nanoDAC device ideal for level-setting requirements such as
generating bias or control voltages in space-constrained and
power-sensitive applications.
4. Reference derived from the power supply.
5. High speed serial interface with clock speeds up to
30 MHz.
6. Designed for very low power consumption. The interface
powers up only during a write cycle.
7. Power-down capability. When powered down, the DAC
typically consumes <100 nA at 3 V.
8. Power-on reset with brownout detection.
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD5641
Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function DescriptionS ............................ 6
Terminology ...................................................................................... 7
Typical Performance Characteristics ............................................. 8
General Description....................................................................... 12
D/A Section................................................................................. 12
Resistor String............................................................................. 12
Output Amplifier........................................................................ 12
Serial Interface ............................................................................ 12
Input Shift Register .................................................................... 12
Interrupt .......................................................................... 13
SYNC
Power-On Reset.......................................................................... 13
Power-Down Modes .................................................................. 13
Microprocessor Interfacing....................................................... 13
Applications..................................................................................... 15
Choosing a Reference as Power Supply for AD5641............. 15
Bipolar Operation Using the AD5641..................................... 15
Using AD5641 with an Opto-Isolated Interface .................... 16
Power Supply Bypassing and Grounding................................ 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
Revision PrD: Preliminary Version
Rev. PrD | Page 2 of 20
Preliminary Technical Data
AD5641
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
14
Bits
Relative Accuracy1
Differential Nonlinearity1
Zero Code Error
16
1
LSB
LSB
mV
mV
A Grade
Guaranteed monotonic by design
All 0s loaded to DAC register
+0.0005
10
Offset Error
Full-Scale Error
Gain Error
0.0004
0.037
5.0
LSB
All 1s loaded to DAC register
% of FSR
µV/°C
ppm of FSR/°C
Zero Code Error Drift
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS2
Output Voltage Range
Output Voltage Settling Time
Slew Rate
2.0
0
VDD
10
V
µs
V/µs
pF
pF
nV/Hz
uv
nV-s
nV-s
ohm
mA
6
Code ¼ to ¾
0.5
470
1000
120
2
5
0.2
1
Capacitive Load Stability
RL = ∞
RL = 2 kΩ
Output Noise Spectral Density
Noise
DAC code = midscale, 1 kHz
DAC code = midscale, 0.1 Hz to 10 Hz bandwidth
1 LSB change around major carry
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short-Circuit Current
LOGIC INPUTS
20
VDD = 3 V/5 V
Input Current
VINL, Input Low Voltage
1
µA
V
V
0.8
0.6
VDD = 5 V
VDD = 2.7 V
VDD = 5 V
VDD = 2.7 V
VINH, Input High Voltage
1.8
1.4
V
V
Pin Capacitance
POWER REQUIREMENTS
VDD
3
pF
2.7
5.5
V
All digital inputs at 0 or VDD
DAC active and excluding load current
VIH = VDD and VIL = GND
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
POWER EFFICIENCY
IOUT/IDD
100
70
µA
µA
VIH = VDD and VIL = GND
0.2
0.05
1
1
µA
µA
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
TBD
%
ILOAD = 2 mA and VDD = 5 V
1Linearity calculated using a reduced code range.
2 Guaranteed by design and characterization, not production tested.
Rev. PrD | Page 3 of 20
AD5641
Preliminary Technical Data
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.
Table 3.
Parameter
Limit1
33
13
12
13
5
Unit
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
2
t1
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t2
t3
t4
t5
t6
t7
t8
t9
4.5
0
33
13
SYNC rising edge to next SCLK fall ignore
1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 30 MHz.
t4
t2
t1
t9
SCLK
SYNC
t8
t3
t7
t6
t5
DIN
D15
D14
D2
D1
D0
D15
D14
Figure 2. Timing Diagram
Rev. PrD | Page 4 of 20
Preliminary Technical Data
AD5641
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
Parameter
Rating
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VDD to GND
Digital Input Voltage to GND
VOUT to GND
−0.3 V to +7.0 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial
Storage Temperature Range
Maximum Junction Temperature
SC70 Package
–40°C to +125°C
–65°C to +160°C
150°C
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 s)
Infrared (15 s)
332°C/W
120°C/W
215°C
220°C
2.0 kV
ESD
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrD | Page 5 of 20
AD5641
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
6
5
4
V
SYNC
OUT
AD5641
TOP VIEW
(Not to Scale)
SCLK
GND
V
DIN
DD
Figure 3 6-Lead SC70 Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Function
1
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data is transferred in on the falling edges of the clocks that follow.
The DAC is updated following the 16th clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
2
3
SCLK
DIN
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
Serial Data Input. This device has a 16-bit shift regi.ster. Data is clocked into the register on the falling edge of the
serial clock input.
4
5
6
VDD
GND
VOUT
Power Supply Input. The AD5641 can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND.
Ground Reference Point for All Circuitry on the AD5641.
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
Rev. PrD | Page 6 of 20
Preliminary Technical Data
TERMINOLOGY
AD5641
Relative Accuracy
Total Unadjusted Error
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL versus code plot can be seen in Figure 4.
Total unadjusted error (TUE) is a measure of the output error
taking all the various errors into account. A typical TUE versus
code plot can be seen in Figure 5.
Zero-Code Error Drift
Differential Nonlinearity
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in µV/°C.
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL versus code plot can be
seen in Figure 7.
Gain Error Drift
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
Digital-to-Analog Glitch Impulse
Zero-Code Error
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 18.
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5641, because the output of the DAC cannot go below 0 V.
Zero-code error is due to a combination of the offset errors in
the DAC and output amplifier. Zero-code error is expressed in
mV. A plot of zero-code error versus temperature can be seen in
Figure 6.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and is measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice
versa.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded to the DAC register. Ideally, the output
should be VDD − 1 LSB. Full-scale error is expressed in percent
of full-scale range. A plot of full-scale error versus temperature
can be seen in Figure 6.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal,
expressed as a percent of the full-scale range.
Rev. PrD | Page 7 of 20
AD5641
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
0.5
0.4
2.0
1.5
0.3
1.0
0.2
0.5
0.1
0
0
–0.5
–1.0
–1.5
–0.1
–0.2
–0.3
0
2k
4k
6k
8k
10k
12k
14k
16k
0
2k
4k
6k
8k
10k
12k
14k
16k
CODE
CODE
Figure 4. Typical INL Plot
Figure 7. Typical DNL Plot
18
16
14
12
10
8
6
4
2
0
256
2k
4k
6k
8k
10k
12k
14k
16k
CODE
Figure 5. Total Unadjusted Error
Figure 8. INL and DNL vs. Supply
Figure 6. Zero-Scale Error and Full-Scale Error vs. Temperature
Figure 9. IDD Histogram @ VDD = 3 V/5 V
Rev. PrD | Page 8 of 20
Preliminary Technical Data
AD5641
0.8
V
= 5V
DD
T
= 25°C
A
0.6
0.4
DAC LOADED WITH FF CODE
0.2
0.0
–0.2
–0.4
–0.6
DAC LOADED WITH 00 CODE
–15
–10
–5
0
5
10
15
I (mA)
Figure 13. Supply Current vs. Code
Figure 14. Supply Current vs. Supply Voltage
Figure 15. Half-Scale Settling Time
Figure 10. Source and Sink Current Capability
Figure 11. Supply Current vs. Temperature
Figure 12. Full-Scale Settling Time
Rev. PrD | Page 9 of 20
AD5641
Preliminary Technical Data
V
V
= 5V
DD
DD
= 25°C
V
T
= 5V
DD
A
T
A
= 25°C
MIDSCALE LOADED
CH1
CH1
V
= 70mV
OUT
CH2
CH1
CH1 5uV/DIV
CH1 1V, CH2, TIME BASE = 20µs/DIV
Figure 19. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth
Figure 16. Power-On Reset to 0 V
V
DD
V
= 5V
DD
= 25°C
V
T
= 5V
DD
= 25
T
A
°
C
CH1
A
CLK
CH2
CH2
V
OUT
V
OUT
CH1 1V, CH2 5V, TIME BASE = 50µs/DIV
CH1 5V, CH2 1V, TIME BASE = 5µs/DIV
Figure 17. VDD vs. VOUT (Power-Down)
Figure 20. Exiting Power-Down
Figure 18. Digital-to-Analog Glitch Impulse
Figure 21. Harmonic Distortion on Digitally Generated Waveform
Rev. PrD | Page 10 of 20
Preliminary Technical Data
AD5641
140
200
180
160
140
120
100
80
NOISE SPECTRAL
DENSITY
FULL SCALE
120
3/4 SCALE
CODE 0x2040
MIDSCALE
100
1/4 SCALE
MIDSCALE
80
FULL SCALE
60
ZERO SCALE
60
40
20
0
ZERO SCALE
40
20
0
1K
10K
100K
0
5
10
15
20
25
FREQUENCY
FREQUENCY (MHz)
Figure 23. Noise Spectral Density
Figure 22. IDD vs. SCLK vs. Code
Rev. PrD | Page 11 of 20
AD5641
Preliminary Technical Data
GENERAL DESCRIPTION
D/A SECTION
OUTPUT AMPLIFIER
The AD5641 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Figure 24 is a block diagram of the DAC
architecture.
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0 V to VDD. It is
capable of driving a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in Figure 10. The slew rate is 0.5 V/µs, with a half-
scale settling time of 8 µs with the output unloaded.
V
DD
REF (+)
SERIAL INTERFACE
RESISTOR
NETWORK
V
DAC REGISTER
OUT
The AD5641 has a 3-wire serial interface (
SYNC
, SCLK, and
REF (–ꢀ)
OUTPUT
AMPLIFIER
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence.
GND
Figure 24. DAC Architecture
The write sequence begins by bringing the
line low. Data
SYNC
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
from the DIN line is clocked into the 16-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5641compatible with high speed
DSPs. On the 16th falling clock edge, the last data bit is clocked
in and the programmed function is executed (a change in DAC
register contents and/or a change in the mode of operation). At
D
16384
⎛
⎜
⎝
⎞
⎟
⎠
VOUT = VDD
×
where D is the decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 16,384.
this stage, the
line might be kept low or brought high. In
SYNC
either case, it must be brought high for a minimum of 33 ns
RESISTOR STRING
before the next write sequence so that a falling edge of
can initiate the next write sequence.
SYNC
The resistor string section is shown in Figure 25. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaran-
teed monotonic.
Because the
buffer draws more current when VIN = 1.8 V
SYNC
than it does when VIN = 0.8 V,
should be idled low
SYNC
between write sequences for even lower power operation of the
part, as mentioned above. However, it must be brought high
again just before the next write sequence.
INPUT SHIFT REGISTER
R
R
The input shift register is 16 bits wide (see Figure 26). The first
two bits are control bits that determine the part’s mode of
operation (normal mode or any one of three power-down
modes). For a complete description of the various modes, see
the Power-Down Modes section. The next 16 bits are the data
bits, which are transferred to the DAC register on the
16th falling edge of SCLK.
TO OUTPUT
AMPLIFIER
R
DB15 (MSB)
DB0 (LSB)
PD1
PD0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R
R
DATA BITS
NORMAL OPERATION
0
0
1
1
0
1
0
1
1 kΩ TO GND
100 kΩ TO GND
POWER-DOWN MODES
THREE-STATE
Figure 25. Resistor String Section
Figure 26. Input Register Contents
Rev. PrD | Page 12 of 20
Preliminary Technical Data
AD5641
SCLK
SYNC
DB15
DB0
DB16
DB0
DIN
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 16TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16TH FALLING EDGE
SYNC
Figure 27.
Interrupt Facility
the part is in power-down mode. There are three different
options: the output is connected internally to GND through a
1 kΩ resistor or a 100 kΩ resistor, or the output is left open-
circuited (three-state). Figure 28 shows the output stage.
INTERRUPT
SYNC
In a normal write sequence, the
line is kept low for at
SYNC
least 16 falling edges of SCLK and the DAC is updated on the
16th falling edge. However, if
is brought high before the
SYNC
16th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 27).
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
POWER-DOWN
CIRCUITRY
POWER-ON RESET
RESISTOR
NETWORK
The AD5641 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
zeros and the output voltage is 0 V. It remains there until a valid
write sequence is made to the DAC. This is useful in applica-
tions in which it is important to know the state of the DAC’s
output while it is in the process of powering up.
Figure 28. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are all shut down when the power-
down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
power-down is typically 2.5 µs for VDD = 5 V and 5 µs for
POWER-DOWN MODES
The AD5641 have four separate modes of operation. These
modes are software-programmable by setting two bits (DB15
and DB14) in the control register. Table 6 shows how the state
of the bits corresponds to the mode of operation of the device.
V
DD = 3 V. See Figure 20 for a plot.
MICROPROCESSOR INTERFACING
AD5641 to ADSP-2101/ADSP-2103 Interface
Table 6. Modes of Operation for the AD5641
Figure 29 shows a serial interface between the AD5641 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in SPORT transmit alternate framing mode.
The ADSP-2101/ADSP-2103 SPORT is programmed through
the SPORT control register and should be configured as follows:
internal clock operation, active low framing, and 16-bit word
length. Transmission is initiated by writing a word to the Tx
register after the SPORT has been enabled.
DB15
DB14
Operating Mode
Normal operation
Power-down mode
1 kΩ to GND
100 kΩ to GND
Three-state
0
0
0
1
1
1
0
1
When both bits are set to 0, the part works normally with its
normal power consumption of 100 µA maximum at 5 V.
However, for the three power-down modes, the supply current
ADSP-2101/ꢁ
AD5641*
ADSP-2103*
falls to <100 nA at 3 V. Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
TFS
DT
SYNC
DIN
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLAIRTY
Figure 29. AD5641 to ADSP-2101/ADSP-2103 Interface
Rev. PrD | Page 13 of 20
AD5641
Preliminary Technical Data
AD5641 to 68HC11/68L11 Interface
AD5641 to 80C51/80L51 Interface
Figure 30 shows a serial interface between the AD5641 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5641, while the MOSI output drives
Figure 32 shows a serial interface between the AD5641 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TXD of the 80C51/80L51 drives SCLK of the AD5641,
the serial data line of the DAC. The
signal is derived
while RXD drives the serial data line of the part. The
SYNC
SYNC
from a port line (PC7). The setup conditions for correct
operation of this interface are as follows: the 68HC11/68L11
should be configured so that its CPOL bit is a 0 and its CPHA
signal is again derived from a bit programmable pin on the port.
In this case, port line P3.3 is used. When data is to be transmit-
ted to the AD5641, P3.3 is taken low.
bit is a 1. When data is being transmitted to the DAC, the
SYNC
The 80C51/80L51 transmits data only in 8-bit bytes; therefore,
only eight falling clock edges occur in the transmit cycle. To
load data to the DAC, P3.3 is left low after the first eight bits are
transmitted, and a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion
of this cycle. The 80C51/80L51 outputs the serial data in a
format that has the LSB first. The AD5641 requires its data with
the MSB as the first bit received. The 80C51/80L51 transmit
routine should take this into account.
line is taken low (PC7). When the 68HC11/68L11 is configured
as above, data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11/68L11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
To load data to the AD5641, PC7 is left low after the first eight
bits are transferred, and a second serial write operation is
performed to the DAC. PC7 is taken high at the end of this
procedure.
AD5641*
80C51/80L51*
68HC11/
68L11
AD5641*
P3.3
TXD
RXD
SYNC
SCLK
DIN
PC7
SCK
SYNC
SCLK
DIN
MOSI
*ADDITIONAL PINS OMITTED FOR CLAIRTY
*ADDITIONAL PINS OMITTED FOR CLAIRTY
Figure 32. AD5641 to 80C51/80L51 Interface
Figure 30. AD5641 to 68HC11/68L11 Interface
AD5641 to MICROWIRE Interface
AD5641 to Blackfin® ADSP-BF53X Interface
Figure 33 shows an interface between the AD5641 and any
MICROWIRE compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5641 on the rising edge of the SK.
Figure 31 shows a serial interface between the AD5641 and the
Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5641, the setup for the interface is as follows: DT0PRI
drives the SDIN pin of the AD5641, while TSCLK0 drives the
AD5641*
MICROWIRE*
SCLK of the part. The
is driven from TFS0.
SYNC
CS
SK
SO
SYNC
SCLK
DIN
AD5641
ADSP-BF53X
DT0PRI
TSCLK0
TFS0
DIN
*ADDITIONAL PINS OMITTED FOR CLAIRTY
SCLK
SYNC
Figure 33. AD5641 to MICROWIRE Interface
*ADDITIONAL PINS OMITTED FOR CLAIRTY
Figure 31. AD5641 to Blackfin ADSP-BF53X Interface
Rev. PrD | Page 14 of 20
Preliminary Technical Data
APPLICATIONS
AD5641
CHOOSING A REFERENCE AS POWER SUPPLY FOR
AD5641
BIPOLAR OPERATION USING THE AD5641
The AD5641 has been designed for single-supply operation, but
a bipolar output range is also possible using the circuit in
Figure 35. The circuit in Figure 35 gives an output voltage range
of 5 V. Rail-to-rail operation at the amplifier output is
achievable using an AD820 or OP295 as the output amplifier.
The AD5641 comes in a tiny SC70 package with less than a
100 µA supply current. Because of this, the choice of reference
depends on the application requirements. For space-saving
applications, the ADR425 is available in an SC70 package and
has excellent drift at 3 ppm/°C. It also provides very good noise
performance at 3.4 µV p-p in the 0.1 Hz to 10 Hz range.
The output voltage for any input code can be calculated as
follows:
Because the supply current required by the AD5641 is
extremely low, it is ideal for low supply applications. The
ADR293 voltage reference is recommended in this case. This
requires 15 µA of quiescent current and can, therefore, drive
multiple DACs in one system, if required.
D
16384
R1+ R2
R1
R2
R1
⎡
⎤
⎛
⎜
⎝
⎞ ⎛
⎠ ⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
VO = VDD
×
×
−V
×
DD
⎟ ⎜
⎢
⎥
⎣
⎦
where D represents the input code in decimal (0 – 16384). With
DD = 5 V, R1 = R2 = 10 kΩ:
V
7V
10×D
16384
5V
⎛
⎜
⎝
⎞
⎟
⎠
VO
=
−5V
ADR425
This is an output voltage range of 5 V with 0x0000 corre-
sponding to a –5 V output, and 0x3FFF corresponding to a
+5 V output.
SYNC
3-WIRE
SERIAL
INTERFACE
V
= 0V TO 5V
OUT
SCLK
DIN
AD5641
R2 = 10kΩ
+5V
Figure 34. ADR425 as Power Supply to AD5641
+5V
R1 = 10kΩ
Some recommended precision references for use as supplies to
the AD5641 are listed in Table 7.
AD820/
OP295
5V
V
V
OUT
DD
Table 7. Precision References for Use with AD5641
10µF
0.1µF
AD5641
–5V
Initial
Temperature
Part
No.
Accuracy Drift
(mV max) (ppm/°C max)
0.1 Hz to 10 Hz
Noise (µV p-p typ)
3-WIRE
SERIAL
INTERFACE
ADR435
ADR425
ADR02
6
6
5
6
3
3
3
25
3.4
3.4
15
5
Figure 35. Bipolar Operation with the AD5641
ADR395
Rev. PrD | Page 15 of 20
AD5641
Preliminary Technical Data
USING AD5641 WITH AN OPTO-ISOLATED
INTERFACE
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5641 should
have separate analog and digital sections, each having its own
area of the board. If the AD5641 is in a system where other
devices require an AGND to DGND connection, the
In process-control applications in industrial environments, it is
often necessary to use an opto-isolated interface to protect and
isolate the controlling circuitry from any hazardous common-
mode voltages that might occur in the area where the DAC is
functioning. Opto-isolators provide isolation in excess of 3 kV.
Because the AD5641 uses a 3-wire serial logic interface, it
requires only three opto-isolators to provide the required
isolation (see Figure 36). The power supply to the part also
needs to be isolated. This is done by using a transformer. On the
DAC side of the transformer, a 5 V regulator provides the 5 V
supply required for the AD5641.
connection should be made at one point only. This ground
point should be as close to the AD5641 as possible.
The power supply to the AD5641 should be bypassed with
10 µF and 0.1 µF capacitors. The capacitors should be physically
as close as possible to the device, with the 0.1 µF capacitor
ideally right up against the device. The 10 µF capacitors are the
tantalum bead type. It is important that the 0.1 µF capacitor
have low effective series resistance (ESR) and effective series
inductance (ESI), such as in common ceramic types of capaci-
tors. This 0.1 µF capacitor provides a low impedance path to
ground for high frequencies caused by transient currents due to
internal logic switching.
+5V
REGULATOR
10µF
0.1µF
POWER
V
DD
10kΩ
V
DD
SCLK
SCLK
SYNC
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals,
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
AD5641
V
DD
10kΩ
10kΩ
V
OUT
SYNC
DATA
V
DD
DIN
GND
Figure 36. AD5641 with an Opto-Isolated Interface
Rev. PrD | Page 16 of 20
Preliminary Technical Data
OUTLINE DIMENSIONS
AD5641
2.00 BSC
4
2.10 BSC
1.25 BSC
PIN 1
1.30 BSC
0.65 BSC
1.00
0.90
0.70
1.10 MAX
0.22
0.08
0.46
0.36
0.26
8°
4°
0°
0.30
0.15
0.10 MAX
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203AB
Figure 37. 6-Lead Plastic Surface Mount Package [SC70]
(KS-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Description
Package Description
6-Lead Plastic Surface Mount Package (SC70)
Package Option
KS-6
AD5641AKS
–40°C to +125°C
16 LSB INL
Rev. PrD | Page 17 of 20
AD5641
NOTES
Preliminary Technical Data
Rev. PrD | Page 18 of 20
Preliminary Technical Data
NOTES
AD5641
Rev. PrD | Page 19 of 20
AD5641
NOTES
Preliminary Technical Data
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04611-0-11/04(PrD)
Rev. PrD | Page 20 of 20
相关型号：
AD5643RBRMZ-3
SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 14-BIT DAC, PDSO10, ROHS COMPLIANT, MO-187BA, MSOP-10
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