AD5259BCPZ10-R7 [ADI]
Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer; 非易失， I2C兼容256位，数字电位器
| 型号： | AD5259BCPZ10-R7 |
| 厂家： | 
ADI |
| 描述： | Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer |
| 文件： | 总24页 (文件大小：989K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Nonvolatile, I2C-Compatible
256-Position, Digital Potentiometer
AD5259
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Nonvolatile memory maintains wiper settings
256-position
Thin LFCSP-10 (3 mm x 3 mm x 0.8 mm) package
Compact MSOP-10 (3 mm × 4.9 mm x 1.1mm) package
I2C®-compatible interface
VLOGIC pin provides increased interface flexibility
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Resistance tolerance stored in EEPROM (0.1% accuracy)
Power-on EEPROM refresh time < 1ms
Software write protect command
RDAC
V
DD
A
RDAC
V
RDAC
LOGIC
EEPROM
W
B
REGISTER
GND
8
8
DATA
CONTROL
SCL
SDA
2
I C
SERIAL
INTERFACE
AD0
AD1
COMMAND
DECODE LOGIC
AD5259
ADDRESS
DECODE LOGIC
POWER-
ON RESET
CONTROL LOGIC
Address Decode Pin AD0 and Pin AD1 allow
4 packages per bus
Figure 1. Block Diagram
100-year typical data retention at 55°C
Wide operating temperature −40°C to +85°C
3 V to 5 V single supply
V
V
DD
LOGIC
A
EEPROM
SCL
RDAC
REGISTER
AND
APPLICATIONS
2
I
C
SDA
AD0
AD1
SERIAL
INTERFACE
LEVEL
LCD panel VCOM adjustment
SHIFTER
W
LCD panel brightness and contrast control
Mechanical potentiometer replacement in new designs
Programmable power supplies
RF amplifier biasing
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
CONTROL
LOGIC
GND
B
Automotive electronics adjustment
Gain control and offset adjustment
Fiber to the home systems
Figure 2. Block Diagram Showing Level Shifters
Electronics level settings
CONNECTION DIAGRAM
GENERAL DESCRIPTION
W
AD0
AD1
SDA
SCL
1
2
3
4
5
10
9
A
B
V
The AD5259 provides a compact, nonvolatile LFCSP-10
(3 mm × 3 mm) or MSOP-10 (3 mm × 4.9 mm) packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function
as mechanical potentiometers1 or variable resistors, but
with enhanced resolution and solid-state reliability.
AD5259
8
TOP VIEW
DD
(Not to Scale)
7
GND
6
V
LOGIC
Figure 3. Pinout
The wiper settings are controllable through an I2C-compatible
digital interface that is also used to read back the wiper register
and EEPROM content. Resistor tolerance is also stored within
EEPROM, providing an end-to-end tolerance accuracy of 0.1%.
1 The terms digital potentiometer, VR (variable resistor), and RDAC are used
interchangeably.
A separate VLOGIC pin delivers increased interface flexibility. For
users who need multiple parts on one bus, Address Bit AD0 and
Address Bit AD1 allow up to four devices on the same bus.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD5259
TABLE OF CONTENTS
Specifications..................................................................................... 3
I2C-Compatible Format ................................................................. 16
Generic Interface........................................................................ 16
Write Modes ................................................................................ 16
Read Modes................................................................................. 17
Store/Restore Modes .................................................................. 17
Tolerance Readback Modes ...................................................... 18
ESD Protection of Digital Pins and Resistor Terminals........ 19
Power-Up Sequence ................................................................... 19
Layout and Power Supply Bypassing ....................................... 19
Multiple Devices on One Bus ................................................... 19
Evaluation Board........................................................................ 19
Display Applications ...................................................................... 20
Circuitry ...................................................................................... 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
Electrical Characteristics............................................................. 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 13
Theory of Operation ...................................................................... 14
Programming the Variable Resistor......................................... 14
Programming the Potentiometer Divider............................... 14
I2C-Compatible Interface............................................................... 15
Writing ......................................................................................... 15
Storing/Restoring ....................................................................... 15
Reading ........................................................................................ 15
REVISION HISTORY
7/05 — Rev. 0 to Rev. A
Added 10-Lead LFCSP.......................................................Universal
Changes to Features Section and
General Description Section........................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2 and Added Figure 4........................................ 5
Changes to Table 4............................................................................ 7
Changes to Figure 27 Caption....................................................... 11
Changes to Theory of Operation Section.................................... 14
Changes to I2C-Compatible Interface Section............................ 15
Changes to Table 5.......................................................................... 16
Changes to Multiple Devices on One Bus Section..................... 19
Updated Figure 49 Caption........................................................... 21
Changes to Ordering Guide .......................................................... 21
2/05 — Revision 0: Initial Version
Rev. A | Page 2 of 24
AD5259
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = VLOGIC = 5 V 10% or 3 V 10%ꢀ VA = VDDꢀ VB = 0 Vꢀ −40°C < TA < +85°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS:
RHEOSTAT MODE
Resistor Differential Nonlinearity
R-DNL
RWB, VA = no connect
LSB
5 kΩ
1± kΩ
5± kΩ/1±± kΩ
–1
−1
−±.5
±±.2
±±.1
±±.1
+1
+1
+±.5
Resistor Integral Nonlinearity
5 kΩ
1± kΩ
5± kΩ/1±± kΩ
Nominal Resistor Tolerance
Resistance Temperature Coefficient
R-INL
RWB, VA = no connect
LSB
–4
±±.3
±±.2
±±.4
+4
+2
+1
+3±
−2
−1
–3±
ΔRAB
(ΔRAB x 1±6)/
(RAB x ΔT)
TA = 25°C, VDD = 5.5 V
Code = ±x±±/±x8±
%
5±±/15
75
ppm/°C
Total Wiper Resistance
RWB
Code = ±x±±
35±
Ω
DC CHARACTERISTICS:
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity
5 kΩ
1± kΩ
5± kΩ/1±± kΩ
Integral Nonlinearity
5 kΩ
DNL
LSB
–1
−±.5
−±.5
±±.2
±±.1
±±.2
+1
+±.5
+±.5
INL
LSB
–1
−±.5
−±.5
±±.2
±±.1
±±.1
+1
+±.5
+±.5
1± kΩ
5± kΩ/1±± kΩ
Full-Scale Error
5 kΩ
VWFSE
Code = ±xFF
LSB
−7
−4
−1
−3
−1.5
−±.4
±
±
±
1± kΩ
5± kΩ/1±± kΩ
Zero-Scale Error
5 kΩ
1± kΩ
5± kΩ/1±± kΩ
VWZSE
Code = ±x±±
LSB
±
±
±
2.5
1
±.2
6±/5
4
3
±.5
Voltage Divider Temperature
Coefficient
(∆VW x 1±6)/
(VW x ∆T)
Code = ±x±±/±x8±
ppm/°C
RESISTOR TERMINALS
Voltage Range
Capacitance A, B
VA, B, W
CA, B
GND
VDD
V
pF
f = 1 MHz, measured to GND,
code = ±x8±
f = 1 MHz, measured to GND,
code = ±x8±
45
6±
1±
Capacitance W
CW
ICM
pF
Common-Mode Leakage
VA = VB = VDD/2
nA
Rev. A | Page 3 of 24
AD5259
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Leakage Current
SDA, AD±, AD1
VIH
VIL
IIL
±.7 × VL
−±.5
VL + ±.5
±.3 × VL
V
V
μA
VIN = ± V or 5 V
VIN = ± V
VIN = 5 V
±.±1
−1.3
±.±1
5
±1
+1
±1
SCL – Logic High
SCL – Logic Low
−2.5
Input Capacitance
POWER SUPPLIES
Power Supply Range
Positive Supply Current
Logic Supply
CIL
pF
VDD
IDD
VLOGIC
ILOGIC
2.7
2.7
5.5
2
5.5
6
V
μA
V
±.1
Logic Supply Current
Programming Mode Current (EEPROM) ILOGIC(PROG)
Power Dissipation
Power Supply Rejection Ratio
DYNAMIC CHARACTERISTICS
Bandwidth −3 dB
VIH = 5 V or VIL = ± V
VIH = 5 V or VIL = ± V
VIH = 5 V or VIL = ± V, VDD = 5 V
VDD = +5 V ± 1±%, code = ±x8±
3
35
15
±±.±±5
μA
mA
μW
%/%
PDISS
PSRR
4±
±±.±6
BW
Code = ±x8±
RAB = 5 kΩ
RAB = 1± kΩ
RAB = 5± kΩ
RAB = 1±± kΩ
RAB = 1± kΩ, VA = 1 V rms,
VB = ±, f = 1 kHz
RAB = 1± kΩ, VAB = 5 V,
±1 LSB error band
2±±±
8±±
16±
8±
kHz
kHz
kHz
kHz
%
Total Harmonic Distortion
VW Settling Time
THDW
tS
±.±1
5±±
9
ns
Resistor Noise Voltage Density
eN_WB
RWB = 5 kΩ, f = 1 kHz
nV/√Hz
1 Typical values represent average readings at 25°C and VDD = 5 V.
Rev. A | Page 4 of 24
AD5259
TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V 10% or 3 V 10%ꢀ VA = VDDꢀ VB = 0 Vꢀ −40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
I2C INTERFACE TIMING
CHARACTERISTICS1
SCL Clock Frequency
tBUF Bus Free Time Between Stop
and Start
fSCL
t1
±
1.3
4±±
kHz
μs
tHD;STA Hold Time (Repeated Start)
t2
After this period, the first clock pulse is
generated.
±.6
μs
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Repeated
Start Condition
t3
t4
t5
1.3
±.6
±.6
μs
μs
μs
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and
SCL Signals
tR Rise Time of Both SDA and
SCL Signals
t6
t7
t8
±
1±±
±.9
μs
ns
ns
3±±
3±±
t9
ns
tSU;STO Setup Time for Stop Condition
EEPROM Data Storing Time
EEPROM Data Restoring Time at
Power On2
t1±
±.6
μs
ms
μs
tEEMEM_STORE
26
3±±
tEEMEM_RESTORE1 VDD rise time dependent. Measure without
decoupling capacitors at VDD and GND.
EEPROM Data Restoring Time upon
tEEMEM_RESTORE2 VDD = 5 V.
3±±
54±
μs
μs
Restore Command2
EEPROM Data Rewritable Time3
FLASH/EE MEMORY RELIABILITY
Endurance4
tEEMEM_REWRITE
1±±
7±±
1±±
kCycles
Years
Data Retention5
1 Standard I2C mode operation guaranteed by design.
2 During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
3 Delay time after power-on PRESET prior to writing new EEPROM data.
4 Endurance is qualified to 1±±,±±± cycles per JEDEC Std. 22 method A117, and is measured at –4±°C, +25°C, and +85°C; typical endurance at +25°C is 7±±,±±± cycles.
5 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of ±.6 eV derates
with junction temperature.
t2
t8
t6
t9
SCL
SDA
t10
t4
t7
t5
t2
t3
t9
t8
t1
P
S
S
P
Figure 4. I2C Interface Timing Diagram
Rev. A | Page 5 of 24
AD5259
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating onlyꢀ functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
VDD, VLOGIC to GND
VA, VB, VW to GND
IMAX
Value
−±.3 V to +7 V
GND − ±.3 V, VDD + ±.3 V
Pulsed1
±2± mA
±5 mA
Continuous
Digital Inputs and Output Voltage
to GND
± V to 7 V
Operating Temperature Range
−4±°C to +85°C
Maximum Junction Temperature
15±°C
(TJMAX
)
Storage Temperature
−65°C to +15±°C
Lead Temperature
(Soldering, 1± sec)
Thermal Resistance2
3±±°C
θJA: MSOP–1±
2±±°C/W
1 Maximum terminal current is bounded by the maximum current handling
of the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 24
AD5259
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
W
AD0
AD1
SDA
SCL
1
2
3
4
5
10
A
B
V
9
AD5259
8
TOP VIEW
DD
(Not to Scale)
7
GND
6
V
LOGIC
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin
Mnemonic
Description
W Terminal, GND ≤ VW ≤ VDD
1
W
.
2
3
4
5
6
7
8
ADO
AD1
SDA
SCL
VLOGIC
GND
VDD
Programmable Pin ± for Multiple Package Decoding. State is registered on power-up.
Programmable Pin 1 for Multiple Package Decoding. State is registered on power-up.
Serial Data Input/Output.
Serial Clock Input. Positive edge triggered.
Logic Power Supply.
Digital Ground.
Positive Power Supply.
9
B
B Terminal, GND ≤ VB ≤ VDD
.
1±
A
A Terminal, GND ≤ VA ≤ VDD.
Rev. A | Page 7 of 24
AD5259
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = VLOGIC = 5.5 V, RAB = 10 kΩ, TA = +25°Cꢀ unless otherwise noted.
1.5
0.25
0.20
0.15
0.10
0.05
0
1.3
2.7V
1.1
0.9
0.7
0.5
0.3
–0.05
–0.10
–0.15
–0.20
–0.25
0.1
–40°C
+25°C
–0.1
–0.3
+85°C
5.5V
–0.5
0
32
64
96
128
160
192
224
256
0
0
0
32
64
96
128
160
192
224
224
224
256
256
256
CODE (Decimal)
CODE (Decimal)
Figure 6. R-INL vs. Code vs. Supply Voltage
Figure 9. DNL vs. Code vs. Temperature
0.5
0.4
0.25
0.20
0.15
0.10
0.05
0
2.7V
0.3
0.2
2.7V
5.5V
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.05
–0.10
–0.15
–0.20
–0.25
5.5V
0
32
64
96
128
160
192
224
256
32
64
96
128
160
192
CODE (Decimal)
CODE (Decimal)
Figure 7. R-DNL vs. Code vs. Supply Voltage
Figure 10. INL vs. Supply Voltages
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
0.15
0.10
0.05
0
2.7V
5.5V
T
= +85°C
A
–0.05
–0.10
–0.15
–0.20
–0.25
–0.05
–0.10
–0.15
–0.20
–0.25
T
= +25°C
T
= –40°C
A
A
0
32
64
96
128
160
192
224
256
32
64
96
128
160
192
CODE (Decimal)
CODE (Decimal)
Figure 8. INL vs. Code vs. Temperature
Figure 11. DNL vs. Code vs. Supply Voltage
Rev. A | Page 8 of 24
AD5259
0.5
0.4
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.3
ZSE @ V = 2.7V
DD
0.2
0.1
+25°C
–40°C
0
ZSE @ V = 5.5V
DD
–0.1
–0.2
–0.3
–0.4
–0.5
+85°C
160 192
–40
–20
0
20
40
60
80
0
32
64
96
128
224
256
TEMPERATURE (°C)
CODE (Decimal)
Figure 12. R-INL vs. Code vs. Temperature
Figure 15. Zero-Scale Error vs. Temperature
1
0.5
0.4
0.3
T
= –40°C
A
0.2
T
= +85°C
A
0.1
0
V
= 5.5V
DD
–0.1
–0.2
–0.3
–0.4
–0.5
T
= +25°C
A
0.1
–40
–20
0
20
40
60
80
0
32
64
96
128
160
192
224
256
TEMPERATURE (°C)
CODE (Decimal)
Figure 13. R-DNL vs. Code vs. Temperature
Figure 16. Supply Current vs. Temperature
6
5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
4
V
= 5.5V
DD
3
FSE @ V = 5.5V
DD
2
1
FSE @ V = 2.7V
DD
V
= 2.7V
DD
0
–1
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Logic Supply Current vs. Temperature vs. VDD
Figure 14. Full-Scale Error vs. Temperature
Rev. A | Page 9 of 24
AD5259
400
300
100kΩ
50kΩ
120
100
80
60
40
20
0
100kΩ Rt @ V = 5.5V
DD
200
10kΩ
100
0
50kΩ Rt @ V = 5.5V
DD
–100
–200
–300
–400
–500
10kΩ Rt @ V = 5.5V
DD
5kΩ
5kΩ Rt @ V = 5.5V
DD
–600
0
–40
–20
0
20
40
60
80
32
64
96
128
160
192
224
256
TEMPERATURE (°C)
CODE (Decimal)
Figure 18. Rheostat Mode Tempco (ΔRAB x 106)/(RAB x ΔT) vs. Code
Figure 21. Total Resistance vs. Temperature
0
–6
70
60
50
40
80
40
H
H
H
–12
–18
–24
–30
–36
–42
–48
–54
–60
20
10
08
H
H
30
10kΩ
20
100kΩ
04
02
H
10
0
H
01
H
–10
–20
5kΩ
50kΩ
–30
–40
1k
10k
100k
1M
10M
0
32
64
96
128
160
192
224
256
CODE (Decimal)
FREQUENCY (Hz)
Figure 19. Potentiometer Mode Tempco (ΔVW x 106)/(VW x ΔT) vs. Code
Figure 22. Gain vs. Frequency vs. Code, RAB = 5 kΩ
0
–6
350
300
250
80
40
H
H
–12
–18
–24
–30
–36
–42
–48
–54
–60
20
10
H
H
R
@ V = 2.7V
DD
WB
200
150
100
50
08
H
04
02
H
H
01
H
R
@ V = 5.5V
DD
WB
0
–40
1k
10k
100k
1M
10M
–20
0
20
40
60
80
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 23. Gain vs. Frequency vs. Code, RAB = 10 kΩ
Figure 20. RWB vs. Temperature
Rev. A | Page 1± of 24
AD5259
0
–6
10k
1k
80
40
H
H
–12
–18
–24
–30
–36
–42
–48
–54
–60
20
10
08
H
H
H
V
= V = 5V
LOGIC
DD
04
H
V
= V
= 3V
LOGIC
DD
02
01
H
H
100
10
1k
10k
100k
1M
0
1
2
3
4
5
V
(V)
FREQUENCY (Hz)
IH
Figure 24. Gain vs. Frequency vs. Code, RAB = 50 kΩ
Figure 27. Logic Supply Current vs. Input Voltage
0
–6
80
60
40
20
0
80
40
H
H
H
CODE = MIDSCALE, V = V
, V = 0V
LOGIC
A
B
–12
–18
–24
–30
–36
–42
–48
–54
–60
PSRR @ V
LOGIC
= 5V DC ± 10% p-p AC
20
10
08
H
H
PSRR @ V
LOGIC
= 3V DC ± 10% p-p AC
04
02
01
H
H
H
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25. Gain vs. Frequency vs. Code, RAB = 100 kΩ
Figure 28. PSRR vs. Frequency
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
100kΩ
80kHz
50kΩ
160kHz
V
W
10kΩ
800kHz
1
5kΩ
2MHz
SCL
2
1k
10k
100k
1M
10M
FREQUENCY (Hz)
400ns/DIV
Figure 26. −3 dB Bandwidth @ Code = 0×80
Figure 29. Digital Feedthrough
Rev. A | Page 11 of 24
AD5259
V
V
W
W
1
1
SCL
2
1μs/DIV
200ns/DIV
Figure 31. Large Signal Settling Time
Figure 30. Midscale Glitch, Code 0×7F to 0×80
Rev. A | Page 12 of 24
AD5259
TEST CIRCUITS
Figure 32 through Figure 37 illustrate the test circuits that define the test conditions used in the product Specifications tables.
V
A
V+ = V
±
10%
DD
ΔV
ΔV
MS
)
V+ = V
1LSB = V+/2
DUT
W
DD
DUT
W
PSRR (dB) = 20 LOG
(
%
N
DD
ΔV
ΔV
A
B
A
MS
ΔV
PSS (%/%) =
DD
%
DD
V+
V+
B
V
V
MS
MS
Figure 32. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 35. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
NO CONNECT
DUT
DUT
+5V
A
W
I
W
A
V
W
IN
AD8610
–5V
V
B
OUT
OFFSET
GND
B
V
MS
+2.5V
Figure 33. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
Figure 36. Test Circuit for Gain vs. Frequency
0.1V
R
=
SW
I
SW
DUT
CODE = 0x00
DUT
W
I
= V /R
DD NOMINAL
W
A
B
V
W
W
I
SW
0.1V
V
MS2
B
R
= [V
– V
]/I
W
MS1
MS2 W
V
MS1
GND TO V
DD
Figure 34. Test Circuit for Wiper Resistance
Figure 37. Test Circuit for Common-Mode Leakage Current
Rev. A | Page 13 of 24
AD5259
THEORY OF OPERATION
The AD5259 is a 256-position digitally-controlled variable
resistor (VR) device. EEPROM is pre-loaded at midscale from
the factory, and initial power-up is, accordingly, at midscale.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A produces a digitally
controlled complementary resistance, RWA. The resistance value
setting for RWA starts at a maximum value of resistance and
decreases as the data loaded in the latch increases in value.
The general equation for this operation is
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance (RAB) of the RDAC between Terminal A
and Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.
The nominal resistance of the VR has 256 contact points accessed
by the wiper terminal. The 8-bit data in the RDAC latch is
decoded to select one of 256 possible settings.
256 − D
256
RWA(D) =
× RAB + 2× RW
(2)
Typical device-to-device matching is process lot dependent and
may vary by up to 30%. For this reason, resistance tolerance is
stored in the EEPROM, enabling the user to know the actual
RAB within 0.1%.
A
A
A
W
W
W
PROGRAMMING THE POTENTIOMETER DIVIDER
B
B
B
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
Wiper W to Terminal B and Wiper W to Terminal A propor-
tional to the input voltage at Terminal A to Terminal B. Unlike
the polarity of VDD to GND, which must be positive, voltage
across Terminal A to Terminal B, Wiper W to Terminal A, and
Wiper W to Terminal B can be at either polarity.
Figure 38. Rheostat Mode Configuration
The general equation determining the digitally programmed
output resistance between Wiper W and Terminal B is
D
256
RWB(D) =
× RAB + 2× RW
(1)
V
I
A
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
W
V
O
RAB is the end-to-end resistance.
B
RW is the wiper resistance contributed by the ON resistance of
each internal switch.
Figure 40. Potentiometer Mode Configuration
A
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at Wiper W to Terminal B starting
at 0 V up to 1 LSB less than 5 V. The general equation defining
the output voltage at VW with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
R
S
R
R
D7
D6
D5
D4
D3
D2
D1
D0
S
S
D
256
256 − D
256
W
VW (D) =
VA +
VB
(3)
A more accurate calculation, which includes the effect of wiper
resistance, VW, is
R
RDAC
S
LATCH
AND
DECODER
R
WB (D)
RAB
RWA(D)
RAB
(4)
VW (D) =
VA +
VB
B
Figure 39. AD5259 Equivalent RDAC Circuit
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly
on the ratio of the Internal Resistors RWA and RWB and not
the absolute values.
In the zero-scale condition, there is a relatively low value finite
wiper resistance. Care should be taken to limit the current flow
between Wiper W and Terminal B in this state to a maximum
pulse current of no more than 20 mA. Otherwise, degradation
or destruction of the internal switch contact can occur.
Rev. A | Page 14 of 24
AD5259
I2C-COMPATIBLE INTERFACE
The master initiates data transfer by establishing a start condi-
tion, which is when a high-to-low transition on the SDA line
occurs while SCL is high (see Figure 4). The next byte is the
slave address byte, which consists of the slave address (first
READING
Assuming the register of interest was not just written to, it is
necessary to write a dummy address and instruction byte. The
instruction byte will vary depending on whether the data that
is wanted is the RDAC register, EEPROM register, or tolerance
register (see Table 11 and Table 16).
7 bits) followed by an R/ bit (see Table 6). When the R/ bit
W
W
is high, the master reads from the slave device. When the R/
bit is low, the master writes to the slave device.
W
After the dummy address and instruction bytes are sent, a repeat
start is necessary. After the repeat start, another address byte is
needed, except this time the R/ bit is logic high. Following this
address byte is the readback byte containing the information
requested in the instruction byte. Read bits appear on the nega-
tive edges of the clock.
The slave address of the part is determined by two configurable
address pins, Pin AD0 and Pin AD1. The state of these two pins
is registered upon power-up and decoded into a corresponding
I2C 7-bit address (see Table 5). The slave address corresponding
to the transmitted address bits responds by pulling the SDA
line low during the ninth clock pulse (this is termed the slave
acknowledge bit). At this stage, all other devices on the bus
remain idle while the selected device waits for data to be
written to, or read from, its serial register.
W
The tolerance register can be read back individually (see
Table 15) or consecutively (see Table 16). Refer to the Read
Modes section for detailed information on the interpretation
of the tolerance bytes.
WRITING
After all data bits have been read or written, a stop condition is
established by the master. A stop condition is defined as a low-to-
high transition on the SDA line while SCL is high. In write mode,
the master pulls the SDA line high during the tenth clock pulse
to establish a stop condition (see Figure 46). In read mode, the
master issues a no acknowledge for the ninth clock pulse (that is,
the SDA line remains high). The master then brings the SDA line
low before the tenth clock pulse, and then raises SDA high to
establish a stop condition (see Figure 47).
In the write mode, the last bit (R/ ) of the slave address byte is
W
logic low. The second byte is the instruction byte. The first three
bits of the instruction byte are the command bits (see Table 6).
The user must choose whether to write to the RDAC register,
EEPROM register, or activate the software write protect (see
Table 7 to Table 10). The final five bits are all zeros (see Table 13
to Table 14). The slave again responds by pulling the SDA line
low during the ninth clock pulse.
The final byte is the data byte MSB first. With the write protect
mode, data is not storedꢀ rather, a logic high in the LSB enables
write protect. Likewise, a logic low disables write protect. The
slave again responds by pulling the SDA line low during the
ninth clock pulse.
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. For example, after the RDAC has acknowl-
edged its slave address and instruction bytes in the write mode,
the RDAC output is updated on each successive byte until a stop
condition is received. If different instructions are needed, the
write/read mode has to start again with a new slave address,
instruction, and data byte. Similarly, a repeated read function
of the RDAC is also allowed.
STORING/RESTORING
In this mode, only the address and instruction bytes are
necessary. The last bit (R/ ) of the address byte is logic
W
low. The first three bits of the instruction byte are the
command bits (see Table 6). The two choices are transfer
data from RDAC to EEPROM (store), or from EEPROM
to RDAC (restore). The final five bits are all zeros (see
Table 13 to Table 14).
Rev. A | Page 15 of 24
AD5259
I2C-COMPATIBLE FORMAT
The following generic, write, read, and store/restore control
registers for the AD5259 all refer to the device addresses listed
in Table 5ꢀ the mode/condition reference key (S, P, SA, MA,
AD1 and AD0 are two-state address pins.
Table 5. Device Address Lookup
AD1 Address Pin
AD0 Address Pin
I2C Device Address
±±11±±±
±±11±1±
1±±11±±
W
NA, , R, and X) is listed below.
±
1
±
1
±
±
1
1
S = Start Condition
P = Stop Condition
1±±111±
SA = Slave Acknowledge
MA = Master Acknowledge
NA = No Acknowledge
W
= Write
R = Read
X = Don’t Care
GENERIC INTERFACE
Table 6. Generic Interface Format
7-Bit Device Address
R/W
S
(See Table 5)
SA C2 C1 C± A4 A3 A2 A1 A± SA D7 D6 D5 D4 D3 D2 D1 D± SA
Instruction Byte Data Byte
P
Slave Address Byte
Table 7. RDAC-to-EEPROM Interface Command Descriptions
C2
C1
C0
Command Description
±
±
±
±
±
1
Operation Between Interface and RDAC.
Operation Between Interface and EEPROM.
±
1
±
Operation Between Interface and Write Protection Register. See Table 1±.
1
±
±
NOP.
1
1
±
1
1
±
Restore EEPROM to RDAC.
Store RDAC to EEPROM.
WRITE MODES
Table 8. Writing to RDAC Register
7-Bit Device Address
S
(See Table 5)
±
SA
SA
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
SA D7 D6 D5 D4 D3 D2 D1 D± SA
Data Byte
P
P
P
Slave Address Byte
Instruction Byte
Table 9. Writing to EEPROM Register
7-Bit Device Address
(See Table 5)
S
±
±
±
1
±
SA D7 D6 D5 D4 D3 D2 D1 D± SA
Data Byte
Slave Address Byte
Instruction Byte
Table 10. Activating/Deactivating Software Write Protect
7-Bit Device Address
(See Table 5)
S
±
SA
±
1
±
±
SA
±
±
±
±
±
±
±
WP SA
Slave Address Byte
Instruction Byte
Data Byte
In order to activate the write protection mode, the WP bit in Table 10 must be logic high. To deactivate the write protection, the
command must be sent again, except with the WP in logic zero state. WP is reset to the deactivated mode if power is cycled off and on.
Rev. A | Page 16 of 24
AD5259
READ MODES
Read modes are referred to as traditional because the first two bytes for all three cases are dummy bytes, which function to place the
pointer towards the correct registerꢀ this is the reason for the repeat start. Theoretically, this step can be avoided if the user reads a register
previously written to. For example, if the EEPROM was just written to, the user can then skip the two dummy bytes and proceed directly
to the slave address byte, followed by the EEPROM readback data.
Table 11. Traditional Readback of RDAC Register Value
7-Bit Device Address
(See Table 5)
7-Bit Device Address
(See Table 5)
S
± SA ± ± ± ± ± ± ± ± SA S
Instruction Byte
1 SA D7 D6 D5 D4 D3 D2 D1 D± NA
Read Back Data
P
Slave Address Byte
Slave Address Byte
↑
Repeat start
Table 12. Traditional Readback of Stored EEPROM Value
7-Bit Device Address
S (See Table 5)
7-Bit Device Address
(See Table 5)
± SA ± ± 1 ± ± ± ± ± SA
Instruction Byte
S
1
SA D7 D6 D5 D4 D3 D2 D1 D± NA P
Read Back Data
Slave Address Byte
Slave Address Byte
↑
Repeat start
STORE/RESTORE MODES
Table 13. Storing RDAC Value to EEPROM
7-Bit Device Address
S
(See Table 5)
±
SA
SA
1
1
±
1
±
±
±
±
±
±
±
±
±
±
SA
SA
P
Slave Address Byte
Instruction Byte
Table 14. Restoring EEPROM to RDAC
7-Bit Device Address
(See Table 5)
S
±
1
±
P
Slave Address Byte
Instruction Byte
Rev. A | Page 17 of 24
AD5259
TOLERANCE READBACK MODES
Table 15. Traditional Readback of Tolerance (Individually)
7-Bit Device Address
7-Bit Device Address
S (See Table 5)
± SA ± ± 1 1 1 1 1 ± SA S (See Table 5)
1 SA D7 D6 D5 D4 D3 D2 D1 D± NA
Sign + Integer Byte
P
Slave Address Byte
Instruction Byte
Slave Address Byte
↑
Repeat start
7-Bit Device Address
S (See Table 5)
7-Bit Device Address
± SA ± ± 1 1 1 1 1 1 SA S (See Table 5)
Instruction Byte Slave Address Byte
1 SA D7 D6 D5 D4 D3 D2 D1 D± NA P
Decimal Byte
Slave Address Byte
↑
Repeat start
Table 16.Traditional Readback of Tolerance (Consecutively)
7-Bit Device
Address
7-Bit Device
Address
S (See Table 5)
± SA ± ± 1 1 1 1 1 ± SA S (See Table 5)
1 SA D7 D6 D5 D4 D3 D2 D1 D± MA D7 D6 D5 D4 D3 D2 D1 D± NA P
Slave Address
Byte
Slave Address
Byte
Sign + Integer Byte
Decimal Byte
Instruction Byte
↑
Repeat start
Calculating RAB Tolerance Stored in Read-Only Memory
A
A
A
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
–6
D1
–7
D0
–8
6
5
4
3
2
1
0
–1
2
–2
2
–3
2
–4
2
–5
2
SIGN
2
2
2
2
2
2
2
2
2
2
SIGN
7 BITS FOR INTEGER NUMBER
8 BITS FOR DECIMAL NUMBER
Figure 41. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions.
(Unit is Percent. Only Data Bytes are Shown.)
In the first memory location, the MSB is designated for the
sign (0 = + and 1= −) and the seven LSBs are designated for
the integer portion of the tolerance. In the second memory
location, all eight data bits are designated for the decimal
portion of tolerance. Note the decimal portion has a limited
accuracy of only 0.1%. For example, if the rated RAB = 10 kΩ
and the data readback from Address 11110 shows 0001 1100,
and Address 11111 shows 0000 1111, then the tolerance can
be calculated as
The AD5259 features a patented RAB tolerance storage in the
nonvolatile memory. The tolerance is stored in the memory
during factory production and can be read by users at any time.
The knowledge of stored tolerance allows users to accurately
calculate RAB. This feature is valuable for precision, rheostat
mode, and open-loop applications where knowledge of abso-
lute resistance is critical.
The stored tolerance resides in the read-only memory and is
expressed as a percentage. The tolerance is stored in two memory
location bytes in sign magnitude binary form (see Figure 41).
MSB: 0 = +
Next 7 MSB: 001 1100 = 28
8 LSB: 0000 1111 = 15 × 2–8 = 0.06
Tolerance = +28.06%
Rounded Tolerance = +28.1% and therefore,
RAB_ACTUAL = 12.810 kΩ
The two EEPROM address bytes are 11110 (sign + integer)
and 11111 (decimal number). The two bytes can be indi-
vidually accessed with two separate commands (see Table 15).
Alternatively, readback of the first byte followed by the second
byte can be done in one command (see Table 16). In the latter
case, the memory pointer will automatically increment from
the first to the second EEPROM location (increments from
11110 to 11111) if read consecutively.
Rev. A | Page 18 of 24
AD5259
ESD PROTECTION OF DIGITAL PINS AND
RESISTOR TERMINALS
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to use compact, minimum lead length layout
design. The leads to the inputs should be as direct as possible
with minimum conductor length. Ground paths should have
low resistance and low inductance.
The AD5259 VDD, VLOGIC, and GND power supplies define the
boundary conditions for proper 3-terminal and digital input
operation. Supply signals present on Terminal A, Terminal B,
and Terminal W that exceed VDD or GND are clamped by the
internal forward biased ESD protection diodes (see Figure 42).
Digital Input SCL and Digital Input SDA are clamped by ESD
protection diodes with respect to VLOGIC and GND as shown in
Figure 43.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disc or chip ceramic capaci-
tors of 0.01 μF to 0.1 μF. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 44). The digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.
V
DD
A
W
B
V
V
DD
DD
+
GND
C2
C1
10μF
0.1μF
AD5259
Figure 42. Maximum Terminal Voltages Set by VDD and GND
V
LOGIC
GND
SCL
SDA
Figure 44. Power Supply Bypassing
MULTIPLE DEVICES ON ONE BUS
GND
The AD5259 has two configurable address pins, Pin AD0 and
Pin AD1. The state of these two pins is registered upon power-
up and decoded into a corresponding I2C-compatible 7-bit
address (see Table 5). This allows up to four devices on the bus
to be written to or read from independently.
Figure 43. Maximum Terminal Voltages Set by VLOGIC and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 42), it
is important to power GND/VDD/VLOGIC before applying any
voltage to Terminal A, Terminal B, and Terminal Wꢀ otherwise,
the diode is forward biased, so the VDD and VLOGIC are powered
unintentionally and may affect the user’s circuit. The ideal power-
up sequence is in the following order: GND, VDD, VLOGIC, digital
inputs, and then VA, VB, VW. The relative order of powering
VA, VB, VW, and the digital inputs is not important as long as
EVALUATION BOARD
An evaluation board, with all necessary software, is available
to program the AD5259 from any PC running Windows® 98/
2000/ XP. The graphical user interface, as shown in Figure 45,
is straightforward and easy to use. More detailed information
is available in the board’s user manual.
they are powered after GND/VDD/VLOGIC
.
Figure 45. AD5259 Evaluation Board Software
Rev. A | Page 19 of 24
AD5259
DISPLAY APPLICATIONS
CIRCUITRY
For this reason, VLOGIC and VDD are provided as two separate
supply pins that can either be tied together or treated inde-
pendentlyꢀ VLOGIC supplying the logic/EEPROM with power,
and VDD biasing up the A, B, and W terminals for added
flexibility.
A special feature of the AD5259 is its unique separation of the
VLOGIC and VDD supply pins. The separation provides greater
flexibility in applications that do not always provide needed
supply voltages.
In particular, LCD panels often require a VCOM voltage in the
range of 3 V to 5 V. The circuit in Figure 46 is the rare excep-
tion in which a 5 V supply is available to power the digital
potentiometer.
VCC (~3.3V)
14.4V
SUPPLIES POWER
TO BOTH THE
MICRO AND THE
LOGIC SUPPLY OF
THE DIGITAL POT
R1
70kΩ
C1
1μF
AD5259
R6
R5
–
V
V
DD
10kΩ 10kΩ
VCC (~3.3V)
5V
14.4V
U1
AD8565
LOGIC
R2
A
B
10kΩ
3.5V < V
COM
< 4.5V
R1
70kΩ
SCL
SDA
GND
+
MCU
W
C1
1μF
AD5259
R6
R5
–
V
V
DD
10kΩ 10kΩ
R3
25kΩ
U1
AD8565
LOGIC
R2
A
B
10kΩ
3.5V < V
COM
< 4.5V
SCL
SDA
GND
+
MCU
W
Figure 47. Circuitry When a Separate Supply is Not Available for VDD
R3
For a more detailed look at this application, refer to the article,
“Simple VCOM Adjustment uses any Logic Supply Voltage” in
the September 30, 2004 issue of EDN magazine.
25kΩ
Figure 46. VCOM Adjustment Application
In the more common case shown in Figure 47, only analog 14.4 V
and digital logic 3.3 V supplies are available. By placing discrete
resistors above and below the digital potentiometer, VDD can
now be tapped off the resistor string itself. Based on the chosen
resistor values, the voltage at VDD in this case equals 4.8 V,
allowing the wiper to be safely operated all the way up to 4.8 V.
The current draw of VDD will not affect that node’s bias because
it is only on the order of microamps. VLOGIC is tied to the MCU’s
3.3 V digital supply because VLOGIC will draw the 35 mA which
is needed when writing to the EEPROM. It would be imprac-
tical to try and source 35 mA through the 70 kΩ resistor,
therefore, VLOGIC is not connected to the same node as VDD.
Rev. A | Page 2± of 24
AD5259
OUTLINE DIMENSIONS
INDEX
AREA
3.00 BSC
PIN 1
INDICATOR
3.00
BSC SQ
10
6
10
1
1.50
BCS SQ
4.90 BSC
3.00 BSC
PIN 1
0.50
BSC
2.48
2.38
2.23
EXPOSED
1
5
PAD
TOP VIEW
(BOTTOM VIEW)
6
5
0.50 BSC
0.95
0.85
0.75
0.50
0.40
0.30
1.74
1.64
1.49
1.10 MAX
0.80 MAX
0.55 TYP
0.80
0.75
0.70
0.80
0.60
0.40
8°
0°
0.15
0.00
0.27
0.17
0.05 MAX
0.02 NOM
SEATING
PLANE
SIDE VIEW
0.23
0.08
COPLANARITY
0.10
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 48. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Figure 49. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5259BRMZ51
Package Description
Package Option
RAB (Ω)
5 k
5 k
5 k
1± k
1± k
1± k
5± k
5± k
5± k
1±± k
1±± k
1±± k
Temperature
–4±°C to +85°C
–4±°C to +85°C
–4±°C to +85°C
–4±°C to +85°C
–4±°C to +85°C
–4±°C to +85°C
–4±°C to +85°C
–4±°C to +85°C
–4±°C to +85°C
–4±°C to +85°C
–4±°C to +85°C
–4±°C to +85°C
Branding
D4P
D4P
1±-Lead MSOP
1±-Lead MSOP
1±-Lead LFCSP_WD
1±-Lead MSOP
1±-Lead MSOP
1±-Lead LFCSP_WD
1±-Lead MSOP
1±-Lead MSOP
1±-Lead LFCSP_WD
1±-Lead MSOP
1±-Lead MSOP
RM-1±
RM-1±
CP-1±-9
RM-1±
RM-1±
CP-1±-9
RM-1±
RM-1±
CP-1±-9
RM-1±
RM-1±
CP-1±-9
AD5259BRMZ5-R71
AD5259BCPZ5-R71
AD5259BRMZ1±1
AD5259BRMZ1±-R71
AD5259BCPZ1±-R71
AD5259BRMZ5±1
AD5259BRMZ5±-R71
AD5259BCPZ5±-R71
AD5259BRMZ1±±1
AD5259BRMZ1±±-R71
AD5259BCPZ1±±-R71
AD5259EVAL2
D4P
D4Q
D4Q
D4Q
D4R
D4R
D4R
D4S
D4S
D4S
1±-Lead LFCSP_WD
Evaluation Board
1 Z = Pb-free part.
2 The evaluation board is shipped with the 1± kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
Rev. A | Page 21 of 24
AD5259
NOTES
Rev. A | Page 22 of 24
AD5259
NOTES
Rev. A | Page 23 of 24
AD5259
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
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