AD5259EVAL [ADI]
Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer; 非易失， I2C兼容256位，数字电位器
| 型号： | AD5259EVAL |
| 厂家： | 
ADI |
| 描述： | Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer |
| 文件： | 总14页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Nonvolatile, I2C Compatible
256-Position, Digital Potentiometer
Preliminary Technical Data
AD5259
parts on one bus, address bits AD0 and AD1 allow up to nine
devices on the same bus.
FEATURES
Nonvolatile memoy maintains wiper settings
256-position
Compact MSOP-10 (3 mm × 4.9 mm) package
I2C® compatible interface
FUNCTIONAL BLOCK DIAGRAMS
VLOGIC pin provides increased interface flexibility.
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Resistance tolerance stored in EEMEM(0.1% accuracy)
Power On EEMEM Refresh Time < 1ms
Software write protect command
Tri-state address decode pins AD0 and AD1
100-year typical data retention at 55°C
Wide operating temperature –40°C to +85°C
+3V to +5V single-supply
VDD
RDAC1
A1
W1
B1
RDAC1
REGISTER
VLOGIC
DGND
RDAC EEPROM
8
DATA
SCL
SDA
I2C
SERIAL
INTERFACE
8
CONTROL
AD0
AD1
COMMAND DECODE LOGIC
ADDRESS DECODE LOGIC
CONTROL LOGIC
POWER
ON RESET
APPLICATIONS
LCD panel VCOM adjustment
LCD panel brightness and contrast control
Mechanical potentiometer replacement in new designs
Programmable power supplies
RF amplifier biasing
Figure 1.
Automotive electronics adjustment
Gain control and offset adjustment
Low resolution DAC replacement
Electronics level settings
1
2
3
4
5
W
10 A
9
8
7
6
B
AD0
AD1
SDA
SCL
AD5259
VDD
TOP VIEW
(Not to Scale)
GND
VLOGIC
GENERAL OVERVIEW
Figure 3. Pinout.
The AD5259 provides a compact nonvolatile 3 mm × 4.9 mm
packaged solution for 256-position adjustment applications.
These devices perform the same electronic adjustment function
as mechanical potentiometers or variable resistors, with
enhanced resolution and solid-state reliability.
The wiper settings are controllable through an I2C compatible
digital interface, which can also be used to read back the wiper
register and EEMEM content. Resistor tolerance is also stored
within EEMEM and can be used to provide an end-to-end
tolerance accuracy of 0.1%. In order to provide added security,
command bits are available to place the part into a write protect
mode in which data can not be written to the EEMEM register.
Note:
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed
Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
In addition, a separate VLOGIC pin provides the user with
increased interface flexibility. For users who need multiple
Rev. PrJ 7/22/04 | Page 1 of 14
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD5259
Preliminary Technical Data
TABLE OF CONTENTS
Electrical Characteristics—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Ordering Guide .......................................................................... 13
ESD Caution................................................................................ 13
Versions .............................................................................................. 3
Timing Characteristics—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions 4
Absolute Maximum Ratings1 .......................................................... 5
Outline Dimensions ....................................................................... 12
REVISION HISTORY
Revision 0: Initial Version
VDD
Vlogic
A
EEPROM
AD5259
RDAC
REGISTER
and
LEVEL
SHIFTER
SCL
I2C SERIAL
INTERFACE
SDA
AD0
AD1
COMMAND
DECODE LOGIC
W
ADDRESS
DECODE LOGIC
CONTROL
LOGIC
GND
B
Figure 3. Block diagram showing level shifters
Rev. PrJ 7/22/04 | Page 2 of 14
Preliminary Technical Data
AD5259
ELECTRICAL CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(VDD = 5 V 10%, or 3 V 10%ꢀ VA = VDDꢀ VB = 0 Vꢀ –40°C < TA < +85°Cꢀ unless otherwise noted.)
Table 1.
Parameter
Symbol
Conditions
Min
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance
Resistance Temperature Coefficient
R-DNL
R-INL
∆RAB
RWB, VA = no connect
RWB, VA = no connect
TA = 2ꢀ°C
–1
–2
–30
0.1
0.2ꢀ
+1
+2
+30
LSB
LSB
%
∆RAB/∆T
VAB = VDD
,
6ꢀ0
ꢀ0
ppm/°C
Wiper = no connect
Code = 0x00
RWB
RWB
120
Ω
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE
Differential Nonlinearity
Integral Nonlinearity
Voltage Divider Temperature Coefficient
Full-Scale Error
DNL
INL
∆VW/∆T
VWFSE
VWZSE
–1
–1
0.1
0.3
30
–1
1
+1
+1
LSB
LSB
ppm/°C
LSB
LSB
Code = 0x80
Code = 0xFF
Code = 0x00
–3
0
0
3
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range
VA,B,W
CA,B
VSS
VDD
V
pF
Capacitance A, B
f = 1 MHz, measured to
GND, Code = 0x80
f = 1 MHz, measured to
GND, Code = 0x80
4ꢀ
60
1
Capacitance W
CW
ICM
pF
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VA = VB = VDD/2
nA
0.7 × VL
–0.ꢀ
VL+0.ꢀ
0.3×VL
1
VIH
VIL
IIL
V
V
µA
pF
Input Logic Low
Input Current
Input Capacitance
VIN = 0 V or ꢀ V
CIL
ꢀ
POWER SUPPLIES
Power Supply Range
VDD
IDD
VLOGIC
ILOGIC(PROG)
PDISS
2.7
2.7
ꢀ.ꢀ
1
VDD
V
µA
Positive Supply Current
Logic Supply(must match logic levels)
Programming Mode Current(EEMEM)
Power Dissipation
VIH = ꢀ V or VIL = 0 V
VIH = ꢀ V or VIL = 0 V
VIH = ꢀ V or VIL = 0 V,
3ꢀ
18
mA
µW
ꢀ0
V
DD = ꢀ V
Power Supply Sensitivity
PSS
VDD = +ꢀ V 10%,
Code = Midscale
0.02
0.0ꢀ %/%
DYNAMIC CHARACTERISTICS
Bandwidth –3dB
BW
RAB = ꢀkΩ/ 10 kΩ/ꢀ0 kΩ/100
kΩ, Code = 0x80
2000/600/
100/40
0.1
kHz
Total Harmonic Distortion
THDW
tS
VA =1 V rms, VB = 0 V,
f = 1 kHz, RAB = 10 kΩ
VA = ꢀ V, VB = 0 V,
1 LSB error band
%
VW Settling Time (1kΩ/10 kΩ/ꢀ0 kΩ/100 kΩ)
Resistor Noise Voltage Density
2
9
µs
eN_WB
RWB = ꢀ kΩ, RS = 0
nV/√Hz
Rev. PrJ 7/22/04 | Page 3 of 14
AD5259
Preliminary Technical Data
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(VDD = +5V 10%, or +3V 10%ꢀ VA = VDDꢀ VB = 0 Vꢀ –40°C < TA < +85°Cꢀ unless otherwise noted.)
Table 2.
Parameter
Symbol
Conditions
Min Typ Max Unit
I2C INTERFACE TIMING CHARACTERISTICS1 (Specifications Apply to All Parts)
SCL Clock Frequency
tBUF Bus Free Time between STOP and START
tHD;STA Hold Time (Repeated START)
fSCL
t1
t2
0
1.3
0.6
400
kHz
µs
µs
After this period, the first clock pulse is
generated.
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Repeated START Condition
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for STOP Condition
t3
t4
tꢀ
t6
t7
t8
t9
t10
1.3
0.6
0.6
0
µs
µs
µs
µs
ns
ns
ns
µs
0.9
100
300
300
0.6
t6
t8
t9
SCL
t10
t5
t7
t4
t2
t3
t9
t8
t1
SDA
P
S
P
Figure 4. I2C Interface Timing Diagram
Rev. PrJ 7/22/04 | Page 4 of 14
Preliminary Technical Data
AD5259
I2C INTERFACE
Table 3. Generic Interface Format
Device Address*
R/W
S
(7-bit)
SA C2 C1 C0 A4 A3 A2 A1 A0 SA D7 D6 Dꢀ D4 D3 D2 D1 D0 SA
P
Slave Address Byte
Instruction Byte
Data Byte
Table 4. Device Address Lookup*
(Note that AD1 and AD0 are tri-state address pins)
Device
AD1
AD0
Address
0011000
0011001
0011010
0101001
0101010
0101011
1001100
1001101
1001110
S = Start Condition
0
NC
1
0
NC
1
0
NC
1
0
0
0
NC
NC
NC
1
P = Stop Condition
SA = Slave Acknowledge
MA = Master Acknowledge
NA = No Acknowledge
X = Don’t Care
1
1
W
= Write
R = Read
Table 5. RDAC-to-EEMEM Interface Command Descriptions
C2
0
C1
0
C0
0
Command Description
Operation between I2C and RDAC
Operation between I2C and EEPROM
Operation between I2C and WP register
NOP
0
0
1
0
1
0
1
0
0
1
0
1
Restore EEPROM to RDAC
Store RDAC to EEPROM
1
1
0
Rev. PrJ 7/22/04 | Page ꢀ of 14
AD5259
Preliminary Technical Data
Write Modes
Table 6. Writing to RDAC register
Device Address*
S
(7-bit)
0
0
SA
SA
0
0
0
0
0
0
0
0
0
0
0
0
SA D7 D6 Dꢀ D4 D3 D2 D1 D0 SA
Data Byte
P
P
Slave Address Byte
Instruction Byte
Table 7. Writing to EEPROM register
Device Address*
S
(7-bit)
1
0
0
0
SA D7 D6 Dꢀ D4 D3 D2 D1 D0 SA
Data Byte
Slave Address Byte
Instruction Byte
Table 8. Activating Software Write Protect
Device Address*
S
(7-bit)
0
SA
0
1
0
0
0
0
0
0
SA
0
0
0
0
0
0
0
WP SA
P
Slave Address Byte
Instruction Byte
Data Byte
Store/Restore Modes
Table 9. Storing RDAC value to EEPROM
Device Address*
S
(7-bit)
0
SA
1
1
0
0
0
0
0
0
0
0
SA
SA
P
P
Slave Address Byte
Instruction Byte
Table 10. Restoring EEPROM to RDAC
Device Address*
S
(7-bit)
0
SA
1
0
1
0
0
0
Slave Address Byte
Instruction Byte
S = Start Condition
P = Stop Condition
SA = Slave Acknowledge
MA = Master Acknowledge
NA = No Acknowledge
X = Don’t Care
W
= Write
R = Read
Rev. PrJ 7/22/04 | Page 6 of 14
Preliminary Technical Data
AD5259
Read Modes
Table 11. Traditional Read back of RDAC Register value
Device Address*
Device Address*
S
(7-bit)
(7-bit)
0
SA
0
0
0
0
0
0
0
0
SA
S
1
SA D7 D6 Dꢀ D4 D3 D2 D1 D0 NA P
Read Back Data
Slave Address Byte
Instruction Byte
Slave Address Byte
↑
Repeat start
Table 12. Traditional Read back of stored EEPROM value
Device Address*
Device Address*
(7-bit)
S
(7-bit)
0
SA
0
0
1
0
0
0
0
0
SA
S
1
SA D7 D6 Dꢀ D4 D3 D2 D1 D0 NA P
Read Back Data
Slave Address Byte
Instruction Byte
Slave Address Byte
↑
Repeat start
Table 13. Traditional Read back of Tolerance
i. Consecutively
Device
Device
Address*
Address*
D
S
(7-bit)
(7-bit)
0 SA 0 0 1 1 1 1 1 0 SA S
Instruction Byte
1 SA D7 D6 Dꢀ D4 D3 D2 D1 0 MA D7 D6 Dꢀ D4 D3 D2 D1 D0 NA P
Slave Address
Byte
Slave Address
Byte
Sign + Integer Byte
Decimal Byte
↑
Repeat start
ii. Individually
Device
Address*
(7-bit)
Device
Address*
(7-bit)
D
S
0 SA 0 0 1 1 1 1 1 0 SA S
Instruction Byte
1 SA D7 D6 Dꢀ D4 D3 D2 D1 0 NA
P
Slave Address
Byte
Slave Address
Byte
Sign + Integer Byte
↑
Repeat start
Device
Address*
(7-bit)
Device
Address*
(7-bit)
D
S
0 SA 0 0 1 1 1 1 1 1 SA S
Instruction Byte
1 SA D7 D6 Dꢀ D4 D3 D2 D1 0 NA
P
Slave Address
Byte
Slave Address
Byte
Decimal Byte
↑
Repeat start
Note: Read modes above are referred to as traditional because the first two bytes for all three cases are “dummy” bytes which function to
place the pointer towards the correct register. This is the reason for the Repeat Start. In theory, this step can be avoided if the user is
interested in reading a register that was previously written to. For example, if the EEPROM was just written to, then the user can skip the
Rev. PrJ 7/22/04 | Page 7 of 14
AD5259
Preliminary Technical Data
two dummy bytes and proceed directly to the “Slave Address Byte” which would be followed by the “Read Back Data”.
Calculating RAB Tolerance Stored in Read-Only Memory
A
A
A
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
–6
D1
–7
D0
–8
6
5
4
3
2
1
0
–1
2
–2
2
–3
2
–4
2
–5
2
SIGN
2
2
2
2
2
2
2
2
2
2
SIGN
7 BITS FOR INTEGER NUMBER
8 BITS FOR DECIMAL NUMBER
Figure 5. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions. (Unit is percent. Only data bytes are shown.)
The AD5259 features a patented RAB tolerance storage in the nonvolatile memory. The tolerance is stored in the memory during factory
production and can be read by users at any time. The knowledge of stored tolerance allows users to calculate RAB accurately. This feature is
valuable for precision, rheostat mode, and open-loop applications where knowledge of absolute resistance is critical.
The stored tolerance resides in the read-only memory, and is expressed as a percentage. The tolerance is stored in two memory locations
in sign magnitude binary form(see Figure 5). The two EEMEM address bytes are 11110(sign+integer) and 11111 (decimal number). The
two bytes can be accessed individually in two separate commands(see Table 13ii). Alternatively, in order to allow read back of the first
byte followed by the second byte in one command(see Table 13i), the memory pointer will automatically increment from the first to the
second EEMEM locations(increments from 11110 to 11111) if read consecutively.
In the first memory location, the MSB is designated for the sign (0 = + and 1= –) and the 7 LSBs are designated for the integer portion of
the tolerance. In the second memory location, all eight data bits are designated for the decimal portion of tolerance. For example, if the
rated RAB = 10 kΩ and the data readback from Address 11110 shows 0001 1100 and Address 11111 shows 0000 1111, then the tolerance
can be calculated as
MSB: 0 = +
Next 7 MSB: 001 1100 = 28
8 LSB: 0000 1111 = 15 × 2–8 = 0.06
Tolerance = +28.06% and therefore
RAB_ACTUAL = 12.806 kΩ
EEMEM Write-Acknowledge Polling
After each write operation to the EEMEM registers, an internal write cycle begins. The I2C interface of the device is disabled. To
determine if the internal write cycle is complete and the I2C interface is enabled, interface polling can be executed. I2C interface polling
can be conducted by sending a start condition followed by the slave address + the write bit. If the I2C interface responds with an ACK, the
write cycle is complete and the interface is ready to proceed with further operations. Other-wise, I2C interface polling can be repeated
until it succeeds.
Rev. PrJ 7/22/04 | Page 8 of 14
Preliminary Technical Data
AD5259
I2C COMPATIBLE 2-WIRE SERIAL BUS
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 4). The
following byte is the Slave Address Byte, which consists of
4. Reading: Assuming the register of interest was not just
written to, it is necessary to write a dummy Address and
Instruction Byte. The Instruction Byte will vary depending
on whether the data that is wanted is the RDAC register,
EEMEM register, or Tolerance register(see Tables 11-13).
The Tolerance register can be read back
the slave address followed by an R/ bit (this bit
W
determines whether data is read from or written to the
slave device).
consecutively(Table 13i) or individually(Table13ii). Refer
to page 8 for detailed information on the interpretation of
the tolerance bytes. After the dummy Address and
Instruction Bytes are sent, a repeat start is necessary. After
the repeat start, another Address Byte is needed except this
The AD5259 has two tri-state configurable address bits,
AD0 and AD1 (see Table 4). The slave whose address
corresponds to the transmitted address responds by pulling
the SDA line low during the ninth clock pulse (this is
termed the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for
data to be written to or read from its serial register. If the
time, the R/ bit is logic high. Following this Address
W
Byte is the Read Back Byte containing the information
requested in the Instruction Byte.
R/ bit is high, the master reads from the slave device. If
W
5. After all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the 10th clock pulse to establish a STOP
condition (see Figure 6). In read mode, the master issues a
No Acknowledge for the ninth clock pulse (i.e., the SDA
line remains high). The master then brings the SDA line
low before the 10th clock pulse, and then raises SDA high to
establish a STOP condition (see Figure 7).
the R/ bit is low, the master writes to the slave device.
W
2. Writing: In the write mode, the last bit(R/ ) of the
W
Address Byte is logic low. The second byte is the
Instruction Byte. The first 3 bits of the Instruction Byte are
the command bits(see Table 5). The final 5 bits indicate
which EEMEM location the pointer moves to. The user
must choose whether to write to the RDAC register,
EEMEM register, or activate the software write protect(see
Tables 6-8).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and
instructing the part only once. For example, after the RDAC has
acknowledged its Slave Address and Instruction Bytes in the
write mode, the RDAC output is updated on each successive
byte. If different instructions are needed, the write/read mode
has to start again with a new Slave Address, Instruction, and
Data Byte. Similarly, a repeated read function of the RDAC is
also allowed.
The final byte is the Data Byte MSB first. In the case of the
write protect mode, data is not being stored. Rather, a
logic high in the LSB will enable write protect and a logic
low will disable write protect.
3. Storing/Restoring: In this mode, only two bytes are
necessaryꢀ Address and Instruction Bytes. The last bit
(R/ ) of the Address Byte is logic low. The first 3 bits of
W
the Instruction Byte are the command bits(see Table 5).
The two choices are transfer data from RDAC to
EEMEM(Store) or from EEMEM to RDAC(Restore). The
final 5 bits are all zeros(see Tables 9-10).
Rev. PrJ 7/22/04 | Page 9 of 14
AD5259
Preliminary Technical Data
DISPLAY APPLICATIONS
Figure 1. VCOM adjustment application assuming that a +5V supply is available. In this case, VDD and VLOGIC would be tied together.
Figure 2. This circuit demonstrates the flexibility of a VLOGIC pin when a separate supply is not available for VDD. VDD can be tapped off
the +14.4V where it is resistor divided down to approximately ~5V. VLOGIC can then be taken off the same supply that powers the MCU’s
logic levels. Now, the 35 mA programming current will be drawn by VLOGIC, and VDD will only draw microamps of supply current used to
bias up the internal switches in the digital potentiometer’s internal resistor string.
Rev. PrJ 7/22/04 | Page 10 of 14
Preliminary Technical Data
AD5259
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C, unless otherwise noted.)
Table 4
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
VDD to GND
VA, VB, VW to GND
IMAX
Value
–0.3 V to +7 V
VSS –0.3V, VDD+0.3V
Pulsed1
20 mA
ꢀ mA
Continuous
Digital Inputs and Output Voltage to GND 0 V to +7 V
Operating Temperature Range
Maximum Junction Temperature (TJMAX
Storage Temperature
–40°C to +8ꢀ°C
)
1ꢀ0°C
–6ꢀ°C to +1ꢀ0°C
300°C
Lead Temperature (Soldering, 10 sec)
Thermal Resistance2 θJA: MSOP-10
200°C/W
NOTES
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA
.
Rev. PrJ 7/22/04 | Page 11 of 14
AD5259
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
W
10 A
9
8
7
6
B
AD0
AD1
SDA
SCL
AD5259
VDD
GND
VLOGIC
TOP VIEW
(Not to Scale)
Figure 2. AD5172 Pin Configuration
Table 5. AD5259 Pin Function Descriptions
Pin
Mnemonic
Description
1
W
W Terminal. GND ≤ VW ≤ VDD
.
2
3
4
ꢀ
6
7
8
9
ADO
AD1
SDA
SCL
VLOGIC
GND
VDD
B
Programmable Tri-State Address Bit 0 for Multiple Package Decoding.
Programmable Tri-State Address Bit 1 for Multiple Package Decoding.
Serial Data Input/Output.
Serial Clock Input. Positive edge triggered.
Logic power supply.
Digital Ground.
Positive Power Supply.
B Terminal. GND ≤ VB ≤ VDD
.
10
A
A Terminal. GND ≤ VA ≤ VDD.
Rev. PrJ 7/22/04 | Page 12 of 14
Preliminary Technical Data
AD5259
Outline Dimensions
3.00 BSC
6
10
4.90 BSC
3.00 BSC
PIN 1
1
5
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.23
0.20
0.17
0.80
0.40
8°
0°
0.15
0.00
0.27
0.17
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 3. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADꢀ2ꢀ9BRMZꢀ1
RAB (Ω)
ꢀk
Temperature
–40°C to +8ꢀ°C
–40°C to +8ꢀ°C
–40°C to +8ꢀ°C
–40°C to +8ꢀ°C
–40°C to +8ꢀ°C
–40°C to +8ꢀ°C
–40°C to +8ꢀ°C
–40°C to +8ꢀ°C
Package Description
MSOP-10
Package Option
RM-10
Branding
D4P
ADꢀ2ꢀ9BRMZꢀ-RL71
ADꢀ2ꢀ9BRMZ101
ADꢀ2ꢀ9BRMZ10-RL71
ADꢀ2ꢀ9BRMZꢀ01
ADꢀ2ꢀ9BRMZꢀ0-RL71
ADꢀ2ꢀ9BRMZ1001
ADꢀ2ꢀ9BRMZ100-RL71
ꢀk
MSOP-10
RM-10
D4P
D4Q
10k
MSOP-10
RM-10
D4Q
D4R
D4R
D4S
D4S
10k
MSOP-10
RM-10
ꢀ0k
MSOP-10
RM-10
ꢀ0k
MSOP-10
RM-10
100k
100k
MSOP-10
RM-10
MSOP-10
RM-10
1 Z = Pb-free part.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrJ 7/22/04 | Page 13 of 14
AD5259
NOTES
Preliminary Technical Data
©
2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
PR05026–0–7/04(PrJ)
Rev. PrJ 7/22/04 | Page 14 of 14
相关型号：
AD5260BRUZ20-REEL7
IC 20K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14, TSSOP-14, Digital Potentiometer
ADI
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