AD5174BCPZ-10-R2_技术文档

Single-Channel, 1024-Position, Digital Rheostat

with SPI Interface and 50-TP Memory

AD5174

FUNCTIONAL BLOCK DIAGRAM

FEATURES

V

DD

Single-channel, 1024-position resolution

10 kΩ nominal resistance

50-times programmable (50-TP) wiper memory

Rheostat mode temperature coefficient: 35 ppm/°C

2.7 V to 5.5 V single-supply operation

2.5 V to 2.75 V dual-supply operation for ac or bipolar

operations

SPI-compatible interface

Wiper setting and memory readback

Power on refreshed from memory

POWER-ON

RESET

AD5174

RDAC

REGISTER

SCLK

SYNC

DIN

A

10

SPI

SERIAL

W

INTERFACE

50-TP

MEMORY

BLOCK

Resistor tolerance stored in memory

Thin LFCSP 10-lead, 3 mm × 3 mm× 0.8 mm package

Compact MSOP, 10-lead, 3 mm × 4.9 mm × 1.1 mm package

SDO

APPLICATIONS

V

EXT_CAP

GND

SS

Figure 1.

Mechanical rheostat replacements

Op-amp: variable gain control

Instrumentation: gain, offset adjustment

Programmable voltage-to-current conversions

Programmable filters, delays, time constants

Programmable power supply

Sensor calibration

GENERAL DESCRIPTION

The AD5174 is a single-channel, 1024-position digital rheostat

that combines industry leading variable resistor performance

with nonvolatile memory (NVM) in a compact package.

The AD5174 device wiper settings are controllable through the

SPI digital interface. Unlimited adjustments are allowed before

programming the resistance value into the 50-TP memory. The

AD5174 does not require any external voltage supply to facili-

tate fuse blow and there are 50 opportunities for permanent

programming. During 50-TP activation, a permanent blow fuse

command freezes the resistance position (analogous to placing

epoxy on a mechanical rheostat).

This device supports both dual-supply operation at 2.5 V to

2.75 V and single-supply operation at 2.7 V to 5.5 V and offers

50-times programmable (50-TP) memory.

The AD5174 is available in a 3 mm × 3mm 10-lead LFCSP

package and in a 10-lead MSOP package. The part is guaranteed

to operate over the extended industrial temperature range of

−40°C to +125°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD5174

TABLE OF CONTENTS

Features .............................................................................................. 1

Shift Register............................................................................... 12

RDAC Register............................................................................ 12

50-TP Memory Block ................................................................ 12

Write Protection ......................................................................... 12

RDAC and 50-TP Read Operation .......................................... 13

Shutdown Mode ......................................................................... 14

Reset............................................................................................. 14

Daisy-Chain Operation............................................................. 15

RDAC Architecture.................................................................... 15

Programming the Variable Resistor......................................... 16

EXT_CAP Capacitor.................................................................. 17

Terminal Voltage Operating Range ......................................... 17

Power-Up Sequence ................................................................... 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Interface Timing Specifications.................................................. 4

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Test Circuits..................................................................................... 11

Theory of Operation ...................................................................... 12

Serial Data Interface................................................................... 12

REVISION HISTORY

3/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

AD5174

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V_DD= 2.7 V to 5.5 V, V_SS= 0 V; V_DD= 2.5 V to 2.75 V, V_SS= −2.5 V to −2.75 V; −40°C < T_A< 125°C, unless otherwise noted.

Table 1.

Parameter

Symbol

R-INL

Test Conditions/Comments

Min

Typ¹Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution

Resistor Integral Nonlinearity^{2, 3}

10

−1

−2.5

−1

Bits

LSB

%

|V_DD− V_SS| = 3.6 V to 5.5 V

|V_DD− V_SS| = 3.3 V to 3.6 V

|V_DD− V_SS| = 2.7 V to 3.3 V

+1

+1.5

+2.5

+1

Resistor Differential Nonlinearity²

Nominal Resistor Tolerance

Resistance Temperature Coefficient^{4, 5}

Wiper Resistance

RESISTOR TERMINALS

Terminal Voltage Range^{4, 6}

Capacitance A⁴

R-DNL

15

35

Code = full scale

Code = zero scale

ppm/°C

Ω

35

70

V_TERM

V_SS

V_DD

V

f = 1 MHz, measured to GND, code = half scale

V_A= V_W

90

40

pF

nA

Capacitance W⁴

Common-Mode Leakage Current⁴

50

DIGITAL INPUTS

Input Logic⁴

High

Low

Input Current

Input Capacitance⁴

DIGITAL OUTPUT

Output Voltage⁴

V_INH

V_INL

I_IN

2.0

V

μA

pF

0.8

1

5

C_IN

High

Low

V_OH

V_OL

R_{PULL_UP}= 2.2 kΩ to V_DD

V_DD− 0.1

V

V_DD= 2.7 V to 5.5 V, V_SS= 0 V

V_DD= 2.5 V to 2.75 V, V_SS= −2.5 V to −2.75 V

0.4

0.6

+1

V

μA

pF

Tristate Leakage Current

Output Capacitance⁴

POWER SUPPLIES

Single-Supply Power Range

Dual-Supply Power Range

Supply Current

−1

5

V_SS= 0 V

2.7

2.5

5.5

2.75

V

Positive

Negative

50-TP Store Current^{4, 7}

I_DD

I_SS

1

μA

−1

Positive

Negative

50-TP Read Current^{4, 8}

I_{DD_OTP_STORE}

I_{SS_OTP_STORE}

4

−4

mA

Positive

Negative

Power Dissipation⁹

Power Supply Rejection Ratio⁴

I_{DD_OTP_READ}

I_{SS_OTP_READ}

P_DISS

500

5.5

μA

μW

dB

−500

−50

V_IH= V_DDor V_IL= GND

PSRR

ΔV_DD/ΔV_SS

=

5 V 10%

−55

Rev. 0 | Page 3 of 20

AD5174

Parameter

DYNAMIC CHARACTERISTICS^{4, 10}

Symbol

Test Conditions/Comments

Min

Typ¹Max

Unit

Bandwidth

Total Harmonic Distortion

Resistor Noise Density

−3 dB, R_AW= 5 kΩ, Terminal W, see Figure 24

V_A= 1 V rms, f = 1 kHz, R_AW= 5 kΩ

R_WB= 5 kΩ, T_A= 25°C, f = 10 kHz

700

−90

13

kHz

dB

nV/√Hz

¹Typical specifications represent average readings at 25°C, V_DD= 5 V, and V_SS= 0 V.

²Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions.

³The maximum current in each code is defined by I_AW= (V_DD− 1)/R_AW

⁴Guaranteed by design and not subject to production test.

⁵See Figure 9 for more details.

.

⁶Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar

signal adjustment.

⁷Different from operating current; the supply current for the fuse program lasts approximately 55 ms.

⁸Different from operating current; the supply current for the fuse read lasts approximately 500 ns.

⁹P_DISSis calculated from (I_DD× V_DD) + (I_SS× V_SS).

¹⁰All dynamic characteristics use V_DD= +2.5 V, V_SS= −2.5 V.

INTERFACE TIMING SPECIFICATIONS

V_DD= 2.7 V to 5.5 V, V_SS= 0 V; V_DD= 2.5 V, V_SS= −2.5 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter

Limit¹

20

10

15

5

Unit

Test Conditions/Comments

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge setup time

Data setup time

2

t₁

ns min

ns max

μs max

ms max

μs max

ms max

t₂

t₃

t₄

t₅

t₆

t₇

5

1

Data hold time

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

SYNC rising edge to next SCLK fall ignored

SCLK rising edge to SDO valid

Memory readback execute time

Memory program time

3

t₈

400

15

450

6

350

600

2

t₉

4

t₁₀

t_{MEMORY_READ}

t_{MEMORY_PROGRAM}

t_RESET

Reset OTP restore time

Power-on 50-TP restore time

5

t_POWER-UP

¹All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

²Maximum SCLK frequency is 50 MHz.

³Refer to t

t

_{MEMORY_READ}and _{MEMORY_PROGRAM}for memory commands operations.

⁴R_{PULL_UP}= 2.2 kΩ to V_DDwith a capacitance load of 168 pF.

⁵Maximum time after V_DD− V_SSis equal to 2.5 V.

Rev. 0 | Page 4 of 20

AD5174

Shift Register and Timing Diagrams

DB9 (MSB)

DB0 (LSB)

D0

D1

C3

C1

C0

D9

D7

D6

D5

D4

D3

D8

0

C2

D2

DATA BITS

CONTROL BITS

Figure 2. Shift Register Content

t₇

t₄

t₂

t₁

SCLK

SYNC

t₉

t₈

t₃

t₅

D1

t₆

DIN

0

C3

C2

D7

D6

D5

D2

D0

SDO

Figure 3. Write Timing Diagram, CPOL=0, CPHA = 1

SCLK

t₉

SYNC

DIN

0

C3

D0

0

C3

D1

D0

t₁₀

SDO

X

Figure 4. Read Timing Diagram, CPOL=0, CPHA = 1

Rev. 0 | Page 5 of 20

AD5174

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3.

Parameter

Rating

V_DDto GND

V_SSto GND

V_DDto V_SS

–0.3 V to +7.0 V

+0.3 V to −7.0 V

7 V

V_A, V_Wto GND

V_SS− 0.3 V, V_DD+ 0.3 V

−0.3 V to V_DD+ 0.3 V

7 V

Digital Input and Output Voltage to GND

EXT_CAP to V_SS

I_A, I_W

THERMAL RESISTANCE

θ_JAis defined by JEDEC specification JESD-51 and the value is

dependent on the test board and test environment.

Pulsed¹

Frequency > 10 kHz

Frequency ≤ 10 kHz

Continuous

6 mA/d²

6 mA/√d²

6 mA

−40°C to +125°C

150°C

Table 4. Thermal Resistance.

1

Package Type

10-Lead LFCSP

10-Lead MSOP

θ_JA

50

θ_JC

3

N/A

Unit

°C/W

Operating Temperature Range³

135

Maximum Junction Temperature

(T_JMaximum)

¹JEDEC 2S2P test board, still air (0 m/sec airflow).

Storage Temperature Range

Reflow Soldering

Peak Temperature

−65°C to +150°C

ESD CAUTION

260°C

Time at Peak Temperature

Package Power Dissipation

20 sec to 40 sec

(T_Jmax − T_A)/θ_JA

¹Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum

applied voltage across any two of the A and W terminals at a given

resistance.

²Pulse duty factor.

³Includes programming of 50-TP memory.

Rev. 0 | Page 6 of 20

AD5174

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

10

9

V

1

2

3

4

5

SYNC

SCLK

DIN

DD

A

AD5174

8

W

V

1

2

3

4

5

10

9

SYNC

SCLK

DIN

DD

A

(EXPOSED

PAD)*

AD5174

V

7

SDO

GND

SS

8

W

6

EXT_CAP

TOP VIEW

(Not to Scale)

V

7

SS

EXT_CAP

SDO

GND

6

*LEAVE FLOATING OR CONNECTED TO V

SS

.

Figure 5. MSOP Pin Configuration

Figure 6. LFCSP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.

Terminal A of RDAC. V_SS≤ V_A≤ V_DD

Wiper Terminal of RDAC. V_SS≤ V_W≤ V_DD

Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic capacitors

and 10 μF capacitors.

1

2

3

4

V_DD

A

W

.

V_SS

5

EXT_CAP

External Capacitor. Connect a 1 μF capacitor between EXT_CAP and V_SS. This capacitor must have a voltage

rating of ≥7 V.

6

7

GND

SDO

Ground Pin, Logic Ground Reference.

Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data

from the shift register in daisy-chain mode or in readback mode.

8

DIN

Serial Data Line. This pin is used in conjunction with the SCLK line to clock data into or out of the 16-bit

input register.

9

SCLK

SYNC

Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be

transferred at rates of up to 50 MHz.

10

Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the shift register and data is transferred in on the falling edges of the subsequent clocks.

The selected register is updated on the rising edge of SYNC following the 16^thclock cycle. If SYNC is taken

high before the 16^thclock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored

by the RDAC.

EPAD

Exposed Pad Leave floating or connected to V_SS

Rev. 0 | Page 7 of 20

AD5174

TYPICAL PERFORMANCE CHARACTERISTICS

0.8

1.0

0.8

0.6

0.4

+25°C

–40°C

+125°C

V

/V = 5V/0V

DD SS

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

0.2

0

128

256

384

512

640

768

896

1023

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VOLTAGE (V)

CODE (Decimal)

Figure 7. R-INL vs. Code vs. Temperature

Figure 10. Supply Current (I_DD) vs. Digital Input Voltage

0.4

0.3

+25°C

–40°C

+125°C

500

400

I

= 5V

DD

300

0.2

200

I

= 3V

0.1

DD

100

I

= 3V

0

SS

0

–100

–200

–300

–400

–500

–0.1

–0.2

–0.3

I

= 5V

SS

128

256

384

512

640

768

896

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100 110

TEMPERATURE (°C)

CODE (Decimal)

Figure 8. R-DNL vs. Code vs. Temperature

Figure 11. Supply Current (I_DD, I_SS) vs. Temperature

700

600

7

6

5

4

3

2

1

V

/V = 5V/0V

DD SS

V

/V = 5V/0V

DD SS

500

400

300

200

100

0

128

256

384

512

640

768

896

0

85 170 255 340 425 510 595 680 765 850 935 1023

CODE (Decimal)

Figure 9. Tempco ΔR_WA/ΔT vs. Code

Figure 12. Theoretical Maximum Current vs. Code

Rev. 0 | Page 8 of 20

AD5174

–20

–25

0

V

/V = 5V/0V

DD SS

CODE = HALF SCALE

0x200

0x100

0x080

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

–30

–35

–40

–45

–50

–55

–60

0x040

0x020

0x010

0x008

0x004

0x002

0x001

V

/V = 5V/0V

DD SS

10

100

1k

10k

100k

1M

1

10

100

1k

10k

100k 1M

10M

FREQUENCY (Hz)

Figure 13. Bandwidth vs. Frequency vs. Code

Figure 16. PSRR vs. Frequency

8

0

–20

V

/V = ±2.5V

DD SS

CODE = HALF SCALE

= 1V rms

f

IN

NOISE BW = 22kHz

7

6

5

4

–40

–60

–80

–100

–120

10

100

1k

10k

0.07

0.09

0.11

0.13

0.15

0.17

1M

100k

FREQUENCY (Hz)

TIME (Seconds)

Figure 14. THD + N vs. Frequency

Figure 17. V_{EXT_CAP}Waveform While Writing Fuse

0

20

10

0

10kΩ

V

/V = ±2.5V

= 200µA

DD SS

I

AW

–20

–10

–20

–30

–40

–50

–60

–70

–40

–60

–80

V

/V = ±2.5V

DD SS

CODE = HALF SCALE

f_IN= 1kHz

NOISE BW = 22kHz

–100

0.001

0.01

0.1

1

–2

0

2

4

AMPLITUDE (V rms)

TIME (µs)

Figure 15. THD + N vs. Amplitude

Figure 18. Maximum Glitch Energy

Rev. 0 | Page 9 of 20

AD5174

1.0

0.006

0.005

0.004

0.003

0.002

0.001

0

V

/V = 5V/0V

= 10µA

DD SS

I

AW

CODE = HALF SCALE

0.5

0

–0.5

–1.0

–0.001

–0.002

V

/V = ±2.5V

= 200µA

DD SS

I

AW

–1.5

–10

0

10

20

30

40

50

60

0

100 200 300 400 500 600 700 800 900 1000

OPERATION AT 150°C (Hours)

TIME (µs)

Figure 19. Digital Feedthrough

Figure 20. Long-Term Drift Accelerated Average by Burn-In

Rev. 0 | Page 10 of 20

AD5174

TEST CIRCUITS

Figure 21 to Figure 25 define the test conditions used in the Specifications section.

DUT

I

W

1GΩ

W

A

V

MS

Figure 24. Gain vs. Frequency

Figure 21. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

DUT

GND

V

I

MS

W

R

=

I

WA

CM

+2.75V

–2.75V

W

CODE = 0x00

DUT

A

R

WA

2

I

W

R

W

A

W

NC

GND

–2.75V

V

MS

NC = NO CONNECT

+2.75V

Figure 25. Common Leakage Current

Figure 22. Wiper Resistance

V+ = V ±10%

DD

V

MS

PSRR (dB) = 20 log

DD

ΔV

%

MS

DD

I

W

PSS (%/%) =

V

DD

W

V+

A

V

MS

Figure 23. Power Supply Sensitivity (PSS, PSRR)

Rev. 0 | Page 11 of 20

AD5174

THEORY OF OPERATION

The AD5174 is designed to operate as a true variable resistor for

analog signals within the terminal voltage range of V_SS< V_TERM

< V_DD. The RDAC register contents determine the resistor wiper

position. The RDAC register acts as a scratchpad register, which

allows unlimited changes of resistance settings. The RDAC register

can be programmed with any position setting by using the SPI

interface. When a desirable wiper position is found, this value

can be stored in a 50-TP memory register. Thereafter, the wiper

position is always restored to that position for subsequent

power-ups. The storing of 50-TP data takes approximately 350 ms;

during this time, the AD5174 locks to prevent any changes from

taking place.

RDAC REGISTER

The RDAC register directly controls the position of the digital

rheostat wiper. For example, when the RDAC register is loaded

with all 0s, the wiper is connected to Terminal A of the variable

resistor. The RDAC register is a standard logic register, and there

is no restriction on the number of changes allowed. The basic

mode of setting the variable resistor wiper position (programming

the RDAC register) is accomplished by loading the serial data

input register with Command 1 (see Table 6) and with the desired

wiper position data.

50-TP MEMORY BLOCK

The AD5174 contains an array of 50-TP programmable memory

registers, which allow the wiper position to be programmed up

to 50 times. Table 10 shows the memory map. When the desired

wiper position is determined, the user can load the serial data

input register with Command 3 (see Table 6), which stores the

wiper position data in a 50-TP memory register. The first address

to be programmed is Location 0x01 (see Table 10); the AD5174

increments the 50-TP memory address for each subsequent

program until the memory is full. Programming data to 50-TP

consumes approximately 4 mA for 55 ms, and takes approx-

imately 350 ms to complete, during which time the shift register

locks to prevent any changes from occurring. Bit C2 of the

control register can be polled to verify that the fuse program

command was completed properly. No change in supply voltage

is required to program the 50-TP memory; however, a 1 μF

capacitor on the EXT_CAP pin is required (see Figure 28).

Prior to 50-TP activation, the AD5174 presets to midscale

on power-up.

The AD5174 also feature a patented 1% end-to-end resistor

tolerance. This simplifies precision, rheostat mode, and open-

loop applications where knowledge of absolute resistance is

critical.

SERIAL DATA INTERFACE

SYNC

The AD5174 contains a serial interface (

, SCLK, DIN,

and SDO) that is compatible with SPI interface standards, as well

as most DSPs. This device allows writing of data via the serial

interface to every register.

SHIFT REGISTER

The shift register is 16 bits wide, as shown in Figure 2. The

16-bit word consists of two unused bits, which should be set to

0, followed by four control bits and 10 RDAC data bits. Data is

loaded MSB first (Bit D9). The four control bits determine the

function of the software command as listed in Table 6. Figure 3

shows a timing diagram of a typical AD5174 write sequence.

WRITE PROTECTION

SYNC

The write sequence begins by bringing the

line low. The

SYNC

pin must be held low until the complete data-word is

At power-up, the serial data input register write commands for

both the RDAC register and the 50-TP memory registers are

disabled. The RDAC write protect bit, C1, of the control register

(see Table 8 and Table 9) is set to 0 by default. This disables any

change of the RDAC register content regardless of the software

commands, except that the RDAC register can be refreshed

from the 50-TP memory using the software reset, Command 4

(see Table 6). To enable programming of the RDAC register,

the write protect bit (Bit C1), of the control register must first

be programmed by loading the serial data input register with

Command 7. To enable programming of the 50-TP memory,

the program enable bit (Bit C0) of the control register, which

is set to 0 by default, must first be set to 1.

SYNC

loaded from the DIN pin. When

returns high, the serial

data-word is decoded according to the instructions in Table 6.

The command bits (Cx) control the operation of the digital

potentiometer. The data bits (Dx) are the values that are loaded

into the decoded register. The AD5174 has an internal counter

that counts a multiple of 16 bits (a frame) for proper operation.

For example, AD5174 works with a 32-bit word but does not

work properly with a 31-bit or 33-bit word. The AD5174

does not require a continuous SCLK when

To minimize power consumption in the digital input buffers,

operate all serial interface pins close to the V_DDsupply rails.

SYNC

is high.

Rev. 0 | Page 12 of 20

AD5174

Data from the selected memory location is clocked out of the

RDAC AND 50-TP READ OPERATION

SDO pin during the next SPI operation. A binary encoded version

address of the most recently programmed wiper memory location

can be read back using Command 6 (see Table 6). This can be used

to monitor the spare memory status of the 50-TP memory block.

A serial data output SDO pin is available for readback of

the internal RDAC register or 50-TP memory contents. The

contents of the RDAC register can be read back through

SDO by using Command 2 (see Table 6). Data from the

RDAC register is clocked out of the SDO pin during the last

10 clocks of the next SPI operation.

Table 7 provides a sample listing for the sequence of serial data

input (DIN) words with the serial data output appearing at the

SDO pin in hexadecimal format for a write and read to both the

RDAC register and the 50-TP memory (Memory Location 20).

It is possible to read back the contents of any of the 50-TP

memory registers through SDO by using Command 5. The

lower six LSB bits, D5 to D0 of the data byte, select which

memory location is to be read back, as shown in Table 10.

Table 6. Command Operation Truth Table

Command[DB13:DB10]

Data[DB9:DB0]¹

D9 D8 D7 D6 D5 D4 D3 D2

Command

Number

C3

0

C2

0

C1

0

C0

0

D1 D0 Operation

0

1

X

NOP: do nothing.

0

1

D9 D8 D7 D6 D5 D4 D3 D2

D1 D0

Write contents of serial register

data to RDAC.

2

0

1

0

1

0

1

0

1

0

1

X

Read contents of RDAC wiper

register.

3

Store wiper setting: store RDAC

setting to 50-TP.

4

Software reset: refresh RDAC with

last 50-TP memory stored value.

5²

6

D5 D4 D3 D2

D1 D0 Read contents of 50-TP from SDO

output in the next frame.

X

Read address of last 50-TP

programmed memory location.

7³

D1 D0

Write contents of serial register

data to control register.

8

9

1

0

1

X

Read contents of control register.

Software shutdown.

D0

D0 = 0; normal mode.

D0 = 1; device placed in shutdown

mode.

¹X is don’t care.

²See Table 10 for 50-TP memory map.

³See Table 9 for bit details.

Rev. 0 | Page 13 of 20

AD5174

SHUTDOWN MODE

RESET

The AD5174 can be shut down by executing the software

shutdown command, Command 9 (see Table 6), and setting

the LSB to 1. This feature places the RDAC in a zero-power-

consumption state where Terminal A is open circuited and

the wiper terminal, W, remains connected. It is possible to

execute any command from Table 6 while the AD5174 is in

shutdown mode. The parts can be taken out of shutdown

mode by executing Command 9 and setting the LSB to 0

or by a software reset, Command 4 (see Table 6).

The AD5174 can be reset through software by executing Com-

mand 4 (see Table 6). The reset command loads the RDAC

register with the contents of the most recently programmed 50-TP

memory location. The RDAC register loads with midscale if no

50-TP memory location has been previously programmed.

Table 7. Write and Read to RDAC and 50-TP Memory

DIN

SDO¹

Action

0x1C03 0xXXXX Enable update of the wiper position and the 50-TP memory contents through the digital interface.

0x0500 0x1C03 Write 0x100 to the RDAC register; wiper moves to ¼ full-scale position.

0x0800 0x0500 Prepares data read from RDAC register.

0x0C00 0x100

Stores RDAC register content into the 50-TP memory. A 16-bit word appears out of SDO, where the last 10 bits contain

the contents of the RDAC register (0x100).

0x1800 0x0C00 Prepares data read of the last programmed 50-TP memory monitor location.

0x0000 0xXX19 NOP Instruction 0 sends a 16-bit word out of SDO, where the six LSBs (that is, last six bits) contain the binary address of

the last programmed 50-TP memory location, for example, 0x19 (see Table 10).

0x1419 0x0000 Prepares data read from Memory Location 0x19.

0x2000 0x0100 Prepares data read from the control register. Sends a 16-bit word out of SDO, where the last 10 bits contain the

contents of Memory Location 0x19.

0x0000 0xXXXX NOP Instruction 0 sends a 16-bit word out of SDO, where the last four bits contain the contents of the control register.

If Bit C2 = 1, the fuse program command was successful.

¹X is don’t care.

Table 8. Control Register Bit Map

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

C2

0

C1

C0

Table 9. Control Register Bit Description

Bit Name

Description

C0

50-TP program enable

0 = 50-TP program disabled (default)

1 = enable device for 50-TP program

RDAC register write protect

0 = wiper position frozen to value in 50-TP memory (default)¹

1 = allow update of wiper position through digital interface

50-TP memory program success bit

C1

C2

0 = fuse program command was unsuccessful (default)

1 = fuse program command was successful

¹Wiper position frozen to the last value programmed in the 50-TP memory. The wiper is frozen to midscale if the 50-TP memory has not been previously programmed.

Rev. 0 | Page 14 of 20

AD5174

Table 10. Memory Map

Data Byte[DB9:DB0]¹

Command Number

D9

X

D8

X

D7

X

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

Register Contents

5

Reserved

X

0

1

1^stprogrammed wiper location (0x01)

2^ndprogrammed wiper location (0x02)

X

0

1

0

X

0

1

3^rdprogrammed wiper location (0x03)

4^thprogrammed wiper location (0x04)

X

0

1

0

…

X

…

X

…

X

…

0

…

0

…

0

…

1

…

0

…

1

…

0

…

10^thprogrammed wiper location (0xA)

…

X

…

X

…

X

…

0

…

0

…

1

…

0

…

1

…

0

…

0

…

20^thprogrammed wiper location (0x14)

…

X

…

X

…

X

…

0

…

0

…

1

…

1

…

1

…

1

…

0

…

30^thprogrammed wiper location (0x1E)

…

X

…

X

…

X

…

0

…

1

…

0

…

1

…

0

…

0

…

0

…

40^thprogrammed wiper location (0x28)

…

X

…

X

…

X

…

0

…

1

…

1

…

0

…

0

…

1

…

0

…

50^thprogrammed wiper location (0x32)

…

X

…

X

…

X

…

0

…

1

…

1

…

1

…

0

…

0

…

1

…

MSB resistance tolerance (0x39)

LSB resistance tolerance (0x3A)

X

0

1

0

1

0

¹X is don’t care.

DAISY-CHAIN OPERATION

RDAC ARCHITECTURE

The serial data output pin (SDO) serves two purposes: it can be

used to read the contents of the wiper setting and 50-TP values

using Command 2 and Command 5, respectively (see Table 6),

or the SDO pin can be used in daisy-chain mode. The remaining

instructions are valid for daisy chaining multiple devices in

simultaneous operations. Data is clocked out of SDO on the

rising edge of SCLK. Daisy chaining minimizes the number

of port pins required from the controlling IC. The SDO pin

contains an open-drain N-channel FET that requires a pull-up

resistor if this pin is used. As shown in Figure 26, users need

to tie the SDO pin of one package to the DIN pin of the next

package. Users may need to increase the clock period, because

the pull-up resistor and the capacitive loading at the SDO-to-

DIN interface may require additional time delay between

subsequent devices. When two AD5174 devices are daisy-

chained, 32 bits of data are required. The first 16 bits go

To achieve optimum performance, Analog Devices, Inc., has

patented the RDAC segmentation architecture for all the digital

potentiometers. In particular, the AD5174 employs a three-stage

segmentation approach as shown in Figure 27. The AD5174

wiper switch is designed with the transmission gate CMOS

topology.

A

R

L

R

M

S

W

10-BIT

ADDRESS

DECODER

R

W

SYNC

to U2, and the second 16 bits go to U1. Keep the

R

W

low until all 32 bits are clocked into their respective serial

SYNC

registers. The

operation.

pin is then pulled high to complete the

Figure 27. Simplified RDAC Circuit

V

DD

R

2.2kΩ

AD5174

U1

AD5174

U2

P

MOSI

µC

SCLK

DIN

SDO

SS

SYNC

SCLK

SYNC SCLK

Figure 26. Daisy-Chain Configuration Using SDO

Rev. 0 | Page 15 of 20

AD5174

Calculate the Actual End-to-End Resistance

PROGRAMMING THE VARIABLE RESISTOR

The resistance tolerance is stored in the internal memory

during factory testing. The actual end-to-end resistance can,

therefore, be calculated (which is valuable for calibration,

tolerance matching, and precision applications).

Rheostat Operation

The nominal resistance between Terminal W and Terminal A,

R_WA, is 10 kΩ and has 1024-tap points accessed by the wiper ter-

minal. The 10-bit data in the RDAC latch is decoded to select

one of the 1024 possible wiper settings. As a result, the general

equation for determining the digitally programmed output

resistance between the W terminal and the A terminal is

The resistance tolerance (in percentage) is stored in fixed-point

format, using a 16-bit sign magnitude binary. The sign bit(0 =

negative and 1 = positive) and the integer part is located in

Address 0x39 as shown in Table 10. Address 0x3A contains the

fractional part as shown in Table 11.

D

1024

R_WA(D) =

×R_WA

(1)

That is, if the data readback from Address 0x39 is 0000001010 and

data from Address 0x3A is 0010110000, then the end-to-end

resistance can be calculated as follows.

where:

D is the decimal equivalent of the binary code loaded in the

10-bit RDAC register.

R

_WAis the end-to-end resistance.

For Memory Location 0x39,

In the zero-scale condition, a finite total wiper resistance of

120 Ω is present. Regardless of which setting the part is oper-

ating in, take care to limit the current between Terminal A and

Terminal W to the maximum continuous current of 6 mA or

a pulse current specified in Table 3. Otherwise, degradation or

possible destruction of the internal switch contact may occur.

DB[9:8]: XX = don’t care

DB[7]: 0 = negative

DB[6:0]: 0001010 = 10

For Memory Location 0x3A,

DB[9:8]: XX = don’t care

DB[7:0]: 10110000 = 176 × 2⁻⁸= 0.6875

Therefore, tolerance = −10.6875% and R_WA(1023)= 8.931 kΩ.

Table 11. End-to-End Resistance Tolerance Bytes

Data Byte¹

Memory Map Address

DB9

X

DB8

X

DB7

Sign

2⁻¹

DB6

2⁶

2⁻²

DB5

2⁵

2⁻³

DB4

2⁴

2⁻⁴

DB3

2³

2⁻⁵

DB2

2²

2⁻⁶

DB1

2¹

2⁻⁷

DB0

2⁰

2⁻⁸

0x39

0x3A

¹X is don’t care.

Rev. 0 | Page 16 of 20

AD5174

The ground pin of the AD5174 is primarily used as a digital

EXT_CAP CAPACITOR

ground reference. To minimize the digital ground bounce, join the

AD5174 ground terminal remotely to the common ground. The

digital input control signals to the AD5174 must be referenced

to the device ground pin (GND) and must satisfy the logic level

defined in the Specifications section. An internal level shift

circuit ensures that the common-mode voltage range of the

three terminals extends from V_SSto V_DD, regardless of the

digital input level.

A 1 μF capacitor to V_SSmust be connected to the EXT_CAP

pin, as shown in Figure 28, on power-up and throughout the

operation of the AD5174.

AD5174

50-TP

MEMORY

EXT_CAP

BLOCK

C1

1µF

POWER-UP SEQUENCE

V

SS

Because there are diodes to limit the voltage compliance at

Terminal A and Terminal W (see Figure 29), it is important to

power V_DD/V_SSfirst before applying any voltage to Terminal A

and Terminal W; otherwise, the diode is forward-biased such

that V_DD/V_SSare powered unintentionally. The ideal power-

up sequence is V_SS, GND, V_DD, digital inputs, V_A, and V_W.

The order of powering V_A, V_W, and the digital inputs is not

important as long as they are powered after V_DD/V_SS.

V

Figure 28. EXT_CAP Hardware Setup

TERMINAL VOLTAGE OPERATING RANGE

The positive V_DDand negative V_SSpower supplies of the AD5174

define the boundary conditions for proper 2-terminal digital

resistor operation. Supply signals present on Terminal A and

Terminal W that exceed V_DDor V_SSare clamped by the internal

forward-biased diodes (see Figure 29).

As soon as V_DDis powered, the power-on preset activates,

which first sets the RDAC to midscale and then restores the

last programmed 50-TP value to the RDAC register.

V

DD

A

W

V

SS

Figure 29. Maximum Terminal Voltages Set by V_DDand V_SS

Rev. 0 | Page 17 of 20

AD5174

OUTLINE DIMENSIONS

2.48

2.38

2.23

3.10

3.00 SQ

2.90

0.50 BSC

6

10

PIN 1 INDEX

EXPOSED

PAD

1.74

1.64

1.49

AREA

0.50

0.40

0.30

5

1

PIN 1

INDICATOR

TOP VIEW

BOTTOM VIEW

(R 0.15)

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.30

0.25

0.20

0.20 REF

Figure 30. 10-Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3mm Body, Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

3.10

3.00

2.90

10

1

6

5

5.15

4.90

4.65

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.50 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.70

0.55

0.40

0.15

0.05

0.23

0.13

6°

0°

0.30

0.15

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 31. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

AD5174BRMZ-10

AD5174BRMZ-10-RL7

AD5174BCPZ-10-R2

AD5174BCPZ-10-RL7

R_AB(kΩ) Resolution Temperature Range

Package Description

10-Lead MSOP

10-Lead LFCSP_WD

Package Option Branding

10

1,024

−40°C to +125°C

RM-10

DDT

DEF

RM-10

CP-10-9

¹Z = RoHS Compliant Part.

Rev. 0 | Page 18 of 20

AD5174

NOTES

Rev. 0 | Page 19 of 20

AD5174

NOTES

registered trademarks are the property of their respective owners.

D08718-0-3/10(0)

Rev. 0 | Page 20 of 20


型号：	AD5174BCPZ-10-R2
厂家：	ADI
描述：	Single-Channel, 1024-Position, Digital Rheostat with SPI Interface and 50-TP Memory 单通道， 1024位数字变阻器，SPI接口和50 -TP存储器存储
文件：	总20页 (文件大小：1003K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5174BCPZ-10-R2 [ADI]

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