AD5175BCPZ-10-R2_技术文档

Single-Channel, 1024-Position, Digital Rheostat

with I²C Interface and 50-TP Memory

AD5175

FUNCTIONAL BLOCK DIAGRAM

FEATURES

V

DD

Single-channel, 1024-position resolution

10 kΩ nominal resistance

50-times programmable (50-TP) wiper memory

Rheostat mode temperature coefficient: 35 ppm/°C

2.7 V to 5.5 V single-supply operation

2.5 V to 2.75 V dual-supply operation for ac or bipolar

operations

POWER-ON

RESET

AD5175

RDAC

REGISTER

SCL

SDA

A

I²C-compatible interface

2

10

I C

SERIAL

INTERFACE

Wiper setting and memory readback

Power on refreshed from memory

Resistor tolerance stored in memory

Thin LFCSP, 10-lead, 3 mm × 3 mm × 0.8 mm package

Compact MSOP, 10-lead 3 mm × 4.9 mm × 1.1 mm package

W

50-TP

MEMORY

BLOCK

ADDR

RESET

V

EXT_CAP

GND

SS

APPLICATIONS

Figure 1.

Mechanical rheostat replacements

Op-amp: variable gain control

Instrumentation: gain, offset adjustment

Programmable voltage to current conversions

Programmable filters, delays, time constants

Programmable power supply

Sensor calibration

GENERAL DESCRIPTION

The AD5175 is a single-channel, 1024-position digital rheostat

that combines industry leading variable resistor performance

with nonvolatile memory (NVM) in a compact package.

voltage supply to facilitate fuse blow and there are 50 oppor-

tunities for permanent programming. During 50-TP activation,

a permanent blow fuse command freezes the resistance position

(analogous to placing epoxy on a mechanical rheostat).

This device supports both dual-supply operation at 2.5 V to

2.75 V and single-supply operation at 2.7 V to 5.5 V, and offers

50-times programmable (50-TP) memory.

The AD5175 is available in a 3 mm × 3mm 10-lead LFCSP

package and in a 10-lead MSOP package. The part is guaranteed

to operate over the extended industrial temperature range of

−40°C to +125°C.

The AD5175 device wiper settings are controllable through the

I²C–compatible digital interface. Unlimited adjustments are

allowed before programming the resistance value into the

50-TP memory. The AD5175 does not require any external

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD5175

TABLE OF CONTENTS

Features .............................................................................................. 1

Shift Register............................................................................... 12

Write Operation.......................................................................... 13

Read Operation........................................................................... 15

RDAC Register............................................................................ 16

50-TP Memory Block ................................................................ 16

Write Protection ......................................................................... 16

50-TP Memory Write-Acknowledge Polling.......................... 18

Reset............................................................................................. 18

Shutdown Mode ......................................................................... 18

RDAC Architecture.................................................................... 18

Programming the Variable Resistor......................................... 18

EXT_CAP Capacitor.................................................................. 19

Terminal Voltage Operating Range ......................................... 19

Power-Up Sequence ................................................................... 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Interface Timing Specifications.................................................. 4

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Test Circuits..................................................................................... 11

Theory of Operation ...................................................................... 12

Serial Data Interface................................................................... 12

REVISION HISTORY

3/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

AD5175

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V_DD= 2.7 V to 5.5 V, V_SS= 0 V; V_DD= 2.5 V to 2.75 V, V_SS= −2.5 V to −2.75 V; −40°C < T_A< +125°C, unless otherwise noted.

Table 1.

Parameter

Symbol

R-INL

Test Conditions/Comments

Min

Typ¹Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution

Resistor Integral Nonlinearity^{2, 3}

10

−1

−2.5

−1

Bits

LSB

%

|V_DD− V_SS| = 3.6 V to 5.5 V

|V_DD− V_SS| = 3.3 V to 3.6 V

|V_DD− V_SS| = 2.7 V to 3.3 V

+1

+1.5

+2.5

+1

Resistor Differential Nonlinearity²

Nominal Resistor Tolerance

Resistance Temperature Coefficient^{4, 5}

Wiper Resistance

RESISTOR TERMINALS

Terminal Voltage Range^{4, 6}

Capacitance A⁴

R-DNL

15

35

Code = full scale

Code = zero scale

ppm/°C

Ω

35

70

V_TERM

V_SS

V_DD

V

f = 1 MHz, measured to GND, code = half scale

V_A= V_W

90

40

pF

nA

Capacitance W⁴

Common-Mode Leakage Current⁴

50

DIGITAL INPUTS

Input Logic⁴

High

Low

Input Current

Input Capacitance⁴

DIGITAL OUTPUT

Output Voltage⁴

V_INH

V_INL

I_IN

2.0

V

μA

pF

0.8

1

5

C_IN

High

Low

V_OH

V_OL

R_{PULL_UP}= 2.2 kΩ to V_DD

V_DD− 0.1

V

V_DD= 2.7 V to 5.5 V, V_SS= 0 V

V_DD= 2.5 V to 2.75 V, V_SS= −2.5 V to −2.75 V

0.4

0.6

+1

V

μA

pF

Tristate Leakage Current

Output Capacitance⁴

POWER SUPPLIES

Single-Supply Power Range

Dual-Supply Power Range

Supply Current

−1

5

V_SS= 0 V

2.7

2.5

5.5

2.75

V

Positive

Negative

50-TP Store Current^{4, 7}

I_DD

I_SS

1

μA

−1

Positive

Negative

50-TP Read Current^{4, 8}

I_{DD_OTP_STORE}

I_{SS_OTP_STORE}

4

−4

mA

Positive

Negative

Power Dissipation⁹

Power Supply Rejection Ratio⁴

I_{DD_OTP_READ}

I_{SS_OTP_READ}

P_DISS

500

5.5

μA

μW

dB

−500

−50

V_IH= V_DDor V_IL= GND

PSRR

ΔV_DD/ΔV_SS

=

5 V 10%

−55

Rev. 0 | Page 3 of 20

AD5175

Parameter

DYNAMIC CHARACTERISTICS^{4, 10}

Symbol

Test Conditions/Comments

Min

Typ¹Max

Unit

Bandwidth

Total Harmonic Distortion

Resistor Noise Density

−3 dB, R_AW= 5 kΩ, Terminal W, see Figure 23

V_A= 1 V rms, f = 1 kHz, R_AW= 5 kΩ

R_WB= 5 kΩ, T_A= 25°C, f = 10 kHz

700

−90

13

kHz

dB

nV/√Hz

¹Typical specifications represent average readings at 25°C, V_DD= 5 V, and V_SS= 0 V.

²Resistor position nonlinearity error (R-INL) is the deviation from the ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions.

³The maximum current in each code is defined by I_AW= (V_DD− 1)/R_AW

⁴Guaranteed by design and not subject to production test.

⁵See Figure 8 for more details.

.

⁶Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar

signal adjustment.

⁷Different from operating current; the supply current for the fuse program lasts approximately 55 ms.

⁸Different from operating current; the supply current for the fuse read lasts approximately 500 ns.

⁹P_DISSis calculated from (I_DD× V_DD) + (I_SS× V_SS).

¹⁰All dynamic characteristics use V_DD= +2.5 V, V_SS= −2.5 V.

INTERFACE TIMING SPECIFICATIONS

V_DD= 2.7 V to 5.5 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

Limit at T_MIN, T_MAX

Parameter

Conditions¹

Standard mode

Fast mode

Min

Max

100

400

Unit

kHz

μs

ns

μs

ns

μs

ns

Description

2

f_SCL

Serial clock frequency

t_HIGH, SCL high time

t_LOW, SCL low time

t_SU;DAT, data setup time

t₁

t₂

t₃

t₄

t₅

t₆

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

Fast mode

High speed mode

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

4

0.6

4.7

1.3

250

100

0

3.45

0.9

t_HD;DAT, data hold time

0

4.7

0.6

4

0.6

160

4.7

1.3

4

t_SU;STA, set-up time for a repeated start condition

t_SU;STA,set-up time for a repeated start condition

t_HD;STA, hold time (repeated) start condition

t_BUF, bus free time between a stop and a start condition

t_SU;STO, setup time for a stop condition

t_RDA, rise time of the SDA signal

t_FDA, fall time of the SDA signal

t_RCL, rise time of the SCL signal

t₇

t₈

0.6

t₉

1000

300

1000

300

t₁₀

t₁₁

t_11A

1000

t_RCL1, rise time of the SCL signal after a repeated start condition

and after an acknowledge bit

Fast mode

300

ns

t_RCL1, rise time of the SCL signal after a repeated start condition

and after an acknowledge bit

t₁₂

t₁₃

Standard mode

Fast mode

RESET pulse time

Fast mode

300

ns

t_FCL, fall time of the SCL signal

Minimum RESET low time

20

0

500

3

t_SP

t_EXEC

50

Pulse width of the spike is suppressed

Command execute time

4, 5

Rev. 0 | Page 4 of 20

AD5175

Limit at T_MIN, T_MAX

Parameter

t_{RDAC_R-PERF}

t_{RDAC_NORMAL}

t_{MEMORY_READ}

t_{MEMORY_PROGRAM}

t_RESET

Conditions¹

Min

Max

2

Unit

μs

ns

μs

ms

μs

Description

RDAC register write command execute time (R-Perf mode)

RDAC register write command execute time (normal mode)

Memory readback execute time

Memory program time

Reset 50-TP restore time

600

6

350

600

2

6

t_POWER-UP

ms

Power-on 50-TP restore time

¹Maximum bus capacitance is limited to 400 pF.

²The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior

of the part.

³Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.

⁴Refer to t_{RDAC_R-PERF}and t_{RDAC_NORMAL}for RDAC register write operations.

⁵Refer to t

t

_{MEMORY_READ}and _{MEMORY_PROGRAM}for memory commands operations.

⁶Maximum time after V_DD− V_SSis equal to 2.5 V.

Shift Register and Timing Diagrams

DB9 (MSB)

DB0 (LSB)

D0

D1

C3

C1

C0

D9

D7

D6

D5

D4

D3

0

C2

D8

D2

DATA BITS

CONTROL BITS

Figure 2. Shift Register Content

t₁₁

t₁₂

t₆

t₈

t₂

SCL

SDA

t₅

t₁

t₆

t₁₀

t₉

t₄

t₃

t₇

P

S

P

t₁₃

RESET

Figure 3. 2-Wire I²C Timing Diagram

Rev. 0 | Page 5 of 20

AD5175

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3.

Parameter

Rating

V_DDto GND

V_SSto GND

V_DDto V_SS

–0.3 V to +7.0 V

+0.3 V to −7.0 V

7 V

V_A, V_Wto GND

V_SS− 0.3 V, V_DD+ 0.3 V

−0.3 V to V_DD+ 0.3 V

7 V

THERMAL RESISTANCE

Digital Input and Output Voltage to GND

EXT_CAP to V_SS

I_A, I_W

θ_JAis defined by JEDEC specification JESD-51 and the value is

dependent on the test board and test environment.

Pulsed¹

6 mA/d²

6 mA/√d²

6 mA

−40°C to +125°C

150°C

Table 4. Thermal Resistance

Frequency > 10 kHz

Frequency ≤ 10 kHz

Continuous

Package Type

10-Lead LFCSP

10-Lead MSOP

θ_JA

θ_JC

3

N/A

Unit

°C/W

50

135¹

Operating Temperature Range³

Maximum Junction Temperature

(T_JMaximum)

¹JEDEC 2S2P test board, still air (0 m/sec airflow).

Storage Temperature Range

Reflow Soldering

Peak Temperature

−65°C to +150°C

ESD CAUTION

260°C

Time at Peak Temperature

Package Power Dissipation

20 sec to 40 sec

(T_Jmax − T_A)/θ_JA

¹Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum

applied voltage across any two of the A and W terminals at a given

resistance.

²Pulse duty factor.

³Includes programming of 50-TP memory.

Rev. 0 | Page 6 of 20

AD5175

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

10 ADDR

V

1

2

3

4

5

DD

A

9

8

7

6

SCL

AD5175

SDA

W

V

1

2

3

4

5

10

9

ADDR

SCL

DD

A

(EXPOSED

PAD)*

AD5175

V

RESET

GND

SS

8

W

SDA

EXT_CAP

TOP VIEW

(Not to Scale)

V

7

SS

EXT_CAP

RESET

GND

6

*LEAVE FLOATING OR CONNECTED TO V

SS

.

Figure 4. MSOP Pin Configuration

Figure 5. LFCSP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.

Terminal A of RDAC. V_SS≤ V_A≤ V_DD

Wiper Terminal of RDAC. V_SS≤ V_W≤ V_DD

1

2

3

4

V_DD

A

W

.

V_SS

Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 ꢀF ceramic capacitors

and 10 ꢀF capacitors.

5

EXT_CAP

External Capacitor. Connect a 1 μF capacitor between EXT_CAP and V_SS. This capacitor must have a voltage

rating of ≥7 V.

6

7

GND

RESET

Ground Pin, Logic Ground Reference.

Hardware Reset Pin. Refreshes the RDAC register with the contents of the 50-TP memory register. Factory

default loads midscale until the first 50-TP wiper memory location is programmed. RESET is active low. Tie RESET

to V_DDif not used.

8

9

SDA

SCL

Serial Data Line. This pin is used in conjunction with the SCL line to clock data into or out of the 16-bit input

registers. It is a bidirectional, open-drain data line that should be pulled to the supply with an external

pull-up resistor.

Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 16-bit

input registers.

10

EPAD

ADDR

Exposed Pad

Tristate Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 6).

Leave floating or connected to V_SS

Rev. 0 | Page 7 of 20

AD5175

TYPICAL PERFORMANCE CHARACTERISTICS

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

V

/V = 5V/0V

DD SS

+25°C

–40°C

+125°C

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

0

–0.1

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VOLTAGE (V)

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 9. Supply Current (I_DD) vs. Digital Input Voltage

Figure 6. R-INL in Normal Mode vs. Code vs. Temperature

500

0.4

+25°C

–40°C

+125°C

400

300

I

= 5V

DD

0.3

0.2

200

I

= 3V

DD

100

0.1

I

= 3V

0

SS

0

–100

–200

–300

–400

–500

–0.1

–0.2

–0.3

I

= 5V

SS

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100 110

TEMPERATURE (°C)

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 7. R-DNL in Normal Mode vs. Code vs. Temperature

Figure 10. Supply Current (I_DD, I_SS) vs. Temperature

700

600

7

6

5

4

3

V

/V = 5V/0V

DD SS

V

/V = 5V/0V

DD SS

500

400

300

200

100

0

2

1

0

128

256

384

512

640

768

896

1023

0

85 170 255 340 425 510 595 680 765 850 935 1023

CODE (Decimal)

Figure 8. Tempco ΔR_WA/ΔT vs. Code

Figure 11. Theoretical Maximum Current vs. Code

Rev. 0 | Page 8 of 20

AD5175

0

–20

–25

V

/V = 5V/0V

DD SS

0x200

0x100

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

CODE = HALF SCALE

–30

–35

–40

–45

–50

–55

0x080

0x040

0x020

0x010

0x008

0x004

0x002

0x001

V

/V = 5V/0V

DD SS

–60

1

10

100

1k

10k

100k 1M

10M

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 12. Bandwidth vs. Frequency vs. Code

Figure 15. PSRR vs. Frequency

8

7

0

V

/V = ±2.5V

DD SS

CODE = HALF SCALE

= 1V rms

f

IN

NOISE BW = 22kHz

–20

–40

–60

6

5

4

–80

–100

–120

0.07

0.09

0.11

0.13

0.15

0.17

10

100

1k

10k

1M

100k

TIME (Seconds)

FREQUENCY (Hz)

Figure 13. THD + N vs. Frequency

Figure 16. V_{EXT_CAP}Waveform While Writing Fuse

20

10

0

V

/V = ±2.5V

= 200µA

10kΩ

DD SS

I

AW

–20

–40

0

–10

–20

–30

–40

–50

–60

–70

–60

–80

V

/V = ±2.5V

DD SS

CODE = HALF SCALE

f_IN= 1kHz

NOISE BW = 22kHz

–100

–2

0

2

4

0.001

0.01

0.1

1

TIME (µs)

AMPLITUDE (V rms)

Figure 17. Maximum Glitch Energy

Figure 14. THD + N vs. Amplitude

Rev. 0 | Page 9 of 20

AD5175

1.0

0.006

0.005

0.004

0.003

0.002

0.001

0

V

/V = 5V/0V

= 10µA

DD SS

I

AW

CODE = HALF SCALE

0.5

0

–0.5

–1.0

–0.001

–0.002

V

/V = ±2.5V

= 200µA

DD SS

I

AW

–1.5

–10

0

10

20

30

40

50

60

0

100 200 300 400 500 600 700 800 900 1000

OPERATION AT 150°C (Hours)

TIME (µs)

Figure 18. Digital Feedthrough

Figure 19. Long-Term Drift Accelerated Average by Burn-In

Rev. 0 | Page 10 of 20

AD5175

TEST CIRCUITS

Figure 20 to Figure 24 define the test conditions used in the Specifications section.

DUT

I

W

1GΩ

W

A

V

MS

Figure 23. Gain vs. Frequency

Figure 20. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

DUT

GND

V

I

MS

I

R

=

CM

WA

W

+2.75V

–2.75V

W

CODE = 0x00

DUT

A

R

WA

2

I

W

R

W

A

W

NC

GND

–2.75V

V

MS

NC = NO CONNECT

+2.75V

Figure 21. Wiper Resistance

Figure 24. Common Leakage Current

V+ = V ±10%

DD

V

MS

PSRR (dB) = 20 log

DD

ΔV

%

MS

DD

I

W

PSS (%/%) =

V

DD

W

V+

A

V

MS

Figure 22. Power Supply Sensitivity (PSS, PSRR)

Rev. 0 | Page 11 of 20

AD5175

THEORY OF OPERATION

The AD5175 is designed to operate as a true variable resistor for

analog signals within the terminal voltage range of V_SS< V_TERM

< V_DD. The RDAC register contents determine the resistor wiper

position. The RDAC register acts as a scratchpad register, which

allows unlimited changes of resistance settings. The RDAC

register can be programmed with any position setting using

the I²C interface. When a desirable wiper position is found, this

value can be stored in a 50-TP memory register. Thereafter, the

wiper position is always restored to that position for subsequent

power-up. The storing of 50-TP data takes approximately 350 ms;

during this time, the AD5175 is locked and does not acknowl-

edge any new command thereby preventing any changes from

taking place. The acknowledge bit can be polled to verify that

the fuse program command is complete.

The 2-wire serial bus protocol operates as follows: The master

initiates a data transfer by establishing a start condition, which

is when a high-to-low transition on the SDA line occurs while

SCL is high. The next byte is the address byte, which consists

W

of the 7-bit slave address and a R/ bit. The slave device

corresponding to the transmitted address responds by pulling

SDA low during the ninth clock pulse (this is termed the acknowl-

edge bit). At this stage, all other devices on the bus remain idle

while the selected device waits for data to be written to, or read

from, its shift register.

Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge bit).

The transitions on the SDA line must occur during the low

period of SCL and remain stable during the high period of SCL.

SERIAL DATA INTERFACE

When all data bits have been read or written, a stop condition is

established. In write mode, the master pulls the SDA line high

during the 10^thclock pulse to establish a stop condition. In read

mode, the master issues a no acknowledge for the ninth clock

pulse, that is, the SDA line remains high. The master then

brings the SDA line low before the 10^thclock pulse, and then

high during the 10^thclock pulse to establish a stop condition.

The AD5175 has a 2-wire I²C-compatible serial interface.

It can be connected to an I²C bus as a slave device under the

control of a master device; see Figure 3 for a timing diagram

of a typical write sequence.

The AD5175 supports standard (100 kHz) and fast (400 kHz)

data transfer modes. Support is not provided for 10-bit

addressing and general call addressing.

SHIFT REGISTER

The AD5175 has a 7-bit slave address. The five MSBs are 01011

and the two LSBs are determined by the state of the ADDR pin.

The facility to make hardwired changes to ADDR allows the

user to incorporate up to three of these devices on one bus, as

outlined in Table 6.

For the AD5175, the shift register is 16 bits wide, as shown in

Figure 2. The 16-bit word consists of two unused bits, which

should be set to 0, followed by four control bits and 10 RDAC data

bits, and data is loaded MSB first (Bit D9). The four control bits

determine the function of the software command (Table 7).

Figure 25 shows a timing diagram of a typical AD5175 write

sequence.

The command bits (Cx) control the operation of the digital

potentiometer and the internal 50-TP memory. The data bits

(Dx) are the values that are loaded into the decoded register.

Table 6. Device Address Selection

ADDR Pin

A1

1

A0

1

7-Bit I²C Device Address

0101111

GND

V_DD

0

1

0

0101100

0101110

NC (No Connection)¹

¹Not available in bipolar mode. V_SS< 0 V.

Rev. 0 | Page 12 of 20

AD5175

Two bytes of data are then written to the RDAC, the most

WRITE OPERATION

significant byte followed by the least significant byte; both

of these data bytes are acknowledged by the AD5175. A stop

condition follows. The write operations for the AD5175 are

shown in Figure 25.

It is possible to write data for the RDAC register or the control

register. When writing to the AD5175, the user must begin with

W

a start command followed by an address byte (R/ = 0), after

which the AD5175 acknowledges that it is prepared to receive

data by pulling SDA low.

A repeated write function gives the user flexibility to update the

device a number of times after addressing the part only once, as

shown in Figure 26.

1

9

1

0

9

SCL

1

0

1

A1

A0

R/W

0

C3

C2

D9

D8

SDA

START BY

C1

C0

ACK. BY

AD5175

ACK. BY

AD5175

MASTER

FRAME 2

FRAME 1

MOST SIGNIFICANT DATA BYTE

SERIAL BUS ADDRESS BYTE

9

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

AD5175

STOP BY

MASTER

FRAME 3

LEAST SIGNIFICANT DATA BYTE

Figure 25. Write Command

Rev. 0 | Page 13 of 20

AD5175

1

9

1

0

9

SCL

1

0

1

A1

A0

R/W

0

C3

C2

C1

C0

D9

D8

SDA

START BY

ACK. BY

AD5175

ACK. BY

AD5175

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

MOST SIGNIFICANT DATA BYTE

9

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

AD5175

FRAME 3

LEAST SIGNIFICANT DATA BYTE

9

1

0

9

SCL (CONTINUED)

SDA (CONTINUED)

0

C3

C2

C1

C0

D9

D8

ACK. BY

AD5175

FRAME 4

MOST SIGNIFICANT DATA BYTE

9

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

AD5175

STOP BY

MASTER

FRAME 5

LEAST SIGNIFICANT DATA BYTE

Figure 26. Multiple Write

Rev. 0 | Page 14 of 20

AD5175

READ OPERATION

When reading data back from the AD5175, the user must first

issue a readback command to the device, this begins with a start

which enables readback of the RDAC register, 50-TP memory,

or the control register. The user can then read back the data

beginning with a start command followed by an address byte

W

command followed by an address byte (R/ = 0), after which

W

(R/ = 1), after which the device acknowledges that it is

the AD5175 acknowledges that it is prepared to receive data by

pulling SDA low.

prepared to transmit data by pulling SDA low. Two bytes of

data are then read from the device, as shown in Figure 27. A

stop condition follows. If the master does not acknowledge the

first byte, the second byte is not transmitted by the AD5175.

Two bytes of data are then written to the AD5175, the most

significant byte followed by the least significant byte; both

of these data bytes are acknowledged by the AD5175. A stop

condition follows. These bytes contain the read instruction,

1

9

1

0

9

SCL

1

SDA

START BY

0

1

A1

A0

R/W

0

C3

C2

C1

C0

D9

D8

ACK. BY

AD5175

ACK. BY

AD5175

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

MOST SIGNIFICANT DATA BYTE

9

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

AD5175

STOP BY

MASTER

FRAME 3

LEAST SIGNIFICANT DATA BYTE

1

9

1

9

SCL

SDA

START BY

1

0

1

A1

A0

R/W

0

X

D9

D8

ACK. BY

AD5175

ACK. BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

MOST SIGNIFICANT DATA BYTE

9

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

NO ACK. BY STOP BY

MASTER MASTER

FRAME 3

LEAST SIGNIFICANT DATA BYTE

Figure 27. Read Command

Rev. 0 | Page 15 of 20

AD5175

Prior to 50-TP activation, the AD5175 presets to midscale on

power-up. It is possible to read back the contents of any of the

50-TP memory registers through the I²C interface by using

Command 5 in Table 7. The lower six LSB bits, D0 to D5 of

the data byte, select which memory location is to be read back.

A binary encoded version address of the most recently pro-

grammed wiper memory location can be read back using

Command 6 in Table 7. This can be used to monitor the

spare memory status of the 50-TP memory block.

RDAC REGISTER

The RDAC register directly controls the position of the digital

rheostat wiper. For example, when the RDAC register is loaded

with all 0s, the wiper is connected to Terminal A of the variable

resistor. It is possible to both write to and read from the RDAC

register using the I²C interface. The RDAC register is a standard

logic register; there is no restriction on the number of changes

allowed.

50-TP MEMORY BLOCK

WRITE PROTECTION

The AD5175 contains an array of 50-TP programmable

memory registers, which allow the wiper position to be pro-

grammed up to 50 times. Table 11 shows the memory map.

Command 3 in Table 7 programs the contents of the RDAC

register to memory. The first address to be programmed is

Location 0x01, see Table 11, and the AD5175 increments the

50-TP memory address for each subsequent program until

the memory is full. Programming data to 50-TP consumes

approximately 4 mA for 55 ms, and takes approximately

350 ms to complete, during which time the shift register is

locked preventing any changes from taking place. Bit C2 of

the control register in Table 10 can be polled to verify that the

fuse program command was successful. No change in supply

voltage is required to program the 50-TP memory; however, a

1 μF capacitor on the EXT_CAP pin is required as shown in

Figure 29.

On power-up, serial data input register write commands for

both the RDAC register and the 50-TP memory registers are

disabled. The RDAC write protect bit (Bit C1) of the control

register (see Table 9 and Table 10), is set to 0 by default. This

disables any change of the RDAC register content regardless

of the software commands, except that the RDAC register can

be refreshed from the 50-TP memory using the software reset,

RESET

Command 4, or through the hardware by the

pin. To

enable programming of the variable resistor wiper position

(programming the RDAC register), the write protect bit

(Bit C1) of the control register must first be programmed.

This is accomplished by loading the serial data input register

with Command 7 (see Table 7). To enable programming of the

50-TP memory block, Bit C0 of the control register, which is set

to 0 by default, must first be set to 1.

Table 7. Command Operation Truth Table

Command[DB13:DB10]

Data[DB9:DB0]¹

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Operation

Command

Number

C3 C2 C1 C0

0

1

0

1

X

NOP: do nothing.

D9 D8 D7 D6 D5 D4 D3 D2 D1

D

Write contents of serial register data

to RDAC.

2

3

0

1

0

1

X

Read contents of RDAC wiper register.

Store wiper setting: store RDAC setting

to 50-TP.

4

0

1

0

1

0

1

0

1

X

Software reset: refresh RDAC with the

last 50-TP memory stored value.

5²

6

D5 D4 D3 D2 D1 D0 Read contents of 50-TP from the SDO

output in the next frame.

X

Read address of the last 50-TP

programmed memory location.

7³

X

D1 D0 Write contents of the serial register data

to the control register.

8

9

1

0

1

X

Read contents of the control register.

D0 Software shutdown.

D0 = 0; normal mode.

D0 = 1; shutdown mode.

¹X is don’t care.

²See Table 11 for the 50-TP memory map.

³See Table 10 for bit details.

Rev. 0 | Page 16 of 20

AD5175

Table 8. Write and Read to RDAC and 50-TP Memory

DIN Action

SDO¹

0x1C03 0xXXXX Enable update of wiper position and 50-TP memory contents through digital interface.

0x0500 0x1C03 Write 0x100 to the RDAC register, wiper moves to ¼ full-scale position.

0x0800 0x0500 Prepare data read from RDAC register.

0x0C00 0x100

Stores RDAC register content into 50-TP memory. 16-bit word appears out of SDO, where the last 10-bits contain the

contents of the RDAC Register 0x100.

0x1800 0x0C00 Prepare data read of the last programmed 50-TP memory monitor location.

0x0000 0xXX19 NOP Instruction 0 sends a 16-bit word out of SDO, where the six LSBs (that is, the last 6 bits) contain the binary address

of the last programmed 50-TP memory location, for example, 0x19 (see Table 11).

0x1419 0x0000 Prepares data read from Memory Location 0x19.

0x2000 0x0100 Prepare data read from the control register. Sends a 16-bit word out of SDO, where the last 10-bits contain the contents

of Memory Location 0x19.

0x0000 0xXXXX NOP Instruction 0 sends a 16-bit word out of SDO, where the last four bits contain the contents of the control register.

If Bit C2 = 1, fuse program command successful.

¹X is don’t care.

Table 9. Control Register Bit Map

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

C2

0

C1

C0

Table 10. Control Register Description

Bit Name

Description

C0

50-TP program enable

0 = 50-TP program disabled (default)

1 = enable device for 50-TP program

RDAC register write protect

0 = wiper position frozen to value in OTP memory (default)¹

1 = allow update of wiper position through a digital interface

50-TP memory program success bit

C1

C2

0 = fuse program command unsuccessful (default)

1 = fuse program command successful

¹Wiper position is frozen to the last value programmed in the 50-TP memory. Wiper freezes to midscale if 50-TP memory has not been previously programmed.

Table 11. Memory Map

Data Byte[DB9:DB0]¹

Command Number

D9

X

D8

X

D7

X

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

Register Contents

5

Reserved

X

0

1

1^stprogrammed wiper location (0x01)

2^ndprogrammed wiper location (0x02)

X

0

1

0

X

0

1

3^rdprogrammed wiper location (0x03)

4^thprogrammed wiper location (0x04)

X

0

1

0

…

X

…

X

…

X

…

0

…

0

…

0

…

1

…

0

…

1

…

0

…

10^thprogrammed wiper location (0xA)

…

X

…

X

…

X

…

0

…

0

…

1

…

0

…

1

…

0

…

0

…

20^thprogrammed wiper location (0x14)

…

X

…

X

…

X

…

0

…

0

…

1

…

1

…

1

…

1

…

0

…

30^thprogrammed wiper location (0x1E)

…

X

…

X

…

X

…

0

…

1

…

0

…

1

…

0

…

0

…

0

…

40^thprogrammed wiper location (0x28)

…

X

…

X

…

X

…

0

…

1

…

1

…

0

…

0

…

1

…

0

…

50^thprogrammed wiper location (0x32)

…

X

…

X

…

X

…

0

…

1

…

1

…

1

…

0

…

0

…

1

…

MSB resistance tolerance (0x39)

LSB resistance tolerance (0x3A)

X

0

1

0

1

0

¹X is don’t care.

Rev. 0 | Page 17 of 20

AD5175

RDAC ARCHITECTURE

50-TP MEMORY WRITE-ACKNOWLEDGE POLLING

To achieve optimum performance, Analog Devices, Inc., has

patented the RDAC segmentation architecture for all the

digital potentiometers. In particular, the AD5175 employs a

three-stage segmentation approach, as shown in Figure 28.

The AD5175 wiper switch is designed with the transmission

gate CMOS topology.

After each write operation to the 50-TP registers, an internal

write cycle begins. The I²C interface of the device is disabled.

To determine if the internal write cycle is complete and the

I²C interface is enabled, interface polling can be executed. I²C

interface polling can be conducted by sending a start condition

followed by the slave address and the write bit. If the I²C inter-

face responds with an acknowledge (ACK), the write cycle is

complete and the interface is ready to proceed with further

operations. Otherwise, I²C interface polling can be repeated

until it completes.

A

R

L

RESET

R

M

The AD5175 can be reset through software by executing

Command 4 (see Table 7) or through hardware on the low

S

W

10-BIT

RESET

pulse of the

pin. The reset command loads the RDAC

ADDRESS

DECODER

R

W

register with the contents of the most recently programmed

50-TP memory location. The RDAC register loads with

midscale if no 50-TP memory location has been previously

W

R

W

RESET

programmed. Tie

to V_DDif the

pin is not used.

SHUTDOWN MODE

Figure 28. Simplified RDAC Circuit

The AD5175 can be shut down by executing the software

shutdown command, Command 9 (see Table 7), and setting

the LSB to 1. This feature places the RDAC in a zero-power-

consumption state where Terminal A is disconnected from the

wiper terminal. It is possible to execute any command from

Table 7 while the AD5175 is in shutdown mode. The part can

be taken out of shutdown mode by executing Command 9 and

setting the LSB to 0, or by issuing a software or hardware reset.

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance between Terminal W and Terminal A,

R_WA, is available in 10 kΩ and has 1024-tap points accessed by

the wiper terminal. The 10-bit data in the RDAC latch is decoded

to select one of the 1024 possible wiper settings. As a result, the

general equation for determining the digitally programmed

output resistance between the W terminal and A terminal is

D

R_WA(D) =

× R_WA

(1)

1024

where:

D is the decimal equivalent of the binary code loaded in the

10-bit RDAC register.

R

_WAis the end-to-end resistance.

In the zero-scale condition, a finite total wiper resistance of

120 Ω is present. Regardless of which setting the part is oper-

ating in, take care to limit the current between the A terminal

to W terminal, and W terminal to B terminal, to the maximum

continuous current of ±± mA, or the pulse current specified in

Table 3. Otherwise, degradation or possible destruction of the

internal switch contact can occur.

Rev. 0 | Page 18 of 20

AD5175

Calculate the Actual End-to-End Resistance

TERMINAL VOLTAGE OPERATING RANGE

The resistance tolerance is stored in the internal memory

during factory testing. The actual end-to-end resistance

can, therefore, be calculated (which is valuable for calibration,

tolerance matching, and precision applications).

The positive V_DDand negative V_SSpower supplies of the AD5175

define the boundary conditions for proper 2-terminal digital

resistor operation. Supply signals present on Terminal A and

Terminal W that exceed V_DDor V_SSare clamped by the internal

forward-biased diodes (see Figure 30).

The resistance tolerance in percentage is stored in fixed-point

format, using a 16-bit sign magnitude binary. The sign bit(0 =

negative and 1 = positive) and the integer part is located in

Address 0x39, as shown in Table 11. Address 0x3A contains

the fractional part, as shown in Table 12.

V

DD

A

That is, if the data readback from Address 0x39 is 0000001010

and data from Address 0x3A is 0010110000, then the end-to-end

resistance can be calculated as follows.

W

For Memory Location 0x39,

DB[9:8]: XX = don’t care

V

SS

Figure 30. Maximum Terminal Voltages Set by V_DDand V_SS

DB[7]: 0 = negative

DB[6:0]: 0001010 = 10

The ground pin of the AD5175 is primarily used as a digital

ground reference. To minimize the digital ground bounce, join

the AD5175 ground terminal remotely to the common ground.

The digital input control signals to the AD5175 must be refe-

renced to the device ground pin (GND) and satisfy the logic

level defined in the Specifications section. An internal level

shift circuit ensures that the common-mode voltage range of

the three terminals extends from V_SSto V_DD, regardless of the

digital input level.

For Memory Location 0x3A,

DB[9:8]: XX = don’t care

DB[7:0]: 10110000 = 176 × 2⁻⁸= 0.6875

Therefore, tolerance = −10.6875% and R_WA(1023)= 8.931 kΩ.

EXT_CAP CAPACITOR

A 1 μF capacitor to V_SSmust be connected to the EXT_CAP pin

(see Figure 29) on power-up and throughout the operation of

the AD5175.

POWER-UP SEQUENCE

Because there are diodes to limit the voltage compliance at

Terminal A and Terminal W (see Figure 30), it is important to

power V_DD/V_SSfirst before applying any voltage to Terminal A

and Terminal W; otherwise, the diode is forward-biased such

that V_DD/V_SSare powered unintentionally. The ideal power-up

sequence is V_SS, GND, V_DD, digital inputs, V_A, and V_W. The

order of powering V_A, V_W, and digital inputs is not important

as long as they are powered after V_DD/V_SS.

AD5175

50-TP

MEMORY

BLOCK

C1

EXT_CAP

1µF

V

SS

V

SS

Figure 29. EXT_CAP Hardware Setup

As soon as V_DDis powered, the power-on preset activates,

which first sets the RDAC to midscale and then restores the

last programmed 50-TP value to the RDAC register.

Table 12. End-to-End Resistance Tolerance Bytes

Data Byte¹

Memory Map Address

DB9

X

DB8

X

DB7

Sign

2⁻¹

DB6

2⁶

2⁻²

DB5

2⁵

2⁻³

DB4

2⁴

2⁻⁴

DB3

2³

2⁻⁵

DB2

2²

2⁻⁶

DB1

2¹

2⁻⁷

DB0

2⁰

2⁻⁸

0x39

0x3A

¹X is don’t care.

Rev. 0 | Page 19 of 20

AD5175

OUTLINE DIMENSIONS

2.48

2.38

2.23

3.10

3.00 SQ

2.90

0.50 BSC

6

10

PIN 1 INDEX

EXPOSED

PAD

1.74

1.64

1.49

AREA

0.50

0.40

0.30

5

1

PIN 1

INDICATOR

TOP VIEW

BOTTOM VIEW

(R 0.15)

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.30

0.25

0.20

0.20 REF

Figure 31. 10-Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

3.10

3.00

2.90

10

1

6

5

5.15

4.90

4.65

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.50 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.70

0.55

0.40

0.15

0.05

0.23

0.13

6°

0°

0.30

0.15

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 32. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

AD5175BRMZ-10

AD5175BRMZ-10-RL7

AD5175BCPZ-10-R2

AD5175BCPZ-10-RL7

R_AB(kΩ)

Resolution

1,024

Temperature Range

−40°C to +125°C

Package Description

10-Lead MSOP

10-Lead LFCSP_WD

Package Option

RM-10

CP-10-9

Branding

DDR

DEG

10

¹Z = RoHS Compliant Part.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D08719-0-3/10(0)

Rev. 0 | Page 20 of 20


型号：	AD5175BCPZ-10-R2
厂家：	ADI
描述：	Single-Channel, 1024-Position, Digital Rheostat with I2C Interface and 50-TP Memory 单通道， 1024位，数字电位器，带有I2C接口和50 -TP存储器转换器电位器数字电位计存储电阻器光电二极管
文件：	总20页 (文件大小：1027K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5175BCPZ-10-R2 [ADI]

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