AD5123BCPZ100-RL7 [ADI]
Quad Channel, 128-/256-Position, I2C Nonvolatile Digital Potentiometer; 四通道， 128 / 256位， I2C ，非易失数字电位器
| 型号： | AD5123BCPZ100-RL7 |
| 厂家： | 
ADI |
| 描述： | Quad Channel, 128-/256-Position, I2C Nonvolatile Digital Potentiometer |
| 文件： | 总28页 (文件大小：642K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad Channel, 128-/256-Position, I2C,
Nonvolatile Digital Potentiometer
Data Sheet
AD5123/AD5143
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
DD
10 kΩ and 100 kΩ resistance options
Resistor tolerance: 8% maximum
Wiper current: 6 mA
Low temperature coefficient: 35 ppm/°C
Wide bandwidth: 3 MHz
AD5123/AD5143
POWER-ON
RESET
RDAC1
A1
INPUT
REGISTER 1
W1
B1
Fast start-up time < 75 μs
RDAC2
A2
Linear gain setting mode
INPUT
W2
B2
REGISTER 2
SCL
SDA
Single- and dual-supply operation
Wide operating temperature: −40°C to +125°C
3 mm × 3 mm package
SERIAL
INTERFACE
RDAC3
7/8
INPUT
REGISTER 3
W3
B3
ADDR
4 kV ESD protection
RDAC4
APPLICATIONS
INPUT
REGISTER 4
W4
B4
Portable electronics level adjustment
LCD panel brightness and contrast controls
Programmable filters, delays, and time constants
Programmable power supplies
EEPROM
MEMORY
GND
V
SS
Figure 1.
GENERAL DESCRIPTION
Table 1. Family Models
The AD5123/AD5143 potentiometers provide a nonvolatile
solution for 128-/256-position adjustment applications, offering
guaranteed low resistor tolerance errors of 8% and up to 6 mA
current density in the Ax, Bx, and Wx pins.
Model
Channel Position Interface Package
AD51231
AD5124
AD5124
AD5143
AD5144
AD5144
Quad
Quad
Quad
Quad
Quad
Quad
128
128
128
256
256
256
256
128
128
256
256
128
256
I2C
LFCSP
LFCSP
TSSOP
LFCSP
LFCSP
TSSOP
SPI/I2C
SPI
I2C
SPI/I2C
SPI
I2C
The low resistor tolerance and low nominal temperature coefficient
simplify open-loop applications as well as applications requiring
tolerance matching.
AD5144A Quad
AD5122 Dual
AD5122A Dual
AD5142 Dual
AD5142A Dual
TSSOP
The linear gain setting mode allows independent programming
of the resistance between the digital potentiometer terminals,
through the RAW and RWB string resistors, allowing very accurate
resistor matching.
SPI
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP
I2C
SPI
I2C
SPI/I2C
SPI/I2C
The high bandwidth and low total harmonic distortion (THD)
ensure optimal performance for ac signals, making the devices
suitable for filter design.
AD5121
AD5141
Single
Single
LFCSP
1 Two potentiometers and two rheostats.
The low wiper resistance of only 40 Ω at the ends of the resistor
array allows for pin-to-pin connection.
The wiper values can be set through an I2C-compatible digital
interface that is also used to read back the wiper register and
EEPROM contents.
The AD5123/AD5143 are available in a compact, 16-lead, 3 mm ×
3 mm LFCSP. The parts are guaranteed to operate over the extended
industrial temperature range of −40°C to +125°C.
Rev. A
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AD5123/AD5143
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 19
RDAC Register and EEPROM.................................................. 19
Input Shift Register .................................................................... 19
I2C Serial Data Interface............................................................ 19
I2C Address.................................................................................. 19
Advanced Control Modes ......................................................... 21
EEPROM or RDAC Register Protection................................. 22
RDAC Architecture.................................................................... 25
Programming the Variable Resistor......................................... 25
Programming the Potentiometer Divider............................... 26
Terminal Voltage Operating Range ......................................... 26
Power-Up Sequence ................................................................... 26
Layout and Power Supply Biasing............................................ 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—AD5123 .......................................... 3
Electrical Characteristics—AD5143 .......................................... 6
Interface Timing Specifications.................................................. 9
Shift Register and Timing Diagrams ....................................... 10
Absolute Maximum Ratings.......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 13
Test Circuits..................................................................................... 18
REVISION HISTORY
3/13—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
10/12—Revision 0: Initial Version
Rev. A | Page 2 of 28
Data Sheet
AD5123/AD5143
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5123
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution
Resistor Integral Nonlinearity2
N
R-INL
7
Bits
RAB = 10 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
RAB = 100 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
−1
−2.5
0.1
1
+1
+2.5
LSB
LSB
−0.5
−1
0.1
0.25 +1
+0.5
LSB
LSB
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance3
R-DNL
−0.5
−8
0.1
1
35
+0.5
+8
LSB
%
ppm/°C
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
Code = full scale
Code = zero scale
RAB = 10 kΩ
55
130
125
400
Ω
Ω
RAB = 100 kΩ
Bottom Scale or Top Scale
Nominal Resistance Match
RBS or RTS
RAB = 10 kΩ
RAB = 100 kΩ
Code = 0xFF
40
60
0.2
80
230
+1
Ω
Ω
%
RAB1/RAB2
−1
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4
INL
RAB = 10 kΩ
RAB = 100 kΩ
−0.5
−0.25
−0.25
0.1
0.1
0.1
+0.5
+0.25
+0.25
LSB
LSB
LSB
Differential Nonlinearity4
Full-Scale Error
DNL
VWFSE
RAB = 10 kΩ
RAB = 100 kΩ
−1.5
−0.5
−0.1
0.1
LSB
LSB
+0.5
Zero-Scale Error
VWZSE
RAB = 10 kΩ
RAB = 100 kΩ
(ΔVW/VW)/ΔT × 106 Code = half scale
1
0.25
5
1.5
0.5
LSB
LSB
ppm/°C
Voltage Divider Temperature
Coefficient3
Rev. A | Page 3 of 28
AD5123/AD5143
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1
Max
Unit
RESISTOR TERMINALS
Maximum Continuous Current
IA, IB, and IW
RAB = 10 kΩ
RAB = 100 kΩ
−6
−1.5
VSS
+6
+1.5
VDD
mA
mA
V
Terminal Voltage Range5
Capacitance A, Capacitance B3
CA, CB
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
25
12
pF
pF
Capacitance W3
CW
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
VA = VW = VB
12
5
15
pF
pF
nA
Common-Mode Leakage Current3
DIGITAL INPUTS
Input Logic3
−500
+500
High
Low
VINH
VINL
VHYST
IIN
0.7 × VDD
0.1 × VDD
V
V
V
µA
pF
0.2 × VDD
1
Input Hysteresis3
Input Current3
Input Capacitance3
DIGITAL OUTPUTS
Output High Voltage3
Output Low Voltage3
CIN
5
VOH
VOL
RPULL-UP = 2.2 kΩ to VDD
ISINK = 3 mA
ISINK = 6 mA
VDD
V
V
V
µA
pF
0.4
0.6
+1
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
−1
2
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
VSS = GND
2.3
2.25
5.5
2.75
V
V
IDD
VIH = VDD or VIL = GND
VDD = 5.5 V
VDD = 2.3 V
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
∆VDD/∆VSS = VDD 10%,
code = full scale
0.7
400
−0.7
2
320
3.5
−66
5.5
µA
nA
µA
mA
µA
µW
dB
Negative Supply Current
EEPROM Store Current3, 6
EEPROM Read Current3, 7
Power Dissipation8
ISS
−5.5
IDD_EEPROM_STORE
IDD_EEPROM_READ
PDISS
Power Supply Rejection Ratio
PSRR
−60
Rev. A | Page 4 of 28
Data Sheet
AD5123/AD5143
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1
Max
Unit
DYNAMIC CHARACTERISTICS9
Bandwidth
BW
−3 dB
RAB = 10 kΩ
RAB = 100 kΩ
3
0.43
MHz
MHz
Total Harmonic Distortion
Resistor Noise Density
VW Settling Time
THD
eN_WB
tS
VDD/VSS = 2.5 V, VA = 1 V rms,
VB = 0 V, f = 1 kHz
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C,
f = 10 kHz
RAB = 10 kΩ
RAB = 100 kΩ
VA = 5 V, VB = 0 V, from
zero scale to full scale,
0.5 LSB error band
−80
−90
dB
dB
7
20
nV/√Hz
nV/√Hz
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
2
µs
µs
12
10
25
−90
1
Crosstalk (CW1/CW2)
CT
nV-sec
nV-sec
dB
Mcycles
kcycles
Years
Analog Crosstalk
Endurance10
CTA
TA = 25°C
100
Data Retention11
50
1 Typical values represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB
.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8 PDISS is calculated from (IDD × VDD).
9 All dynamic characteristics use VDD/VSS
= 2.5 V.
10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
Rev. A | Page 5 of 28
AD5123/AD5143
Data Sheet
ELECTRICAL CHARACTERISTICS—AD5143
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1 Max
Unit
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution
N
R-INL
8
Bits
Resistor Integral Nonlinearity2
RAB = 10 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
RAB = 100 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
−2
−5
0.2
1.5
+2
+5
LSB
LSB
−1
−2
−0.5
−8
0.1
0.5
0.2
1
+1
+2
+0.5
+8
LSB
LSB
LSB
%
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance3
R-DNL
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
Code = full scale
Code = zero scale
RAB = 10 kΩ
35
ppm/°C
55
130
125
400
Ω
Ω
RAB = 100 kΩ
Bottom Scale or Top Scale
Nominal Resistance Match
RBS or RTS
RAB = 10 kΩ
RAB = 100 kΩ
Code = 0xFF
40
60
0.2
80
230
+1
Ω
Ω
%
RAB1/RAB2
−1
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4
INL
RAB = 10 kΩ
RAB = 100 kΩ
−1
−0.5
−0.5
0.2
0.1
0.2
+1
+0.5
+0.5
LSB
LSB
LSB
Differential Nonlinearity4
Full-Scale Error
DNL
VWFSE
RAB = 10 kΩ
RAB = 100 kΩ
−2.5
−1
−0.1
0.2
LSB
LSB
+1
Zero-Scale Error
VWZSE
RAB = 10 kΩ
RAB = 100 kΩ
(ΔVW/VW)/ΔT × 106 Code = half scale
1.2
0.5
5
3
1
LSB
LSB
ppm/°C
Voltage Divider Temperature
Coefficient3
Rev. A | Page 6 of 28
Data Sheet
AD5123/AD5143
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1 Max
Unit
RESISTOR TERMINALS
Maximum Continuous Current
IA, IB, and IW
RAB = 10 kΩ
RAB = 100 kΩ
−6
−1.5
VSS
+6
+1.5
VDD
mA
mA
V
Terminal Voltage Range5
Capacitance A, Capacitance B3
CA, CB
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
25
12
pF
pF
Capacitance W3
CW
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
VA = VW = VB
12
5
15
pF
pF
nA
Common-Mode Leakage Current3
DIGITAL INPUTS
Input Logic3
−500
+500
High
Low
VINH
VINL
VHYST
IIN
0.7 × VDD
0.1 × VDD
V
V
V
µA
pF
0.2 × VDD
1
Input Hysteresis3
Input Current3
Input Capacitance3
DIGITAL OUTPUTS
Output High Voltage3
Output Low Voltage3
CIN
5
VOH
VOL
RPULL-UP = 2.2 kΩ to VDD
ISINK = 3 mA
ISINK = 6 mA
VDD
V
V
V
µA
pF
0.4
0.6
+1
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
−1
2
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
VSS = GND
2.3
2.25
5.5
2.75
V
V
IDD
VIH = VDD or VIL = GND
VDD = 5.5 V
VDD = 2.3 V
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
∆VDD/∆VSS = VDD 10%,
code = full scale
0.7
400
−0.7
2
320
3.5
−66
5.5
µA
nA
µA
mA
µA
µW
dB
Negative Supply Current
EEPROM Store Current3, 6
EEPROM Read Current3, 7
Power Dissipation8
ISS
−5.5
IDD_EEPROM_STORE
IDD_EEPROM_READ
PDISS
Power Supply Rejection Ratio
PSRR
−60
Rev. A | Page 7 of 28
AD5123/AD5143
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1 Max
Unit
DYNAMIC CHARACTERISTICS9
Bandwidth
BW
−3 dB
RAB = 10 kΩ
RAB = 100 kΩ
3
0.43
MHz
MHz
Total Harmonic Distortion
Resistor Noise Density
VW Settling Time
THD
eN_WB
tS
VDD/VSS = 2.5 V, VA = 1 V rms,
VB = 0 V, f = 1 kHz
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C,
f = 10 kHz
RAB = 10 kΩ
RAB = 100 kΩ
VA = 5 V, VB = 0 V, from
zero scale to full scale,
0.5 LSB error band
−80
−90
dB
dB
7
20
nV/√Hz
nV/√Hz
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
2
µs
µs
12
10
25
−90
1
Crosstalk (CW1/CW2)
CT
nV-sec
nV-sec
dB
Mcycles
kcycles
Years
Analog Crosstalk
Endurance10
CTA
TA = 25°C
100
Data Retention11
50
1 Typical values represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB
.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8 PDISS is calculated from (IDD × VDD).
9 All dynamic characteristics use VDD/VSS
= 2.5 V.
10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
Rev. A | Page 8 of 28
Data Sheet
AD5123/AD5143
INTERFACE TIMING SPECIFICATIONS
VDD = 2.3 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. I2C Interface
Parameter1
Test Conditions/Comments Min
Typ Max Unit Description
2
fSCL
Standard mode
Fast mode
100
400
kHz
kHz
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Serial clock frequency
SCL high time, tHIGH
SCL low time, tLOW
t1
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
4.0
0.6
4.7
1.3
250
100
0
t2
t3
Data setup time, tSU; DAT
Data hold time, tHD; DAT
t4
3.45
0.9
0
t5
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
4.7
0.6
4
0.6
4.7
1.3
4
Setup time for a repeated start condition, tSU; STA
Hold time (repeated) for a start condition, tHD; STA
Bus free time between a stop and a start condition, tBUF
Setup time for a stop condition, tSU; STO
Rise time of SDA signal, tRDA
t6
t7
t8
0.6
t9
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
1000 ns
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
300
300
300
ns
ns
ns
t10
t11
t11A
Fall time of SDA signal, tFDA
1000 ns
300 ns
1000 ns
Rise time of SCL signal, tRCL
Standard mode
Rise time of SCL signal after a repeated start condition
and after an acknowledge bit, tRCL1 (not shown in Figure 3)
Fast mode
Standard mode
Fast mode
20 + 0.1 CL
300
300
300
50
ns
ns
ns
ns
ms
µs
µs
µs
t12
Fall time of SCL signal, tFCL
20 + 0.1 CL
0
3
tSP
Fast mode
Pulse width of suppressed spike (not shown in Figure 3)
Memory program time (not shown in Figure 3)
Memory readback time (not shown in Figure 3)
Power-on EEPROM restore time (not shown in Figure 3)
Reset EEPROM restore time (not shown in Figure 3)
4
tEEPROM_PROGRAM
15
7
50
tEEPROM_READBACK
30
5
tPOWER_UP
tRESET
75
30
1 Maximum bus capacitance is limited to 400 pF.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the part.
3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
4 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
5 Maximum time after VDD − VSS is equal to 2.3 V.
Rev. A | Page 9 of 28
AD5123/AD5143
Data Sheet
SHIFT REGISTER AND TIMING DIAGRAMS
DB15 (MSB)
DB8
A0
DB7
D7
DB0 (LSB)
D0
D1
A1
D6
D5
D4
D3
C3
C2
C1
C0
A3
A2
D2
DATA BITS
CONTROL BITS
ADDRESS BITS
Figure 2. Input Shift Register Contents
t11
t12
t6
t8
t2
SCL
SDA
t5
t1
t6
t10
t9
t4
t3
t7
P
S
S
P
Figure 3. I2C Serial Interface Timing Diagram (Typical Write Sequence)
Rev. A | Page 10 of 28
Data Sheet
AD5123/AD5143
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter
VDD to GND
VSS to GND
Rating
−0.3 V to +7.0 V
+0.3 V to −7.0 V
7 V
VDD to VSS
VA, VW, VB to GND
VSS − 0.3 V, VDD + 0.3 V or
+7.0 V (whichever is less)
THERMAL RESISTANCE
IA, IW, IB
θJA is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
Pulsed1
Frequency > 10 kHz
Table 6. Thermal Resistance
RAW = 10 kΩ
RAW = 100 kΩ
6 mA/d2
1.5 mA/d2
Package Type
θJA
89.51
θJC
Unit
16-Lead LFCSP
3
°C/W
Frequency ≤ 10 kHz
RAW = 10 kΩ
6 mA/√d2
1.5 mA/√d2
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
RAW = 100 kΩ
Digital Inputs
−0.3 V to VDD + 0.3 V or
+7 V (whichever is less)
−40°C to +125°C
150°C
ESD CAUTION
3
Operating Temperature Range, TA
Maximum Junction Temperature,
TJ Maximum
Storage Temperature Range
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Package Power Dissipation
ESD4
−65°C to +150°C
260°C
20 sec to 40 sec
(TJ max − TA)/θJA
4 kV
FICDM
1.5 kV
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 d = pulse duty factor.
3 Includes programming of EEPROM memory.
4 Human body model (HBM) classification.
Rev. A | Page 11 of 28
AD5123/AD5143
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
12 V
DD
A1
W1
B1
1
2
3
4
AD5123/
AD5143
11 B4
10 W4
TOP VIEW
W3
9 B2
(Not to Scale)
NOTES
1. INTERNALLY CONNECT THE
EXPOSED PAD TO V
.
SS
Figure 4. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
Terminal A of RDAC1. VSS ≤ VA ≤ VDD.
1
A1
2
3
4
5
W1
B1
W3
B3
Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.
Terminal B of RDAC1. VSS ≤ VB ≤ VDD.
Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD.
Terminal B of RDAC3. VSS ≤ VB ≤ VDD.
6
7
VSS
A2
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Terminal A of RDAC2. VSS ≤ VA ≤ VDD.
8
9
W2
B2
Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.
Terminal B of RDAC2. VSS ≤ VB ≤ VDD.
10
11
12
13
14
15
16
W4
B4
Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD.
Terminal B of RDAC4. VSS ≤ VB ≤ VDD.
VDD
SCL
SDA
ADDR
GND
EPAD
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Serial Clock Line. Data is clocked in at the logic low transition.
Serial Data Input/Output.
Programmable Address for Multiple Package Decoding.
Ground Pin, Logic Ground Reference.
Internally Connect the Exposed Paddle to VSS.
Rev. A | Page 12 of 28
Data Sheet
AD5123/AD5143
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.2
0.1
10kΩ, +125°C
10kΩ, +25°C
0.4
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
0.3
0
100kΩ, –40°C
0.2
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
0
100
200
0
100
200
CODE (Decimal)
CODE (Decimal)
Figure 5. R-INL vs. Code (AD5143)
Figure 8. R-DNL vs. Code (AD5143)
0.20
0.10
0.05
0.15
0.10
0
0.05
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
0
–0.05
–0.10
–0.15
–0.20
–0.25
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
0
50
100
0
50
100
CODE (Decimal)
CODE (Decimal)
Figure 6. R-INL vs. Code (AD5123)
Figure 9. R-DNL vs. Code (AD5123)
0.10
0.05
0.3
0.2
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
0
0.1
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
0
–0.1
–0.2
–0.3
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
0
100
200
0
100
200
CODE (Decimal)
CODE (Decimal)
Figure 10. DNL vs. Code (AD5143)
Figure 7. INL vs. Code (AD5143)
Rev. A | Page 13 of 28
AD5123/AD5143
Data Sheet
0.15
0.10
0.05
0
0.06
0.04
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
–0.05
–0.10
–0.15
0
50
100
0
50
100
CODE (Decimal)
CODE (Decimal)
Figure 11. INL vs. Code (AD5123)
Figure 14. DNL vs. Code (AD5123)
450
400
350
300
250
200
150
100
50
450
100kΩ
10kΩ
10kΩ
100kΩ
400
350
300
250
200
150
100
50
0
0
–50
–50
0
0
50
25
100
50
150
75
200
100
255
127
AD5143
AD5123
0
0
50
25
100
50
150
75
200
100
255 AD5142A
AD5122A
127
CODE (Decimal)
CODE (Decimal)
Figure 12. Potentiometer Mode Temperature Coefficient ((ΔVW/VW)/ΔT × 106) vs.
Code
Figure 15. Rheostat Mode Temperature Coefficient ((ΔRWB/RWB)/ΔT × 106)
vs. Code
800
1200
I
I
I
, V = 2.3V
V
= GND
V
V
V
V
= 2.3V
= 3.3V
= 5V
DD DD
SS
DD
DD
DD
DD
, V = 3.3V
DD DD
700
600
500
400
300
200
100
0
, V = 5V
DD DD
= 5.5V
1000
800
600
400
200
0
–40
10
60
110 125
0
1
2
3
4
5
TEMPERATURE (°C
)
INPUT VOLTAGE (V)
Figure 13. Supply Current vs. Temperature
Figure 16. IDD Current vs. Digital Input Voltage
Rev. A | Page 14 of 28
Data Sheet
AD5123/AD5143
10
0
0
0x80 (0x40)
0x80 (0x40)
0x40 (0x20)
0x20 (0x10)
0x10 (0x08)
0x8 (0x04)
0x40 (0x20)
–10
–10
–20
–30
–40
–50
–60
–70
–80
–90
0x20 (0x10)
–20
0x10 (0x08)
0x4 (0x02)
0x2 (0x01)
0x1 (0x00)
0x8 (0x04)
–30
0x4 (0x02)
0x2 (0x01)
0x00
0x1 (0x00)
–40
0x00
–50
AD5143 (AD5123)
AD5143 (AD5123)
–60
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. 10 kΩ Gain vs. Frequency and Code
Figure 20. 100 kΩ Gain vs. Frequency and Code
–40
0
10kΩ
100kΩ
10kΩ
100kΩ
V
/V = ±2.5V
= 1V rms
= GND
DD SS
V
V
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
B
–50
–60
CODE = HALF SCALE
NOISE FILTER = 22kHz
–70
–80
V
f
/V = ±2.5V
DD SS
–90
= 1kHz
CODE = HALF SCALE
NOISE FILTER = 22kHz
IN
–100
20
200
2k
FREQUENCY (Hz)
20k
200k
0.001 0.01
0.1
1
VOLTAGE (V rms)
Figure 18. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency
Figure 21. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude
20
10
0
V
R
/V = ±2.5V
DD SS
= 10kΩ
AB
0
–20
–10
–20
–30
–40
–50
–60
–70
–40
–60
–80
QUARTER SCALE
–80
QUARTER SCALE
MIDSCALE
V
R
/V = ±2.5V
MIDSCALE
DD SS
FULL-SCALE
= 100kΩ
FULL-SCALE
AB
–100
–90
10
10
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19. Normalized Phase Flatness vs. Frequency, RAB = 10 kΩ
Figure 22. Normalized Phase Flatness vs. Frequency, RAB = 100 kΩ
Rev. A | Page 15 of 28
AD5123/AD5143
Data Sheet
0.0025
0.0020
0.0015
0.0010
0.0005
0
1.2
1.0
0.8
0.6
0.4
0.2
0
600
500
400
300
200
100
0
100kΩ, V
100kΩ, V
100kΩ, V
100kΩ, V
100kΩ, V
100kΩ, V
= 2.3V
= 2.7V
= 3V
DD
DD
DD
DD
DD
DD
= 3.6V
= 5V
= 5.5V
10kΩ, V
10kΩ, V
10kΩ, V
10kΩ, V
10kΩ, V
10kΩ, V
= 2.3V
= 2.7V
= 3V
DD
DD
DD
DD
DD
DD
= 3.6V
= 5V
= 5.5V
–600 –500 –400 –300 –200 –100
0
100 200 300 400 500 600
0
1
2
3
4
5
RESISTOR DRIFT (ppm)
VOLTAGE (V)
Figure 23. Incremental Wiper On Resistance vs. Positive Power Supply (VDD
)
Figure 26. Resistor Lifetime Drift
10
0
10kΩ, RDAC1
100kΩ, RDAC1
10kΩ + 0pF
V
V
= 5V ±10% AC
DD
SS
10kΩ + 75pF
= GND, V = 4V, V = GND
A B
9
–10
–20
–30
–40
–50
–60
–70
–80
–90
10kΩ + 150pF
10kΩ + 250pF
100kΩ + 0pF
100kΩ + 75pF
100kΩ + 150pF
100kΩ + 250pF
CODE = MIDSCALE
8
7
6
5
4
3
2
1
0
10
100
1k
10k
100k
1M
10M
0
0
20
10
40
20
60
30
80
40
100
50
120
60 AD5123
AD5143
FREQUENCY (Hz)
CODE (Decimal)
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 24. Maximum Bandwidth vs. Code and Net Capacitance
0.020
0.8
0x80 TO 0x7F 100kΩ
0x80 TO 0x7F 10kΩ
0.7
0.015
0.010
0.005
0
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.005
–0.010
–0.015
–0.020
–0.1
0
500
1000
1500
2000
0
5
10
15
TIME (ns)
TIME (µs)
Figure 25. Maximum Transition Glitch
Figure 28. Digital Feedthrough
Rev. A | Page 16 of 28
Data Sheet
AD5123/AD5143
0
7
6
5
4
3
2
1
0
10kΩ
SHUTDOWN MODE ENABLED
100kΩ
–20
–40
–60
–80
10kΩ
–100
–120
100kΩ
10
100
1k
10k
100k
1M
10M
AD5143
AD5123
0
0
50
25
100
50
150
75
200
100
250
125
FREQUENCY (Hz)
CODE (Decimal)
Figure 29. Shutdown Isolation vs. Frequency
Figure 30. Theoretical Maximum Current vs. Code
Rev. A | Page 17 of 28
AD5123/AD5143
Data Sheet
TEST CIRCUITS
Figure 31 to Figure 35 define the test conditions used in the Specifications section.
NC
DUT
A
V
I
A
W
V+ = V ±10%
DD
W
V
Δ
MS
V
A
B
PSRR (dB) = 20 LOG
DD
)
(
ΔV
B
W
DD
V+
~
V
ΔV
%
MS
MS
PSS (%/%) =
V
MS
ΔV
%
DD
NC = NO CONNECT
Figure 34. Power Supply Sensitivity and
Power Supply Rejection Ratio (PSS, PSRR)
Figure 31. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
0.1V
R
=
SW
I
DUT
B
SW
CODE = 0x00
W
+
–
DUT
V+ = V
DD
1LSB = V+/2
0.1V
I
SW
N
A
W
V+
V
TO V
DD
SS
B
A = NC
V
MS
Figure 32. Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 35. Incremental On Resistance
DUT
A
W
I
= V /R
DD NOMINAL
W
V
W
B
V
R
= V /I
MS1 W
MS1
W
NC = NO CONNECT
Figure 33. Wiper Resistance
Rev. A | Page 18 of 28
Data Sheet
AD5123/AD5143
THEORY OF OPERATION
I2C SERIAL DATA INTERFACE
The AD5123/AD5143 digital programmable potentiometers are
designed to operate as true variable resistors for analog signals
within the terminal voltage range of VSS < VTERM < VDD. The resistor
wiper position is determined by the RDAC register contents. The
RDAC register acts as a scratchpad register that allows unlimited
changes of resistance settings. A secondary register (the input
register) can be used to preload the RDAC register data.
The AD5123/AD5143 has 2-wire, I2C-compatible serial interfaces.
These devices can be connected to an I2C bus as a slave device,
under the control of a master device. See Figure 3 for a timing
diagram of a typical write sequence.
The AD5123/AD5143 supports standard (100 kHz) and fast
(400 kHz) data transfer modes. Support is not provided for
10-bit addressing and general call addressing.
The RDAC register can be programmed with any position setting
using the I2C interface (depending on the model). When a desirable
wiper position is found, this value can be stored in the EEPROM
memory. Thereafter, the wiper position is always restored to
that position for subsequent power-ups. The storing of EEPROM
data takes approximately 15 ms; during this time, the device is
locked and does not acknowledge any new command, preventing
any changes from taking place.
The 2-wire serial bus protocol operates as follows:
1. The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address
W
and an R/ bit. The slave device corresponding to the
transmitted address responds by pulling SDA low during
the ninth clock pulse (this is called the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its shift register.
RDAC REGISTER AND EEPROM
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with 0x80 (AD5143, 256 taps), the wiper is connected to
half scale of the variable resistor. The RDAC register is a standard
logic register; there is no restriction on the number of changes
allowed.
W
If the R/ bit is set high, the master reads from the slave
W
device. However, if the R/ bit is set low, the master writes
to the slave device.
It is possible to both write to and read from the RDAC register
using the digital interface (see Table 9).
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
3. When all data bits have been read from or written to, a stop
condition is established. In write mode, the master pulls the
SDA line high during the tenth clock pulse to establish a stop
condition. In read mode, the master issues a no acknowledge
for the ninth clock pulse (that is, the SDA line remains high).
The master then brings the SDA line low before the tenth
clock pulse, and then high again during the tenth clock pulse
to establish a stop condition.
The contents of the RDAC register can be stored to the EEPROM
using Command 9 (see Table 9). Thereafter, the RDAC register
always sets at that position for any future on-off-on power supply
sequence. It is possible to read back data saved into the EEPROM
with Command 3 (see Table 9).
Alternatively, the EEPROM can be written to independently
using Command 11 (see Table 15).
INPUT SHIFT REGISTER
For the AD5123/AD5143, the input shift register is 16 bits wide,
as shown in Figure 2. The 16-bit word consists of four control
bits, followed by four address bits and by eight data bits.
I2C ADDRESS
The facility to make hardwired changes to ADDR allows the
user to incorporate up to three of these devices on one bus as
outlined in Table 8.
If the AD5143 RDAC or EEPROM registers are read from or
written to, the lowest data bit (Bit 0) is ignored.
Data is loaded MSB first (Bit 15). The four control bits determine
the function of the software command, as listed in Table 9 and
Table 15.
Table 8. I2C Address Selection
ADDR Pin
7-Bit I2C Device Address
0101000
VDD
No connect1
GND
0101010
0101011
1 Not available in bipolar mode ( VSS < 0 V).
Rev. A | Page 19 of 28
AD5123/AD5143
Data Sheet
Table 9. Reduced Commands Operation Truth Table
Control
Bits[DB15:DB12]
Address
Bits[DB11:DB8]1
Data Bits[DB7:DB0]1
Command
Number
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
1
0
0
0
0
0
0
0
1
X
0
X
0
X
X
X
X
X
X
X
X
X
X
NOP: do nothing
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register
data to RDAC
2
3
0
0
0
0
1
1
0
1
0
0
0
0
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register
data to input register
A1 A0
X
X
X
X
X
X
D1 D0 Read back contents
D1
0
1
D0
1
1
Data
EEPROM
RDAC
9
0
0
1
1
1
1
0
1
1
1
1
0
1
1
1
0
0
0
0
X
0
A1 A0
A1 A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
X
Copy RDAC register to EEPROM
Copy EEPROM into RDAC
Software reset
10
14
15
0
X
X
X
A3
A1 A0
D0 Software shutdown
D0
0
1
Condition
Normal mode
Shutdown mode
1 X = don’t care.
Table 10. Reduced Address Bits Table
A3
A2
X1
0
A1
X1
0
A0
X1
0
Channel
Stored Channel Memory
Not applicable
RDAC1
1
0
All channels
RDAC1
0
0
0
1
RDAC2
RDAC2
0
0
1
0
RDAC3
RDAC3
0
0
1
1
RDAC4
RDAC4
1 X = don’t care.
Rev. A | Page 20 of 28
Data Sheet
AD5123/AD5143
Low Wiper Resistance Feature
ADVANCED CONTROL MODES
The AD5123/AD5143 include two commands to reduce the wiper
resistance between the terminals when the devices achieve full scale
or zero scale. These extra positions are called bottom scale, BS, and
top scale, TS. The resistance between Terminal A and Terminal W
at top scale is specified as RTS. Similarly, the bottom scale resistance
between Terminal B and Terminal W is specified as RBS.
The AD5123/AD5143 digital potentiometers include a set of user
programming features to address the wide number of applications
for these universal adjustment devices (see Table 15 and Table 17).
Key programming features include the following:
•
•
•
•
•
•
•
•
Input register
Linear gain setting mode
Low wiper resistance feature
Linear increment and decrement instructions
6 dB increment and decrement instructions
Burst mode (I2C only)
The contents of the RDAC registers are unchanged by entering
in these positions. There are three ways to exit from top scale
and bottom scale: by using Command 12 or Command 13
(see Table 15); by loading new data in an RDAC register, which
includes increment/decrement operations; or by entering
shutdown mode, Command 15 (see Table 15).
Reset
Shutdown mode
Table 11 and Table 12 show the truth tables for the top scale
position and the bottom scale position, respectively, when the
potentiometer or linear gain setting mode is enabled.
Input Register
The AD5123/AD5143 include one input register per RDAC
register. These registers allow preloading of the value for the
associated RDAC register. These registers can be written to using
Command 2 and read back using Command 3 (see Table 15).
Table 11. Top Scale Truth Table
Linear Gain Setting Mode
Potentiometer Mode
RAW
RAB
RWB
RAW
RWB
This feature allows a synchronous and asynchronous update of
one or all of the RDAC registers at the same time.
RAB
RTS
RAB
Table 12. Bottom Scale Truth Table
The transfer from the input register to the RDAC register is
done synchronously by Command 8 (see Table 15).
Linear Gain Setting Mode
Potentiometer Mode
RAW
RWB
RAW
RWB
If new data is loaded in an RDAC register, this RDAC register
automatically overwrites the associated input register.
RTS
RBS
RAB
RBS
Linear Increment and Decrement Instructions
Linear Gain Setting Mode
The increment and decrement commands (Command 4 and
Command 5 in Table 15) are useful for linear step adjustment
applications. These commands simplify microcontroller
software coding by allowing the controller to send an increment
or decrement command to the device. The adjustment can be
individual or in a ganged potentiometer arrangement, where all
wiper positions are changed at the same time.
The patented architecture of the AD5123/AD5143 allows the
independent control of each string resistor, RAW, and RWB. To enable
linear gain setting mode, use Command 16 (see Table 15) to set
Bit D2 of the control register (see Table 17).
This mode of operation can control the potentiometer as two
independent rheostats connected at a single point, W terminal,
as opposed to potentiometer mode where each resistor is
For an increment command, executing Command 4 automatically
moves the wiper to the next resistance RDAC position. This
command can be executed in a single channel or multiple channels.
complementary, RAW = RAB − RWB
.
This mode enables a second input and an RDAC register per
channel, as shown in Table 16; however, the actual RDAC
contents remain unchanged. The same operations are valid
for potentiometer and linear setting gain modes. The parts
restore in potentiometer mode after a reset or power-up.
Rev. A | Page 21 of 28
AD5123/AD5143
Data Sheet
±± dB Increment and Decrement Instructions
Reset
Two programming instructions produce logarithmic taper
increment or decrement of the wiper position control by
an individual potentiometer or by a ganged potentiometer
arrangement where all RDAC register positions are changed
simultaneously. The +6 dB increment is activated by Command 6,
and the −6 dB decrement is activated by Command 7 (see Table 15).
For example, starting with the zero-scale position and executing
Command 6 ten times moves the wiper in 6 dB steps to the full-
scale position. When the wiper position is near the maximum
setting, the last 6 dB increment instruction causes the wiper to
go to the full-scale position (see Table 13).
The AD5123/AD5143 can be reset through software by executing
Command 14 (see Table 15). The reset command loads the
RDAC registers with the contents of the EEPROM and takes
approximately 30 µs. The EEPROM is preloaded to midscale at
the factory, and initial power-up is, accordingly, at midscale.
Shutdown Mode
The AD5123/AD5143 can be placed in shutdown mode by
executing the software shutdown command, Command 15
(see Table 15), and setting the LSB (D0) to 1. This feature places
the RDAC in a zero power consumption state where the device
operates in potentiometer mode, Terminal A is open-circuited,
and the wiper, Terminal W, is connected to Terminal B; however, a
finite wiper resistance of 40 Ω is present. When the device is
configured in linear gain setting mode, the resistor addressed,
Incrementing the wiper position by +6 dB essentially doubles
the RDAC register value, whereas decrementing the wiper
position by −6 dB halves the register value. Internally, the
AD5123/AD5143 use shift registers to shift the bits left and
right to achieve a 6 dB increment or decrement. These
functions are useful for various audio/video level adjustments,
especially for white LED brightness settings in which human
visual responses are more sensitive to large adjustments than to
small adjustments.
R
AW or RWB, is internally place at high impedance. Table 14
shows the truth table depending on the device operating mode.
The contents of the RDAC register are unchanged by entering
shutdown mode. However, all commands listed in Table 15 are
supported while in shutdown mode. Execute Command 15 (see
Table 15) and set the LSB (D0) to 0 to exit shutdown mode.
Table 13. Detailed Left Shift and Right Shift Functions for
the 6 dB Step Increment and Decrement
Table 14. Truth Table for Shutdown Mode
Linear Gain Setting Mode
Potentiometer Mode
Left Shift (+6 dB/Step)
Right Shift (−6 dB/Step)
RAW
RWB
RAW RWB
0000 0000
1111 1111
High impedance High impedance High impedance RBS
0000 0001
0111 1111
0000 0010
0000 0100
0011 1111
0001 1111
EEPROM OR RDAC REGISTER PROTECTION
The EEPROM and RDAC registers can be protected by disabling
any update to these registers. This can be done by using software or
by using hardware. If these registers are protected by software,
set Bit D0 and/or Bit D1 (see Table 17), which protects the RDAC
and EEPROM registers independently.
0000 1000
0001 0000
0010 0000
0100 0000
0000 1111
0000 0111
0000 0011
0000 0001
1000 0000
0000 0000
1111 1111
0000 0000
When RDAC is protected, the only operation allowed is to copy
the EEPROM into the RDAC register.
Burst Mode
By enabling the burst mode, multiple data bytes can be sent to
the part consecutively. After the command byte, the part
interprets the consecutive bytes as data bytes for the command.
A new command can be sent by generating a repeat start or by a
stop and start condition.
The burst mode is activated by setting Bit D3 of the control
register (see Table 17).
Rev. A | Page 22 of 28
Data Sheet
AD5123/AD5143
Table 15. Advance Commands Operation Truth Table
Control
Bits[DB15:DB12]
Address
Bits[DB11:DB8]1
Data Bits[DB7:DB0]1
Command
Number
C3
0
C2
0
C1
0
C0
0
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
NOP: do nothing
0
1
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to RDAC
2
3
0
0
0
0
1
1
0
1
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to input register
X
A2 A1 A0
X
X
X
X
X
X
D1 D0 Read back contents
D1
0
D0
0
Data
Input register
EEPROM
0
1
1
0
Control
register
1
1
RDAC
4
5
6
7
8
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
A3 A2 A1 A0
A3 A2 A1 A0
A3 A2 A1 A0
A3 A2 A1 A0
A3 A2 A1 A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
X
Linear RDAC increment
Linear RDAC decrement
+6 dB RDAC increment
−6 dB RDAC decrement
Copy input register to RDAC
(software LRDAC)
9
0
1
1
1
0
0
A1 A0
A1 A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
Copy RDAC register to
EEPROM
10
11
0
1
1
0
1
0
1
0
0
0
0
0
Copy EEPROM into RDAC
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to EEPROM
12
1
0
0
1
A3 A2 A1 A0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
D0 Top scale
D0 = 0; normal mode
D0 = 1; shutdown mode
D0 Bottom scale
13
1
0
0
1
A3 A2 A1 A0
D0 = 1; enter
D0 = 0; exit
14
15
1
1
0
1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Software reset
A3 A2 A1 A0
D0 Software shutdown
D0 = 0; normal mode
D0 = 1; device placed in
shutdown mode
16
1
1
0
1
X
X
X
X
X
X
X
X
D3 D2 D1 D0 Copy serial register data to
control register
1 X = don’t care.
Table 16. Address Bits
Potentiometer Mode
Linear Gain Setting Mode
Stored RDAC
Memory
A3
1
0
A2
X1
0
A1
X1
0
A0
X1
0
Input Register
All channels
RDAC1
RDAC Register
All channels
RDAC1
Input Register
All channels
RWB1
RDAC Register
All channels
RWB1
Not applicable
RDAC1
0
0
1
0
0
0
0
1
Not applicable
RDAC2
Not applicable
RDAC2
RAW1
RWB2
RAW1
RWB2
Not applicable
RDAC2
0
0
1
0
0
1
1
0
Not applicable
RDAC3
Not applicable
RDAC3
RAW2
RWB3
RAW2
RWB3
Not applicable
RDAC3
0
0
1
0
1
1
0
1
Not applicable
RDAC4
Not applicable
RDAC4
RAW3
RWB4
RAW3
RWB4
Not applicable
RDAC4
0
1
1
1
Not applicable
Not applicable
RAW4
RAW4
Not applicable
1 X = don’t care.
Rev. A | Page 23 of 28
AD5123/AD5143
Data Sheet
Table 17. Control Register Bit Descriptions
Bit Name
Description
D0
RDAC register write protect
0 = wiper position frozen to value in EEPROM memory
1 = allows update of wiper position through digital interface (default)
EEPROM program enable
D1
D2
D3
0 = EEPROM program disabled
1 = enables device for EEPROM program (default)
Linear setting mode/potentiometer mode
0 = potentiometer mode (default)
1 = linear gain setting mode
Burst mode
0 = disabled (default)
1 = enabled (no disable after stop or repeat start condition)
Rev. A | Page 24 of 28
Data Sheet
AD5123/AD5143
The nominal resistance between Terminal A and Terminal B,
RAB, is 10 kꢀ or 100 kꢀ, and has 128/256 tap points accessed by
the wiper terminal. The 7-bit/8-bit data in the RDAC latch is
decoded to select one of the 128/256 possible wiper settings. The
general equations for determining the digitally programmed
output resistance between Terminal W and Terminal B are
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5123/AD5143 employ a
three-stage segmentation approach, as shown in Figure 36. The
AD5123/AD5143 wiper switch is designed with the transmission
gate CMOS topology and with the gate voltage derived from
AD5123:
VDD and VSS.
D
128
From 0x00 to 0x7F (1)
From 0x00 to 0xFF (2)
R
WB (D)
RAB RW
RAB RW
A
S
TS
AD5143:
R
R
H
H
D
256
RWB (D)
R
M
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
R
M
R
R
AB is the end-to-end resistance.
L
L
RW is the wiper resistance.
W
R
In potentiometer mode, similar to the mechanical potentiometer,
the resistance between Terminal W and Terminal A also produces
a digitally controlled complementary resistance, RWA. RWA also
gives a maximum of 8% absolute. RWA starts at the maximum
resistance value and decreases as the data loaded into the latch
increases. The general equations for this operation are
7-BIT/8-BIT
ADDRESS
DECODER
R
R
M
R
H
M
R
H
S
BS
AD5123:
B
128 D
128
R
AW (D)
RAB RW
RAB RW
From 0x00 to 0x7F (3)
From 0x00 to 0xFF (4)
AD5143:
Figure 36. AD5123/AD5143 Simplified RDAC Circuit
256 D
256
R
AW (D)
Top Scale/Bottom Scale Architecture
In addition, the AD5123/AD5143 include new positions to
where:
reduce the resistance between terminals. These positions are
called bottom scale and top scale. At bottom scale, the typical
wiper resistance decreases from 130 Ω to 60 Ω (RAB = 100 kΩ).
At top scale, the resistance between Terminal A and Terminal W is
decreased by 1 LSB, and the total resistance is reduced to 60 Ω
(RAB = 100 kΩ).
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
R
AB is the end-to-end resistance.
RW is the wiper resistance.
If the part is configured in linear gain setting mode, the resistance
between Terminal W and Terminal A is directly proportional
to the code loaded in the associate RDAC register. The general
equations for this operation are
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation— 8% Resistor Tolerance
The AD5123/AD5143 operate in rheostat mode when only two
terminals are used as a variable resistor. The unused terminal can
be floating, or it can be tied to Terminal W, as shown in Figure 37.
AD5123:
D
128
From 0x00 to 0x7F (5)
From 0x00 to 0xFF (6)
R
AW (D)
RAB RW
A
A
A
AD5143:
W
W
W
D
256
R
AW (D)
RAB RW
B
B
B
where:
Figure 37. Rheostat Mode Configuration
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
R
AB is the end-to-end resistance.
RW is the wiper resistance.
Rev. A | Page 25 of 28
AD5123/AD5143
Data Sheet
V
DD
In the bottom scale condition or top scale condition, a finite
total wiper resistance of 40 Ω is present. Regardless of which
setting the part is operating in, limit the current between
Terminal A to Terminal B, Terminal W to Terminal A, and
Terminal W to Terminal B, to the maximum continuous
current of ±± mA or to the pulse current specified in Table 5.
Otherwise, degradation or possible destruction of the internal
switch contact can occur.
A
W
B
V
SS
PROGRAMMING THE POTENTIOMETER DIVIDER
Figure 39. Maximum Terminal Voltages Set by VDD and VSS
Voltage Output Operation
POWER-UP SEQUENCE
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input voltage
at A to B, as shown in Figure 38.
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 39), it is
important to power up VDD first before applying any voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that VDD is powered unintentionally. The
ideal power-up sequence is VSS, VDD, digital inputs, and VA, VB,
and VW. The order of powering VA, VB, VW, and digital inputs is
not important as long as they are powered after VSS and VDD.
Regardless of the power-up sequence and the ramp rates of the
power supplies, once VDD is powered, the power-on preset
activates, which restores EEPROM values to the RDAC registers.
V
A
A
W
V
OUT
B
V
B
Figure 38. Potentiometer Mode Configuration
Connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at VW with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use a compact, minimum lead
length layout design. Ensure that the leads to the input are as
direct as possible with a minimum conductor length. Ground
paths should have low resistance and low inductance. It is also
good practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 40 illustrates the basic supply bypassing configuration
for the AD5123/AD5143.
RWB(D)
RAB
R
AW (D)
RAB
VW (D)
VA
VB
(7)
where:
RWB(D) can be obtained from Equation 1 and Equation 2.
RAW(D) can be obtained from Equation 3 and Equation 4.
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RAW and RWB, and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
V
V
DD
DD
+
+
C3
C1
10µF
0.1µF
AD5123/
AD5143
C4
10µF
C2
0.1µF
TERMINAL VOLTAGE OPERATING RANGE
V
V
SS
SS
The AD5123/AD5143 are designed with internal ESD diodes
for protection. These diodes also set the voltage boundary of
the terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed VDD are
clamped by the forward-biased diode. There is no polarity
GND
Figure 40. Power Supply Bypassing
constraint between VA, VW, and VB, but they cannot be higher
than VDD or lower than VSS.
Rev. A | Page 26 of 28
Data Sheet
AD5123/AD5143
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
4
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
8
5
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
AD5123BCPZ10-RL7
AD5123BCPZ100-RL7 100
AD5143BCPZ10-RL7 10
AD5143BCPZ100-RL7 100
EVAL-AD5143DBZ
RAB (kΩ) Resolution Interface Temperature Range Package Description Package Option Branding
10
128
128
256
256
I2C
I2C
I2C
I2C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
Evaluation Board
CP-16-22
CP-16-22
CP-16-22
CP-16-22
DGZ
DH0
DH1
DH2
1 Z = RoHS Compliant Part.
2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all of the available resistor value options.
Rev. A | Page 27 of 28
AD5123/AD5143
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10878-0-3/13(A)
Rev. A | Page 28 of 28
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