AD5141BCPZ10-RL7 [ADI]
Single Channel, 128-/256-Position, I2C/SPI, Nonvolatile Digital Potentiometer; 单通道， 128 / 256位， I2C / SPI ，非易失性数字电位计
| 型号： | AD5141BCPZ10-RL7 |
| 厂家： | 
ADI |
| 描述： | Single Channel, 128-/256-Position, I2C/SPI, Nonvolatile Digital Potentiometer |
| 文件： | 总32页 (文件大小：673K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Channel, 128-/256-Position, I2C/SPI,
Nonvolatile Digital Potentiometer
Data Sheet
AD5121/AD5141
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
LOGIC
DD
INDEP
10 kΩ and 100 kΩ resistance options
Resistor tolerance: 8% maximum
Wiper current: 6 mA
Low temperature coefficient: 35 ppm/°C
Wide bandwidth: 3 MHz
AD5121/
AD5141
POWER-ON
RESET
RDAC
INPUT
Fast start-up time < 75 µs
Linear gain setting mode
A
RESET
DIS
W
B
REGISTER
Single- and dual-supply operation
Independent logic supply: 1.8 V to 5.5 V
Wide operating temperature: −40°C to +125°C
3 mm × 3 mm LFCSP package
4 kV ESD protection
SCLK/SCL
SDI/SDA
7/8
SERIAL
INTERFACE
EEPROM
MEMORY
SYNC/ADDR0
SDO/ADDR1
GND
V
SS
APPLICATIONS
WP
Figure 1.
Portable electronics level adjustment
LCD panel brightness and contrast controls
Programmable filters, delays, and time constants
Programmable power supplies
GENERAL DESCRIPTION
Table 1. Family Models
Model
Channel Position Interface Package
The AD5121/AD5141 potentiometers provide a nonvolatile
solution for 128-/256-position adjustment applications, offering
guaranteed low resistor tolerance errors of 8% and up to 6 mA
current density in the A, B, and W pins.
AD51231
AD5124
AD5124
AD51431
AD5144
AD5144
Quad
Quad
Quad
Quad
Quad
Quad
128
128
128
256
256
256
256
128
128
256
256
128
256
I2C
LFCSP
LFCSP
TSSOP
LFCSP
LFCSP
TSSOP
SPI/I2C
SPI
I2C
The low resistor tolerance and low nominal temperature coefficient
simplify open-loop applications as well as applications requiring
tolerance matching.
SPI/I2C
SPI
I2C
AD5144A Quad
AD5122 Dual
AD5122A Dual
AD5142 Dual
AD5142A Dual
TSSOP
The linear gain setting mode allows independent programming
of the resistance between the digital potentiometer terminals,
through RAW and RWB string resistors, allowing very accurate
resistor matching.
SPI
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP
I2C
SPI
I2C
SPI/I2C
SPI/I2C
AD5121
AD5141
Single
Single
The high bandwidth and low total harmonic distortion (THD)
ensure optimal performance for ac signals, making it suitable
for filter design.
LFCSP
1 Two potentiometers and two rheostats.
The low wiper resistance of only 40 Ω at the ends of the resistor
array allows for pin-to-pin connection.
The wiper values can be set through an SPI-/I2C-compatible digital
interface that is also used to read back the wiper register and
EEPROM contents.
The AD5121/AD5141 is available in a compact, 16-lead, 3 mm ×
3 mm LFCSP. The parts are guaranteed to operate over the
extended industrial temperature range of −40°C to +125°C.
Rev. 0
Document Feedback
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
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Tel: 781.329.4700
Technical Support
©2012 Analog Devices, Inc. All rights reserved.
www.analog.com
AD5121/AD5141
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Shift Register .................................................................... 20
Serial Data Digital Interface Selection, DIS............................ 20
SPI Serial Data Interface............................................................ 20
I2C Serial Data Interface............................................................ 22
I2C Address.................................................................................. 22
Advanced Control Modes ......................................................... 23
EEPROM or RDAC Register Protection................................. 24
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—AD5121 .......................................... 3
Electrical Characteristics—AD5141 .......................................... 6
Interface Timing Specifications.................................................. 9
Shift Register and Timing Diagrams ....................................... 10
Absolute Maximum Ratings.......................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Typical Performance Characteristics ........................................... 14
Test Circuits..................................................................................... 19
Theory of Operation ...................................................................... 20
RDAC Register and EEPROM.................................................. 20
LRDAC
)..................................... 24
Load RDAC Input Register (
INDEP Pin................................................................................... 24
RDAC Architecture.................................................................... 27
Programming the Variable Resistor......................................... 27
Programming the Potentiometer Divider............................... 28
Terminal Voltage Operating Range ......................................... 29
Power-Up Sequence ................................................................... 29
Layout and Power Supply Biasing............................................ 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
10/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
Data Sheet
AD5121/AD5141
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5121
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless
otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution
Resistor Integral Nonlinearity2
N
R-INL
7
Bits
RAB = 10 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
RAB = 100 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
−1
−2.5
0.1
1
+1
+2.5
LSB
LSB
−0.5
−1
0.1
0.25 +1
+0.5
LSB
LSB
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance3
R-DNL
−0.5
−8
0.1
1
35
+0.5
+8
LSB
%
ppm/°C
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
Code = full scale
Code = zero scale
RAB = 10 kΩ
55
130
125
400
Ω
Ω
RAB = 100 kΩ
Bottom Scale or Top Scale
RBS or RTS
RAB = 10 kΩ
RAB = 100 kΩ
40
60
80
230
Ω
Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4
INL
RAB = 10 kΩ
RAB = 100 kΩ
−0.5
−0.25
−0.25
0.1
0.1
0.1
+0.5
+0.25
+0.25
LSB
LSB
LSB
Differential Nonlinearity4
Full-Scale Error
DNL
VWFSE
RAB = 10 kΩ
RAB = 100 kΩ
−1.5
−0.5
−0.1
0.1
LSB
LSB
+0.5
Zero-Scale Error
VWZSE
RAB = 10 kΩ
RAB = 100 kΩ
(ΔVW/VW)/ΔT × 106 Code = half scale
1
0.25
5
1.5
0.5
LSB
LSB
ppm/°C
Voltage Divider Temperature
Coefficient3
Rev. 0 | Page 3 of 32
AD5121/AD5141
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1
Max
Unit
RESISTOR TERMINALS
Maximum Continuous Current
IA, IB, and IW
RAB = 10 kΩ
RAB = 100 kΩ
−6
−1.5
VSS
+6
+1.5
VDD
mA
mA
V
Terminal Voltage Range5
Capacitance A, Capacitance B3
CA, CB
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
25
12
pF
pF
Capacitance W3
CW
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
VA = VW = VB
12
5
15
pF
pF
nA
Common-Mode Leakage Current3
−500
+500
DIGITAL INPUTS
Input Logic3
High
VINH
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
0.8 × VLOGIC
0.7 × VLOGIC
V
V
Low
VINL
VHYST
IIN
0.2 × VLOGIC
1
V
V
µA
pF
Input Hysteresis3
Input Current3
0.1 × VLOGIC
Input Capacitance3
DIGITAL OUTPUTS
Output High Voltage3
Output Low Voltage3
CIN
5
VOH
VOL
RPULL-UP = 2.2 kΩ to VLOGIC
ISINK = 3 mA
ISINK = 6 mA, VLOGIC > 2.3 V
VLOGIC
V
V
V
µA
pF
0.4
0.6
+1
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
−1
2
Single-Supply Power Range
Dual-Supply Power Range
Logic Supply Range
VSS = GND
2.3
2.25
1.8
5.5
V
V
V
V
2.75
VDD
VDD
Single supply, VSS = GND
Dual supply, VSS < GND
VIH = VLOGIC or VIL = GND
VDD = 5.5 V
2.25
Positive Supply Current
IDD
0.7
400
−0.7
2
320
1
5.5
µA
nA
µA
mA
µA
nA
µW
dB
VDD = 2.3 V
Negative Supply Current
EEPROM Store Current3, 6
EEPROM Read Current3, 7
Logic Supply Current
Power Dissipation8
Power Supply Rejection Ratio
ISS
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
−5.5
IDD_EEPROM_STORE
IDD_EEPROM_READ
ILOGIC
PDISS
PSRR
120
−60
3.5
−66
∆VDD/∆VSS = VDD 10%,
code = full scale
Rev. 0 | Page 4 of 32
Data Sheet
AD5121/AD5141
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1
Max
Unit
DYNAMIC CHARACTERISTICS9
Bandwidth
BW
−3 dB
RAB = 10 kΩ
RAB = 100 kΩ
3
0.43
MHz
MHz
Total Harmonic Distortion
Resistor Noise Density
VW Settling Time
THD
eN_WB
tS
VDD/VSS = 2.5 V, VA = 1 V rms,
VB = 0 V, f = 1 kHz
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C,
f = 10 kHz
RAB = 10 kΩ
−80
−90
dB
dB
7
20
nV/√Hz
nV/√Hz
RAB = 100 kΩ
VA = 5 V, VB = 0 V, from
zero scale to full scale,
0.5 LSB error band
RAB = 10 kΩ
RAB = 100 kΩ
TA = 25°C
2
12
1
µs
µs
Mcycles
kcycles
Years
Endurance10
100
Data Retention11
50
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB
.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD/VSS
= 2.5 V, and VLOGIC = 2.5 V.
10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
Rev. 0 | Page 5 of 32
AD5121/AD5141
Data Sheet
ELECTRICAL CHARACTERISTICS—AD5141
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless
otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1 Max
Unit
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution
N
R-INL
8
Bits
Resistor Integral Nonlinearity2
RAB = 10 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
RAB = 100 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
−2
−5
0.2
1.5
+2
+5
LSB
LSB
−1
−2
−0.5
−8
0.1
0.5
0.2
1
+1
+2
+0.5
+8
LSB
LSB
LSB
%
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance3
R-DNL
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
Code = full scale
Code = zero scale
RAB = 10 kΩ
35
ppm/°C
55
130
125
400
Ω
Ω
RAB = 100 kΩ
Bottom Scale or Top Scale
RBS or RTS
RAB = 10 kΩ
RAB = 100 kΩ
40
60
80
230
Ω
Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4
INL
RAB = 10 kΩ
RAB = 100 kΩ
−1
−0.5
−0.5
0.2
0.1
0.2
+1
+0.5
+0.5
LSB
LSB
LSB
Differential Nonlinearity4
Full-Scale Error
DNL
VWFSE
RAB = 10 kΩ
RAB = 100 kΩ
−2.5
−1
−0.1
0.2
LSB
LSB
+1
Zero-Scale Error
VWZSE
RAB = 10 kΩ
RAB = 100 kΩ
(ΔVW/VW)/ΔT × 106 Code = half scale
1.2
0.5
5
3
1
LSB
LSB
ppm/°C
Voltage Divider Temperature
Coefficient3
Rev. 0 | Page 6 of 32
Data Sheet
AD5121/AD5141
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1 Max
Unit
RESISTOR TERMINALS
Maximum Continuous Current
IA, IB, and IW
RAB = 10 kΩ
RAB = 100 kΩ
−6
−1.5
VSS
+6
+1.5
VDD
mA
mA
V
Terminal Voltage Range5
Capacitance A, Capacitance B3
CA, CB
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
25
12
pF
pF
Capacitance W3
CW
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
VA = VW = VB
12
5
15
pF
pF
nA
Common-Mode Leakage Current3
−500
+500
DIGITAL INPUTS
Input Logic3
High
VINH
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
0.8 × VLOGIC
0.7 × VLOGIC
V
V
Low
VINL
VHYST
IIN
0.2 × VLOGIC
1
V
V
µA
pF
Input Hysteresis3
Input Current3
0.1 × VLOGIC
Input Capacitance3
DIGITAL OUTPUTS
Output High Voltage3
Output Low Voltage3
CIN
5
VOH
VOL
RPULL-UP = 2.2 kΩ to VLOGIC
ISINK = 3 mA
ISINK = 6 mA, VLOGIC > 2.3V
VLOGIC
V
V
V
µA
pF
0.4
0.6
+1
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
−1
2
Single-Supply Power Range
Dual-Supply Power Range
Logic Supply Range
VSS = GND
2.3
2.25
1.8
5.5
V
V
V
V
2.75
VDD
VDD
Single supply, VSS = GND
Dual supply, VSS < GND
VIH = VLOGIC or VIL = GND
VDD = 5.5 V
2.25
Positive Supply Current
IDD
0.7
400
−0.7
2
320
1
5.5
µA
nA
µA
mA
µA
nA
µW
dB
VDD = 2.3 V
Negative Supply Current
EEPROM Store Current3, 6
EEPROM Read Current3, 7
Logic Supply Current
Power Dissipation8
Power Supply Rejection Ratio
ISS
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
−5.5
IDD_EEPROM_STORE
IDD_EEPROM_READ
ILOGIC
PDISS
PSR
120
−60
3.5
−66
∆VDD/∆VSS = VDD 10%,
code = full scale
Rev. 0 | Page 7 of 32
AD5121/AD5141
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1 Max
Unit
DYNAMIC CHARACTERISTICS9
Bandwidth
BW
−3 dB
RAB = 10 kΩ
RAB = 100 kΩ
3
0.43
MHz
MHz
Total Harmonic Distortion
Resistor Noise Density
VW Settling Time
THD
eN_WB
tS
VDD/VSS = 2.5 V, VA = 1 V rms,
VB = 0 V, f = 1 kHz
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C,
f = 10 kHz
RAB = 10 kΩ
−80
−90
dB
dB
7
20
nV/√Hz
nV/√Hz
RAB = 100 kΩ
VA = 5 V, VB = 0 V, from
zero scale to full scale,
0.5 LSB error band
RAB = 10 kΩ
RAB = 100 kΩ
TA = 25°C
2
12
1
µs
µs
Mcycles
kcycles
Years
Endurance10
100
Data Retention11
50
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor integral nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB
.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD/VSS
= 2.5 V, and VLOGIC = 2.5 V.
10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
Rev. 0 | Page 8 of 32
Data Sheet
AD5121/AD5141
INTERFACE TIMING SPECIFICATIONS
VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. SPI Interface
Parameter1
Test Conditions/Comments
Min
20
30
10
15
10
15
10
5
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
t1
VLOGIC > 1.8 V
VLOGIC = 1.8 V
VLOGIC > 1.8 V
VLOGIC = 1.8 V
VLOGIC > 1.8 V
VLOGIC = 1.8 V
SCLK cycle time
t2
t3
SCLK high time
SCLK low time
t4
t5
t6
t7
SYNC-to-SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to next SCLK fall ignored
Minimum SYNC high time
5
10
20
2
t8
3
t9
50
SCLK rising edge to SDO valid
SYNC rising edge to SDO pin disable
t10
500
1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Refer to t
t
for memory commands operations (see Table 6).
EEPROM_PROGRAM and
EEPROM_READBACK
3 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF.
Table 5. I2C Interface
Parameter1 Test Conditions/Comments
Min
Typ Max Unit Description
2
fSCL
t1
Standard mode
Fast mode
Standard mode
Fast mode
100
400
kHz
kHz
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Serial clock frequency
4.0
0.6
4.7
1.3
250
100
0
SCL high time, tHIGH
t2
Standard mode
Fast mode
SCL low time, tLOW
t3
Standard mode
Fast mode
Data setup time, tSU; DAT
t4
Standard mode
Fast mode
3.45
0.9
Data hold time, tHD; DAT
0
t5
Standard mode
Fast mode
4.7
0.6
4
0.6
4.7
1.3
4
Setup time for a repeated start condition, tSU; STA
Hold time (repeated) for a start condition, tHD; STA
Bus free time between a stop and a start condition, tBUF
Setup time for a stop condition, tSU; STO
Rise time of SDA signal, tRDA
t6
Standard mode
Fast mode
t7
Standard mode
Fast mode
t8
Standard mode
Fast mode
0.6
t9
Standard mode
Fast mode
1000 ns
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
300
300
300
ns
ns
ns
t10
t11
t11A
Standard mode
Fast mode
Standard mode
Fast mode
Fall time of SDA signal, tFDA
1000 ns
300 ns
1000 ns
Rise time of SCL signal, tRCL
Standard mode
Rise time of SCL signal after a repeated start condition
and after an acknowledge bit, tRCL1 (not shown in Figure 3)
Fast mode
20 + 0.1 CL
300
ns
Rev. 0 | Page 9 of 32
AD5121/AD5141
Data Sheet
Parameter1 Test Conditions/Comments
Min
Typ Max Unit Description
t12
Standard mode
Fast mode
Fast mode
300
300
50
ns
ns
ns
Fall time of SCL signal, tFCL
20 + 0.1 CL
0
3
tSP
Pulse width of suppressed spike (not shown in Figure 3)
1 Maximum bus capacitance is limited to 400 pF.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the part.
3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
Table 6. Control Pins
Parameter
Min
1
Typ
Max
Unit
µs
Description
t1
End command to LRDAC falling edge
Minimum LRDAC low time
t2
50
0.1
ns
t3
10
50
30
75
µs
RESET low time
1
tEEPROM_PROGRAM
15
7
ms
µs
Memory program time (not shown in Figure 6)
Memory readback time (not shown in Figure 6)
Power-on EEPROM restore time (not shown in Figure 6)
Reset EEPROM restore time (not shown in Figure 6)
tEEPROM_READBACK
2
tPOWER_UP
µs
µs
tRESET
30
1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
2 Maximum time after VDD − VSS is equal to 2.3 V.
SHIFT REGISTER AND TIMING DIAGRAMS
DB15 (MSB)
DB8
A0
DB7
D7
DB0 (LSB)
D0
D1
A1
D6
D5
D4
D3
C3
C2
C1
C0
A3
A2
D2
DATA BITS
CONTROL BITS
ADDRESS BITS
Figure 2. Input Shift Register Contents
t11
t12
t6
t8
t2
SCL
SDA
t5
t1
t6
t10
t9
t4
t3
t7
P
S
S
P
Figure 3. I2C Serial Interface Timing Diagram (Typical Write Sequence)
t4
t1
t2
t7
SCLK
SYNC
t3
t8
t5
t6
SDI
C3
C2
C1
C0
D7
D6
D5
D2
D1
D0
t9
t10
SDO
C3*
C2*
C1*
C0*
D7*
D6*
D5*
D2*
D1*
D0*
*PREVIOUS COMMAND RECEIVED.
Figure 4. SPI Serial Interface Timing Diagram, CPOL = 0, CPHA = 1
Rev. 0 | Page 10 of 32
Data Sheet
AD5121/AD5141
t1
t2
t7
t4
SCLK
SYNC
t3
t8
t5
t6
SDI
C3
C2
C1
C0
D7
D6
D5
D2
D1
D0
t9
t10
SDO
C3*
C2*
C1*
C0*
D7*
D6*
D5*
D2*
D1*
D0*
*PREVIOUS COMMAND RECEIVED.
Figure 5. SPI Serial Interface Timing Diagram, CPOL = 1, CPHA = 0
SCLK
SPI INTERFACE
SYNC
SCL
2
I C INTERFACE
SDA
P
t2
t1
LRDAC
RESET
t3
Figure 6. Control Pins Timing Diagram
Rev. 0 | Page 11 of 32
AD5121/AD5141
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 7.
Parameter
VDD to GND
VSS to GND
VDD to VSS
Rating
−0.3 V to +7.0 V
+0.3 V to −7.0 V
7 V
VLOGIC to GND
−0.3 V to VDD + 0.3 V or
THERMAL RESISTANCE
+7.0 V (whichever is less)
VA, VW, VB to GND
VSS − 0.3 V, VDD + 0.3 V or
+7.0 V (whichever is less)
θJA is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
IA, IW, IB
Pulsed1
Table 8. Thermal Resistance
Package Type
θJA
θJC
Unit
Frequency > 10 kHz
RAW = 10 kΩ
RAW = 100 kΩ
6 mA/d2
1.5 mA/d2
16-Lead LFCSP
89.51
3
°C/W
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
Frequency ≤ 10 kHz
RAW = 10 kΩ
RAW = 100 kΩ
6 mA/√d2
1.5 mA/√d2
ESD CAUTION
Digital Inputs
−0.3 V to VLOGIC + 0.3 V or
+7 V (whichever is less)
−40°C to +125°C
150°C
3
Operating Temperature Range, TA
Maximum Junction Temperature,
TJ Maximum
Storage Temperature Range
Reflow Soldering
−65°C to +150°C
Peak Temperature
260°C
Time at Peak Temperature
Package Power Dissipation
20 sec to 40 sec
(TJ max − TA)/θJA
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 d = pulse duty factor.
3 Includes programming of EEPROM memory.
Rev. 0 | Page 12 of 32
Data Sheet
AD5121/AD5141
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
GND 1
A 2
12 SDI/SDA
11
10
9
SCLK/SCL
AD5121/
AD5141
W 3
B 4
V
LOGIC
TOP VIEW
(Not to Scale)
V
DD
NOTES
1. INTERNALLY CONNECT THE
EXPOSED PAD TO V
.
SS
Figure 7. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
Ground Pin, Logic Ground Reference.
Terminal A of RDAC. VSS ≤ VA ≤ VDD
Wiper terminal of RDAC. VSS ≤ VW ≤ VDD
Terminal B of RDAC. VSS ≤ VB ≤ VDD
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
1
2
3
4
5
6
GND
A
W
B
VSS
.
.
.
SYNC/ADDR0 Programmable Address (ADDR0) for Multiple Package Decoding, DIS = 1.
Synchronization Data Input, Active Low. When SYNC returns high, data is loaded into the RDAC register, DIS = 0.
7
8
RESET
DIS
Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at logic low. If this pin is not
used, tie RESET to VLOGIC
Digital Interface Select (SPI/I2C Select). SPI when DIS = 0 (GND), I2C when DIS = 1 (VLOGIC). This pin cannot be left
floating.
.
9
10
11
VDD
VLOGIC
SCLK/SCL
Positive Power Supply. Decouple this pin with 0.1µF ceramic capacitors and 10 µF capacitors.
Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
SPI Serial Clock Line (SCLK). Data is clocked in at logic low transition.
I2C Serial Clock Line (SCL). Data is clocked in at logic low transition.
Serial Data Input/Output (SDA), When DIS = 1.
12
13
SDI/SDA
WP
Serial Data Input (SDI), When DIS = 0.
Optional Write Protect. This pin prevents any changes to the present RDAC and EEPROM contents, except when
reloading the content of the EEPROM into the RDAC register. WP is activated at logic low. If this pin is not used,
tie WP to VLOGIC
14
SDO/ADDR1
Programmable Address (ADDR1) for Multiple Package Decoding, When DIS = 1.
Serial Data Output (SDO). This is an open-drain output pin, and it needs an external pull-up resistor when DIS = 0.
15
16
INDEP
LRDAC
EPAD
Linear Gain Setting Mode at Power-Up. Each string resistor is loaded from its associate memory location. If
INDEP is enabled, it cannot be disabled by the software.
Load RDAC. Transfers the contents of the input register to the RDAC register. This allows asynchronous RDAC
update. LRDAC is activated low. If this pin is not used, tie LRDAC to VLOGIC
.
Internally Connect the Exposed Pad to VSS.
Rev. 0 | Page 13 of 32
AD5121/AD5141
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.2
0.1
10kΩ, +125°C
10kΩ, +25°C
0.4
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
0.3
0
100kΩ, –40°C
0.2
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
0
100
200
0
100
200
CODE (Decimal)
CODE (Decimal)
Figure 8. R-INL vs. Code (AD5141)
Figure 11. R-DNL vs. Code (AD5141)
0.20
0.10
0.05
0.15
0.10
0
0.05
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
0
–0.05
–0.10
–0.15
–0.20
–0.25
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
0
50
100
0
50
100
CODE (Decimal)
CODE (Decimal)
Figure 9. R-INL vs. Code (AD5121)
Figure 12. R-DNL vs. Code (AD5121)
0.10
0.05
0.3
0.2
0.1
0
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.1
–0.2
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
–0.3
0
0
100
200
100
200
CODE (Decimal)
CODE (Decimal)
Figure 13. DNL vs. Code (AD5141)
Figure 10. INL vs. Code (AD5141)
Rev. 0 | Page 14 of 32
Data Sheet
AD5121/AD5141
0.15
0.10
0.05
0
0.06
0.04
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
–0.05
–0.10
–0.15
0
50
100
0
50
100
CODE (Decimal)
CODE (Decimal)
Figure 14. INL vs. Code (AD5121)
Figure 17. DNL vs. Code (AD5121)
450
400
350
300
250
200
150
100
50
450
100kΩ
10kΩ
10kΩ
100kΩ
400
350
300
250
200
150
100
50
0
0
–50
–50
AD5141
AD5121
AD5142
AD5122
0
0
50
25
100
50
150
75
200
100
255
127
0
0
50
25
100
50
150
75
200
100
255
127
CODE (Decimal)
CODE (Decimal)
Figure 18. Rheostat Mode Temperature Coefficient ((ΔRWB/RWB)/ΔT × 106)
vs. Code
Figure 15. Potentiometer Mode Temperature Coefficient ((ΔVW/VW)/ΔT × 106)
vs. Code
1200
800
2
I
I
I
, V
=
=
=
2.3V
3.3V
5V
I
I
I
,
,
,
V
V
V
= 2.3V
= 3.3V
= 5V
V
V
= V
DD LOGIC
I C, V
= 1.8V
= 2.3V
= 3.3V
= 5V
DD DD
LOGIC LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
2
I C, V
, V
= GND
DD DD
LOGIC LOGIC
SS
2
I C, V
700
600
500
400
300
200
100
0
, V
DD DD
LOGIC LOGIC
2
I C, V
1000
800
600
400
200
0
2
I C, V
= 5.5V
= 1.8V
= 2.3V
= 3.3V
= 5V
SPI, V
SPI, V
SPI, V
SPI, V
SPI, V
= 5.5V
0
1
2
3
4
5
–40
10
60
TEMPERATURE (°C)
110 125
INPUT VOLTAGE (V)
Figure 19. ILOGIC Current vs. Digital Input Voltage
Figure 16. Supply Current vs. Temperature
Rev. 0 | Page 15 of 32
AD5121/AD5141
Data Sheet
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0x80 (0x40)
0x40 (0x20)
0x20 (0x10)
0x10 (0x08)
0x8 (0x04)
0x80 (0x40)
0x40 (0x20)
–10
0x20 (0x10)
–20
0x10 (0x08)
0x4 (0x02)
0x2 (0x01)
0x1 (0x00)
0x8 (0x04)
–30
0x4 (0x02)
0x00
0x2 (0x01)
0x1 (0x00)
–40
0x00
–50
AD5121/AD5141
–60
AD5121/AD5141
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20. 10 kΩ Gain vs. Frequency vs. Code
Figure 23. 100 kΩ Gain vs. Frequency vs. Code
–40
–50
–60
–70
–80
–90
–100
0
10kΩ
10kΩ
100kΩ
V
/V = ±2.5V
= 1V rms
= GND
DD SS
100kΩ
V
V
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
B
CODE = HALF SCALE
NOISE FILTER = 22kHz
V
f
/V = ±2.5V
DD SS
= 1kHz
CODE = HALF SCALE
NOISE FILTER = 22kHz
IN
0.001
0.01
0.1
1
20
200
2k
FREQUENCY (Hz)
20k
200k
VOLTAGE (V rms)
Figure 24. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude
Figure 21. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency
10
0
20
V
R
/V = ±2.5V
DD SS
= 10kΩ
AB
0
–20
–10
–20
–30
–40
–50
–60
–40
–60
–70
–80
QUARTER SCALE
QUARTER SCALE
MIDSCALE
–80
V
R
/V = ±2.5V
MIDSCALE
DD SS
FULL-SCALE
= 100kΩ
AB
FULL-SCALE
–90
10
–100
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25. Normalized Phase Flatness vs. Frequency, RAB = 100 kΩ
Figure 22. Normalized Phase Flatness vs. Frequency, RAB = 10 kΩ
Rev. 0 | Page 16 of 32
Data Sheet
AD5121/AD5141
0.0025
0.0020
0.0015
0.0010
0.0005
0
1.2
1.0
0.8
0.6
0.4
0.2
600
500
400
300
200
100
100kΩ, V
100kΩ, V
100kΩ, V
100kΩ, V
100kΩ, V
100kΩ, V
= 2.3V
= 2.7V
= 3V
DD
DD
DD
DD
DD
DD
= 3.6V
= 5V
= 5.5V
10kΩ, V
10kΩ, V
10kΩ, V
10kΩ, V
10kΩ, V
10kΩ, V
= 2.3V
= 2.7V
= 3V
DD
DD
DD
DD
DD
DD
= 3.6V
= 5V
= 5.5V
0
0
0
–600 –500 –400 –300 –200 –100
0
100 200 300 400 500 600
1
2
3
4
5
RESISTOR DRIFT (ppm)
VOLTAGE (V)
Figure 26. Incremental Wiper On Resistance vs. VDD
Figure 29. Resistor Lifetime Drift
10
9
8
7
6
5
4
3
2
1
0
0
10kΩ
10kΩ + 0pF
100kΩ
10kΩ + 75pF
10kΩ + 150pF
10kΩ + 250pF
100kΩ + 0pF
100kΩ + 75pF
100kΩ + 150pF
100kΩ + 250pF
–10
–20
–30
–40
–50
–60
–70
–80
–90
10
100
1k
10k
100k
1M
10M
0
0
20
10
40
20
60
30
80
40
100
50
120
60 AD5121
AD5141
FREQUENCY (Hz)
CODE (Decimal)
Figure 30. Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 27. Maximum Bandwidth vs. Code vs. Net Capacitance
0.020
0.8
0x80 TO 0x7F, 100kΩ
V
V
V
/V = ±2.5V
DD SS
0x80 TO 0x7F, 10kΩ
= V
A
B
DD
SS
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.015
0.010
0.005
0
= V
–0.005
–0.010
–0.015
–0.020
–0.1
0
500
1000
1500
2000
0
5
10
15
TIME (ns)
TIME (µs)
Figure 31. Digital Feedthrough
Figure 28. Maximum Transition Glitch
Rev. 0 | Page 17 of 32
AD5121/AD5141
Data Sheet
7
6
5
4
3
2
1
0
0
10kΩ
SHUTDOWN MODE ENABLED
100kΩ
–20
–40
–60
–80
10kΩ
–100
100kΩ
–120
10
100
1k
10k
100k
1M
10M
0
0
50
25
100
50
150
75
200
100
250
125
AD5141
AD5121
FREQUENCY (Hz)
CODE (Decimal)
Figure 32. Shutdown Isolation vs. Frequency
Figure 33. Theoretical Maximum Current vs. Code
Rev. 0 | Page 18 of 32
Data Sheet
AD5121/AD5141
TEST CIRCUITS
Figure 34 to Figure 38 define the test conditions used in the Specifications section.
NC
DUT
A
V
I
A
W
V+ = V ±10%
DD
W
V
Δ
MS
V
A
B
PSRR (dB) = 20 LOG
DD
)
(
ΔV
B
W
DD
V+
~
V
ΔV
%
MS
MS
PSS (%/%) =
V
MS
ΔV
%
DD
NC = NO CONNECT
Figure 37. Power Supply Sensitivity and
Figure 34. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
Power Supply Rejection Ratio (PSS and PSRR)
0.1V
R
=
SW
I
DUT
B
SW
CODE = 0x00
W
+
–
DUT
V+ = V
DD
1LSB = V+/2
0.1V
I
SW
N
A
W
V+
V
TO V
DD
SS
B
A = NC
V
MS
Figure 35. Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 38. Incremental on Resistance
NC
DUT
A
W
I
= V /R
DD NOMINAL
W
V
W
B
V
R
= V /I
MS1 W
MS1
W
NC = NO CONNECT
Figure 36. Wiper Resistance
Rev. 0 | Page 19 of 32
AD5121/AD5141
Data Sheet
THEORY OF OPERATION
The AD5121/AD5141 digital programmable potentiometers are
designed to operate as true variable resistors for analog signals
within the terminal voltage range of VSS < VTERM < VDD. The
resistor wiper position is determined by the RDAC register
contents. The RDAC register acts as a scratchpad register that
allows unlimited changes of resistance settings. A secondary
register (the input register) can be used to preload the RDAC
register data.
SERIAL DATA DIGITAL INTERFACE SELECTION, DIS
The AD5121/AD5141 LFSCP provides the flexibility of a selectable
interface. When the digital interface select (DIS) pin is tied low,
the SPI mode is engaged. When the DIS pin is tied high, the I2C
mode is engaged.
SPI SERIAL DATA INTERFACE
The AD5121/AD5141 contain a 4-wire, SPI-compatible digital
interface (SDI,
begins by bringing the
held low until the complete data-word is loaded from the SDI pin.
Data is loaded in at the SCLK falling edge transition, as shown
in Figure 4. When
, SDO, and SCLK). The write sequence
SYNC
The RDAC register can be programmed with any position setting
using the I2C or SPI interface (depending on the model). When
a desirable wiper position is found, this value can be stored in
the EEPROM memory. Thereafter, the wiper position is always
restored to that position for subsequent power-ups. The storing
of EEPROM data takes approximately 18 ms; during this time,
the device is locked and does not acknowledge any new command,
preventing any changes from taking place.
SYNC
SYNC
pin must be
line low. The
SYNC
returns high, the serial data-word is
decoded according to the instructions in Table 16.
The AD5121/AD5141 do not require a continuous SCLK
SYNC
when
is high. To minimize power consumption in the
RDAC REGISTER AND EEPROM
digital input buffers when the part is enabled, operate all serial
interface pins close to the VLOGIC supply rails.
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with 0x80 (AD5141, 256 taps), the wiper is connected to
half scale of the variable resistor. The RDAC register is a standard
logic register; there is no restriction on the number of changes
allowed.
SYNC
Interruption
In a standalone write sequence for the AD5121/AD5141,
SYNC
the
instruction is decoded when
SYNC
line is kept low for 16 falling edges of SCLK, and the
SYNC
is pulled high. However, if
line is kept low for less than 16 falling edges of SCLK,
the
It is possible to both write to and read from the RDAC register
using the digital interface (see Table 16).
the input shift register content is ignored, and the write sequence is
considered invalid.
The contents of the RDAC register can be stored to the EEPROM
using Command 9 (see Table 16). Thereafter, the RDAC register
always sets at that position for any future on-off-on power
supply sequence. It is possible to read back data saved into the
EEPROM with Command 3 (see Table 16).
SDO Pin
The serial data output pin (SDO) serves two purposes: to read
back the contents of the control, EEPROM, RDAC, and input
registers using Command 3 (see Table 11 and Table 16), and to
connect the AD5121/AD5141 to daisy-chain mode.
Alternatively, the EEPROM can be written to independently
using Command 1 (see Table 16).
The SDO pin contains an internal open-drain output that needs an
external pull-up resistor. The SDO pin is enabled when
pulled low, and the data is clocked out of SDO on the rising
edge of SCLK.
SYNC
is
INPUT SHIFT REGISTER
For the AD5121/AD5141, the input shift register is 16 bits wide,
as shown in Figure 2. The 16-bit word consists of four control
bits, followed by four address bits and by eight data bits
If the AD5121 RDAC or EEPROM registers are read from or
written to the lowest data bit (Bit 0) is ignored.
Data is loaded MSB first (Bit 15). The four control bits determine
the function of the software command, as listed in Table 11 and
Table 16.
Rev. 0 | Page 20 of 32
Data Sheet
AD5121/AD5141
Daisy-Chain Connection
To prevent data from mislocking (for example, due to noise) the
part includes an internal counter, if the clock falling edges count
is not a multiple of 8, the part ignores the command. A valid
Daisy chaining minimizes the number of port pins required from
the controlling IC. As shown in Figure 39, the SDO pin of one
package must be tied to the SDI pin of the next package. The clock
period may need to be increased because the propagation delay
of the line between subsequent devices. When two AD5121/
AD5141 devices are daisy chained, 32 bits of data are required.
The first 16 bits assigned to U2, and the second 16 bits assigned
SYNC
clock count is 16, 24, or 32. The counter resets when
returns high.
SYNC
to U1, as shown in Figure 40. Keep the
pin low until all
SYNC
32 bits are clocked into their respective serial registers. The
pin is then pulled high to complete the operation. A typical
connection is shown in Figure 39.
V
V
LOGIC
LOGIC
AD5121/
AD5141
AD5121/
AD5141
R
P
2.2kΩ
R
P
2.2kΩ
SDI
SDO
U2
MOSI
SDI
U1
SDO
MICROCONTROLLER
MISO
SCLK
SS
SYNC
SCLK
SYNC
SCLK
Figure 39. Daisy-Chain Configuration
18
SCLK
1
2
16
17
32
SYNC
MOSI
DB15
DB0
DB15
DB15
DB0
INPUT WORD FOR U2
INPUT WORD FOR U1
INPUT WORD FOR U2
SDO_U1
DB0
DB15
DB0
UNDEFINED
Figure 40. Daisy-Chain Diagram
Rev. 0 | Page 21 of 32
AD5121/AD5141
Data Sheet
I2C SERIAL DATA INTERFACE
3. When all data bits have been read from or written to, a stop
condition is established. In write mode, the master pulls the
SDA line high during the tenth clock pulse to establish a stop
condition. In read mode, the master issues a no acknowledge
for the ninth clock pulse (that is, the SDA line remains high).
The master then brings the SDA line low before the tenth
clock pulse, and then high again during the tenth clock pulse
to establish a stop condition.
The AD5141 has 2-wire, I2C-compatible serial interface. These
devices can be connected to an I2C bus as a slave device, under the
control of a master device. See Figure 3 for a timing diagram of a
typical write sequence.
The AD5141 supports standard (100 kHz) and fast (400 kHz) data
transfer modes. Support is not provided for 10-bit addressing
and general call addressing.
I2C ADDRESS
The 2-wire serial bus protocol operates as follows:
The AD5141 has two different pin address options available, as
shown in Table 10.
1. The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address
Table 10. 24-Lead LFCSP Device Address Selection
ADDR0 Pin
ADDR1 Pin
7-Bit I2C Device Address
0100000
0100010
0100011
W
and an R/ bit. The slave device corresponding to the
VDD
VDD
VDD
VDD
No connect1
GND
transmitted address responds by pulling SDA low during
the ninth clock pulse (this is called the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its shift register.
VDD
No connect1
No connect1
No connect1
GND
GND
GND
0101000
0101010
0101011
0101100
0101110
0101111
No connect1
GND
W
If the R/ bit is set high, the master reads from the slave
VDD
No connect1
GND
W
device. However, if the R/ bit is set low, the master writes
to the slave device.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
1 Not available in bipolar mode (VSS < 0 V) or in low voltage mode (VLOGIC = 1.8 V).
Table 11. Simple Command Operation Truth Table
Control
Bits[DB15:DB12]
Address
Bits[DB11:DB8]1
Data Bits[DB7:DB0]1
Command
Number
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
1
0
0
0
0
0
0
0
1
X
0
X
0
X
0
X
0
X
X
X
X
X
X
X
X
NOP: do nothing
D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register
data to RDAC
2
3
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register
data to input register
X
X
X
X
X
X
X
D1 D0 Read back contents
D1
0
1
D0
1
1
Data
EEPROM
RDAC
9
0
0
1
1
1
1
0
1
1
1
1
0
1
1
1
0
X
X
X
0
X
X
X
0
0
0
X
0
0
0
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
X
Copy RDAC register to EEPROM
Copy EEPROM into RDAC
Software reset
10
14
15
D0 Software shutdown
D0
0
1
Condition
Normal mode
Shutdown mode
1 X = don’t care.
Rev. 0 | Page 22 of 32
Data Sheet
AD5121/AD5141
Low Wiper Resistance Feature
ADVANCED CONTROL MODES
The AD5121/AD5141 include two commands to reduce the wiper
resistance between the terminals when they achieve full scale or
zero scale. These extra positions are called bottom scale, BS, and
top scale, TS. The resistance between Terminal A and Terminal W
at top scale is specified as RTS. Similarly, the bottom scale resistance
between Terminal B and Terminal W is specified as RBS.
The AD5121/AD5141 digital potentiometers include a set of user
programming features to address the wide number of applications
for these universal adjustment devices (see Table 16 and Table 18).
Key programming features include the following:
•
•
•
•
•
•
•
•
Input register
Linear gain setting mode
Low wiper resistance feature
Linear increment and decrement instructions
6 dB increment and decrement instructions
Burst mode (I2C only)
The contents of the RDAC registers are unchanged by entering
in these positions. There are two ways to exit from top scale and
bottom scale: by using Command 12 or Command 13 (see
Table 16); or by loading new data in an RDAC register, which
includes increment/decrement operations and a shutdown
command.
Reset
Shutdown mode
Table 12 and Table 13 show the truth tables for the top scale
position and the bottom scale position, respectively, when linear
gain setting mode is enabled.
Input Register
The AD5121/AD5141 include one input register per RDAC
register. This register allows preloading of the value for the
associated RDAC register.
Table 12. Top Scale Truth Table
Linear Gain Setting Mode
Potentiometer Mode
This feature allows a synchronous and asynchronous update of
one or all the RDAC registers at the same time.
RAW
RAB
RWB
RAW
RWB
RAB
RTS
RAB
These registers can be written to using Command 2 and read back
from using Command 3 (see Table 16).
Table 13. Bottom Scale Truth Table
Linear Gain Setting Mode
Potentiometer Mode
The transfer from the input register to the RDAC register is
RAW
RWB
RAW
RWB
done asynchronously by the
pin or synchronously by
LRDAC
RTS
RBS
RAB
RBS
Command 8 (see Table 16).
Linear Increment and Decrement Instructions
If new data is loaded in an RDAC register, this RDAC register
automatically overwrites the associated input register.
The increment and decrement commands (Command 4 and
Command 5 in Table 16) are useful for linear step adjustment
applications. These commands simplify microcontroller software
coding by allowing the controller to send an increment or
decrement command to the device. The adjustment can be
individual or in a ganged potentiometer arrangement, where
all wiper positions are changed at the same time.
Linear Gain Setting Mode
The patented architecture of the AD5121/AD5141 allows the
independent control of each string resistor, RAW and RWB. To
enable this feature, use Command 16 (see Table 16) to set Bit D2
of the control register (see Table 18).
This mode of operation can control the potentiometer as two
independent rheostats connected at a single point, W terminal,
as opposed to potentiometer mode where each resistor is
For an increment command, executing Command 4 automatically
moves the wiper to the next resistance segment position. This
command can be executed in a single channel or multiple channels.
complementary, RAW = RAB − RWB
.
±± dB Increment and Decrement Instructions
This feature enables a second input and an RDAC register per
channel, as shown in Table 16; however, the actual RDAC contents
remain unchanged. The same operations are valid for
potentiometer and linear gain setting modes.
Two programming instructions produce logarithmic taper
increment or decrement of the wiper position control by
an individual potentiometer or by a ganged potentiometer
arrangement where all RDAC register positions are changed
simultaneously. The +6 dB increment is activated by Command 6,
and the −6 dB decrement is activated by Command 7 (see Table 16).
For example, starting with the zero-scale position and executing
Command 6 ten times moves the wiper in 6 dB steps to the full-
scale position. When the wiper position is near the maximum
setting, the last 6 dB increment instruction causes the wiper to go
to the full-scale position (see Table 14).
If the INDEP pin is pulled high, the device powers up in linear
gain setting mode and loads the values stored in the associated
memory locations for each channel (see Table 17). The INDEP pin
and D2 bit are connected internally to a logic OR gate, if any or
both are 1, the parts cannot operate in potentiometer mode.
Rev. 0 | Page 23 of 32
AD5121/AD5141
Data Sheet
Incrementing the wiper position by +6 dB essentially doubles
the RDAC register value, whereas decrementing the wiper
position by −6 dB halves the register content. Internally, the
AD5121/AD5141 use shift registers to shift the bits left and
right to achieve a 6 dB increment or decrement. These functions
are useful for various audio/video level adjustments, especially
for white LED brightness settings in which human visual responses
are more sensitive to large adjustments than to small adjustments.
Table 15. Truth Table for Shutdown Mode
Linear Gain Setting Mode Potentiometer Mode
A2 AW
WB
AW
WB
RBS
N/A1
0
1
N/A1
Open
N/A1
Open
N/A1
Open
1 N/A = not applicable.
EEPROM OR RDAC REGISTER PROTECTION
The EEPROM and RDAC registers can be protected by disabling
any update to these registers. This can be done by using software or
by using hardware. If these registers are protected by software,
set Bit D0 and/or Bit D1 (see Table 18), which protects the RDAC
and EEPROM registers independently.
Table 14. Detailed Left Shift and Right Shift Functions for
the 6 dB Step Increment and Decrement
Left Shift (+6 dB/Step)
Right Shift (−6 dB/Step)
0000 0000
1111 1111
0000 0001
0111 1111
If the registers are protected by hardware, pull the
pin low.
WP
pin is pulled low when the part is executing a command,
0000 0010
0011 1111
If the
WP
0000 0100
0001 1111
the protection is not enabled until the command is completed.
0000 1000
0000 1111
0001 0000
0010 0000
0100 0000
1000 0000
0000 0111
0000 0011
0000 0001
0000 0000
When RDAC is protected, the only operation allowed is to copy
the EEPROM into the RDAC register.
LOAD RDAC INPUT REGISTER (LRDAC)
software or hardware transfers data from the input
LRDAC
1111 1111
0000 0000
register to the RDAC register (and therefore updates the wiper
position). By default, the input register has the same value as the
RDAC register; therefore, only the input register that has been
updated using Command 2 is updated.
Burst Mode (I2C Only)
By enabling the burst mode, multiple data bytes can be sent to the
part consecutively. After the command byte, the part interprets the
consecutive bytes as data bytes for the first command.
Software
, Command 8, allows updating of a single RDAC
LRDAC
A new command can be sent by generating a repeat start or by a
stop and start condition.
register or all of the channels at once (see Table 16). This is a
synchronous update.
The burst mode is activated by setting Bit D3 of the control
register (see Table 18), and if a reset or power-down is performed,
it automatically resets.
The hardware
is completely asynchronous and copies
LRDAC
the content of all the input registers into the associated RDAC
registers. If a command is executed, to avoid data corruption,
any transition in the
Reset
pin is ignored by the part.
LRDAC
The AD5121/AD5141 can be reset through software by
executing Command 14 (see Table 16) or through hardware on
INDEP PIN
If the INDEP pin is pulled high at power-up, the part operates
in linear gain setting mode, loading each string resistor, RAW and
the low pulse of the
pin. The reset command loads the
RESET
RDAC register with the contents of the EEPROM and takes
approximately 30 µs. The EEPROM is preloaded to midscale at
the factory, and initial power-up is, accordingly, at midscale.
RWB, with the value stored into the EEPROM (see Table 17). If
the pin is pulled low, the part powers up in potentiometer mode.
The INDEP pin and the D2 bit are connected internally to a logic
OR gate, if any or both are 1, the part cannot operate in
potentiometer mode (see Table 18).
Tie
to V if the
pin is not used.
RESET
RESET
DD
Shutdown Mode
The AD5121/AD5141 can be placed in shutdown mode by
executing the software shutdown command, Command 15 (see
Table 16); and by setting the LSB (D0) to 1. This feature places
the RDAC in a special state. The contents of the RDAC register are
unchanged by entering shutdown mode. However, all commands
listed in Table 16 are supported while in shutdown mode. Execute
Command 15 (see Table 16) and set the LSB (D0) to 0 to exit
shutdown mode.
Rev. 0 | Page 24 of 32
Data Sheet
AD5121/AD5141
Table 16. Advance Commands Operation Truth Table
Control
Bits[DB15:DB12]
Address
Bits[DB11:DB8]1
Data Bits[DB7:DB0]1
Command
Number
C3
0
C2
0
C1
0
C0
0
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
1
X
0
X
X
0
X
X
X
X
X
X
X
X
X
NOP: do nothing
0
0
0
1
A2
A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to RDAC
2
3
0
0
0
0
1
1
0
1
0
A2
0
A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to input register
X
A2 A1 A0
X
X
X
X
X
X
D1 D0 Read back contents
D1
0
0
D0
0
1
Data
Input register
EEPROM
1
0
Control
register
1
1
RDAC
4
5
6
7
8
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
A3 A2
A3 A2
A3 A2
A3 A2
A3 A2
0
0
0
0
0
A0
A0
A0
A0
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
X
Linear RDAC increment
Linear RDAC decrement
+6 dB RDAC increment
−6 dB RDAC decrement
Copy input register to RDAC
(software LRDAC)
9
0
1
1
1
0
A2
0
A0
X
X
X
X
X
X
X
1
Copy RDAC register to
EEPROM
10
11
0
1
1
0
1
0
1
0
0
0
A2
A2
0
0
A0
X
X
X
X
X
X
X
0
Copy EEPROM into RDAC
A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to EEPROM
12
1
0
0
1
A3 A2
0
A0
1
X
X
X
X
X
X
D0 Top scale
D0 = 0; normal mode
D0 = 1; shutdown mode
D0 Bottom scale
13
1
0
0
1
A3 A2
0
A0
0
X
X
X
X
X
X
D0 = 1; enter
D0 = 0; exit
14
15
1
1
0
1
1
0
1
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Software reset
A3 A2
A0
D0 Software shutdown
D0 = 0; normal mode
D0 = 1; device placed in
shutdown mode
16
1
1
0
1
X
X
X
X
X
X
X
X
D3 D2 D1 D0 Copy serial register data to
control register
1 X = don’t care.
Table 17. Address Bits
Potentiometer Mode
Linear Gain Setting Mode
Stored RDAC
Memory
A3
1
0
A2
X1
0
A1
X1
0
A0
X1
0
Input Register
All channels
RDAC
RDAC Register
All channels
RDAC
Input Register
All channels
RWB
RDAC Register
All channels
RWB
Not applicable
RDAC/RWB
0
0
0
0
1
0
0
0
0
0
1
1
0
1
0
1
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
RAW
RAW
Not applicable
RAW
MSB tolerance
LSB tolerance
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
1 X = don’t care.
Rev. 0 | Page 25 of 32
AD5121/AD5141
Data Sheet
Table 18. Control Register Bit Descriptions
Bit Name
Description
D0
RDAC register write protect
0 = wiper position frozen to value in EEPROM memory
1 = allows update of wiper position through digital interface (default)
EEPROM program enable
D1
D2
D3
0 = EEPROM program disabled
1 = enables device for EEPROM program (default)
Linear setting mode/potentiometer mode
0 = potentiometer mode (default)
1 = linear gain setting mode
Burst mode (I2C only)
0 = disabled (default)
1 = enabled (no disable after stop or repeat start condition)
Rev. 0 | Page 26 of 32
Data Sheet
AD5121/AD5141
RDAC ARCHITECTURE
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—±8% Resistor Tolerance
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5121/AD5141 employ a
three-stage segmentation approach, as shown in Figure 41. The
AD5121/AD5141 wiper switch is designed with the transmission
gate CMOS topology and with the gate voltage derived from
The AD5121/AD5141 operate in rheostat mode when only two
terminals are used as a variable resistor. The unused terminal can
be floating, or it can be tied to Terminal W, as shown in Figure 42.
A
A
A
W
W
W
V
DD and VSS.
A
S
TS
B
B
B
Figure 42. Rheostat Mode Configuration
R
R
H
The nominal resistance between Terminal A and Terminal B,
RAB, is 10 kΩ or 100 kΩ, and has 128/256 tap points accessed by
the wiper terminal. The 7-bit/8-bit data in the RDAC latch is
decoded to select one of the 128/256 possible wiper settings. The
general equations for determining the digitally programmed
output resistance between Terminal W and Terminal B are
R
M
H
R
M
R
L
L
W
AD5121:
R
7-BIT/8-BIT
ADDRESS
DECODER
D
128
From 0x00 to 0x7F (1)
From 0x00 to 0xFF (2)
R
R
WB (D) =
×RAB + RW
×RAB + RW
M
R
H
AD5141:
R
M
D
256
R
H
RWB (D) =
S
BS
where:
B
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
R
R
AB is the end-to-end resistance.
W is the wiper resistance.
Figure 41. AD5121/AD5141 Simplified RDAC Circuit
Top Scale/Bottom Scale Architecture
In potentiometer mode, similar to the mechanical
potentiometer, the resistance of the RDAC between Terminal
W and Terminal A also produces a digitally controlled
complementary resistance, RWA. RWA also gives a maximum of 8%
absolute resistance error. RWA starts at the maximum resistance
value and decreases as the data loaded into the latch increases.
The general equations for this operation are
In addition, the AD5121/AD5141 include new positions to
reduce the resistance between terminals. These positions are
called bottom scale and top scale. At bottom scale, the typical
wiper resistance decreases from 130 Ω to 60 Ω (RAB = 100 kΩ).
At top scale, the resistance between Terminal A and Terminal W
is decreased by 1 LSB, and the total resistance is reduced to 60 Ω
(RAB = 100 kΩ).
AD5121:
128 − D
128
R
AW (D) =
×RAB + RW
From 0x00 to 0x7F (3)
From 0x00 to 0xFF (4)
AD5141:
256 − D
256
R
AW (D) =
×RAB + RW
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
R
R
AB is the end-to-end resistance.
W is the wiper resistance.
Rev. 0 | Page 27 of 32
AD5121/AD5141
Data Sheet
If the part is configured in linear gain setting mode, the resistance
between Terminal W and Terminal A is directly proportional
to the code loaded in the associate RDAC register. The general
equations for this operation are
That is, if the data readback from Address 0x02 is 00000010, and
the data readback from Address 0x03 is 10110000, the end-to-end
resistance can be calculated as follows.
For Memory Map Address 0x02, DB[7] = 0 = negative, and
DB[6:0] = 0000010 = 2.
AD5121:
D
128
For Memory Map Address 0x03, DB[7:0] = 10110000 = 176 × 2−8 =
0.6875, and therefore, tolerance = −2.6875%, and RAB = 9.731 kΩ.
From 0x00 to 0x7F (5)
From 0x00 to 0xFF (6)
R
AW (D) =
× RAB + RW
AD5141:
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
D
256
R
AW (D) =
× RAB + RW
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input voltage
at A to B, as shown in Figure 43.
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
V
A
A
RAB is the end-to-end resistance.
W
V
OUT
R
W is the wiper resistance.
B
V
In the bottom scale condition or top scale condition, a finite
total wiper resistance of 40 Ω is present. Regardless of which
setting the part is operating in, limit the current between
Terminal A to Terminal B, Terminal W to Terminal A, and
Terminal W to Terminal B, to the maximum continuous current
of 6 mA or to the pulse current specified in Table 7. Otherwise,
degradation or possible destruction of the internal switch
contact can occur.
B
Figure 43. Potentiometer Mode Configuration
Connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at VW with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
R
WB(D)
R
AW (D)
RAB
Calculate the Actual End-to-End Resistance
VW (D) =
×VA +
×VB
(7)
RAB
The resistance tolerance is stored in the internal memory during
factory testing. Therefore, the actual end-to-end resistance can
be calculated (which is valuable for calibration, tolerance matching,
and precision applications).
where:
R
R
WB(D) can be obtained from Equation 1 and Equation 2.
AW(D) can be obtained from Equation 3 and Equation 4.
The resistance tolerance (in percentage) is stored in fixed point
format, using a 16-bit sign magnitude binary. The sign bit
(0 = negative and 1 = positive) and the integer part are located
in Address 0x02, as shown in Table 19. Address 0x03 contains
the fractional part, as shown in Table 19.
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RAW and RWB, and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
Table 19. End-to-End Resistance Tolerance Bytes
Data Byte
Memory Map Address
DB7
Sign
2−1
DB6
26
2−2
DB5
25
2−3
DB4
24
2−4
DB3
23
2−5
DB2
22
2−6
DB1
21
2−7
DB0
20
2−8
0x02
0x03
Rev. 0 | Page 28 of 32
Data Sheet
AD5121/AD5141
TERMINAL VOLTAGE OPERATING RANGE
LAYOUT AND POWER SUPPLY BIASING
The AD5121/AD5141 are designed with internal ESD diodes
for protection. These diodes also set the voltage boundary of
the terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed VDD are
clamped by the forward-biased diode. There is no polarity
constraint between VA, VW, and VB, but they cannot be higher
than VDD or lower than VSS.
It is always a good practice to use a compact, minimum lead
length layout design. Ensure that the leads to the input are as
direct as possible with a minimum conductor length. Ground
paths should have low resistance and low inductance. It is also
good practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 µF to 10 µF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 45 illustrates the basic supply bypassing configuration
for the AD5121/AD5141.
V
DD
A
V
V
LOGIC
V
V
LOGIC
DD
DD
W
B
+
+
+
C3
C1
C5
0.1µF
C6
10µF
10µF
0.1µF
AD5121/
AD5141
C4
10µF
C2
0.1µF
V
V
DD
SS
V
SS
GND
Figure 44. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Figure 45. Power Supply Bypassing
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 44), it is
important to power up VDD first before applying any voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that VDD is powered unintentionally. The
ideal power-up sequence is VSS, VDD, VLOGIC, digital inputs, and
VA, VB, and VW. The order of powering VA, VB, VW, and digital
inputs is not important as long as they are powered after VSS,
V
DD, and VLOGIC. Regardless of the power-up sequence and the
ramp rates of the power supplies, once VLOGIC is powered, the
power-on preset activates, which restores EEPROM values to
the RDAC registers.
Rev. 0 | Page 29 of 32
AD5121/AD5141
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
4
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
8
5
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 46. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
RAB (kΩ) Resolution Interface Temperature Range Package Description Package Option Branding
AD5121BCPZ10-RL7
AD5121BCPZ100-RL7 100
AD5141BCPZ10-RL7 10
AD5141BCPZ100-RL7 100
EVAL-AD5141DBZ
10
128
128
256
256
SPI/I2C
SPI/I2C
SPI/I2C
SPI/I2C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
Evaluation Board
CP-16-22
CP-16-22
CP-16-22
CP-16-22
DHE
DHF
DHC
DHD
1 Z = RoHS Compliant Part
2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with both of the available resistor value options.
Rev. 0 | Page 30 of 32
Data Sheet
NOTES
AD5121/AD5141
Rev. 0 | Page 31 of 32
AD5121/AD5141
NOTES
Data Sheet
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10940-0-10/12(0)
Rev. 0 | Page 32 of 32
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