AD5122WBCPZ10-RL7 [ADI]
Dual Channel, 128-/256-Position, SPI, Nonvolatile Digital Potentiometer;
| 型号： | AD5122WBCPZ10-RL7 |
| 厂家： | 
ADI |
| 描述： | Dual Channel, 128-/256-Position, SPI, Nonvolatile Digital Potentiometer 转换器 电阻器 |
| 文件： | 总32页 (文件大小：751K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Channel, 128-/256-Position, SPI,
Nonvolatile Digital Potentiometer
Data Sheet
AD5122/AD5142
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
DD
LOGIC
INDEP
10 kΩ and 100 kΩ resistance options
Resistor tolerance: 8% maximum
Wiper current: 6 mA
Low temperature coefficient: 35 ppm/°C
Wide bandwidth: 3 MHz
POWER-ON
RESET
AD5122/
AD5142
RDAC1
A1
W1
B1
Fast start-up time <75 µs
Linear gain setting mode
Single- and dual-supply operation
Independent logic supply: 1.8 V to 5.5 V
Wide operating temperature: −40°C to +125°C
3 mm × 3 mm package option
INPUT
RESET
SCLK
REGISTER 1
SERIAL
INTERFACE
RDAC2
A2
W2
B2
SDI
7/8
INPUT
REGISTER 2
SYNC
SDO
EEPROM
MEMORY
Qualified for automotive applications
APPLICATIONS
GND
V
SS
Portable electronics level adjustment
LCD panel brightness and contrast controls
Programmable filters, delays, and time constants
Programmable power supplies
Figure 1.
The AD5122/AD5142 are available in a compact, 16-lead, 3 mm ×
3 mm LFCSP and a 16-lead TSSOP. The devices are guaranteed
to operate over the extended industrial temperature range of
−40°C to +125°C.
GENERAL DESCRIPTION
The AD5122/AD5142 potentiometers provide a nonvolatile
solution for 128-/256-position adjustment applications, offering
guaranteed low resistor tolerance errors of 8% and up to 6 mA
current density in the Ax, Bx, and Wx pins.
Table 1. Family Models
The low resistor tolerance and low nominal temperature coefficient
simplify open-loop applications as well as applications requiring
tolerance matching.
Model
Channel Position Interface Package
AD51231
AD5124
AD5124
AD51431
AD5144
AD5144
Quad
Quad
Quad
Quad
Quad
Quad
128
128
128
256
256
256
256
128
128
256
256
128
256
I2C
LFCSP
LFCSP
TSSOP
LFCSP
LFCSP
TSSOP
SPI/I2C
SPI
The linear gain setting mode allows independent programming
of the resistance between the digital potentiometer terminals
through the RAW and RWB string resistors, allowing accurate
resistor matching.
I2C
SPI/I2C
SPI
I2C
AD5144A Quad
AD5122 Dual
AD5122A Dual
AD5142 Dual
AD5142A Dual
TSSOP
The high bandwidth and low total harmonic distortion (THD)
ensure optimal performance for ac signals, making these devices
suitable for filter design.
SPI
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP
I2C
SPI
I2C
SPI/I2C
SPI/I2C
The low wiper resistance of only 40 Ω at the ends of the resistor
array allows pin to pin connection.
AD5121
AD5141
Single
Single
LFCSP
The wiper values can be set through an SPI-compatible digital
interface that also reads back the wiper register and EEPROM
contents.
1 Two potentiometers and two rheostats.
Rev. C
Document Feedback
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5122/AD5142
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
RDAC Register and EEPROM.................................................. 20
Input Shift Register .................................................................... 20
SPI Serial Data Interface............................................................ 20
Advanced Control Modes ......................................................... 23
EEPROM or RDAC Register Protection................................. 24
INDEP Pin................................................................................... 24
RDAC Architecture.................................................................... 27
Programming the Variable Resistor......................................... 27
Programming the Potentiometer Divider............................... 28
Terminal Voltage Operating Range ......................................... 28
Power-Up Sequence ................................................................... 28
Layout and Power Supply Biasing............................................ 28
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 30
Automotive Products................................................................. 30
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—AD5122 .......................................... 3
Electrical Characteristics—AD5142 .......................................... 6
Interface Timing Specifications.................................................. 9
Shift Register and Timing Diagrams ....................................... 10
Absolute Maximum Ratings.......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 14
Test Circuits..................................................................................... 19
Theory of Operation ...................................................................... 20
REVISION HISTORY
5/2017—Rev. B to Rev. C
Changes to RDAC Architecture Section ..................................... 27
Changes to Ordering Guide.......................................................... 30
Added Automotive Products Section .......................................... 30
Changes to Figure 6 and Table 8................................................... 12
Changes to Figure 16 and Figure 17............................................. 15
Changes to EEPROM or RDAC Register Protection Section........ 24
Updated Outline Dimensions....................................................... 29
Changes to Ordering Guide .......................................................... 30
2/2016—Rev. 0 to Rev. A
Changes to Features Section ............................................................1
Added Endnote, Table 2 ...................................................................5
Added Endnote, Table 3 ...................................................................8
Added Endnote, Table 4 ...................................................................9
Changes to Figure 3 Caption and Figure 4 Caption .................. 10
Changes to Table 6.......................................................................... 11
Changes to Figure 6........................................................................ 12
6/2016—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Logic Supply Current Parameter, Table 2 ................. 4
Changes to Logic Supply Current Parameter, Table 3 ................. 7
Changes to Figure 16...................................................................... 15
Added Figure 17; Renumbered Sequentially .............................. 15
Changes to Figure 18...................................................................... 16
Change to Linear Gain Setting Mode Section ............................ 23
10/2012—Revision 0: Initial Version
Rev. C | Page 2 of 32
Data Sheet
AD5122/AD5142
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5122
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless
otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution
Resistor Integral Nonlinearity2
N
R-INL
7
Bits
RAB = 10 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
RAB = 100 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
−1
−2.5
0.1
1
+1
+2.5
LSB
LSB
−0.5
−1
0.1
0.25 +1
+0.5
LSB
LSB
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance3
R-DNL
−0.5
−8
0.1
1
35
+0.5
+8
LSB
%
ppm/°C
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
Code = full scale
Code = zero scale
RAB = 10 kΩ
55
130
125
400
Ω
Ω
RAB = 100 kΩ
Bottom Scale or Top Scale
RBS or RTS
RAB = 10 kΩ
RAB = 100 kΩ
Code = 0xFF
40
60
0.2
80
230
+1
Ω
Ω
%
Nominal Resistance Match
RAB1/RAB2
−1
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4
INL
RAB = 10 kΩ
RAB = 100 kΩ
−0.5
−0.25
−0.25
0.1
0.1
0.1
+0.5
+0.25
+0.25
LSB
LSB
LSB
Differential Nonlinearity4
Full-Scale Error
DNL
VWFSE
RAB = 10 kΩ
RAB = 100 kΩ
−1.5
−0.5
−0.1
0.1
LSB
LSB
+0.5
Zero-Scale Error
VWZSE
RAB = 10 kΩ
RAB = 100 kΩ
(ΔVW/VW)/ΔT × 106 Code = half scale
1
0.25
5
1.5
0.5
LSB
LSB
ppm/°C
Voltage Divider Temperature
Coefficient3
Rev. C | Page 3 of 32
AD5122/AD5142
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ1
Max
Unit
RESISTOR TERMINALS
Maximum Continuous Current
IA, IB, and IW
RAB = 10 kΩ
RAB = 100 kΩ
−6
−1.5
VSS
+6
+1.5
VDD
mA
mA
V
Terminal Voltage Range5
Capacitance A, Capacitance B3
CA, CB
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
25
12
pF
pF
Capacitance W3
CW
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
VA = VW = VB
12
5
15
pF
pF
nA
Common-Mode Leakage Current3
−500
+500
DIGITAL INPUTS
Input Logic3
High
VINH
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
0.8 × VLOGIC
0.7 × VLOGIC
V
V
Low
VINL
VHYST
IIN
0.2 × VLOGIC
1
V
V
µA
pF
Input Hysteresis3
Input Current3
0.1 × VLOGIC
Input Capacitance3
DIGITAL OUTPUTS
Output High Voltage3
Output Low Voltage3
CIN
5
VOH
VOL
RPULL-UP = 2.2 kΩ to VLOGIC
ISINK = 3 mA
ISINK = 6 mA, VLOGIC > 2.3 V
VLOGIC
V
V
V
µA
pF
0.4
0.6
+1
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
−1
2
Single-Supply Power Range
Dual-Supply Power Range
Logic Supply Range
VSS = GND
2.3
2.25
1.8
5.5
V
V
V
V
2.75
VDD
VDD
Single supply, VSS = GND
Dual supply, VSS < GND
VIH = VLOGIC or VIL = GND
VDD = 5.5 V
2.25
Positive Supply Current
IDD
0.7
5.5
µA
nA
µA
mA
µA
µA
µW
dB
VDD = 2.3 V
400
−0.7
2
320
0.05
3.5
Negative Supply Current
EEPROM Store Current3, 6
EEPROM Read Current3, 7
Logic Supply Current
ISS
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
−5.5
IDD_EEPROM_STORE
IDD_EEPROM_READ
ILOGIC
PDISS
PSRR
1.4
Power Dissipation8
Power Supply Rejection Ratio
∆VDD/∆VSS = VDD 10%,
code = full scale
−66
−60
Rev. C | Page 4 of 32
Data Sheet
AD5122/AD5142
Parameter
Symbol
Test Conditions/Comments
Min
Typ1
Max
Unit
DYNAMIC CHARACTERISTICS9
Bandwidth
BW
−3 dB
RAB = 10 kΩ
RAB = 100 kΩ
3
0.43
MHz
MHz
Total Harmonic Distortion
Resistor Noise Density
VW Settling Time
THD
eN_WB
tS
VDD/VSS = 2.5 V, VA = 1 V rms,
VB = 0 V, f = 1 kHz
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C,
f = 10 kHz
RAB = 10 kΩ
−80
−90
dB
dB
7
20
nV/√Hz
nV/√Hz
RAB = 100 kΩ
VA = 5 V, VB = 0 V, from
zero scale to full scale,
0.5 LSB error band
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
2
µs
µs
12
10
25
−90
1
Crosstalk (CW1/CW2
)
CT
nV-sec
nV-sec
dB
Mcycles
kcycles
Years
Analog Crosstalk
Endurance10
CTA
TA = 25°C
100
Data Retention11, 12
50
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB
.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD/VSS
= 2.5 V, and VLOGIC = 2.5 V.
10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
12 50 years applies to an endurance of 1k cycles. An endurance of 100k cycles has an equivalent retention lifetime of 5 years.
Rev. C | Page 5 of 32
AD5122/AD5142
Data Sheet
ELECTRICAL CHARACTERISTICS—AD5142
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless
otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ1 Max
Unit
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution
N
R-INL
8
Bits
Resistor Integral Nonlinearity2
RAB = 10 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
RAB = 100 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
−2
−5
0.2
1.5
+2
+5
LSB
LSB
−1
−2
−0.5
−8
0.1
0.5
0.2
1
+1
+2
+0.5
+8
LSB
LSB
LSB
%
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance3
R-DNL
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
Code = full scale
Code = zero scale
RAB = 10 kΩ
35
ppm/°C
55
130
125
400
Ω
Ω
RAB = 100 kΩ
Bottom Scale or Top Scale
RBS or RTS
RAB = 10 kΩ
RAB = 100 kΩ
Code = 0xFF
40
60
0.2
80
230
+1
Ω
Ω
%
Nominal Resistance Match
RAB1/RAB2
−1
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4
INL
RAB = 10 kΩ
RAB = 100 kΩ
−1
−0.5
−0.5
0.2
0.1
0.2
+1
+0.5
+0.5
LSB
LSB
LSB
Differential Nonlinearity4
Full-Scale Error
DNL
VWFSE
RAB = 10 kΩ
RAB = 100 kΩ
−2.5
−1
−0.1
0.2
LSB
LSB
+1
Zero-Scale Error
VWZSE
RAB = 10 kΩ
RAB = 100 kΩ
(ΔVW/VW)/ΔT × 106 Code = half scale
1.2
0.5
5
3
1
LSB
LSB
ppm/°C
Voltage Divider Temperature
Coefficient3
Rev. C | Page 6 of 32
Data Sheet
AD5122/AD5142
Parameter
Symbol
Test Conditions/Comments
Min
Typ1 Max
Unit
RESISTOR TERMINALS
Maximum Continuous Current
IA, IB, and IW
RAB = 10 kΩ
RAB = 100 kΩ
−6
−1.5
VSS
+6
+1.5
VDD
mA
mA
V
Terminal Voltage Range5
Capacitance A, Capacitance B3
CA, CB
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
25
12
pF
pF
Capacitance W3
CW
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
VA = VW = VB
12
5
15
pF
pF
nA
Common-Mode Leakage Current3
−500
+500
DIGITAL INPUTS
Input Logic3
High
VINH
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
0.8 × VLOGIC
0.7 × VLOGIC
V
V
Low
VINL
VHYST
IIN
0.2 × VLOGIC
1
V
V
µA
pF
Input Hysteresis3
Input Current3
0.1 × VLOGIC
Input Capacitance3
DIGITAL OUTPUTS
Output High Voltage3
Output Low Voltage3
CIN
5
VOH
VOL
RPULL-UP = 2.2 kΩ to VLOGIC
ISINK = 3 mA
ISINK = 6 mA, VLOGIC > 2.3 V
VLOGIC
V
V
V
µA
pF
0.4
0.6
+1
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
−1
2
Single-Supply Power Range
Dual-Supply Power Range
Logic Supply Range
VSS = GND
2.3
2.25
1.8
5.5
V
V
V
V
2.75
VDD
VDD
Single supply, VSS = GND
Dual supply, VSS < GND
VIH = VLOGIC or VIL = GND
VDD = 5.5 V
2.25
Positive Supply Current
IDD
0.7
5.5
µA
nA
µA
mA
µA
µA
µW
dB
VDD = 2.3 V
400
−0.7
2
320
0.05
3.5
Negative Supply Current
EEPROM Store Current3, 6
EEPROM Read Current3, 7
Logic Supply Current
ISS
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
−5.5
IDD_EEPROM_STORE
IDD_EEPROM_READ
ILOGIC
PDISS
PSRR
1.4
Power Dissipation8
Power Supply Rejection Ratio
∆VDD/∆VSS = VDD 10%,
code = full scale
−66
−60
Rev. C | Page 7 of 32
AD5122/AD5142
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ1 Max
Unit
DYNAMIC CHARACTERISTICS9
Bandwidth
BW
−3 dB
RAB = 10 kΩ
RAB = 100 kΩ
3
0.43
MHz
MHz
Total Harmonic Distortion
Resistor Noise Density
VW Settling Time
THD
eN_WB
tS
VDD/VSS = 2.5 V, VA = 1 V rms,
VB = 0 V, f = 1 kHz
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C,
f = 10 kHz
RAB = 10 kΩ
−80
−90
dB
dB
7
20
nV/√Hz
nV/√Hz
RAB = 100 kΩ
VA = 5 V, VB = 0 V, from
zero scale to full scale,
0.5 LSB error band
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
2
µs
µs
12
10
25
−90
1
Crosstalk (CW1/CW2
)
CT
nV-sec
nV-sec
dB
Mcycles
kcycles
Years
Analog Crosstalk
Endurance10
CTA
TA = 25°C
100
Data Retention11, 12
50
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB
.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD/VSS
= 2.5 V, and VLOGIC = 2.5 V.
10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
12 50 years applies to an endurance of 1k cycles. An endurance of 100k cycles has an equivalent retention lifetime of 5 years.
Rev. C | Page 8 of 32
Data Sheet
AD5122/AD5142
INTERFACE TIMING SPECIFICATIONS
VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. SPI Interface1
Parameter2
Test Conditions/Comments
Min
20
30
10
15
10
15
10
5
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
t1
VLOGIC > 1.8 V
VLOGIC = 1.8 V
VLOGIC > 1.8 V
VLOGIC = 1.8 V
VLOGIC > 1.8 V
VLOGIC = 1.8 V
SCLK cycle time
t2
t3
SCLK high time
SCLK low time
t4
t5
t6
t7
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to next SCLK fall ignored
Minimum SYNC high time
5
10
20
3
t8
4
t9
50
SCLK rising edge to SDO valid
SYNC rising edge to SDO pin disable
t10
500
1 Refer to the AN-1248 for additional information about the serial peripheral interface.
2 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 Refer to t
t
for memory commands operations (see Table 5).
EEPROM_PROGRAM and
EEPROM_READBACK
4 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF.
Table 5. Control Pins
Parameter
Min
Typ
Max
10
Unit
µs
Description
t1
0.1
RESET low time
1
tEEPROM_PROGRAM
15
7
50
30
75
ms
µs
µs
Memory program time (not shown in Figure 5)
Memory readback time (not shown in Figure 5)
Start-up time (not shown in Figure 5)
Reset EEPROM restore time (not shown in Figure 5)
tEEPROM_READBACK
2
tPOWER_UP
tRESET
30
µs
1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
2 Maximum time after VDD − VSS is equal to 2.3 V.
Rev. C | Page 9 of 32
AD5122/AD5142
Data Sheet
SHIFT REGISTER AND TIMING DIAGRAMS
DB15 (MSB)
DB8
A0
DB7
D7
DB0 (LSB)
D0
D1
A1
D6
D5
D4
D3
C3
C2
C1
C0
A3
A2
D2
DATA BITS
CONTROL BITS
ADDRESS BITS
Figure 2. Input Shift Register Contents
t4
t1
t2
t7
SCLK
SYNC
t3
t8
t5
t6
SDI
C3
C2
C1
C0
D7
D6
D5
D2
D1
D0
t9
t10
SDO
C3*
C2*
C1*
C0*
D7*
D6*
D5*
D2*
D1*
D0*
*PREVIOUS COMMAND RECEIVED.
Figure 3. SPI Serial Interface Timing Diagram, Clock Polarity (CPOL) = 0, Clock Phase (CPHA) = 1
t1
t2
t7
t4
SCLK
SYNC
t3
t8
t5
t6
SDI
C3
C2
C1
C0
D7
D6
D5
D2
D1
D0
t9
t10
SDO
C3*
C2*
C1*
C0*
D7*
D6*
D5*
D2*
D1*
D0*
*PREVIOUS COMMAND RECEIVED.
Figure 4. SPI Serial Interface Timing Diagram, Clock Polarity (CPOL) = 1, Clock Phase (CPHA) = 0
SCLK
SYNC
t1
RESET
Figure 5. Control Pins Timing Diagram
Rev. C | Page 10 of 32
Data Sheet
AD5122/AD5142
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 6.
Parameter
VDD to GND
VSS to GND
VDD to VSS
Rating
−0.3 V to +7.0 V
+0.3 V to −7.0 V
7 V
VLOGIC to GND
−0.3 V to VDD + 0.3 V or
+7.0 V (whichever is less)
VSS − 0.3 V, VDD + 0.3 V or
+7.0 V (whichever is less)
THERMAL RESISTANCE
VA, VW, VB to GND
θJA is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
IA, IW, IB
Pulsed1
Frequency > 10 kHz
RAW = 10 kΩ
RAW = 100 kΩ
Frequency ≤ 10 kHz
RAW = 10 kΩ
Table 7. Thermal Resistance
Package Type
16-Lead LFCSP
16-Lead TSSOP
θJA
89.51
150.41
θJC
3
27.6
Unit
°C/W
°C/W
6 mA/d2
1.5 mA/d2
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
6 mA/√d2
1.5 mA/√d2
−0.3 V to VLOGIC + 0.3 V or
+7 V (whichever is less)
−40°C to +125°C
150°C
RAW = 100 kΩ
Digital Inputs
ESD CAUTION
3
Operating Temperature Range, TA
Maximum Junction Temperature,
TJ Maximum
Storage Temperature Range
Reflow Soldering
−65°C to +150°C
Peak Temperature
260°C
Time at Peak Temperature
Package Power Dissipation
FICDM
20 sec to 40 sec
(TJ max − TA)/θJA
1.5 kV
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 d = pulse duty factor.
3 Includes programming of EEPROM memory.
Rev. C | Page 11 of 32
AD5122/AD5142
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
GND 1
A1 2
SDI
12
11
10
9
AD5122/
AD5142
TOP VIEW
(Not to Scale)
SCLK
V
W1 3
LOGIC
V
4
B1
DD
NOTES
1.ꢀEXPOSED PAD. CONNECT THE EXPOSED PAD TO THE
POTENTIAL OF THE V PIN, OR, ALTERNATIVELY, LEAVE
SS
IT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED
THAT THE PAD BE THERMALLY CONNECTED TO A COPPER
PLANE FOR ENHANCED THERMAL PERFORMANCE.
Figure 6. 16-Lead LFCSP Pin Configuration
Table 8. 16-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
Ground Pin, Logic Ground Reference.
Terminal A of RDAC1. VSS ≤ VA ≤ VDD
Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD
Terminal B of RDAC1. VSS ≤ VB ≤ VDD
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Terminal A of RDAC2. VSS ≤ VA ≤ VDD
Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD
Terminal B of RDAC2. VSS ≤ VB ≤ VDD
1
2
GND
A1
.
3
W1
.
4
B1
.
5
VSS
6
A2
.
7
W2
.
8
B2
.
9
VDD
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Serial Clock Line. Data is clocked in at the logic low transition.
10
11
12
13
14
15
VLOGIC
SCLK
SDI
SDO
SYNC
INDEP
Serial Data Input.
Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor.
Synchronization Input, Active Low. When SYNC returns high, data is loaded into the input shift register.
Linear Gain Setting Mode at Power-Up. Each string resistor is loaded independently from the associated
memory location. If INDEP is enabled, it cannot be disabled by software.
16
RESET
EPAD
Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is
not used, tie RESET to VLOGIC
.
Exposed Pad. Connect this exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically
unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced
thermal performance.
Rev. C | Page 12 of 32
Data Sheet
AD5122/AD5142
1
2
3
4
5
6
7
8
INDEP
16
15
14
13
12
11
10
9
SYNC
SDO
SDI
RESET
GND
A1
AD5122/
AD5142
TOP VIEW
(Not to Scale)
SCLK
W1
B1
V
LOGIC
V
DD
V
B2
SS
A2
W2
Figure 7. 16-Lead TSSOP, SPI Interface Pin Configuration
Table 9. 16-Lead TSSOP, SPI Interface Pin Function Descriptions
Pin No. Mnemonic Description
1
INDEP
Linear Gain Setting Mode at Power-Up. Each string resistor is loaded independently from the associated
memory location. If INDEP is enabled, it cannot be disabled by software.
2
RESET
Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is
not used, tie RESET to VLOGIC
Ground Pin, Logic Ground Reference.
Terminal A of RDAC1. VSS ≤ VA ≤ VDD
Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD
Terminal B of RDAC1. VSS ≤ VB ≤ VDD
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Terminal A of RDAC2. VSS ≤ VA ≤ VDD
Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD
Terminal B of RDAC2. VSS ≤ VB ≤ VDD
.
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
A1
W1
B1
VSS
A2
W2
B2
VDD
VLOGIC
SCLK
SDI
SDO
SYNC
.
.
.
.
.
.
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Serial Clock Line. Data is clocked in at the logic low transition.
Serial Data Input.
Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor.
Synchronization Input, Active Low. When SYNC returns high, data is loaded into the input shift register.
Rev. C | Page 13 of 32
AD5122/AD5142
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.2
0.1
10kΩ, +125°C
10kΩ, +25°C
0.4
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
0.3
0
100kΩ, –40°C
0.2
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
0
100
200
0
100
200
CODE (Decimal)
CODE (Decimal)
Figure 8. R-INL vs. Code (AD5142)
Figure 11. R-DNL vs. Code (AD5142)
0.10
0.05
0.20
0.15
0.10
0
0.05
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
0
–0.05
–0.10
–0.15
–0.20
–0.25
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
0
50
100
0
50
100
CODE (Decimal)
CODE (Decimal)
Figure 12. R-DNL vs. Code (AD5122)
Figure 9. R-INL vs. Code (AD5122)
0.10
0.05
0.3
0.2
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
0
0.1
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
0
–0.1
–0.2
–0.3
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
0
100
200
0
100
200
CODE (Decimal)
CODE (Decimal)
Figure 13. DNL vs. Code (AD5142)
Figure 10. INL vs. Code (AD5142)
Rev. C | Page 14 of 32
Data Sheet
AD5122/AD5142
0.15
0.10
0.05
0
1000
900
800
700
600
500
400
300
200
100
0
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
V
V
= V
LOGIC
= GND
V
V
V
= 2.3V
= 3.3V
= 5.5V
DD
SS
LOGIC
LOGIC
LOGIC
–0.05
–0.10
–0.15
0
50
100
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
CODE (Decimal)
Figure 17. ILOGIC vs. Temperature
Figure 14. INL vs. Code (AD5122)
0.06
0.04
450
400
350
300
250
200
150
100
50
100kΩ
10kΩ
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
0
–50
AD5142
AD5122
0
0
50
25
100
50
150
75
200
100
255
127
0
50
100
CODE (Decimal)
CODE (Decimal)
Figure 15. Potentiometer Mode Temperature Coefficient ((ΔVW/VW)/ΔT × 106)
vs. Code
Figure 18. DNL vs. Code (AD5122)
450
800
10kΩ
V
V
= V
LOGIC
= GND
DD
SS
100kΩ
400
350
300
250
200
150
100
50
700
600
500
400
300
200
100
0
V
V
V
= 2.3V
= 3.3V
= 5.5V
DD
DD
DD
0
–50
AD5142
AD5122
0
0
50
25
100
50
150
75
200
100
255
127
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
CODE (Decimal)
Figure 19. Rheostat Mode Temperature Coefficient ((ΔRWB/RWB)/ΔT × 106)
vs. Code
Figure 16. IDD vs. Temperature
Rev. C | Page 15 of 32
AD5122/AD5142
Data Sheet
20
0
1.2
1.0
0.8
0.6
0.4
0.2
0
V
V
V
V
V
= 1.8V
= 2.3V
= 3.3V
= 5V
V
R
/V = ±2.5V
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
DD SS
= 10kΩ
AB
= 5.5V
–20
–40
–60
–80
–100
QUARTER SCALE
MIDSCALE
FULL-SCALE
0
1
2
3
4
5
10
100
1k
10k
100k
1M
10M
INPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 20. ILOGIC Current vs. Digital Input Voltage
Figure 23. Normalized Phase Flatness vs. Frequency, RAB = 10 kΩ
0
–10
–20
–30
–40
–50
–60
10
0x80 (0x40)
0
0x80 (0x40)
0x40 (0x20)
0x20 (0x10)
0x40 (0x20)
–10
0x20 (0x10)
–20
–30
–40
–50
–60
–70
–80
–90
0x10 (0x08)
0x8 (0x04)
0x10 (0x08)
0x8 (0x04)
0x4 (0x02)
0x4 (0x02)
0x2 (0x01)
0x1 (0x00)
0x2 (0x01)
0x1 (0x00)
0x00
0x00
AD5142 (AD5122)
AD5142 (AD5122)
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21. 10 kΩ Gain vs. Frequency vs. Code
Figure 24. 100 kΩ Gain vs. Frequency vs. Code
–40
–50
–60
–70
–80
–90
–100
0
10kΩ
100kΩ
10kΩ
V
/V = ±2.5V
DD SS
= 1V rms
= GND
100kΩ
V
V
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
B
CODE = HALF SCALE
NOISE FILTER = 22kHz
V
f
/V = ±2.5V
DD SS
= 1kHz
CODE = HALF SCALE
NOISE FILTER = 22kHz
IN
20
200
2k
FREQUENCY (Hz)
20k
200k
0.001
0.01
0.1
1
VOLTAGE (V rms)
Figure 22. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency
Figure 25. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude
Rev. C | Page 16 of 32
Data Sheet
AD5122/AD5142
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10
0x80 TO 0x7F 100kΩ
0x80 TO 0x7F 10kΩ
0
–10
–20
–30
–40
–50
–60
–70
QUARTER SCALE
–80
V
R
/V = ±2.5V
MIDSCALE
DD SS
= 100kΩ
FULL-SCALE
AB
–0.1
–90
10
0
5
10
15
100
1k
10k
100k
1M
TIME (µs)
FREQUENCY (Hz)
Figure 29. Maximum Transition Glitch
Figure 26. Normalized Phase Flatness vs. Frequency, RAB = 100 kΩ
0.0025
0.0020
0.0015
0.0010
0.0005
0
1.2
600
100kΩ, V
100kΩ, V
100kΩ, V
100kΩ, V
100kΩ, V
100kΩ, V
= 2.3V
= 2.7V
= 3V
DD
DD
DD
DD
DD
DD
1.0
0.8
0.6
0.4
0.2
0
= 3.6V
= 5V
500
400
300
200
100
0
= 5.5V
10kΩ, V
10kΩ, V
10kΩ, V
10kΩ, V
10kΩ, V
10kΩ, V
= 2.3V
= 2.7V
= 3V
DD
DD
DD
DD
DD
DD
= 3.6V
= 5V
= 5.5V
–600 –500 –400 –300 –200 –100
0
100 200 300 400 500 600
0
1
2
3
4
5
RESISTOR DRIFT (ppm)
VOLTAGE (V)
Figure 30. Resistor Lifetime Drift
Figure 27. Incremental Wiper On Resistance vs. Positive Power Supply (VDD
)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
10
10kΩ, RDAC1
100kΩ, RDAC1
V
V
= 5V ±10% AC
DD
SS
10kΩ + 0pF
= GND, V = 4V, V = GND
A
B
10kΩ + 75pF
9
CODE = MIDSCALE
10kΩ + 150pF
10kΩ + 250pF
8
100kΩ + 0pF
100kΩ + 75pF
100kΩ + 150pF
100kΩ + 250pF
7
6
5
4
3
2
1
0
10
100
1k
10k
100k
1M
10M
AD5142
120
60 AD5122
0
0
20
10
40
20
60
30
80
40
100
50
FREQUENCY (Hz)
CODE (Decimal)
Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 28. Maximum Bandwidth vs. Code vs. Net Capacitance
Rev. C | Page 17 of 32
AD5122/AD5142
Data Sheet
0.020
0.015
0.010
0.005
0
7
6
5
4
3
2
1
0
10kΩ
100kΩ
–0.005
–0.010
–0.015
–0.020
AD5142
250
0
500
1000
1500
2000
0
0
50
25
100
50
150
75
200
100
AD5122
125
TIME (ns)
CODE (Decimal)
Figure 32. Digital Feedthrough
Figure 34. Theoretical Maximum Current vs. Code
0
–20
10kΩ
100kΩ
SHUTDOWN MODE ENABLED
–40
–60
–80
–100
–120
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 33. Shutdown Isolation vs. Frequency
Rev. C | Page 18 of 32
Data Sheet
AD5122/AD5142
TEST CIRCUITS
Figure 35 to Figure 39 define the test conditions used in the Specifications section.
NC
DUT
A
V
I
A
W
V+ = V ±10%
DD
W
∆V
MS
V
A
B
PSRR (dB) = 20 LOG
DD
)
(
∆V
B
W
DD
V+
~
V
∆V
%
MS
MS
PSS (%/%) =
V
MS
∆V
%
DD
NC = NO CONNECT
Figure 38. Power Supply Sensitivity and
Power Supply Rejection Ratio (PSS, PSRR)
Figure 35. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
0.1V
R
=
SW
I
DUT
B
SW
CODE = 0x00
W
+
–
DUT
V+ = V
DD
1LSB = V+/2
0.1V
I
SW
N
A
W
V+
V
SS
TO V
DD
B
A = NC
V
MS
Figure 36. Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 39. Incremental On Resistance
NC
DUT
A
W
I
= V /R
W DD NOMINAL
V
W
B
V
R
= V
/I
MS1
W
MS1 W
NC = NO CONNECT
Figure 37. Wiper Resistance
Rev. C | Page 19 of 32
AD5122/AD5142
Data Sheet
THEORY OF OPERATION
The AD5122/AD5142 digital programmable potentiometers are
designed to operate as true variable resistors for analog signals
within the terminal voltage range of VSS < VTERM < VDD. The resistor
wiper position is determined by the RDAC register contents. The
RDAC register acts as a scratchpad register that allows unlimited
changes of resistance settings. A secondary register (the input
register) can preload the RDAC register data.
SPI SERIAL DATA INTERFACE
The AD5122/AD5142 contain a 4-wire, SPI-compatible digital
SYNC
interface (SDI,
begins by bringing the
, SDO, and SCLK). The write sequence
SYNC SYNC
line low. The
pin must be
held low until the complete data-word is loaded from the SDI
pin. Data is loaded in at the SCLK falling edge transition, as
shown in Figure 3 and Figure 4. When
SYNC
returns high, the
The RDAC register can be programmed with any position setting
using the SPI interface (depending on the model). When a
desirable wiper position is found, this value can be stored in the
EEPROM memory. Thereafter, the wiper position is always
restored to that position for subsequent power-ups. The storing
of EEPROM data takes approximately 15 ms; during this time,
the device is locked and does not acknowledge any new command,
preventing any changes from taking place.
serial data-word is decoded according to the instructions in
Table 16.
To minimize power consumption in the digital input buffers
when the device is enabled, operate all serial interface pins close
to the VLOGIC supply rails.
SYNC
Interruption
In a standalone write sequence for the AD5122/AD5142,
SYNC
the
instruction is decoded when
SYNC
line is kept low for 16 falling edges of SCLK, and the
RDAC REGISTER AND EEPROM
SYNC
is pulled high. However, if
line is kept low for less than 16 falling edges of SCLK,
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with 0x80 (AD5142, 256 taps), the wiper is connected to
half scale of the variable resistor. The RDAC register is a standard
logic register; there is no restriction on the number of changes
allowed.
the
the input shift register content is ignored, and the write sequence is
considered invalid.
SDO Pin
The serial data output pin (SDO) serves two purposes: to read
back the contents of the control, EEPROM, RDAC, and input
registers using Command 3 (see Table 10 and Table 16), and to
connect the AD5122/AD5142 to daisy-chain mode.
It is possible to both write to and read from the RDAC register
using the digital interface (see Table 10).
The contents of the RDAC register can be stored to the EEPROM
using Command 9 (see Table 16). Thereafter, the RDAC register
always sets at that position for any future on-off-on power
supply sequence. It is possible to read back data saved into the
EEPROM with Command 3 (see Table 10).
The SDO pin contains an internal open-drain output that needs an
external pull-up resistor. The SDO pin is enabled when
pulled low, and the data is clocked out of SDO on the rising
edge of SCLK, as shown in Figure 3 and Figure 4.
SYNC
is
Alternatively, the EEPROM can be written to independently
using Command 11 (see Table 16).
INPUT SHIFT REGISTER
For the AD5122/AD5142, the input shift register is 16 bits wide,
as shown in Figure 2. The 16-bit word consists of four control
bits, followed by four address bits and by eight data bits.
If the AD5122 RDAC or EEPROM registers are read from or
written to, the lowest data bit (Bit 0) is ignored.
Data is loaded MSB first (Bit 15). The four control bits determine
the function of the software command as listed in Table 10 and
Table 16.
Rev. C | Page 20 of 32
Data Sheet
AD5122/AD5142
Daisy-Chain Connection
To prevent data from mislocking (for example, due to noise) the
device includes an internal counter, if the clock falling edges
count is not a multiple of 8, the device ignores the command. A
valid clock count is 16, 24, or 32. The counter resets
Daisy chaining minimizes the number of port pins required from
the controlling IC. As shown in Figure 40, the SDO pin of one
package must be tied to the SDI pin of the next package. The clock
period can be increased because of the propagation delay of the
line between subsequent devices. When two AD5122/AD5142
devices are daisy chained, 32 bits of data are required. The first
16 bits assigned to U2, and the second 16 bits assigned to U1, as
SYNC
when
returns high.
SYNC
shown in Figure 41. Keep the
pin low until all 32 bits are
SYNC
clocked into their respective serial registers. The
pin is
then pulled high to complete the operation. A typical connection is
shown in Figure 40.
V
V
LOGIC
LOGIC
AD5122/
AD5142
AD5122/
AD5142
R
P
2.2kΩ
R
P
2.2kΩ
SDI
SDO
U2
MOSI
SDI
U1
SDO
MICROCONTROLLER
MISO
SCLK
SS
SYNC
SCLK
SYNC
SCLK
Figure 40. Daisy-Chain Configuration
18
SCLK
1
2
16
17
32
SYNC
MOSI
DB15
DB0
DB15
DB15
DB0
INPUT WORD FOR U2
INPUT WORD FOR U1
INPUT WORD FOR U2
SDO_U1
DB0
DB15
DB0
UNDEFINED
Figure 41. Daisy-Chain Diagram
Rev. C | Page 21 of 32
AD5122/AD5142
Data Sheet
Table 10. Reduced Commands Operation Truth Table
Control
Bits[DB15:DB12]
Address
Bits[DB11:DB8]1
Data Bits[DB7:DB0]1
Command
Number
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
1
0
0
0
0
0
0
0
1
X
0
X
0
X
0
X
X
X
X
X
X
X
X
X
NOP: do nothing.
A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register
data to RDAC
2
3
0
0
0
0
1
1
0
1
0
0
0
0
A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register
data to input register
X
A1 A0
X
X
X
X
X
X
D1 D0 Read back contents
D1
0
1
D0
1
1
Data
EEPROM
RDAC
9
0
0
1
1
1
1
0
1
1
1
1
0
1
1
1
0
0
0
0
X
0
0
0
X
0
A0
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
X
Copy RDAC register to EEPROM
Copy EEPROM into RDAC
Software reset
10
14
15
0
X
A3
A0
D0 Software shutdown
D0
0
1
Condition
Normal mode
Shutdown mode
1X means don’t care.
Table 11. Reduced Address Bits Table
A3
A2
X1
0
A1
X1
0
A0
X1
0
Channel
Stored Channel Memory
Not applicable
RDAC1
1
0
All channels
RDAC1
0
0
0
0
0
1
1
0
RDAC2
Not applicable
Not applicable
RDAC2
1X means don’t care.
Rev. C | Page 22 of 32
Data Sheet
AD5122/AD5142
Low Wiper Resistance Feature
ADVANCED CONTROL MODES
The AD5122/AD5142 include two commands to reduce the wiper
resistance between the terminals when the devices achieve full scale
or zero scale. These extra positions are called bottom scale, BS, and
top scale, TS. The resistance between Terminal A and Terminal W
at top scale is specified as RTS. Similarly, the bottom scale resistance
between Terminal B and Terminal W is specified as RBS.
The AD5122/AD5142 digital potentiometers include a set of user
programming features to address the wide number of applications
for these universal adjustment devices (see Table 16 and Table 18).
Key programming features include the following:
•
•
•
•
•
•
•
Input register
Linear gain setting mode
Low wiper resistance feature
Lineal increment and decrement instructions
6 dB increment and decrement instructions
Reset
The contents of the RDAC registers are unchanged by entering
in these positions. There are three ways to exit from top scale
and bottom scale: by using Command 12 or Command 13 (see
Table 16); by loading new data in an RDAC register, which
includes increment/decrement operations; or by entering
shutdown mode, Command 15 (see Table 16).
Shutdown mode
Table 12 and Table 13 show the truth tables for the top scale
position and the bottom scale position, respectively, when the
potentiometer or linear gain setting mode is enabled.
Input Register
The AD5122/AD5142 include one input register per RDAC
register. These registers allow preloading of the value for the
associated RDAC register. These registers can be written to using
Command 2 and read back from using Command 3 (see Table 16).
Table 12. Top Scale Truth Table
Linear Gain Setting Mode
Potentiometer Mode
This feature allows a synchronous update of one or all the
RDAC registers at the same time.
RAW
RAB
RWB
RAW
RWB
RAB
RTS
RAB
The transfer from the input register to the RDAC register is
done synchronously by Command 8 (see Table 16).
Table 13. Bottom Scale Truth Table
Linear Gain Setting Mode
Potentiometer Mode
If new data is loaded into an RDAC register, this RDAC register
automatically overwrites the associated input register.
RAW
RWB
RAW
RWB
RTS
RBS
RAB
RBS
Linear Gain Setting Mode
The proprietary architecture of the AD5122/AD5142 allows the
independent control of each string resistor, RAW and RWB. To
enable this feature, use Command 16 (see Table 16) to set Bit D2
of the control register (see Table 18).
Linear Increment and Decrement Instructions
The increment and decrement commands (Command 4 and
Command 5 in Table 16) are useful for linear step adjustment
applications. These commands simplify microcontroller software
coding by allowing the controller to send an increment or
decrement command to the device. The adjustment can be
individual or in a ganged potentiometer arrangement, where
all wiper positions are changed at the same time.
This mode of operation can control the potentiometer as two
independent rheostats connected at a single point, W terminal,
as opposed to potentiometer mode where each resistor is
complementary, RAW = RAB − RWB
.
This feature enables a second input and an RDAC register per
channel, as shown in Table 17; however, the actual RDAC contents
remain unchanged. The same operations are valid for
For an increment command, executing Command 4 automatically
moves the wiper to the next RDAC position. This command
can be executed in a single channel or multiple channels.
potentiometer mode and linear gain setting mode.
If the INDEP pin is pulled high, the device powers up in linear
gain setting mode and loads the values stored in the associated
memory locations for each channel (see Table 17). The INDEP pin
and D2 bit are connected internally to a logic or gate, if any or
both are 1, the devices cannot operate in potentiometer mode.
Rev. C | Page 23 of 32
AD5122/AD5142
Data Sheet
±± dB Increment and Decrement Instructions
Shutdown Mode
Two programming instructions produce logarithmic taper
increment or decrement of the wiper position control by
an individual potentiometer or by a ganged potentiometer
arrangement where all RDAC register positions are changed
simultaneously. The +6 dB increment is activated by Command 6,
and the −6 dB decrement is activated by Command 7 (see Table 16).
For example, starting with the zero-scale position and executing
Command 6 ten times moves the wiper in 6 dB steps to the full-
scale position. When the wiper position is near the maximum setting,
the last 6 dB increment instruction causes the wiper to go to the
full-scale position (see Table 14).
The AD5122/AD5142 can be placed in shutdown mode by
executing the software shutdown command, Command 15 (see
Table 16); and by setting the LSB (D0) to 1. This feature places
the RDAC in a special state. The contents of the RDAC register are
unchanged by entering shutdown mode. However, all commands
listed in Table 16 are supported while in shutdown mode. Execute
Command 15 (see Table 16) and set the LSB (D0) to 0 to exit
shutdown mode.
Table 15. Truth Table for Shutdown Mode
Linear Gain Setting Mode
Potentiometer Mode
A2 AW
WB
AW
WB
RBS
N/A1
Incrementing the wiper position by +6 dB essentially doubles the
RDAC register value, whereas decrementing the wiper position by
−6 dB halves the register value. Internally, the AD5122/AD5142
use shift registers to shift the bits left and right to achieve a 6 dB
increment or decrement. These functions are useful for various
audio/video level adjustments, especially for white LED brightness
settings in which human visual responses are more sensitive to
large adjustments than to small adjustments.
0
1
N/A1
Open
N/A1
Open
N/A1
Open
1 N/A means not applicable.
EEPROM OR RDAC REGISTER PROTECTION
The EEPROM and RDAC registers can be protected by disabling
any update to these registers. This can be done by using software. If
these registers are protected by software, set Bit D0 and/or Bit D1
(see Table 18), which protects the EEPROM and RDAC registers
independently.
Table 14. Detailed Left Shift and Right Shift Functions for
the 6 dB Step Increment and Decrement
Left Shift (+6 dB/Step)
Right Shift (−6 dB/Step)
When RDAC is protected, the only operation allowed is to copy
the EEPROM into the RDAC register.
0000 0000
0000 0001
0000 0010
1111 1111
0111 1111
0011 1111
INDEP PIN
If the INDEP pin is pulled high at power-up, the device operates
in linear gain setting mode, loading each string resistor, RAWx and
0000 0100
0000 1000
0001 1111
0000 1111
RWBx, with the value stored into the EEPROM (see Table 17). If
0001 0000
0000 0111
the pin is pulled low, the device powers up in potentiometer mode.
0010 0000
0000 0011
0100 0000
1000 0000
1111 1111
0000 0001
0000 0000
0000 0000
The INDEP pin and the D2 bit are connected internally to a logic
OR gate, if any or both are 1, the device cannot operate in
potentiometer mode (see Table 18).
Reset
The AD5122/AD5142 can be reset through software by executing
Command 14 (see Table 16) or through hardware on the low pulse
RESET
of the
pin. The reset command loads the RDAC registers
with the contents of the EEPROM and takes approximately 30 µs.
The EEPROM is preloaded to midscale at the factory, and initial
RESET
power-up is, accordingly, at midscale. Tie
RESET
to VLOGIC if
the
pin is not used.
Rev. C | Page 24 of 32
Data Sheet
AD5122/AD5142
Table 16. Advance Command Operation Truth Table
Control
Bits[DB15:DB12]
Address
Bits[DB11:DB8]1
Data Bits[DB7:DB0]1
Command
Number
C3
0
C2
0
C1
0
C0
0
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
1
X
0
X
X
0
X
X
X
X
X
X
X
X
X
NOP: do nothing
0
0
0
1
A2
A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to RDAC
2
3
0
0
0
0
1
1
0
1
0
0
A2
0
A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to input
register
A2 A1 A0
X
X
X
X
X
X
D1 D0 Read back contents
D1
0
0
D0
0
1
Data
Input register
EEPROM
1
0
Control
register
1
1
RDAC
4
5
6
7
8
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
A3 A2
A3 A2
A3 A2
A3 A2
A3 A2
0
0
0
0
0
A0
A0
A0
A0
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
X
Linear RDAC increment
Linear RDAC decrement
+6 dB RDAC increment
−6 dB RDAC decrement
Copy input register to RDAC
(software LRDAC)
9
0
1
1
1
0
A2
0
0
A0
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
Copy RDAC register to
EEPROM
10
11
0
1
1
0
1
0
1
0
0
0
A2
0
Copy EEPROM into RDAC
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to EEPROM
12
1
0
0
1
A3 A2
0
0
A0
A0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
D0 Top scale
D0 = 0; normal mode
D0 = 1; shutdown mode
D0 Bottom scale
13
1
0
0
1
A3 A2
D0 = 1; enter
D0 = 0; exit
14
15
1
1
0
1
1
0
1
0
X
X
X
0
X
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
Software reset
A3 A2
A0
D0 Software shutdown
D0 = 0; normal mode
D0 = 1; device placed in
shutdown mode
16
1
1
0
1
X
X
X
X
X
X
X
X
X
D2 D1 D0 Copy serial register data to
control register
1 X means don’t care.
Rev. C | Page 25 of 32
AD5122/AD5142
Data Sheet
Table 17. Address Bits
Potentiometer Mode
Input Register RDAC Register
Linear Gain Setting Mode
Stored Channel
Memory
A3
1
0
0
0
A2
X1
0
1
0
A1
X1
0
0
0
A0
X1
0
0
1
Input Register
RDAC Register
All channels
RWB1
All channels
RDAC1
All channels
RDAC1
All channels
RWB1
Not applicable
RDAC1/RWB1
Not applicable
RAW1
Not applicable
RDAC2
Not applicable
RDAC2
RAW1
RWB2
RAW1
RWB2
0
0
0
1
0
0
0
1
1
1
0
1
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
RAW2
Not applicable
Not applicable
RAW2
Not applicable
Not applicable
Not applicable
RDAC2/RWB2
RAW2
1 X means don’t care.
Table 18. Control Register Bit Descriptions
Bit Name
Description
D0
RDAC register write protect
0 = wiper position frozen to value in EEPROM memory
1 = allows update of wiper position through digital interface (default)
EEPROM program enable
D1
D2
0 = EEPROM program disabled
1 = enables device for EEPROM program (default)
Lineal setting mode/potentiometer mode
0 = potentiometer mode (default)
1 = linear gain setting mode
Rev. C | Page 26 of 32
Data Sheet
AD5122/AD5142
The nominal resistance between Terminal A and Terminal B, RAB,
is 10 kꢀ or 100 kꢀ, and has 128/256 tap points accessed by the
wiper terminal. The 7-bit/8-bit data in the RDAC latch is decoded
to select one of the 128/256 possible wiper settings. The general
equations for determining the digitally programmed output
resistance between Terminal W and Terminal B are
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., uses a
proprietary RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5122/AD5142 employ a
three stage segmentation approach, as shown in Figure 42. The
AD5122/AD5142 wiper switch is designed with the transmission
gate CMOS topology and with the gate voltage derived from
AD5122:
VDD and VSS.
D
128
R
WB (D)
RAB RW
RAB RW
From 0x00 to 0x7F (1)
From 0x00 to 0xFF (2)
A
S
TS
AD5142:
R
R
H
H
D
256
RWB (D)
R
M
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
R
M
R
L
L
W
R
In potentiometer mode, similar to the mechanical potentiometer,
the resistance between Terminal W and Terminal A also produces
a digitally controlled complementary resistance, RWA. RWA also
gives a maximum of 8% absolute resistance error. RWA starts at the
maximum resistance value and decreases as the data loaded into
the latch increases. The general equations for this operation are
7-BIT/8-BIT
ADDRESS
DECODER
R
R
M
R
H
M
R
H
S
BS
AD5122:
B
128 D
128
R
AW (D)
RAB RW
RAB RW
From 0x00 to 0x7F (3)
From 0x00 to 0xFF (4)
AD5142:
Figure 42. AD5122/AD5142 Simplified RDAC Circuit
256 D
256
R
AW (D)
Top Scale/Bottom Scale Architecture
In addition, the AD5122/AD5142 include new positions to
where:
reduce the resistance between terminals. These positions are
called bottom scale and top scale. At bottom scale, the typical
wiper resistance decreases from 130 Ω to 60 Ω (RAB = 100 kΩ).
At top scale, the resistance between Terminal A and Terminal W is
decreased by 1 LSB, and the total resistance is reduced to 60 Ω
(RAB = 100 kΩ).
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
R
AB is the end-to-end resistance.
RW is the wiper resistance.
If the device is configured in linear gain setting mode, the
resistance between Terminal W and Terminal A is directly
proportional to the code loaded in the associate RDAC register.
The general equations for this operation are
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation— 8% Resistor Tolerance
The AD5122/AD5142 operate in rheostat mode when only two
terminals are used as a variable resistor. The unused terminal can
be floating, or it can be tied to Terminal W, as shown in Figure 43.
AD5122:
D
128
R
AW (D)
RAB RW
From 0x00 to 0x7F (5)
From 0x00 to 0xFF (6)
A
A
A
AD5142:
W
W
W
D
256
R
AW (D)
RAB RW
B
B
B
where:
Figure 43. Rheostat Mode Configuration
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
R
AB is the end-to-end resistance.
RW is the wiper resistance.
Rev. C | Page 27 of 32
AD5122/AD5142
Data Sheet
V
DD
In the bottom scale condition or top scale condition, a finite
total wiper resistance of 40 Ω is present. Regardless of which
setting the device is operating in, limit the current between
Terminal A to Terminal B, Terminal W to Terminal A, and
Terminal W to Terminal B, to the maximum continuous current
of ±± mA or to the pulse current specified in Table ±. Otherwise,
degradation or possible destruction of the internal switch
contact can occur.
A
W
B
V
SS
PROGRAMMING THE POTENTIOMETER DIVIDER
Figure 45. Maximum Terminal Voltages Set by VDD and VSS
Voltage Output Operation
POWER-UP SEQUENCE
The digital potentiometer easily generates a voltage divider at
wiper to B and wiper to A that is proportional to the input voltage
at A to B, as shown in Figure 44.
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 45), it is
important to power up VDD first before applying any voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that VDD is powered unintentionally. The
ideal power-up sequence is VSS, VDD, VLOGIC, digital inputs, and
VA, VB, and VW. The order of powering VA, VB, VW, and digital
inputs is not important as long as they are powered after VSS,
VDD, and VLOGIC. Regardless of the power-up sequence and the
ramp rates of the power supplies, once VLOGIC is powered, the
power-on preset activates, which restores EEPROM values to
the RDAC registers.
V
A
A
W
V
OUT
B
V
B
Figure 44. Potentiometer Mode Configuration
Connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at VW with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use a compact, minimum lead
length layout design. Ensure that the leads to the input are as
direct as possible with a minimum conductor length. Ground
paths must have low resistance and low inductance. It is also
good practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 4± illustrates the basic supply bypassing configuration
for the AD5122/AD5142.
RWB(D)
RAB
R
AW (D)
RAB
VW (D)
VA
VB
(7)
where:
R
R
WB(D) can be obtained from Equation 1 and Equation 2.
AW(D) can be obtained from Equation 3 and Equation 4.
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RAW and RWB, and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
V
V
LOGIC
V
V
LOGIC
DD
DD
+
+
+
C3
C1
C5
0.1µF
C6
10µF
10µF
0.1µF
AD5122/
AD5142
TERMINAL VOLTAGE OPERATING RANGE
C4
C2
10µF
0.1µF
The AD5122/AD5142 are designed with internal ESD diodes
V
V
SS
SS
GND
for protection. These diodes also set the voltage boundary of the
terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed VDD are
clamped by the forward-biased diode. There is no polarity
constraint between VA, VW, and VB, but they cannot be higher
than VDD or lower than VSS.
Figure 46. Power Supply Bypassing
Rev. C | Page 28 of 32
Data Sheet
AD5122/AD5142
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
13
16
TIONS
INDICATOR AREA OP
(SEE DETAIL A)
0.50
BSC
12
1
1.75
1.60 SQ
1.45
EXPOSED
PAD
9
4
8
5
0.50
0.40
0.30
0.20 MIN
TOP VIEW
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TOJEDEC STANDARDS MO-220-WEED-6.
Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-22)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 48. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. C | Page 29 of 32
AD5122/AD5142
Data Sheet
ORDERING GUIDE
Package
Option
Model1, 2,3
RAB (kΩ) Resolution Interface Temperature Range
Package Description
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Branding
AD5122BCPZ10-RL7
AD5122BCPZ100-RL7
AD5122WBCPZ10-RL7
AD5122BRUZ10
10
128
128
128
128
128
128
128
128
256
256
256
256
256
256
256
256
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
CP-16-22 DH8
CP-16-22 DH9
CP-16-22 DMY
RU-16
RU-16
RU-16
100
10
10
100
10
10
AD5122BRUZ100
AD5122BRUZ10-RL7
AD5122WBRUZ10-RL7
AD5122BRUZ100-RL7
AD5142BCPZ10-RL7
AD5142BCPZ100-RL7
AD5142WBCPZ10-RL7
AD5142BRUZ10
RU-16
RU-16
100
10
100
10
10
100
10
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
CP-16-22 DH5
CP-16-22 DH6
CP-16-22 DN0
RU-16
RU-16
RU-16
AD5142BRUZ100
AD5142BRUZ10-RL7
AD5142WBRUZ10-RL7
AD5142BRUZ100-RL7
EVAL-AD5142DBZ
10
100
16-Lead TSSOP
16-Lead TSSOP
RU-16
RU-16
Evaluation Board
1 Z = RoHS Compliant Part.
2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all of the available resistor value options.
3 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD5122W and AD5142W models are available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
Rev. C | Page 30 of 32
Data Sheet
NOTES
AD5122/AD5142
Rev. C | Page 31 of 32
AD5122/AD5142
NOTES
Data Sheet
©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10880-0-5/17(C)
Rev. C | Page 32 of 32
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