AD4115BCPZ-RL7_技术文档

Single-Supply, Multichannel, 125 kSPS,

24-Bit, Sigma-Delta ADC with 10 V Inputs

Data Sheet

AD4115

FEATURES

GENERAL DESCRIPTION

24-bit ADC with integrated AFE

The AD4115 is a low power, low noise, 24-bit, sigma-delta (Σ-Δ)

Fast and flexible output rate: 2.5 SPS to 125 kSPS

Channel scan data rate of 24,845 SPS per channel

(40.25 µs settling)

analog-to-digital converter (ADC) that integrates an analog

front end (AFE) for fully differential or single-ended, high

impedance (≥1 MΩ), bipolar, 10 V voltage inputs.

85 dB common mode rejection of 50 Hz and 60 Hz at

20 SPS per channel

10 V inputs, either 8 differential or 16 single-ended

VIN pin absolute maximum rating 65 V

Absolute input pin voltage up to 20 V

Minimum 1 MΩ impedance

The AD4115 integrates key analog and digital signal

conditioning blocks to configure eight individual setups for

each analog input channel in use. The AD4115 features a

maximum channel scan rate of 24,845 kSPS (40.25 µs) for fully

settled data.

The embedded 2.5 V, low drift ( 5 ppm/°C), band gap internal

reference (with output reference buffer) reduces the external

component count.

On-chip 2.5 V reference

0.12% initial accuracy at 25°C, 5 ppm/°C (typical) drift

Internal or external clock

Power supplies

AVDD = 4.5 V to 5.5 V

IOVDD = 2 V to 5.5 V

Total current consumption AVDD + IOVDD (I_DD) = 10.4 mA

Temperature range: −40°C to +105°C

3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK)

SPI, QSPI, MICROWIRE, and DSP compatible

The digital filter allows flexible settings, including simultaneous

50 Hz and 60 Hz rejection at a 27.27 SPS output data rate. The

user can select different filter settings depending on the

requirements of each channel in the application. The automatic

channel sequencer enables the ADC to switch through each

enabled channel.

The precision performance of the AD4115 is achieved by

integrating the proprietary iPassives® technology from Analog

Devices, Inc. The AD4115 is factory calibrated to achieve a high

degree of specified accuracy.

APPLICATIONS

Process control

Programmable logic controller (PLC) and distributed control

system (DCS) modules

The AD4115 operates with a single power supply that allows

simplified use in galvanically isolated applications. The specified

operating temperature range is −40°C to +105°C. The AD4115

is housed in a 40-lead, 6 mm × 6 mm LFCSP.

Instrumentation and measurement

Rev. 0

Document Feedback

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice.

No license is granted by implication or otherwise under any patent or patent rights of Analog

Devices. Trademarks and registeredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

AD4115

Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Calibration Modes ..................................................................... 31

Digital Interface.............................................................................. 32

Checksum Protection ................................................................ 32

CRC Calculation......................................................................... 33

Integrated Functions...................................................................... 35

General-Purpose Input/Output ............................................... 35

External Multiplexer Control................................................... 35

Delay ............................................................................................ 35

16-Bit and 24-Bit Conversions................................................. 35

DOUT_RESET ........................................................................... 35

Synchronization ......................................................................... 35

Error Flags................................................................................... 36

DATA_STAT Function............................................................. 36

IOSTRENGTH Function .......................................................... 36

Internal Temperature Sensor ................................................... 37

Applications Information ............................................................. 38

Grounding and Layout.............................................................. 38

Register Summary .......................................................................... 39

Register Details ............................................................................... 41

Communications Register ........................................................ 41

Status Register............................................................................. 42

ADC Mode Register................................................................... 43

Interface Mode Register ............................................................ 44

Register Check............................................................................ 45

Data Register............................................................................... 45

GPIO Configuration Register................................................... 46

ID Register .................................................................................. 47

Channel Register 0 to Channel Register 15............................ 47

Applications ...................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications .................................................................................... 4

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings ........................................................... 8

Thermal Resistance...................................................................... 8

Electrostatic Discharge (ESD) Ratings...................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions ............................ 9

Typical Performance Characteristics........................................... 11

Theory of Operation ...................................................................... 14

Power Supplies............................................................................ 15

Digital Communication ............................................................ 15

AD4115 Reset.............................................................................. 15

Configuration Overview............................................................ 17

Noise Performance and Resolution ............................................. 20

Circuit Description......................................................................... 22

Muliplexer ................................................................................... 22

Voltage Inputs............................................................................. 22

Absolute Input Pin Voltages..................................................... 23

Data Output Coding .................................................................. 23

AD4115 Reference Options ...................................................... 23

Buffered Reference Input .......................................................... 24

Clock Source ............................................................................... 24

Digital Filter .................................................................................... 26

Sinc5 + Sinc1 Filter .................................................................... 26

Sinc3 Filter................................................................................... 26

Single-Cycle Settling Mode....................................................... 26

Enhanced 50 Hz and 60 Hz Rejection Filters......................... 27

Operating Modes............................................................................ 29

Continuous Conversion Mode................................................. 29

Continuous Read Mode ............................................................ 29

Single Conversion Mode ........................................................... 29

Standby Mode and Power-Down Mode ................................. 31

Setup Configuration Register 0 to Setup Configuration

Register 7 ..................................................................................... 48

Filter Configuration Register 0 to Filter Configuration

Register 7 ..................................................................................... 49

Offset Register 0 to OFFSET Register 7 .................................. 50

Gain Register 0 to Gain Register 7........................................... 50

Outline Dimensions....................................................................... 51

Ordering Guide .......................................................................... 51

REVISION HISTORY

7/2020—Revision 0: Initial Version

Rev. 0 | Page 2 of 51

Data Sheet

AD4115

FUNCTIONAL BLOCK DIAGRAM

AVDD REGCAPA

REF– REF+ REFOUT

IOVDD REGCAPD

BUFFERED

PRECISION

REFERENCE

1.8V

LDO

1.8V

LDO

INTERNAL

REFERENCE

VIN0

VIN1

VIN2

VIN3

VIN4

VIN5

RAIL-TO-RAIL

REFERENCE

CS

INPUT BUFFERS

VIN6

SCLK

DIN

PRECISION

VIN7

VIN8

VOLTAGE

SERIAL

INTERFACE

DIGITAL

FILTER

DIVIDER

MUX

VIN9

VIN10

Σ-Δ ADC

DOUT/RDY

SYNC

VIN11

VIN12

VIN13

VIN14

ERROR

VIN15

VINCOM

AD4115

VBIAS–

XTAL AND INTERNAL

CLOCK OSCILLATOR

CIRCUITRY

GPO CONTROL

TEMPERATURE

SENSOR

AVSS

GPIO0 GPIO1 GPO2 GPO3

XTAL1 XTAL2/CLKIO

Figure 1.

Rev. 0 | Page 3 of 51

AD4115

Data Sheet

SPECIFICATIONS

AVDD = 4.5 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = 0 V, DGND = 0 V, VBIAS− = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master

clock (MCLK) = 8 MHz, T_A= T_MINto T_MAX(−40°C to +105°C), unless otherwise noted. V_REFis the reference voltage, FS is full scale, and

FSR is full-scale range.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

VOLTAGE INPUTS

Differential Input Voltage Range¹

Specified performance

Functional

−10

−V_REF× 10

−20

1

+10

+V_REF× 10

+20

V

MΩ

mV

µV/°C

% FS

ppm/°C

% FSR

Absolute Input Pin Voltage

Input Impedance

Offset Error²

Offset Drift

Gain Error

Gain Drift

Integral Nonlinearity (INL)

Total Unadjusted Error (TUE)³

T_A= 25°C

1.5

8

0.05

1

0.01

T_A= 25°C, internal V_REF

0.07

0.1

0.12

0.07

0.08

% FSR

dB

0°C to 105°C, internal V_REF

−40°C to +105°C, internal V_REF

25°C, external V_REF

−40°C to +105°C, external V_REF

AVDD for input voltage (V_IN) = 1 V

Power Supply Rejection Ratio (PSRR)

70

Common-Mode Rejection Ratio

(CMRR)

V_IN= 1 V

At DC

At 50 Hz and 60 Hz

85

120

dB

20 Hz output data rate (postfilter), 50 Hz

1 Hz and 60 Hz 1 Hz

50 Hz 1 Hz and 60 Hz 1 Hz

Internal clock, 20 SPS ODR (postfilter)

External clock, 20 SPS ODR (postfilter)

See Table 16 and Table 17

Normal Mode Rejection³

71

85

90

dB

Resolution

Noise

See Table 16 and Table 17

ADC SPEED AND PERFORMANCE

ADC Output Data Rate (ODR)

No Missing Codes³

INTERNAL REFERENCE

Output Voltage

One channel, see Table 16

2.5

24

125,000

SPS

Bits

Excluding sinc3 filter ≥ 62.5 kHz notch

100 nF external capacitor to AVSS

REFOUT with respect to AVSS

REFOUT, T_A= 25°C

2.5

5

V

%

Initial Accuracy^{3, 4}

−0.12

−10

+0.12

+12

+10

Temperature Coefficient

ppm/°C

mA

Reference Load Current (I_LOAD

)

PSRR

AVDD (line regulation)

95

32

4.5

215

200

25

dB

5

Load Regulation (∆V_OUT/∆I_LOAD

Voltage Noise (e_N)

)

ppm/mA

µV rms

nV/√Hz

µs

0.1 Hz to 10 Hz, 2.5 V reference

1 kHz, 2.5 V reference

100 nF REFOUT capacitor

Voltage Noise Density

Turn On Settling Time

Short-Circuit Current (I_SC)

EXTERNAL REFERENCE INPUTS

Differential Input Range

Absolute Voltage Limits

Buffers Disabled

mA

V_REF= (REF+) − (REF−)

1

2.5

AVDD

V

AVSS − 0.05

AVSS

AVDD + 0.05

AVDD

V

Buffers Enabled

External Reference Input Current

Rev. 0 | Page 4 of 51

Data Sheet

AD4115

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Buffers Disabled

Input Current

Input Current Drift

36

1.2

3

µA/V

nA/V/°C

External clock

Internal clock

Buffers Enabled

Input Current

Input Current Drift

Normal Mode Rejection

CMRR

400

0.6

nA

nA/°C

95

dB

TEMPERATURE SENSOR

Accuracy

Sensitivity

After user calibration at 25°C

With respect to AVSS

2

477

°C

µV/K

GENERAL-PURPOSE OUTPUTS

(GPIO0, GPIO1, GPO2, GPO3)

Floating State Output Capacitance

Output Voltage³

5

pF

High (V_OH

Low (V_OL

CLOCK

Internal Clock

Frequency

Accuracy

)

Source current (I_SOURCE) = 200 µA

Sink current (I_SINK) = 800 µA

AVDD − 1

V

)

AVSS + 0.4

+2.5%

8

MHz

%

−2.5%

Duty Cycle

Output Voltage

V_OH

50

%

0.8 × IOVDD

V

V_OL

0.4

Crystal

Frequency

Start-Up Time

External Clock (CLKIO)

Duty Cycle

LOGIC INPUTS

Input Voltage³

14

30

16

10

8

16.384

MHz

µs

MHz

%

8.192

70

50

High (V_INH

)

2 V ≤ IOVDD < 2.3 V

2.3 V ≤ IOVDD ≤ 5.5 V

2 V ≤ IOVDD < 2.3 V

0.65 × IOVDD

0.7 × IOVDD

V

Low (V_INL

)

0.35 ×

IOVDD

2.3 V ≤ IOVDD ≤ 5.5 V

IOVDD ≥ 2.7 V

IOVDD < 2.7 V

0.7

0.25

0.2

V

µA

Hysteresis

0.08

0.04

−10

Leakage Current

LOGIC OUTPUT (DOUT/RDY)

Output Voltage³

V_OH

+10

IOVDD ≥ 4.5 V, I_SOURCE= 1 mA

2.7 V ≤ IOVDD < 4.5 V, I_SOURCE= 500 µA

IOVDD < 2.7 V, I_SOURCE= 200 µA

IOVDD ≥ 4.5 V, I_SINK= 2 mA

2.7 V ≤ IOVDD < 4.5 V, I_SINK= 1 mA

IOVDD < 2.7 V, I_SINK= 400 µA

Floating state

0.8 × IOVDD

V

µA

pF

V_OL

0.4

+10

Leakage Current³

Output Capacitance

POWER REQUIREMENTS

Power Supply Voltage

−10

Floating state

10

Rev. 0 | Page 5 of 51

AD4115

Data Sheet

Parameter

Test Conditions/Comments

Min

4.5

−2.75

2

Typ

Max

5.5

0

5.5

6.35

Unit

AVDD to AVSS

AVSS to DGND

IOVDD to DGND

IOVDD to AVSS

POWER SUPPLY CURRENTS⁶

V

For AVSS < DGND

All outputs unloaded, digital inputs

connected to IOVDD or DGND

Full Operating Mode

AVDD Current

IOVDD Current

Including internal reference

Internal clock

All V_IN= 0 V

9.4

1.4

210

185

11.5

1.8

mA

µA

Standby Mode

Power-Down Mode

POWER DISSIPATION

Full Operating Mode

Standby Mode

All V_IN= 0 V

µA

52

1

925

mW

µW

Power-Down Mode

¹The full specification is guaranteed for a differential input signal of 10 V. The device is functional up to a differential input signal of V_REF× 10. However, the specified

absolute pin voltage must not be exceeded for the proper function.

²Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected.

³Specification is not production tested but is supported by characterization data at the initial product release.

⁴This specification includes moisture sensitivity level (MSL) preconditioning effects.

⁵V_OUTis the output voltage.

⁶This specification is with no load on the REFOUT pin and the digital output pins.

TIMING CHARACTERISTICS

IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, capacitive load (C_LOAD) = 20 pF, unless otherwise noted.

Table 2.

Parameter^{1, 2}

Limit at T_MINor T_MAX

Unit

Test Conditions/Comments

SCLK

t₃

t₄

25

ns min

SCLK high pulse width

SCLK low pulse width

READ OPERATION

t₁

0

ns min

ns max

ns min

ns max

ns min

ns max

ns min

CS falling edge to DOUT/RDY active time

IOVDD = 4.75 V to 5.5 V

IOVDD = 2 V to 3.6 V

SCLK active edge to data valid delay⁴

IOVDD = 4.75 V to 5.5 V

IOVDD = 2 V to 3.6 V

Bus relinquish time after CS inactive edge

15

40

0

12.5

25

2.5

20

0

3

t₂

5

t₅

t₆

t₇

SCLK inactive edge to CS inactive edge

10

SCLK inactive edge to DOUT/RDY high/low

WRITE OPERATION

t₈

0

8

5

ns min

CS falling edge to SCLK active edge setup time⁴

Data valid to SCLK edge setup time

Data valid to SCLK edge hold time

CS rising edge to SCLK edge hold time

t₉

t₁₀

t₁₁

¹Sample tested during initial release to ensure compliance.

²See Figure 2 and Figure 3.

³This parameter is defined as the time required for the output to cross the V_OLor V_OHlimit.

⁴The SCLK active edge is the falling edge of SCLK.

5

RDY

DOUT/

returns high after a data register read. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while

is high. Ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read

RDY

DOUT/

only once.

Rev. 0 | Page 6 of 51

Data Sheet

AD4115

Timing Diagrams

CS (I)

t₆

t₁

t₅

MSB

LSB

DOUT/RDY (O)

t₇

t₂

t₃

SCLK (I)

t₄

I = INPUT, O = OUTPUT

Figure 2. Read Cycle Timing Diagram

CS (I)

t₁₁

t₈

SCLK (I)

DIN (I)

t₉

t₁₀

MSB

LSB

I = INPUT, O = OUTPUT

Figure 3. Write Cycle Timing Diagram

Rev. 0 | Page 7 of 51

AD4115

Data Sheet

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Table 3.

Parameter

Rating

AVDD to AVSS

AVDD to DGND

IOVDD to DGND

IOVDD to AVSS

AVSS to DGND

VINx to AVSS

Reference Input Voltage to AVSS

Digital Input Voltage to DGND

Digital Output Voltage to DGND

Digital Input Current

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

Lead Soldering, Reflow Temperature

−0.3 V to +6.5 V

−0.3 V to +7.5 V

−3.25 V to +0.3 V

−65 V to +65 V

−0.3 V to AVDD + 0.3 V

−0.3 V to IOVDD + 0.3 V

10 mA

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

θ_JCis the thermal resistance from the junction to the package case.

Table 4. Thermal Resistance

Package Type

CP-40-15¹

θ_JA

34²

θ_JC

2.63³

Unit

°C/W

¹4-Layer JEDEC PCB.

²Thermal impedance simulated values are based on JEDEC 2S2P thermal test

PCB with 16 thermal vias. θ_JAis specified for a device soldered on a JEDEC

test PCB for surface-mount packages. See JEDEC JESD51.

−40°C to +105°C

−65°C to +150°C

150°C

³A cold plate is attached to the PCB bottom and measured at the exposed paddle.

260°C

ELECTROSTATIC DISCHARGE (ESD) RATINGS

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the

operational section of this specification is not implied.

Operation beyond the maximum operating conditions for

extended periods may affect product reliability.

The following ESD information is provided for handling of

ESD-sensitive devices in an ESD protected area only.

Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.

Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.

ESD Ratings for AD4115

Table 5. AD4115, 40-Lead LFCSP

ESD Model

Withstand Threshold (v)

Class

1C

C3

HBM

CDM

1000

1250

ESD CAUTION

Rev. 0 | Page 8 of 51

Data Sheet

AD4115

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VINCOM

VIN0

1

2

3

4

5

6

7

8

9

30 VIN8

29 VIN7

VIN1

28 VIN6

VIN2

VIN3

REFOUT

REGCAPA

AVSS

27 VIN5

AD4115

26 VIN4

TOP VIEW

25 GPO2

24 GPIO1

23 GPIO0

22 REGCAPD

21 DGND

(Not to Scale)

AVDD

DNC 10

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT ANYTHING TO DNC.

DNC IS INTERNALLY CONNECTED TO AVSS.

2. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A SIMILAR PAD ON

THE PCB THAT IS UNDER THE EXPOSED PAD TO CONFER MECHANICAL

STRENGTH TO THE PACKAGE AND FOR HEAT DISSIPATION. THE EXPOSED

PAD MUST BE CONNECTED TO AVSS THROUGH THIS PAD ON THE PCB.

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic¹Type²Description

1

2

3

4

5

6

7

VINCOM

AI

Voltage Input Common. Voltage inputs are referenced to VINCOM when the inputs are configured as

single-ended. Connect VINCOM to analog ground.

Voltage Input 0. VIN0 is either referenced to VINCOM in single-ended configuration or referenced to a

positive input of an input pair with VIN1 in differential configuration.

Voltage Input 1. VIN1 is either referenced to VINCOM in single-ended configuration or referenced to a

negative input of an input pair with VIN0 in differential configuration.

Voltage Input 2. VIN2 is either referenced to VINCOM in single-ended configuration or referenced to a

positive input of an input pair with VIN3 in differential configuration.

Voltage Input 3. VIN3 is either referenced to VINCOM in single-ended configuration or referenced to a

negative input of an input pair with VIN2 in differential configuration.

Internal Reference Buffered Output. The output is 2.5 V with respect to AVSS. Decouple REFOUT to AVSS

using a 0.1 µF capacitor.

Analog Low Dropout (LDO) Regulator Output. Decouple REGCAPA to AVSS using a 1 µF capacitor and a

0.1 µF capacitor.

VIN0

AI

VIN1

AI

VIN2

AI

VIN3

AI

REFOUT

REGCAPA

AO

8

9

10

11

12

13

AVSS

AVDD

DNC

VBIAS−

XTAL1

XTAL2/CLKIO AI/DI

P

N/A

AI

Negative Analog Supply. AVSS ranges from −2.75 V to 0 V and is nominally set to 0 V.

Analog Supply Voltage. AVDD ranges from 3.0 V to 5.5 V with respect to AVSS.

Do Not Connect. Do not connect anything to DNC. DNC is internally connected to AVSS.

Voltage Bias Negative. VBIAS− sets the bias voltage for the voltage input AFE. Connect VBIAS− to AVSS.

Input 1 for Crystal.

Input 2 for Crystal/Clock Input or Output. See the CLOCKSEL bit settings in the ADC Mode Register

section for more information.

14

DOUT/RDY

DO

Serial Data Output/Data Ready Output. The DOUT/RDY dual-purpose pin functions as a serial data

output pin to access the output shift register on the ADC. The output shift register can contain data from

any on-chip data or control registers. The data-word or control word information is placed on the

DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the

DOUT/RDY output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a

data ready pin and goes low to indicate the completion of a conversion. If the data is not read after the

conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as

an interrupt to a processor that indicates that valid data is available.

15

DIN

DI

Serial Data Input to the Input Shift Register on the ADC. Data in the input shift register is transferred to

the control registers on the ADC, and the register address (RA) bits of the communications register

identify the appropriate register. Data is clocked in on the rising edge of SCLK.

16

17

SCLK

CS

DI

Serial Clock Input. The SCLK serial clock input is used for data transfers to and from the ADC. SCLK has a

Schmitt triggered input.

Chip Select Input. CS is an active low logic input used to select the ADC. Use CS to select the ADC in

systems with more than one device on the serial bus. CS can be hardwired low to allow the ADC to

Rev. 0 | Page 9 of 51

AD4115

Data Sheet

Pin No. Mnemonic¹

Type²Description

operate in 3-wire mode with SCLK, DIN, and DOUT/RDY used to interface with the device. When CS is

high, the DOUT/RDY output is tristated.

18

ERROR

DI/O

Error Input/Output or General-Purpose Output. ERROR can be used in one of the following three modes:

Active low error input mode. This mode sets the ADC_ERROR bit in the status register.

Active low, open-drain error output mode. The status register error bits are mapped to the ERROR pin.

The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error

on any device can be observed.

General-purpose output mode. The status of the pin is controlled by the ERR_DAT bit in the GPIOCON

register. ERROR is referenced between IOVDD and DGND.

19

20

SYNC

DI

P

Synchronization Input. SYNC allows digital filter and analog modulator synchronization when using

multiple devices.

Digital Input/Output Supply Voltage. The IOVDD voltage ranges from 2 V to 5.5 V (nominal). IOVDD is

independent of AVDD. For example, IOVDD operates at 3.3 V when AVDD equals 5 V, or vice versa. If

AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V.

IOVDD

21

22

DGND

REGCAPD

P

AO

Digital Ground.

Digital LDO Regulator Output. REGCAPD is for decoupling purposes only. Decouple REGCAPD to DGND

using a 1 µF capacitor.

23

24

25

26

GPIO0

GPIO1

GPO2

VIN4

DI/O

DO

General-Purpose Input/Output 0. Logic input/output on GPIO0 is referred to the AVDD and AVSS supplies.

General-Purpose Input/Output 1. Logic input/output on GPIO1 is referred to the AVDD and AVSS supplies.

General-Purpose Output 2. Logic output on GPO2 is referred to the AVDD and AVSS supplies.

Voltage Input 4. VIN4 is either referenced to VINCOM in single-ended configuration or referenced to a

positive input of an input pair with VIN5 in differential configuration.

AI

27

28

29

30

31

32

33

34

35

36

37

VIN5

AI

Voltage Input 5. VIN5 is either referenced to VINCOM in single-ended configuration or referenced to a

negative input of an input pair with VIN4 in differential configuration.

Voltage Input 6. VIN6 is either referenced to VINCOM in single-ended configuration or referenced to a

positive input of an input pair with VIN7 in differential configuration.

Voltage Input 7. VIN7 is either referenced to VINCOM in single-ended configuration or referenced to a

negative input of an input pair with VIN6 in differential configuration.

Voltage Input 8. VIN8 is either referenced to VINCOM in single-ended configuration or referenced to a

positive input of an input pair with VIN9 in differential configuration.

Voltage Input 9. VIN9 is either referenced to VINCOM in single-ended configuration or referenced to a

negative input of an input pair with VIN8 in differential configuration.

Voltage Input 10. VIN10 is either referenced to VINCOM in single-ended configuration or referenced to a

positive input of an input pair with VIN11 in differential configuration.

Voltage Input 11. VIN11 is either referenced to VINCOM in single-ended configuration or referenced to a

negative input of an input pair with VIN10 in differential configuration.

Voltage Input 12. VIN12 is either referenced to VINCOM in single-ended configuration or referenced to a

positive input of an input pair with VIN13 in differential configuration.

VIN6

VIN7

VIN8

VIN9

VIN10

VIN11

VIN12

VIN13

VIN14

VIN15

Voltage Input 13. VIN13 is either referenced to VINCOM in single-ended configuration or referenced to a

negative input of an input pair with VIN12 in differential configuration.

Voltage Input 14. VIN14 is either referenced to VINCOM in single-ended configuration or referenced to a

positive input of an input pair with VIN15 in differential configuration.

Voltage Input 15. VIN15 is either referenced to VINCOM in single-ended configuration or referenced to a

negative input of an input pair with VIN14 in differential configuration.

38

39

GPO3

REF−

DO

AI

General-Purpose Output 3. Logic output on GPO3 is referred to the AVDD and AVSS supplies.

Reference Input Negative Terminal. The REF− voltage can span from AVSS to AVDD − 1 V. The reference

can be selected through the REF_SELx bits in the setup configuration registers.

40

REF+

EP

AI

P

Reference Input Positive Terminal. An external reference can be applied between REF+ and REF−. The

REF+ voltage can span from AVDD to AVSS + 1 V. The reference can be selected through the REF_SELx

bits in the setup configuration registers.

Exposed Pad. Solder the exposed pad to a similar pad on the PCB that is under the exposed pad to

confer mechanical strength to the package and for heat dissipation. The exposed pad must be

connected to AVSS through this pad on the PCB.

¹The dual function pin mnemonics are referenced by the relevant function only throughout this data sheet.

²AI is analog input, AO is analog output, P is power supply, N/A is not applicable, DI is digital input, DO is digital output, and DI/O is bidirectional digital input/output.

Rev. 0 | Page 10 of 51

Data Sheet

AD4115

TYPICAL PERFORMANCE CHARACTERISTICS

8387974

350

8387973

8387972

8387971

8387970

8387969

8387968

8387967

8387966

8387965

300

250

200

150

100

50

0

200

400

600

800

1000

SAMPLE NUMBER

ADC CODE

Figure 8. Histogram (Output Data Rate = 2.5 SPS)

Figure 5. Noise (Output Data Rate = 2.5 SPS)

60

50

40

30

20

10

0

8388000

8387990

8387980

8387970

8387960

8387950

8387940

8387930

0

200

400

600

800

1000

SAMPLE NUMBER

ADC CODE

Figure 6. Noise (Output Data Rate = 2.5 kSPS)

Figure 9. Histogram (Output Data Rate = 2.5 kSPS)

8388050

8388000

8387950

8387900

8387850

8387800

8387750

25

20

15

10

5

0

200

400

600

800

1000

SAMPLE NUMBER

ADC CODE

Figure 10. Histogram (Output Data Rate = 125 kSPS

Figure 7. Noise (Output Data Rate = 125 kSPS)

Rev. 0 | Page 11 of 51

AD4115

Data Sheet

–60

30

–70

25

20

15

10

5

–80

–90

–100

–110

–120

–130

–140

–150

–160

10

0

20

30

40

50

60

7.996 7.999 8.002 8.005 8.008 8.011 8.014 8.017

V

FREQUENCY (Hz)

IN

FREQUENCY (MHz)

Figure 11. CMRR vs. V^INFrequency (VIN = 0.1 V, Output Data Rate = 20 SPS,

Enhanced Filter)

Figure 14. Internal Oscillator Frequency and

Accuracy Distribution Histogram

–40

–50

35

30

25

20

15

10

5

–60

–70

–80

–90

–100

–110

–120

–130

0

1

10

100

1k

10k

100k

1M

10M

100M

–4.8

–4.0 –3.2 –2.4

–1.6 –0.8

0

0.8

1.6

V

FREQUENCY (Hz)

OFFSET ERROR (mV)

IN

Figure 12. PSRR vs. V_INFrequency

Figure 15. Offset Error Distribution Histogram

10

8

30

25

20

15

10

5

6

4

2

0

–2

–4

0

3.2

3.9

4.6

5.3

6.0

6.7

7.4

8.1

–10

–8

–6

–4

–2

0

2

4

6

8

10

OFFSET ERROR DRIFT (µV/°C)

V

(V)

IN

Figure 16. Offset Error Drift Distribution Histogram

Figure 13. INL vs. V_IN

Rev. 0 | Page 12 of 51

Data Sheet

AD4115

35

30

25

20

15

10

5

30

25

20

15

10

5

0

0.68

0.81

0.94

1.07

1.20

1.33

1.46

1.59

GAIN ERROR DRIFT (ppm/°C)

GAIN ERROR (% of Full Scale)

Figure 17. Gain Error Distribution Histogram

Figure 18. Gain Error Drift Distribution Histogram

Rev. 0 | Page 13 of 51

AD4115

Data Sheet

THEORY OF OPERATION

The AD4115 offers a fast settling, high resolution, multiplexed

ADC with high levels of configurability, including the following

features:

The AD4115 includes two separate linear regulator blocks for

the analog and digital circuitry. The analog LDO regulator

regulates the AVDD supply to 1.8 V.

The linear regulator for the digital IOVDD supply performs a

function similar to the LDO regulator and regulates the input

voltage applied at the IOVDD pin to 1.8 V. The serial interface

signals always operate from the IOVDD supply seen at the pin.

For example, if 3.3 V is applied to the IOVDD pin, the interface

logic inputs and outputs operate at this level.

•

Eight fully differential voltage inputs or 16 single-ended

voltage inputs.

High impedance voltage divider with integrated precision

matched resistors

Embedded proprietary iPassives® technology within a

small device footprint.

Per channel configurability where up to eight different

setups can be defined. A separate setup can be mapped to

each channel. Each setup allows the user to configure

whether the buffers are enabled or disabled, gain and offset

correction, filter type, ODR, and reference source selection.

Highly configurable digital filter enabling conversion rates

up to 125 kSPS on a single channel and 24.845 kSPS

switching.

The AD4115 is designed for a multitude of factory automation

and process control applications, including PLC and DCS

modules. The AD4115 reduces overall system cost and design

burden and maintains a high level of accuracy. The AD4115

offers the following system benefits:

•

A single 5 V power supply.

Guaranteed minimum 1 MΩ input impedance.

Overrange voltage greater than 10 V.

Reduced calibration costs.

The AD4115 includes a precision, 2.5 V, low drift ( 5 ppm/°C),

band gap internal reference. Use this reference in ADC

conversions to reduce the external component count. When

enabled, the internal reference is output to the REFOUT pin.

The internal reference can be used as a low noise biasing

voltage for the external circuitry and must be connected to a

0.1 μF decoupling capacitor.

High channel count.

16MHz

CX2

CX1

OPTIONAL EXTERNAL

CRYSTAL CIRCUITRY

CAPACITORS

12

XTAL1

XTAL2/CLKIO 13

DOUT/RDY 14

CLKIN

OPTIONAL

EXTERNAL

CLOCK

DOUT/RDY

DIN

INPUT

2

3

VIN0

VIN1

15

DIN

16

SCLK

CS

SCLK

17

CS

IOVDD

0.1µF

20

21

IOVDD

DGND

AD4115

37

VIN15

REGCAPD 22

0.1µF

1µF

AVDD

REFOUT

9

1

VINCOM

0.1µF

6

7

0.1µF

11

VBIAS–

REGCAPA

0.1µF

1µF

AVSS

8

Figure 19. Typical Connection Diagram

Rev. 0 | Page 14 of 51

Data Sheet

AD4115

determine the specific register to which the read or write

operation applies (see Table 20).

POWER SUPPLIES

The AD4115 has two independent power supply pins, AVDD

and IOVDD. The AD4115 has no specific requirements for a

power supply sequence. However, when all power supplies are

stable, a device reset is required. See the AD4115 Reset section

for information on how to reset the device.

When the read or write operation to the selected register is

complete, the interface returns to the default state to expect a

write operation to the communications register.

Figure 21 and Figure 22 show a write to and a read from a

register by writing the 8-bit command to the communications

register followed by the data for the addressed register.

AVDD powers the internal 1.8 V analog LDO regulator that

powers the ADC core. AVDD also powers the crosspoint

multiplexer and integrated input buffers. AVDD is referenced to

AVSS, and AVDD − AVSS = 5 V. AVDD and AVSS can be a

single 5 V supply or 2.5 V split supplies. Consider the absolute

maximum ratings when using split supplies (see the Absolute

Maximum Ratings section).

Figure 21 shows an 8-bit command with the register address

followed by 8 bits, 16 bits, or 24 bits of data where the data

length on DIN depends on the selected register. Figure 22

shows an 8-bit command with the register address followed by

8 bits, 16 bits, 24 bits, or 32 bits of data where the data length

on DOUT depends on the selected register.

IOVDD powers the internal 1.8 V digital LDO regulator that

powers the ADC digital logic. IOVDD sets the voltage levels for

the serial peripheral interface (SPI) of the ADC. IOVDD is

referenced to DGND, and the voltage from IOVDD to DGND can

vary from 2 V (minimum) to 5.5 V (maximum).

To verify correct communication with the device, read the ID

register. The ID register is a read only register and contains the

value of 0x38DX for the AD4115. The communication register

and ID register details are described in Table 7 and Table 8.

Single-Supply Operation (AVSS = DGND)

8-BIT COMMAND

UP TO 24-BIT INPUT

8-BIT CRC

CS

When the AD4115 is powered from a single supply connected

to AVDD, the supply must be 5 V. In this configuration, AVSS

and DGND can be shorted together on a single ground plane.

CMD

DATA

CRC

DIN

IOVDD can range from 2 V to 5.5 V in this unipolar input

configuration.

SCLK

DIGITAL COMMUNICATION

Figure 21. Writing to a Register

The AD4115 has either a 3-wire or 4-wire SPI interface that is

compatible with QSPI™, MICROWIRE®, and digital signal

processors (DSPs). The interface operates in SPI Mode 3 and can

8-BIT COMMAND UP TO 32-BIT OUTPUT

8-BIT CRC

CS

be operated with tied low. In SPI Mode 3, SCLK idles high, the

CMD

falling edge of SCLK is the drive edge, and the rising edge of

SCLK is the sample edge. Data is clocked out on the falling

(drive) edge and data is clocked in on the rising (sample) edge.

DIN

DOUT/

RDY

DATA

CRC

DRIVE EDGE

SAMPLE EDGE

SCLK

Figure 22. Reading from a Register

Figure 20. SPI Mode 3 SCLK Edges

AD4115 RESET

Accessing the ADC Register Map

When a power-up cycle completes and the power supplies are

stable, a device reset is required. If interface synchronization is

lost, a device reset is required. A write operation of at least 64 serial

clock cycles with DIN high returns the ADC to the default state

by resetting the entire device, including the register contents.

The communications register controls access to the full ADC

register map. This register is an 8-bit, write only register. On

power-up or after a reset, the digital interface defaults to a state

where the interface expects a write to the communications

register. Therefore, all communication begins by writing to the

communications register.

CS

Alternatively, if

is used with the digital interface, returning

high sets the digital interface to the default state and halts any

serial interface operation.

The data written to the communications register determines

which register is accessed and if the next operation is a read or

write. The RA bits (Bits[5:0] in Register Address 0x00)

Rev. 0 | Page 15 of 51

AD4115

Data Sheet

Table 7. Communications Register Bit Map

Register Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

R/W

0x00 COMMS

[7:0]

WEN

R/W

RA

0x00

W

Table 8. ID Register Bit Map

Register Name

Bits

Bit 7

Bit 6

Bit 3

Bit 2

Bit 1

Bit 0

Reset

R/W

0x07 ID

[15:0]

ID

0x38DX¹

R

¹X means don’t care.

Rev. 0 | Page 16 of 51

Data Sheet

AD4115

Channel Configuration

CONFIGURATION OVERVIEW

The AD4115 has 16 independent channels and eight independent

setups. The user can select any input pair on any channel, as

well as any of the eight setups for any channel, which allows full

flexibility in the channel configuration. This flexibility allows per

channel configuration when using differential inputs and single-

ended inputs because each channel can have an individual

dedicated setup.

After a power-on or reset, the AD4115 default configuration is

as follows:

•

Channel configuration: Channel 0 is enabled, the VIN0

and VIN1 pair is selected as the input. Setup 0 is selected

(see the Setup Configuration section for more information).

Setup configuration: the analog input buffers and the

reference input buffers are disabled. The REF+ and REF− pins

are selected as the reference source. Note that for this setup,

the default channel does not operate correctly because the

input buffers must be enabled for a VINx input.

•

Channel Registers

The channel registers select which voltage input is used for the

corresponding channel. Each channel register contains a channel

enable/disable bit and the setup selection bits that select from

eight available setups to use for the channel.

•

Filter configuration: the sinc5 + sinc1 filter is selected and

the maximum output data rate of 125 kSPS is selected.

ADC mode: continuous conversion mode and the internal

oscillator are enabled. The internal reference is disabled.

Interface mode: cyclic redundancy check (CRC) and the

data and status output are disabled.

When the AD4115 operates with more than one channel enabled,

the channel sequencer cycles through the enabled channels in

sequential order from Channel 0 to Channel 15. If a channel is

disabled, that channel is skipped by the sequencer. Details on

the channel register for Channel 0 are shown in Table 9.

Note that only a few of the register setting options are shown in

this example list. For full register information, see the Register

Details section.

Figure 23 shows an overview of the suggested flow for changing

the ADC configuration, divided into the following three blocks:

•

Channel configuration.

Setup configuration.

ADC mode and interface mode configuration.

A

CHANNEL CONFIGURATION

SELECT INPUT AND SETUP FOR EACH ADC CHANNEL

B

C

SETUP CONFIGURATION

8 POSSIBLE ADC SETUPS

SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE

ADC MODE AND INTERFACE MODE CONFIGURATION

SELECT ADC OPERATING MODE, CLOCK SOURCE,

ENABLE CRC, DATA AND STATUS, AND MORE

Figure 23. Suggested ADC Configuration Flow

Table 9. Channel Register 0 Bit Map

Register Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

R/W

0x10 CH0

[15:8]

[7:0]

CH_EN0

SETUP_SEL0

Reserved

INPUT0[9:8]

0x8001

R/W

INPUT0[7:0]

Rev. 0 | Page 17 of 51

AD4115

Data Sheet

Setup Configuration Registers

Setup Configuration

The setup configuration registers allow the user to select

between bipolar mode and unipolar mode to determine the ADC

output coding. The user can also select the reference source using

these registers. Three reference source options are available: a

reference connected between the REF+ and REF− pins, the

internal reference, or using AVDD – AVSS as the reference.

The input and reference buffers can also be enabled or disabled

using these registers.

The AD4115 has eight independent setups. Each setup consists

of the following four types of registers:

•

Setup configuration register

Filter configuration register

Gain register

Offset register

For example, Setup 0 consists of Setup Configuration

Register 0, Filter Configuration Register 0, Gain Register 0, and

Offset Register 0. Figure 24 shows the grouping of these

registers. The setup is selectable from the channel registers (see

the Channel Configuration section), which allows each channel

to be assigned to one of the eight separate setups. Table 10 through

Table 13 show the four registers that are associated with Setup 0.

This structure is repeated for Setup 1 to Setup 7.

Filter Configuration Registers

The filter configuration registers select which digital filter is

used at the output of the ADC modulator. Set the bits in these

registers to select the order of the filter and the output data rate.

For more information, see the Digital Filter section.

SETUP CONFIGURATION

REGISTERS

FILTER CONFIGURATION

REGISTERS

GAIN REGISTERS

OFFSET REGISTERS

SETUPCON0

SETUPCON1

SETUPCON2

SETUPCON3

SETUPCON4

SETUPCON5

SETUPCON6

SETUPCON7

FILTCON0

FILTCON1

FILTCON2

FILTCON3

FILTCON4

FILTCON5

FILTCON6

FILTCON7

GAIN0

GAIN1

GAIN2

GAIN3

GAIN4

GAIN5

GAIN6

GAIN7

OFFSET0

0x30

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

OFFSET1

0x31

OFFSET2

0x32

OFFSET3

0x33

OFFSET4

0x34

OFFSET5

0x35

OFFSET6

0x36

OFFSET7

0x37

SELECT PERIPHERAL

FUNCTIONS FOR

ADC CHANNEL

SELECT DIGITAL

FILTER TYPE

AND OUTPUT DATA RATE

GAIN CORRECTION

OPTIONALLY

OFFSET CORRECTION

OPTIONALLY PROGRAMMED

PER SETUP AS REQUIRED

PROGRAMMED

PER SETUP AS REQUIRED

INPUT BUFFERS

REFERENCE INPUT BUFFERS

REFERENCE SOURCE

125kSPS TO 2.5SPS

SINC5 + SINC1

SINC3

SINC3 MAP

ENHANCED 50Hz/60Hz

Figure 24. ADC Setup Register Grouping

Table 10. Setup Configuration Register 0

Register Name

Bits

Bit 7

Bit 6

Bit 5 Bit 4

BI_UNIPOLAR0

Bit 3

Bit 2

REFBUF0+ REFBUF0−

Reserved

Bit 1 Bit 0 Reset

R/W

0x20

SETUPCON0 [15:8]

[7:0]

Reserved

INBUF0

0x1000 R/W

Reserved

REF_SEL0

Table 11. Filter Configuration Register 0

Register Name

Bits

Bit 7

Bit 6 Bit 5 Bit 4 Bit 3

Bit 2 Bit 1 Bit 0 Reset

ENHFILT0 0x0500

R/W

0x28 FILTCON0

[15:8]

[7:0]

SINC3_MAP0

Reserved

ORDER0

ENHFILTEN0

R/W

ODR0

Table 12. Gain Register 0

Register

Name

Bits

Bits[23:0]

Reset

0x5XXXX0

R/W

0x38

GAIN0

[23:0]

GAIN0

Table 13. Offset Register 0

Register

Name

Bits

Bits[23:0]

OFFSET0

Reset

R/W

0x30

OFFSET0

[23:0]

0x800000

Rev. 0 | Page 18 of 51

Data Sheet

AD4115

also select the standby and power-down modes, as well as any

of the calibration modes. The ADC mode register also contains

the clock source select bits and internal reference enable bit. The

reference select bits are contained in the setup configuration

registers (see the Setup Configuration section for more

information). The details of the ADC mode register are shown in

Table 14.

Gain Registers

The gain registers are 24-bit, read and write registers that hold

the gain calibration coefficient for the ADC. The power-on reset

value of the gain registers is 0x5XXXX0.

Offset Registers

The offset registers are 24-bit, read and write registers that hold

the offset calibration coefficient for the ADC. The power-on

reset value of the offset registers is 0x800000.

Interface Mode Register

The interface mode register configures the digital interface

operation. This register allows the user to control data-word

length, CRC enable, data plus status read, and continuous read

mode. The details of this register are shown in Table 15. For

more information, see the Digital Interface section.

ADC Mode and Interface Mode Configuration

The ADC mode register and the interface mode register configure

the core peripherals for the AD4115 to use, as well as the mode

for the digital interface.

ADC Mode Register

The ADC mode register primarily sets the ADC conversion

mode to either continuous or single conversion. The user can

Table 14. ADC Mode Register

Register

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

R/W

0x01

ADCMODE

[15:8]

[7:0]

REF_EN

Reserved

SING_CYC

Mode

Reserved

Delay

0x2000

R/W

CLOCKSEL

Reserved

Table 15. Interface Mode Register

Register Name Bits Bit 7

Bit

2

Bit 6

Reserved

Bit 5

Bit 4

Bit 3

Bit 1

Bit 0

Reset

R/W

0x02

IFMODE [15:8]

ALT_

SYNC

IOSTRENGTH

Reserved

DOUT_RESET 0x0000 R/W

[7:0]

CONTREAD DATA_ REG_

STAT CHECK

Reserved

CRC_EN

Reserved WL16

Rev. 0 | Page 19 of 51

AD4115

Data Sheet

NOISE PERFORMANCE AND RESOLUTION

Table 16 to Table 17 show the rms noise, peak-to-peak noise,

effective resolution, and noise free (peak-to-peak) resolution of the

device for various ODRs. These values are typical and are

measured with an external 2.5 V reference and with the ADC

continuously converting on multiple channels. The values in

Table 16 and Table 17 are generated for the 10 V voltage input

range, with a differential input voltage of 0 V. Note that the

peak-to-peak resolution is calculated based on the peak-to-peak

noise. The peak-to-peak resolution represents the resolution for

which there is no code flicker.

Table 16. 1ꢀ V Voltage Input RMS Noise Resolution vs. ODR Using a Sinc5 + Sinc1 Filter

Default Output Data Rate Output Data Rate (SPS per

Notch

Frequency Noise

(Hz)

Effective

Peak-to-Peak

Resolution

(μV p-p) (Bits)

(SPS), SING_CYC = 0 and

Single Channel Enabled

Channel), SING_CYC = 1 or

Settling

Resolution Noise

Multiple Channels Enabled Time¹

(μV rms)²(Bits)

125,000

62,500

31,250

25,000

15,625

10,390

4994

2498

1000

500

395.5

200

100

59.87

49.92

20

24,845

20,725

15,564

13,841

10,390

4,994

2,499

1,000

500

395.26

200

100

59.89

49.92

20.

16.66

10

40.25 μs

125,000

62,500

31,250

25,000

15,625

140.36

124.42

99.14

89.57

72.94

71.01

45.67

32.42

20.24

13.88

12.61

9.702

7.36

5.38

5.52

4.52

4.07

3.15

2.92

2.49

17.12

17.29

17.62

17.77

18.06

18.10

18.74

19.23

19.91

20.46

20.60

20.98

21.37

21.83

21.79

22.08

22.23

22.6

926.38

821.17

654.32

591.16

481.40

468.67

301.42

213.97

133.58

91.61

83.23

64.03

48.58

35.51

36.43

29.83

26.86

16.1

14.40

14.57

14.90

15.05

15.34

15.38

16.02

16.51

17.19

17.74

17.87

18.25

18.65

19.10

19.07

19.35

19.51

20.2

48.25 μs

64.25 μs

72.25 μs

96.25 μs

200.25 μs 5952.4

400.25 μs 2717.4

1 ms

1033.1

508.1

400.6

201.3

100.3

59.98

50

20.01

16.67

10

2 ms

2.53 ms

5 ms

10 ms

16.7 ms

20.03 ms

50 ms

60.03 ms

100 ms

200 ms

400 ms

16.7

10

5

2.5

5

2.5

5

2.5

22.7

12.1

12

20.7

¹The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.

²The noise values are based on 1000 samples for data rates ≥ 395.5 SPS per channel and based on 100 samples for data rates ≤ 200 SPS per channel.

Table 17. 1ꢀ V Voltage Input RMS Noise Resolution vs. ODR Using a Sinc3 Filter

Default Output Data

Rate (SPS), SING_CYC = 0 Output Data Rate (SPS per

and Single Channel

Enabled

Notch

Frequency Noise

(Hz)

Effective

Peak-to-Peak

Resolution

(μV p-p) (Bits)

Channel), SING_CYC = 1 or

Multiple Channels Enabled

Settling

Time¹

Resolution Noise

(μV rms)²(Bits)

125,000

62,500

31,250

25,000

15,625

10,416.7

5000

2500

1000

500

400.6

200

41,152

20,704

10,384

8,313

5,200

3,469

24.3 μs

48.3 μs

96.3 μs

120.3 μs

192.3 μs

288.3 μs

600.3 μs

1.2 ms

3 ms

6 ms

7.49 ms

15 ms

30 ms

50.02 ms 59.98

60 ms 50.00

125,000

62,500

31,250

25,000

15,625

10,417

5000

2500

1000

500.0

400.6

200.0

100.0

1008

176.41

82.49

73.71

57.99

46.93

31.45

22.83

14.35

10.82

9.66

14.28

16.79

17.89

18.05

18.40

18.70

19.28

19.74

20.41

20.82

20.98

21.39

21.71

22.02

22.09

6652

1164

11.55

14.07

15.16

15.33

15.67

15.98

16.56

17.02

17.69

18.10

18.26

18.66

18.99

19.30

19.37

544.43

486.49

382.73

309.74

207.57

150.68

94.71

71.41

63.76

48.18

38.35

31.02

29.57

1,666

833.33

333.33

166.67

133.51

66.67

33.33

19.99

16.67

7.30

5.81

4.70

4.48

100

59.98

50

Rev. 0 | Page 20 of 51

Data Sheet

AD4115

Default Output Data

Rate (SPS), SING_CYC = 0 Output Data Rate (SPS per

and Single Channel

Enabled

Notch

Frequency Noise

(Hz)

Effective

Peak-to-Peak

Resolution

(µV p-p) (Bits)

Channel), SING_CYC = 1 or

Multiple Channels Enabled

Settling

Time¹

Resolution Noise

(µV rms)²(Bits)

20

16.67

10

5

2.5

6.67

5.56

3.33

1.67

0.83

150 ms

180 ms

300 ms

600 ms

1.2 s

20.00

16.67

10.00

5.00

3.30

2.78

2.95

2.63

2.43

22.53

22.78

22.7

21.78

18.35

14.9

11.9

19.81

20.06

20.4

20.7

2.50

¹The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.

²The noise values are based on 1000 samples for data rates ≥381 SPS per channel and based on 100 samples for data rates ≤200.3 SPS per channel.

Rev. 0 | Page 21 of 51

AD4115

Data Sheet

CIRCUIT DESCRIPTION

resistors that enable an input range of 20 V from a single 5 V

power supply.

MULIPLEXER

The device has 17 voltage input pins, VIN0 to VIN15 and

VINCOM. Each pin connects to the internal multiplexer. The

multiplexer enables these inputs to be configured as input pairs.

The AD4115 can have up to 16 active channels. When more

than one channel is enabled, the channels are automatically

sequenced in order from the lowest enabled channel number to

the highest enabled channel number. The multiplexer output

connects to the input of the integrated true rail-to-rail buffers.

These buffers can be bypassed and the multiplexer output can

be directly connected to the ADC switched capacitor input. The

simplified input circuits are shown in Figure 25.

Enable the input buffers in the corresponding setup configuration

register for the voltage input channels (see Table 29).

Fully Differential Inputs

The differential inputs are paired together in the following

pairs: VIN0 and VIN1, VIN2 and VIN3, VIN4 and VIN5, VIN6

and VIN7, VIN8 and VIN9, VIN10 and VIN11, VIN12 and

VIN13, and VIN14 and VIN15.

Single-Ended Inputs

The user can measure up to 16 different single-ended voltage

inputs. In this case, each voltage input must be paired with the

VINCOM pin. Connect the VINCOM pin externally to the

AVSS pin.

VOLTAGE INPUTS

The AD4115 can be set up to have either 16 single-ended inputs

or eight fully differential inputs. The voltage divider on the AFE

has a division ratio of 10 and consists of precision matched

AVDD

AVSS

MULTIPLEXER

222kΩ

1MΩ

222kΩ 222kΩ

VIN0

VIN1

+

AVDD

AVSS

1MΩ

AVDD

AVSS

–

1MΩ

VINCOM

VBIAS–

222kΩ

222kΩ 222kΩ

Figure 25. Simplified Voltage Input Circuit

Rev. 0 | Page 22 of 51

Data Sheet

AD4115

where:

ABSOLUTE INPUT PIN VOLTAGES

N = 24 (the number of bits).

The AD4115 voltage input pins are specified for an accuracy of

10 V, specifically for the differential voltage between any two

voltage input pins.

V_INis the input voltage.

V

_REFis the reference voltage.

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage that results in

a code of 000 … 000, a zero differential input voltage that results

in a code of 100 … 000, and a positive full-scale input voltage

that results in a code of 111 … 111. The output code for any

analog input voltage is represented with the following equation:

The voltage input pins have separate specifications for the

absolute voltage that can be applied, and the unique design of

the voltage divider network of the analog front end enables

overvoltage robustness on the AD4115, which means the

allowed overvoltages vary depending on the AVDD supply.

Figure 26 shows the different degrees of robustness that can be

achieved for AVDD = 5 V. Figure 26 provides a visual

representation and guidance on how an overvoltage on a

voltage pin can affect the overall device accuracy.

Code = 2^{N – 1}× ((V_IN× 0.1/V_REF) + 1)

AD4115 REFERENCE OPTIONS

The AD4115 provides the reference option of either supplying

an external reference to the REF+ and REF− device pins using

AVDD – AVSS as the reference, or allowing use of the internal

2.5 V, low noise, low drift reference. To select the reference

source to be used by the analog input, set the REF_SELx bits,

Bits[5:4], in the corresponding setup configuration register

appropriately. The structure of the Setup Configuration Register 0

is shown in Table 10. By default, the AD4115 uses an external

reference on power-up.

The guaranteed accuracy section of Figure 26 shows the voltage

range that can be applied to a voltage input pin and achieve

guaranteed accuracy.

The no loss of accuracy sections show the voltage levels that can

be applied without degrading the accuracy of other channels.

The no damage to device sections show the allowable positive

and negative voltages that can be applied to a voltage input pin

without exceeding the absolute maximum. The performance of

other channels is degraded, but the performance recovers when

the overvoltage is removed. This voltage range is specified as an

absolute maximum rating of 65 V.

Internal Reference

The AD4115 includes a low noise, low drift, internal voltage

reference that has a 2.5 V output. The internal reference is

output on the REFOUT pin after the REF_EN bit in the ADC

mode register is set and is decoupled to AVSS with a 0.1 μF

capacitor. The AD4115 internal reference is disabled by default

on power-up.

Operation beyond the maximum operating conditions for

extended periods can affect product reliability.

AVDD = 5V

ABSOLUTE MAXIMUM RATING

+65V

NO DAMAGE TO DEVICE

External Reference

The AD4115 has a fully differential reference input applied

through the REF+ and REF− pins. Standard low noise, low drift

voltage references, such as the ADR4525, are recommended for

this use. Apply the external reference to the AD4115 reference

pins, as shown in Figure 27. Decouple the output of any external

reference to AVSS. As shown in Figure 27, the ADR4525 output

is decoupled with a 0.1 μF capacitor at the output for stability

purposes. The output is connected to a 4.7 μF capacitor that

acts as a reservoir for any dynamic charge required by the ADC

and is followed by another 0.1 μF decoupling capacitor at the

REF+ input. This capacitor is placed as close as possible to the

REF+ and REF− pins.

+30V

+20V

NO LOSS OF ACCURACY ON OTHER CHANNELS

GUARANTEED ACCURACY

–20V

–25V

NO LOSS OF ACCURACY ON OTHER CHANNELS

NO DAMAGE TO DEVICE

–65V

ABSOLUTE MAXIMUM RATING

Figure 26. Absolute Input Pin Voltages, AVDD = 5 V

The REF− pin is connected directly to the AVSS potential. When

an external reference is used instead of the internal reference

to supply the AD4115, ensure that the REFOUT pin is not

hardwired to AVSS, which can draw a large current on power-

up. The internal reference is controlled by the REF_EN bit (Bit

15) in the ADC mode register, as shown in Table 14. If the

internal reference is not used elsewhere in the application,

ensure that the REF_EN bit is disabled.

DATA OUTPUT CODING

When the ADC is configured for unipolar operation, the output

code is natural (straight) binary with a zero differential input

voltage that results in a code of 00 … 00, a midscale voltage that

results in a code of 100 … 000, and a full-scale input voltage

that results in a code of 111 … 111.

The output code for any input voltage is represented with the

following equation:

Code = (2^N× V_IN× 0.1)/V_REF

Rev. 0 | Page 23 of 51

AD4115

Data Sheet

AD4115

3V TO 18V

ADR4525²

2.5V VREF

REF+

REF–

40

39

0.1µF

4.7µF

1

2

ALL DECOUPLING IS TO AVSS.

ANY OF THE ADR45x FAMILY REFERENCES CAN BE USED.

ADR4525 ENABLES REUSE OF THE 3.3V ANALOG SUPPLY

NEEDED FOR AVDD TO POWER THE REFERENCE V

.

IN

Figure 27. ADR4525 Connected to AD4115 REF+ and REF− Pins

output driver. The extent to which the performance is affected

depends on the IOVDD voltage supply. Higher IOVDD

voltages create a wider logic output swing from the driver and

affect performance to a greater extent. This effect is further

exaggerated if the IOSTRENGTH bit of the interface mode

register is set at higher IOVDD levels (see Table 23).

BUFFERED REFERENCE INPUT

The AD4115 has true rail-to-rail, integrated, precision unity-

gain buffers on both ADC reference inputs. The buffers provide

high input impedance and allow high impedance external sources

to be directly connected to the reference inputs. The integrated

reference buffers can fully drive the internal reference switch

capacitor sampling network to simplify the reference circuit

requirements. Each reference input buffer amplifier is fully

chopped and minimizes the offset error drift and 1/f noise of the

buffer. When using a voltage reference, such as the ADR4525,

these buffers are not required because the reference has proper

decoupling and can drive the reference inputs directly.

External Crystal

If higher precision, lower jitter clock sources are required, the

AD4115 can use an external crystal to generate the master clock.

The crystal connects to the XTAL1 and XTAL2/CLKIO pins. The

FA-20H, a 16 MHz, 10 ppm, 9 pF crystal from Epson-Toyocom

is available in a surface-mount package and is acceptable for this

use. As shown in Figure 28, insert two capacitors (CX1 and CX2)

from the traces connecting the crystal to the XTAL1 and XTAL2/

CLKIO pins. These capacitors allow circuit tuning. Connect these

capacitors to the DGND pin. The value for these capacitors

depends on the length and capacitance of the trace connections

between the crystal and the XTAL1 and XTAL2/CLKIO pins.

Therefore, the values of these capacitors differ depending on

the PCB layout and the crystal used.

CLOCK SOURCE

The AD4115 uses a nominal master clock of 8 MHz and can

source the device sampling clock from one of the following

three sources:

•

An internal oscillator.

An external crystal. Use a 16 MHz crystal automatically

divided internally to set the 8 MHz clock.

An external clock source.

•

AD4115

1

CX1

All output data rates listed in this data sheet relate to a master

clock rate of 8 MHz. Using a lower clock frequency from, for

instance, an external source scales any listed data rate propor-

tionally. To achieve the specified data rates, particularly rates

for rejection of 50 Hz and 60 Hz, use a 8 MHz clock. To select

the master clock source, set the CLOCKSEL bits (Bits[3:2]) in the

ADC mode register, as shown in Table 14. The default

12

13

XTAL1

XTAL2/CLKIO

CX2

1

DECOUPLE TO DGND

Figure 28. External Crystal Connections

operation on power-up and reset of the AD4115 is to operate

with the internal oscillator. The user can use the SINC3_MAPx

bits in the filter configuration registers to fine tune the output

data rate and filter notch at low output data rates.

The external crystal circuitry can be sensitive to the SCLK edges

depending on the SCLK frequency, IOVDD voltage, crystal

circuitry layout, and the crystal used. During crystal startup, any

disturbances caused by the SLCK edges can cause double edges

on the crystal input, which results in invalid conversions until

the crystal voltage reaches a high enough level such that any

interference from the SCLK edges is insufficient to cause

double clocking. To avoid this double clocking, ensure that the

crystal circuitry reaches a sufficient voltage level after startup

before applying any serial clocks.

Internal Oscillator

The internal oscillator runs at 16 MHz and is internally divided

down to 2 MHz for the modulator. The internal oscillator can

be used as the ADC master clock and is the default clock source

for the AD4115, which is specified with an accuracy of −2.5% to

+2.5%.

The internal clock oscillator can be output on the XTAL2/

CLKIO pin. In this case, the clock output is driven to the

IOVDD logic level. This option can affect the AD4115 dc

performance because of the disturbance introduced by the

Because of the nature of the crystal circuitry, it is recommended

to perform empirical testing of the circuit under the required

conditions with the final PCB layout and crystal to ensure

correct operation.

Rev. 0 | Page 24 of 51

Data Sheet

AD4115

External Clock

The AD4115 can also use an externally supplied clock. In systems

where an externally supplied clock is used, the external clock is

routed to the XTAL2/CLKIO pin. In this configuration, the

XTAL2/ CLKIO pin accepts the externally sourced clock and

routes the clock input to the modulator. The logic level of this

clock input is defined by the voltage applied to the IOVDD pin.

Rev. 0 | Page 25 of 51

AD4115

Data Sheet

DIGITAL FILTER

The AD4115 has the following three flexible filter options to

optimize noise, settling time, and rejection:

Figure 31 shows the frequency domain filter response for the

sinc3 filter. The sinc3 filter has fast roll-off over frequency and

has wide notches for optimal notch frequency rejection.

•

The sinc5 + sinc1 filter.

The sinc3 filter.

Enhanced 50 Hz and 60 Hz rejection filters.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

50Hz AND 60Hz

POSTFILTER

SINC1

SINC5

SINC3

Figure 29. Digital Filter Block Diagram

To configure the filter and output data rate, set the appropriate

bits in the filter configuration register for the selected setup. Each

channel can use a different setup and, therefore, a different

filter and output data rate. See the Register Details section for

more information.

–120

0

50

100

FREQUENCY (Hz)

150

Figure 31. Sinc3 Filter Response

SINC5 + SINC1 FILTER

The output data rates with the accompanying settling time and

rms noise for the sinc3 filter are shown in Table 17. To fine tune

the output data rate for the sinc3 filter, set the SINC3_MAPx bit in

the appropriate filter configuration register. If this bit is set, the

filter register mapping changes to directly program the sinc3 filter

decimation rate. All other options are eliminated. To calculate the

data rate when on a single channel, use the following equation:

The sinc5 + sinc1 filter is targeted at multiplexed applications

and achieves single-cycle settling at output data rates of

≤10 kSPS. The sinc5 block output is fixed at the maximum rate

of 125 kSPS, and the sinc1 block output data rate can be varied

to control the final ADC output data rate. Figure 30 shows the

frequency domain response of the sinc5 + sinc1 filter at a

50 SPS output data rate. The sinc5 + sinc1 filter has narrow

notches and a slow roll-off over frequency.

Output Data Rate = f_MOD/(32 × FILTCONx[14:0])

where:

0

f

_MODis the modulator rate (MCLK/2) and is equal to 4 MHz.

FILTCONx[14:0] is the contents of the filter configuration

–20

–40

registers with the MSB excluded.

For example, to achieve an output data rate of 50 SPS with the

SINC3_MAPx bit enabled, set the FILTCONx register,

Bits[14:0], to a value of 2500.

–60

SINGLE-CYCLE SETTLING MODE

–80

To configure the AD4115 to be in a single-cycle settling mode,

set the SING_CYC bit in the ADC mode register so that only

fully settled data is output. This mode reduces the output data

rate to be equal to the ADC settling time for the selected output

data rate to achieve single-cycle settling. This bit has no effect

on the sinc5 + sinc1 filter at output data rates of ≤10 kSPS or

when multiple channels are enabled.

–100

–120

0

50

100

FREQUENCY (Hz)

150

Figure 30. Sinc5 + Sinc1 Filter Response at 50 SPS ODR

The output data rates with the accompanying settling time and

rms noise for the sinc5 + sinc1 filter are shown in Table 16.

Figure 32 shows a step on the analog input with single-cycle

settling mode disabled and the sinc3 filter selected. The analog

input requires at least three cycles after the step change for the

output to reach the final settled value.

SINC3 FILTER

The sinc3 filter achieves optimal single-channel noise performance

at lower rates and is most suitable for single-channel applications.

The sinc3 filter always has a settling time (t_SETTLE) equal to the

following equation:

t

_SETTLE= 3/Output Data Rate

Rev. 0 | Page 26 of 51

Data Sheet

AD4115

ANALOG

INPUT

ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS

FULLY

The enhanced filters provide rejection of 50 Hz and 60 Hz

simultaneously and allow the user to trade off settling time and

rejection. These filters can operate at up to 27.27 SPS or reject

up to 90 dB of 50 Hz 1 Hz and 60 Hz 1 Hz interference. These

filters postfilter the output of the sinc5 + sinc1 filter to operate.

For this reason, the user must select the sinc5 + sinc1 filter

when using the enhanced filters to achieve the specified settling

time and noise performance. Table 18 shows the enhanced

filter output data rates with the accompanying settling time,

rejection, and voltage input rms noise and resolution. Figure 34

to Figure 41 show the frequency domain plots of the responses

from the enhanced filters.

SETTLED

ADC

OUTPUT

1/ODR

Figure 32. Step Input Without Single-Cycle Settling

Figure 33 shows the same step on the analog input with single-

cycle settling enabled. The analog input requires at least a single

cycle for the output to be fully settled. The output data rate, as

RDY

indicated by the

of the filter at the selected output data rate.

signal, reduces to equal the settling time

ANALOG

INPUT

FULLY

SETTLED

ADC

OUTPUT

t_SETTLE

Figure 33. Step Input with Single Cycle Settling

Table 18. Enhanced Filter Output Data Rate, Settling Time, Rejection, and Voltage Input Noise

Output Data

Rate (SPS)

Settling Time Simultaneous Rejection of 50 Hz Noise

Peak-to-Peak

(ms)

36.67

40

1 Hz and 60 Hz 1 Hz (dB)¹

47

(µV rms) Resolution (Bits)

Comments

27.27

25

20

6.44

6.09

5.54

5.38

19.1

19.2

19.35

19.51

See Figure 34 and Figure 37

See Figure 35 and Figure 38

See Figure 36 and Figure 39

See Figure 40 and Figure 41

62

85

90

50

60

16.667

¹Master clock = 2.00 MHz.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

100

200

300

400

500

600

0

100

200

300

400

500

600

FREQUENCY (Hz)

Figure 34. 27.27 SPS ODR, 36.67 ms Settling Time

Figure 35. 25 SPS ODR, 40 ms Settling Time

Rev. 0 | Page 27 of 51

AD4115

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–100

100

200

300

400

500

600

40

45

50

55

60

65

70

FREQUENCY (Hz)

Figure 36. 20 SPS ODR, 50 ms Settling Time

Figure 39. 20 SPS ODR, 50 ms Settling Time (40 Hz to 70 Hz)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

40

45

50

55

60

65

70

0

100

200

300

400

500

600

FREQUENCY (Hz)

Figure 37. 27.27 SPS ODR, 36.67 ms Settling Time (40 Hz to 70 Hz)

Figure 40. 16.667 SPS ODR, 60 ms Settling Time

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

40

45

50

55

60

65

70

40

45

50

55

60

65

70

FREQUENCY (Hz)

Figure 38. 25 SPS ODR, 40 ms Settling Time (40 Hz to 70 Hz)

Figure 41. 16.667 SPS ODR, 60 ms Settling Time (40 Hz to 70 Hz)

Rev. 0 | Page 28 of 51

Data Sheet

AD4115

OPERATING MODES

The AD4115 has nine operating modes that can be set from the

ADC mode register and interface mode register (see Table 22

and Table 23). These modes include the following:

serial clocks are applied to the AD4115 to read the data-word,

the serial output register resets shortly before the next

conversion is complete, and the new conversion is placed in the

output serial register. The ADC must be configured for

continuous conversion mode to use continuous read mode. To

enable continuous read mode, set the CONTREAD bit in the

interface mode register. When this bit is set, the only serial

interface operations possible are reads from the data register. To

exit continuous read mode, issue a dummy read of the ADC data

•

Continuous conversion mode

Continuous read mode

Single conversion mode

Standby mode

Power-down mode

Four calibration modes

RDY

register command (0x44) while the

output is low.

CS

Alternatively, apply a software reset (64 serial clocks with

= 0

CONTINUOUS CONVERSION MODE

and DIN = 1) to reset the ADC and all register contents. The

dummy read and the software reset are the only commands that

the interface recognizes after the interface is placed in

continuous read mode. Hold DIN low in continuous read mode

until an instruction is to be written to the device.

Continuous conversion mode (see Figure 42) is the default

power-up mode. The AD4115 converts continuously, and the

RDY

bit in the status register goes low each time a conversion is

CS

RDY

output also goes low when a

complete. If

is low, the

conversion is complete. To read a conversion, write to the

communications register to indicate that the next operation is a

read of the data register. When the data-word is read from the

If multiple ADC channels are enabled, each channel is output

in turn with the status bits appended to the data if the

DATA_STAT bit is set in the interface mode register. The four

LSBs of the status register indicate the channel to which the

conversion corresponds.

RDY

data register, the DOUT/

pin goes high. The user can read

this register additional times, if required. However, ensure that

the data register is not accessed at the completion of the next

conversion. Otherwise, the new conversion word is lost.

SINGLE CONVERSION MODE

When several channels are enabled, the ADC automatically

sequences through the enabled channels and performs one

conversion on each channel. When all channels are converted,

the sequence starts again with the first channel. The channels

are converted in order from the lowest enabled channel to the

highest enabled channel. The data register updates as soon as

In single conversion mode (see Figure 44), the AD4115

performs a single conversion and is placed in standby mode

RDY

when the conversion is complete. The

indicate the completion of a conversion. When the data-word is

RDY

output goes low to

read from the data register, the

register can be read several times, if required, even when the

RDY

output goes high. The data

RDY

each conversion is available. The

output pulses low each

output goes high.

time a conversion is available and the user can then read the

conversion while the ADC converts the next enabled channel.

If several channels are enabled, the ADC automatically

sequences through the enabled channels and performs a

conversion on each channel. When the first conversion starts,

If the DATA_STAT bit in the interface mode register is set to 1,

the conversion data and the contents of the status register are

output each time the data register is read. The four LSBs of the

status register indicate the channel to which the conversion

corresponds.

RDY

the

conversion is available and

RDY

output goes high and remains high until a valid

CS

is low. When the conversion is

output goes low and the ADC selects the

available, the

next channel and begins a conversion. The user can read the

present conversion while the next conversion is performed.

When the next conversion is complete, the data register

updates, which allows the user a limited period in which to read

the conversion. When the ADC performs a single conversion

on each selected channel, the ADC returns to standby mode.

CONTINUOUS READ MODE

In continuous read mode (see Figure 43), it is not required to

write to the communications register before reading ADC data.

RDY

Apply only the required number of serial clocks after the

output goes low to indicate the end of a conversion. When the

RDY

If the DATA_STAT bit in the interface mode register is set to 1,

the contents of the status register and the conversion are output

each time the data register is read. The four LSBs of the status

register indicate the channel to which the conversion corresponds.

conversion is read, the

output returns high until the next

conversion is available. In this mode, the data can be read only

once. Ensure that the data-word is read before the next

conversion is complete. If the user has not read the conversion

before the completion of the next conversion, or if insufficient

Rev. 0 | Page 29 of 51

AD4115

Data Sheet

CS

0x44

DIN

DATA

DOUT/RDY

SCLK

Figure 42. SPI Communication in Continuous Conversion Mode

CS

0x02

0x0080

DIN

DATA

DOUT/RDY

SCLK

Figure 43. SPI Communication in Continuous Read Mode

CS

0x01

0x8010

0x44

DIN

DATA

DOUT/RDY

SCLK

Figure 44. SPI Communication in Single Conversion Mode

Rev. 0 | Page 30 of 51

Data Sheet

AD4115

initiates. When the calibration is complete, the contents of the

STANDBY MODE AND POWER-DOWN MODE

RDY

corresponding offset or gain register update, the

bit in the

In standby mode, most blocks are powered down. The LDO

regulators remain active so that the registers maintain the

individual register contents. The crystal oscillator remains

active if selected. To power down the clock in standby mode,

set the CLOCKSEL bits in the ADC mode register to 00

(internal oscillator).

RDY

CS

is

status register resets, the

output pin returns low (if

low), and the AD4115 reverts to standby mode.

During an internal offset calibration both modulator inputs are

connected internally to the selected negative analog input pin,

and the user must ensure that the voltage on the selected negative

analog input pin does not exceed the allowed limits and is free

from excessive noise and interference. A full-scale input voltage

automatically connects to the ADC input to perform an

internal full-scale calibration.

In power-down mode, all blocks are powered down, including

the LDO regulators. All registers lose the individual register

contents and the GPIO outputs are placed in three-state. To

prevent accidental entry into power-down mode, place the

ADC in standby mode first. Exiting power-down mode

For system calibrations, apply the system zero-scale (offset) and

system full-scale (gain) voltages to the input pins before

initiating the calibration modes. As a result, errors external to

the AD4115 are removed. The calibration range of the ADC

gain for a system full-scale calibration on a voltage input is

from 3.75 × V_REFto 10.5 × V_REF. If 10.5 × V_REFis greater than the

absolute input voltage specification for the applied AVDD, use the

specification as the upper limit instead of 10.5 × V_REF(see the

Specifications section).

CS

requires a serial interface reset (64 serial clocks with

= 0 and

DIN = 1). A delay of 500 µs is recommended before issuing a

subsequent serial interface command to allow the LDO

regulator to power up.

CALIBRATION MODES

The AD4115 allows the user to perform a two-point calibration

to eliminate any offset and gain errors. The following four

calibration modes are used to eliminate these offset and gain

errors on a per setup basis:

An internal zero-scale calibration only removes the offset error

of the ADC core. This calibration does not remove error from

the resistive front end. A system zero-scale calibration reduces

the offset error to the order of the noise on that channel.

•

Internal zero-scale calibration mode

Internal full-scale calibration mode

System zero-scale calibration mode

System full-scale calibration mode

From an operational point of view, treat a calibration like

another ADC conversion. Always perform an offset calibration,

if required, before a full-scale calibration. Set the system

Only one channel can be active during calibration. After each

conversion, the ADC conversion result is scaled using the ADC

calibration registers before being written to the data register.

RDY

software to monitor the

bit in the status register or the

RDY

output to determine the end of a calibration via a polling

sequence or an interrupt driven routine. All calibrations require

a time equal to the settling time of the selected filter and output

data rate to be completed.

The default value of the offset register is 0x800000, and the

default value of the gain register is 0x5XXXX0. The following

equations show the calculations used to scale the ADC conversion

result. In unipolar mode, the ideal relationship (not considering

the ADC gain error and offset error) is calculated as follows:

Any calibration can be performed at any output data rate.

Lower output data rates result in higher calibration accuracy

and the calibration is accurate for all output data rates. A new

offset calibration is required for a given channel if the reference

source for that channel is changed.

Data = ((0.075 × V_IN/V_REF) × 2²³– (Offset − 0x800000)) ×

(Gain/0x400000) × 2

In bipolar mode, the ideal relationship (not considering the

ADC gain error and offset error) is calculated as follows:

The AD4115 provides access to the on-chip offset and gain

calibration registers to allow the microprocessor to read the

device calibration coefficients and to write the stored

calibration coefficients. A read or write of the offset and gain

registers can be performed at any time except during an

internal or self calibration.

Data = ((0.075 × V_IN/V_REF) × 2²³– (Offset − 0x800000)) ×

(Gain/0x400000) + 0x800000

To start a calibration, write the relevant value to the Mode bits

RDY

in the ADC mode register Bits[6:4]. The DOUT/

pin and

bit in the status register go high when the calibration

RDY

the

Rev. 0 | Page 31 of 51

AD4115

Data Sheet

DIGITAL INTERFACE

The programmable functions of the AD4115 are accessible via

CHECKSUM PROTECTION

CS

the SPI. The serial interface consists of four signals: , DIN,

The AD4115 has a checksum mode that can be used to improve

interface robustness. Use the checksum to ensure that only valid

data is written to a register and to allow the data read from a

register to be validated. If an error occurs during a register

write, the CRC_ERROR bit is set in the status register. To

ensure that the register write is complete, read back the register

and verify the checksum.

RDY

SCLK, and DOUT/

. The DIN line transfers data into the

on-chip registers. The DOUT output accesses data from the on-

chip registers. SCLK is the serial clock input for the device. All

data transfers (either on DIN or on DOUT) occur with respect to

the SCLK signal.

RDY

The DOUT/

where the line goes low if

available in the data register. The pin resets high when a read

RDY

pin also functions as a data ready signal

CS

is low when a new data-word is

For CRC checksum calculations during a write operation, the

following polynomial is always used:

operation from the data register is complete. The

output

x⁸+ x²+ x + 1

also goes high before updating the data register to indicate

when not to read from the device to ensure that a data read is not

attempted while the register is updated. Take care to avoid

During read operations, the user can select between this

polynomial and a similar exclusive OR (XOR) function. The

XOR function requires less time to process on the host

microcontroller than the polynomial-based checksum. The

CRC_EN bits in the interface mode register enable and disable

the checksum and allow the user to select between the

polynomial checksum and the simple XOR checksum.

RDY

reading from the data register when the

go low. To ensure that no data read occurs, always monitor the

RDY RDY

signal is about to

output. Start reading the data register as soon as

goes low and ensure a sufficient SCLK rate such that the read is

CS

completed before the next conversion result.

is used to select a

The checksum is appended to the end of each read and write

transaction. The checksum calculation for the write transaction

is calculated using the 8-bit command word and the 8-bit to

24-bit data. For a read transaction, the checksum is calculated

using the command word and the 8-bit to 32-bit data output.

Figure 21 and Figure 22 show SPI write and read transactions,

respectively.

device and can be used to decode the AD4115 in systems where

several components are connected to the serial bus.

The timing diagrams in Figure 2 and Figure 3 show interfacing

CS

to the AD4115 using

to decode the device. Figure 2 shows

the timing for a read operation from the AD4115, and Figure 3

shows the timing for a write operation to the AD4115. The user

RDY

can read from the data register several times even though the

If checksum protection is enabled when continuous read mode

is active, an implied read data command of 0x44 occurs before

each data transmission, which must be accounted for when

calculating the checksum value. The checksum protection ensures

a nonzero checksum value even if the ADC data equals 0x000000.

output returns high after the first read operation. Ensure that

the read operations are complete before the next output update

occurs. In continuous read mode, the data register can be read

only once.

CS

To operate the serial interface in 3-wire mode, tie

low. In

lines are used to

communicate with the AD4115. The end of the conversion can

RDY

this case, the SCLK, DIN, and DOUT/

also be monitored using the

bit in the status register.

CS

To reset the serial interface, write 64 serial clocks with

= 0

and DIN = 1. A reset returns the interface to the state in which the

interface expects a write to the communications register. This

operation resets the contents of all registers to the power-on values.

Following a reset, wait 500 µs before addressing the serial interface.

Rev. 0 | Page 32 of 51

Data Sheet

AD4115

MSB is adjacent to the leftmost Logic 1 of the new result and

CRC CALCULATION

the procedure is repeated. This process is repeated until the

original data is reduced to a value less than the polynomial.

This value is the 8-bit checksum.

Polynomial

The checksum, which is eight bits wide, is generated using the

following polynomial:

Example of a Polynomial CRC Calculation—24-Bit Word:

0x654321 (Eight Command Bits and 16-Bit Data)

x⁸+ x²+ x + 1

To generate the checksum, the data is left shifted by eight bits

to create a number ending in eight Logic 0s. The polynomial is

aligned so that the MSB is adjacent to the leftmost Logic 1 of

the data. An XOR function is applied to the data to produce a

new, shorter number. The polynomial is aligned again so that the

An example of generating the 8-bit checksum using the

polynomial based checksum is as follows:

Initial value

011001010100001100100001

01100101010000110010000100000000

100000111

left shifted eight bits

polynomial

x⁸+ x²+ x + 1 =

100100100000110010000100000000

100000111

XOR result

polynomial

100011000110010000100000000

100000111

XOR result

polynomial

11111110010000100000000

100000111

XOR result

polynomial value

XOR result

1111101110000100000000

100000111

polynomial value

XOR result

111100000000100000000

100000111

polynomial value

XOR result

11100111000100000000

100000111

polynomial value

XOR result

1100100100100000000

100000111

polynomial value

XOR result

100101010100000000

100000111

polynomial value

XOR result

101101100000000

100000111

polynomial value

XOR result

1101011000000

100000111

polynomial value

XOR result

101010110000

100000111

polynomial value

XOR result

1010001000

100000111

polynomial value

checksum = 0x86.

10000110

Rev. 0 | Page 33 of 51

AD4115

Data Sheet

01100101

01000011

00100110

00100001

00000111

0x65

XOR Calculation

0x43

The checksum, which is eight bits wide, is generated by splitting

the data into bytes and then performing an XOR of the bytes.

XOR result

0x21

Example of an XOR Calculation—24-Bit Word: 0x654321

(Eight Command Bits and 16-Bit Data)

CRC

Using the previous polynomial example, divide the checksum

into three bytes (0x65, 0x43, and 0x21) which results in the

following XOR calculation:

Rev. 0 | Page 34 of 51

Data Sheet

AD4115

INTEGRATED FUNCTIONS

GENERAL-PURPOSE INPUT/OUTPUT

DOUT_RESET

The AD4115 has two general-purpose digital input/output pins

(GPIO0 and GPIO1) and two general-purpose digital output

pins (GPO2 and GPO3). The GPIO0 and GPIO1 pins can be

configured either as inputs or as outputs, but GPO2 and GPO3

are outputs only. To enable the GPIOx and GPOx pins, use the

following bits in the GPIOCON register: IP_EN0 and IP_EN1

(or OP_EN0 and OP_EN1) for GPIO0 and GPIO1, and

OP_EN2_3 for GPO2 and GPO3.

RDY

pin. By default,

this pin outputs the signal. During a data read, this pin outputs

the data from the register being read. When the read is complete,

signal after a short fixed period

of time (t₇). Note that this time may be too short for some

The serial interface uses a shared DOUT/

RDY

the pin reverts to output the

CS

microcontrollers and can be extended until the pin is brought

high. Set the DOUT_RESET bit in the interface mode register

CS

to 1 to extend the time and require that

must frame each

When the GPIO0 or GPIO1 pin is enabled as an input, the logic

level at the pin is contained in the GP_DATA0 bit or

read operation and complete the serial interface transaction.

SYNCHRONIZATION

Normal Synchronization

GP_DATA1 bit of the GPIOCON register, respectively. When

the GPIO0, GPIO1, GPO2, or GPO3 pin is enabled as an

output, the GP_DATA0, GP_DATA1, GP_DATA2, or

GP_DATA3 bit, respectively, determines the logic level output

at the pin. The logic levels for these pins are referenced to

AVDD and AVSS and the outputs have an amplitude of either

5 V or 3.3 V, depending on the AVDD − AVSS voltage.

When the SYNC_EN bit in the GPIOCON register is set to 1,

SYNC

the

SYNC

pin functions as a synchronization input pin. The

input allows the user to reset the modulator and the digital

filter without affecting any setup conditions on the device. This

reset allows the user to start gathering samples of the analog

SYNC

input from a known point in time, that is, the

rising

ERROR

The

pin can also be used as a general-purpose output if

edge. This pin must be low for at least one master clock cycle to

ensure that synchronization occurs. If multiple channels are

enabled, the sequencer is reset to the first enabled channel.

the ERR_EN bits in the GPIOCON register are set to 11. In this

configuration, the ERR_DAT bit in the GPIOCON register

ERROR

determines the logic level output at the

level for the pin is referenced to IOVDD and DGND, and the

ERROR

pin. The logic

If multiple AD4115 devices are operated from a common master

clock, the devices can be synchronized so that the corresponding

data registers are updated simultaneously. Synchronization is

typically completed after each AD4115 performs a calibration or

when calibration coefficients are loaded into the device calibration

pin resets the digital filter

and the analog modulator and places the AD4115 into a consistent

pin is low, the AD4115 remains in

rising edge, the modulator and filter

are taken out of this reset state and the device starts to gather

input samples again on the next master clock edge.

pin has an active pull-up.

EXTERNAL MULTIPLEXER CONTROL

If an external multiplexer is used to increase the channel count,

the multiplexer logic pins can be controlled using the AD4115

GPIOx and GPOx pins. When the MUX_IO bit is set in the

GPIOCON register, the timing of the GPIOx pins is controlled

by the ADC and the channel change is synchronized with the

ADC, which eliminates any need for external synchronization.

SYNC

registers. A falling edge on the

SYNC

known state. While the

SYNC

this state. On the

DELAY

The user can insert a programmable delay before the AD4115

starts to take samples. This delay allows an external amplifier or

multiplexer to settle and alleviates the specification requirements

for the external amplifier or multiplexer. Eight programmable

settings, ranging from 0 µs to 8 ms, can be set using the delay bits

in the ADC mode register (Register 0x01, Bits[10:8]).

The device exits reset on the master clock falling edge following

SYNC

the

are synchronized, take the

rising edge to ensure that all devices begin sampling on the

SYNC

low to high transition. Therefore, when multiple devices

SYNC

pin high on the master clock

master clock falling edge. If the

pin is not taken high in

sufficient time, a difference can occur of one master clock cycle

between the devices. That is, the instant at which conversions

are available differs from device to device by a maximum of one

master clock cycle.

16-BIT AND 24-BIT CONVERSIONS

By default, the AD4115 generates 24-bit conversions. However,

the width of the conversions can be reduced to 16 bits. Set

Bit WL16 in the interface mode register to 1 to round all data

conversions to 16 bits. Clear this bit to set the width of the data

conversions to 24 bits.

SYNC

The

command for a single channel when in normal synchronization

SYNC

input can also be used as a start conversion

mode. In this mode, the rising edge of the

RDY

input starts a

output indicates

conversion, and the falling edge of the

when the conversion is complete. The settling time of the filter

is required for each data register update. When the conversion

SYNC

is complete, bring the

next conversion start signal.

input low in preparation for the

Rev. 0 | Page 35 of 51

AD4115

Data Sheet

Alternate Synchronization Mode

ERROR

Input/Output

SYNC

In alternate synchronization mode, the

input operates as

ERROR

The

pin functions as an error input/output pin or as a

a start conversion command when several AD4115 channels are

enabled. Set the ALT_SYNC bit in the interface mode register to 1

to enable an alternate synchronization scheme. When the

general-purpose output pin. The ERR_EN bits in the

GPIOCON register determine the function of the pin.

ERROR

When the ERR_EN bits are set to 10, the

pin functions as

SYNC

input is taken low, the ADC completes the conversion

on the enabled channel, selects the next channel in the

SYNC

an open-drain error output. The three error bits in the status

register (ADC_ERROR, CRC_ERROR, and REG_ERROR) are

sequence, and then waits until the

input is taken high to

output goes low when the

ERROR

OR’ed, inverted, and mapped to the

ERROR

output. Therefore, the

output indicates that an error has occurred. Read the

status register to identify the error source.

ERROR

RDY

start the conversion. The

conversion is complete on the current channel, and the data

register is updated with the corresponding conversion. The

When the ERR_EN bits are set to 01, the

as an error input. The error output of another component can

ERROR

pin functions

SYNC

input does not interfere with the sampling on the

currently selected channel but allows the user to control the

instant at which the conversion begins on the next channel in

the sequence.

be connected to the AD4115

indicates when an error occurs on either the device or the

ERROR

input so that the AD4115

external component. The value on the

input is inverted

Alternate synchronization mode can only be used when several

channels are enabled. Do not use this mode when a single

channel is enabled.

and OR’ed with the errors from the ADC conversion, and the

result is indicated via the ADC_ERROR bit in the status register.

ERROR

The value of the

in the GPIO configuration register.

ERROR

input is reflected in the ERR_DAT bit

ERROR FLAGS

The status register contains three error bits (ADC_ERROR,

CRC_ERROR, and REG_ERROR) that flag errors in the ADC

conversion, errors in the CRC check, and errors caused by

The

input/output is disabled when the ERR_EN bits are

ERROR

set to 00. When the ERR_EN bits are set to 11, the

operates as a general-purpose output where the ERR_DAT bit

determines the logic level of the pin.

ERROR

changes in the registers, respectively. The

also indicate that an error has occurred.

output can

DATA_STAT FUNCTION

ADC_ERROR

The contents of the status register can be appended to each

conversion on the AD4115 using the DATA_STAT bit in the

IFMODE register. This function is useful if several channels are

enabled. Each time a conversion is output, the contents of the

status register are appended. The four LSBs of the status register

indicate to which channel the conversion corresponds. In

addition, the user can determine if any errors are flagged by the

error bits.

The ADC_ERROR bit in the status register flags any errors that

occur during the conversion process. The flag is set when an

overrange or underrange result is output from the ADC. The

ADC also outputs all 0s or all 1s when an undervoltage or

overvoltage occurs, respectively. This flag only resets when the

overvoltage or undervoltage is removed. This flag is not reset by

a read of the data register.

CRC_ERROR

IOSTRENGTH FUNCTION

If the CRC value that accompanies a write operation does not

correspond with the information sent, the CRC_ERROR flag is

set. The flag resets as soon as the status register is explicitly read.

The serial interface can operate with a power supply as low as

RDY

2 V. However, at this low voltage, the DOUT/

pin may not

have sufficient drive strength if there is moderate parasitic

capacitance on the PCB or if the SCLK frequency is high. The

IOSTRENGTH bit in the interface mode register increases the

REG_ERROR

The REG_ERROR flag is used in conjunction with the

REG_CHECK bit in the interface mode register. When the

REG_CHECK bit is set, the AD4115 monitors the values in

the on-chip registers. If a bit changes, the REG_ERROR bit is

set to 1. For writes to the on-chip registers, set the REG_CHECK

bit to 0. When the registers are updated, the REG_CHECK bit

can be set to 1. The AD4115 calculates a checksum of the on-chip

registers. If one register value has changed, the REG_ERROR bit is

set to 1. If an error is flagged, set the REG_CHECK bit to 0 to

clear the REG_ERROR bit in the status register. The register

check function does not monitor the data register, status

register, or interface mode register.

RDY

drive strength of the DOUT/

pin.

Rev. 0 | Page 36 of 51

Data Sheet

AD4115

The temperature sensor requires the input buffers to be enabled on

both inputs and for the internal reference to be enabled.

INTERNAL TEMPERATURE SENSOR

The AD4115 has an integrated temperature sensor that can be

used as a guide for the ambient temperature at which the device

is operating. The ambient temperature can be used for

diagnostic purposes or as an indicator of when the application

circuit must rerun a calibration routine to consider a shift in

operating temperature. Select the temperature sensor using the

multiplexer in the same way as an input channel.

To use the temperature sensor, calibrate the device in a known

temperature (25°C) and take a conversion as a reference point.

The temperature sensor has a nominal sensitivity of 477 μV/K.

The difference in this ideal slope and the slope measured

calibrates the temperature sensor. The temperature sensor is

specified with a 2°C typical accuracy after calibration at 25°C.

Calculate the temperature with the following equation:

Temperature = (Conversion Result/477 µV) − 273.15

Rev. 0 | Page 37 of 51

AD4115

Data Sheet

APPLICATIONS INFORMATION

supply lines to the AD4115 must use as wide a trace as possible

to provide low impedance paths and reduce glitches on the

power supply line. Shield the fast switching signals, such as

clocks, with digital ground to prevent radiating noise to other

sections of the PCB and never run clock signals near the inputs.

Avoid digital and analog signal crossover. Run traces on

opposite sides of the PCB at right angles to each other. This

layout reduces the effects of feedthrough on the PCB. A

microstrip technique is optimal but is not always possible with

a double sided PCB. In this technique, the component side of

the PCB is dedicated to ground planes and signals are placed on

the solder side.

GROUNDING AND LAYOUT

The inputs and reference inputs are differential and most

voltages in the analog modulator are common-mode voltages. The

high common-mode rejection of the device removes common-

mode noise on these inputs. The analog and digital supplies to

the AD4115 are independent and separately pinned out to

minimize coupling between the analog and digital sections of the

device. The digital filter provides rejection of broadband noise

on the power supplies, except at integer multiples of the master

clock frequency.

The digital filter also removes noise from the analog inputs

and reference inputs, provided that these noise sources do

not saturate the analog modulator. As a result, the AD4115 is

more immune to noise interference than a conventional high

resolution converter. However, because the resolution of the

AD4115 is high and the noise levels from the converter are low,

take care regarding grounding and layout.

Ensure that proper decoupling is used when using high resolution

ADCs. The AD4115 has two power supply pins, AVDD and

IOVDD. The AVDD pin is referenced to AVSS, and the

IOVDD pin is referenced to DGND. Decouple AVDD with a

10 µF tantalum capacitor in parallel with a 0.1 µF capacitor to

AVSS on each pin. Place the 0.1 µF capacitor as close as possible

to the device on each supply, ideally directly against the device.

Decouple IOVDD with a 10 µF tantalum capacitor in parallel

with a 0.1 µF capacitor to DGND. Decouple all inputs to AVSS.

If an external reference is used, decouple the REF+ and REF−

pins to AVSS.

The PCB that houses the ADC must be designed so that the

analog and digital sections are separated and confined to

certain areas of the PCB. A minimum etch technique is optimal

for ground planes and results in optimal shielding.

In any layout, the user must keep in mind the flow of currents

in the system to ensure that the paths for all return currents are

as close as possible to the paths that the currents took to reach

the corresponding destinations.

The AD4115 has two on-chip LDO regulators. One regulator

regulates the AVDD supply and the other regulates the IOVDD

supply. For the REGCAPA pin, use 1 µF and 0.1 µF capacitors

to decouple to AVSS. Similarly, for the REGCAPD pin, use a

1 µF capacitor to decouple to DGND.

Avoid running digital lines under the device. This layout

couples noise onto the die and allows the analog ground plane

to run under the AD4115 to prevent noise coupling. The power

Rev. 0 | Page 38 of 51

Data Sheet

AD4115

REGISTER SUMMARY

Table 19. Register Summary

Register Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x00

0x80

R/W

W

0x00

0x01

COMMS

Status

[7:0] WEN

[7:0] RDY

W

RA

R/

ADC_ERROR CRC_ERROR REG_ERROR

Channel

R

ADCMODE [15:8] REF_EN

[7:0] Reserved

Reserved

SING_CYC

Mode

Reserved

Delay

Reserved

DOUT_

0x2000 R/W

CLOCKSEL

IOSTRENGTH

0x02

0x03

IFMODE

[15:8]

Reserved

ALT_SYNC

Reserved

0x0000 R/W

RESET

[7:0] CONTREAD DATA_STAT REG_CHECK Reserved

CRC_EN

Reserved

WL16

REGCHECK [23:16]

REGISTER_CHECK[23:16]

REGISTER_CHECK[15:8]

REGISTER_CHECK[7:0]

Data[23:16]

0x000000 R

0x0800 R/W

[15:8]

[7:0]

0x04

Data

[23:0]

[15:8]

[7:0]

Data[15:8]

Data[7:0]

0x06

0x07

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

GPIOCON [15:8]

[7:0] GP_DATA3

[15:8]

Reserved

OP_EN2_3 MUX_IO

IP_EN0

SYNC_EN

OP_EN1

ERR_EN

ERR_DAT

GP_DATA2 IP_EN1

OP_EN0 GP_DATA1

GP_DATA0

ID

ID[15:8]

ID[7:0]

0x38DX

R

[7:0]

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH9

CH10

CH11

CH12

CH13

CH14

CH15

[15:8] CH_EN0

[7:0]

SETUP_SEL0

Reserved

INPUT0[9:8]

0x8001 R/W

0x0001 R/W

0x1000 R/W

INPUT0[7:0]

INPUT1[7:0]

INPUT2[7:0]

INPUT3[7:0]

INPUT4[7:0]

INPUT5[7:0]

INPUT6[7:0]

INPUT7[7:0]

INPUT8[7:0]

INPUT9[7:0]

Input10[7:0]

INPUT11[7:0]

INPUT12[7:0]

INPUT13[7:0]

INPUT14[7:0]

INPUT15[7:0]

[15:8] CH_EN1

[7:0]

SETUP_SEL1

SETUP_SEL2

SETUP_SEL3

SETUP_SEL4

SETUP_SEL5

SETUP_SEL6

SETUP_SEL7

SETUP_SEL8

SETUP_SEL9

SETUP_SEL10

SETUP_SEL11

SETUP_SEL12

SETUP_SEL13

SETUP_SEL14

SETUP_SEL15

Reserved

INPUT1[9:8]

INPUT2[9:8]

INPUT3[9:8]

INPUT4[9:8]

INPUT5[9:8]

INPUT6[9:8]

INPUT7[9:8]

INPUT8[9:8]

INPUT9[9:8]

INPUT10[9:8]

INPUT11[9:8]

INPUT12[9:8]

INPUT13[9:8]

INPUT14[9:8]

INPUT15[9:8]

INBUF0

[15:8] CH_EN2

[7:0]

[15:8] CH_EN3

[7:0]

[15:8] CH_EN4

[7:0]

[15:8] CH_EN5

[7:0]

[15:8] CH_EN6

[7:0]

[15:8] CH_EN7

[7:0]

[15:8] CH_EN8

[7:0]

[15:8] CH_EN9

[7:0]

[15:8] CH_EN10

[7:0]

[15:8] CH_EN11

[7:0]

[15:8] CH_EN12

[7:0]

[15:8] CH_EN13

[7:0]

[15:8] CH_EN14

[7:0]

[15:8] CH_EN15

[7:0]

SETUPCON0 [15:8]

[7:0]

Reserved

BI_UNIPOLAR0 REFBUF0+ REFBUF0−

REF_SEL0 Reserved

BI_UNIPOLAR1 REFBUF1+ REFBUF1−

REF_SEL1 Reserved

Rev. 0 | Page 39 of 51

SETUPCON1 [15:8]

[7:0]

INBUF1

AD4115

Data Sheet

Register Name

Bits

Bit 7

Bit 6

Reserved

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INBUF2

Reset

R/W

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

SETUPCON2 [15:8]

[7:0]

BI_UNIPOLAR2 REFBUF2+ REFBUF2−

0x1000 R/W

0x0500 R/W

REF_SEL2

Reserved

SETUPCON3 [15:8]

[7:0]

BI_UNIPOLAR3 REFBUF3+ REFBUF3−

INBUF3

INBUF4

INBUF5

INBUF6

INBUF7

REF_SEL3

REF_SEL4

SETUPCON4 [15:8]

[7:0]

BI_UNIPOLAR4 REFBUF4+ REFBUF4−

Reserved

SETUPCON5 [15:8]

[7:0]

BI_UNIPOLAR5 REFBUF5+ REFBUF5−

REF_SEL5

Reserved

SETUPCON6 [15:8]

[7:0]

BI_UNIPOLAR6 REFBUF6+ REFBUF6−

REF_SEL6

Reserved

SETUPCON7 [15:8]

[7:0]

BI_UNIPOLAR7 REFBUF7+ REFBUF7−

REF_SEL7

Reserved

ORDER0

Reserved

ORDER1

Reserved

ORDER2

Reserved

ORDER3

Reserved

ORDER4

Reserved

ORDER5

Reserved

ORDER6

Reserved

ORDER7

Reserved

FILTCON0 [15:8] SINC3_MAP0

[7:0] Reserved

ENHFILTEN0

ENHFILTEN1

ENHFILTEN2

ENHFILTEN3

ENHFILTEN4

ENHFILTEN5

ENHFILTEN6

ENHFILTEN7

ENHFILT0

ODR0

ODR1

ODR2

ODR3

ODR4

ODR5

ODR6

ODR7

FILTCON1 [15:8] SINC3_MAP1

[7:0] Reserved

ENHFILT1

ENHFILT2

ENHFILT3

ENHFILT4

ENHFILT5

ENHFILT6

ENHFILT7

FILTCON2 [15:8] SINC3_MAP2

[7:0] Reserved

FILTCON3 [15:8] SINC3_MAP3

[7:0] Reserved

FILTCON4 [15:8] SINC3_MAP4

[7:0] Reserved

FILTCON5 [15:8] SINC3_MAP5

[7:0] Reserved

FILTCON6 [15:8] SINC3_MAP6

[7:0] Reserved

FILTCON7 [15:8] SINC3_MAP7

[7:0] Reserved

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

OFFSET0

OFFSET1

OFFSET2

OFFSET3

OFFSET4

OFFSET5

OFFSET6

OFFSET7

GAIN0

[23:0]

OFFSET0[23:0]

0x800000 R/W

0x5XXXX0 R/W

OFFSET1[23:0]

OFFSET2[23:0]

OFFSET3[23:0]

OFFSET4[23:0]

OFFSET5[23:0]

OFFSET6[23:0]

OFFSET7[23:0]

GAIN0[23:0]

GAIN1[23:0]

GAIN2[23:0]

GAIN3[23:0]

GAIN4[23:0]

GAIN5[23:0]

GAIN6[23:0]

GAIN7[23:0]

GAIN1

GAIN2

GAIN3

GAIN4

GAIN5

GAIN6

GAIN7

Rev. 0 | Page 40 of 51

Data Sheet

AD4115

REGISTER DETAILS

COMMUNICATIONS REGISTER

Address: 0x00, Reset: 0x00, Name: COMMS

All access to the on-chip registers must start with a write to the communications register. This write determines which register is

accessed next and whether that operation is a write or a read.

Table 20. Bit Descriptions for COMMS

Bits

Bit Name

Settings

Description

Reset

0x0

Access

W

7

WEN

This bit must be low to begin communications with the ADC.

6

R/W

This bit determines if the command is a read or write operation.

0x0

W

0

1

Write command.

Read command.

[5:0]

RA

The register address bits determine the register to be read from or

written to as part of the current communication.

0x00

W

000000 Status register.

000001 ADC mode register.

000010 Interface mode register.

000011 Register checksum register.

000100 Data register.

000110 GPIO configuration register.

000111 ID register.

010000 Channel Register 0.

010001 Channel Register 1.

010010 Channel Register 2.

010011 Channel Register 3.

010100 Channel Register 4.

010101 Channel Register 5.

010110 Channel Register 6.

010111 Channel Register 7.

011000 Channel Register 8.

011001 Channel Register 9.

011010 Channel Register 10.

011011 Channel Register 11.

011100 Channel Register 12.

011101 Channel Register 13.

011110 Channel Register 14.

011111 Channel Register 15.

100000 Setup Configuration Register 0.

100001 Setup Configuration Register 1.

100010 Setup Configuration Register 2.

100011 Setup Configuration Register 3.

100100 Setup Configuration Register 4.

100101 Setup Configuration Register 5.

100110 Setup Configuration Register 6.

100111 Setup Configuration Register 7.

101000 Filter Configuration Register 0.

101001 Filter Configuration Register 1.

101010 Filter Configuration Register 2.

101011 Filter Configuration Register 3.

101100 Filter Configuration Register 4.

101101 Filter Configuration Register 5.

101110 Filter Configuration Register 6.

101111 Filter Configuration Register 7.

Rev. 0 | Page 41 of 51

AD4115

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

110000 Offset Register 0.

110001 Offset Register 1.

110010 Offset Register 2.

110011 Offset Register 3.

110100 Offset Register 4.

110101 Offset Register 5.

110110 Offset Register 6.

110111 Offset Register 7.

111000 Gain Register 0.

111001 Gain Register 1.

111010 Gain Register 2.

111011 Gain Register 3.

111100 Gain Register 4.

111101 Gain Register 5.

111110 Gain Register 6.

111111 Gain Register 7.

STATUS REGISTER

Address: 0x00, Reset: 0x80, Name: Status

The status register is an 8-bit register that contains ADC and serial interface status information. The register can optionally be appended

to the data register by setting the DATA_STAT bit in the interface mode register.

Table 21. Bit Descriptions for STATUS

Bits

Bit Name

Settings

Description

Reset

Access

7

RDY

The status of RDY is output to the DOUT/RDY pin when CS is low and a

register is not being read. This bit goes low when the ADC writes a new

result to the data register. In ADC calibration modes, this bit goes low

when the ADC writes the calibration result. RDY is brought high

automatically by a read of the data register.

0x1

R

0

1

New data result available.

Awaiting new data result.

6

ADC_ERROR

By default, this bit indicates if an ADC overrange or underrange occurred.

The ADC result is clamped to 0xFFFFFF for overrange errors and 0x000000

for underrange errors. This bit is updated when the ADC result is written

and is cleared at the next update after removing the overrange or

underrange condition.

0x0

R

0

1

No error.

Error.

5

4

CRC_ERROR

REG_ERROR

This bit indicates if a CRC error occurred during a register write. For

register reads, the host microcontroller determines if a CRC error

occurred. This bit is cleared by a read of this register.

No error.

CRC error.

0x0

R

0

1

This bit indicates if the content of one of the internal registers changes

from the value calculated when the register integrity check is activated.

The check is activated by setting the REG_CHECK bit in the interface

mode register. This bit is cleared by clearing the REG_CHECK bit.

0

1

No error.

Error.

Rev. 0 | Page 42 of 51

Data Sheet

AD4115

Bits

Bit Name

Settings

Description

Reset

0x0

Access

[3:0]

Channel

These bits indicate which channel was active for the ADC conversion

whose result is currently in the data register. This channel may be

different from the channel currently being converted. The mapping is a

direct map from the channel register. Therefore, Channel 0 results in 0x0

and Channel 15 results in 0xF.

R

0000 Channel 0.

0001 Channel 1.

0010 Channel 2.

0011 Channel 3.

0100 Channel 4.

0101 Channel 5.

0110 Channel 6.

0111 Channel 7.

1000 Channel 8.

1001 Channel 9.

1010 Channel 10.

1011 Channel 11.

1100 Channel 12.

1101 Channel 13.

1110 Channel 14.

1111 Channel 15.

ADC MODE REGISTER

Address: 0x01, Reset: 0x2000, Name: ADCMODE

The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets

RDY

the filter and the

bits and starts a new conversion or calibration.

Table 22. Bit Descriptions for ADCMODE

Bits

Bit Name

Settings

Description

Reset

Access

15

REF_EN

Enables internal reference and outputs a buffered 2.5 V to the REFOUT

pin.

0x0

R/W

0

1

Disabled.

Enabled.

Reserved

14

13

This bit is reserved. Set this bit to 0.

0x0

R/W

SING_CYC

This bit can be used when only a single channel is active to set the ADC to 0x1

only output at the settled filter data rate.

0

1

Disabled.

Enabled.

[12:11] Reserved

These bits are reserved. Set these bits to 0.

0x0

R

[10:8]

Delay

These bits allow a programmable delay to be added after a channel

switch to allow the settling of external circuitry before the ADC starts

processing its input.

R/W

000 0 µs.

001 8 µs.

010 32 µs.

011 80 µs.

100 200 µs.

101 400 µs.

110 1 ms.

111 2 ms.

7

Reserved

This bit is reserved. Set this bit to 0.

0x0

R

Rev. 0 | Page 43 of 51

AD4115

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

[6:4]

Mode

These bits control the operating mode of the ADC. See the Operating

Modes section for more information.

0x0

R/W

000 Continuous conversion mode.

001 Single conversion mode.

010 Standby mode.

011 Power-down mode.

100 Internal offset calibration.

101 Internal gain calibration

110 System offset calibration.

111 System gain calibration.

[3:2]

[1:0]

CLOCKSEL

Reserved

These bits select the ADC clock source. Selecting the internal oscillator

also enables the internal oscillator.

00 Internal oscillator.

01 Internal oscillator output on the XTAL2/CLKIO pin.

10 External clock input on the XTAL2/CLKIO pin.

11 External crystal on the XTAL1 pin and the XTAL2/CLKIO pin.

These bits are reserved. Set these bits to 0.

0x0

R/W

R

INTERFACE MODE REGISTER

Address: 0x02, Reset: 0x0000, Name: IFMODE

The interface mode register configures various serial interface options.

Table 23. Bit Descriptions for IFMODE

Bits

Bit Name

Settings

Description

Reset

0x0

Access

R

[15:13] Reserved

These bits are reserved. Set these bits to 0.

12

11

ALT_SYNC

This bit enables a different behavior of the SYNC pin to allow the use of

SYNC as a control for conversions when cycling channels.

0x0

R/W

0

1

Disabled.

Enabled.

IOSTRENGTH

This bit controls the drive strength of the DOUT/RDY pin. Set this bit when 0x0

reading from the serial interface at high speed with a low IOVDD supply

and moderate capacitance.

R/W

0

1

Disabled (default).

Enabled.

[10:9]

8

Reserved

These bits are reserved. Set these bits to 0.

See the DOUT_RESET section.

Disabled.

0x0

R

DOUT_RESET

R/W

0

1

Enabled.

7

6

CONTREAD

DATA_STAT

This bit enables the continuous read mode of the ADC data register. The ADC

must be configured in continuous conversion mode to use continuous

read mode. For more details, see the Operating Modes section.

Disabled.

Enabled.

0x0

R/W

0

1

This bit enables the status register to be appended to the data register

when read so that channel and status information are transmitted with

the data. Appending the status register is the only way to be sure that the

channel bits read from the status register correspond to the data in the

data register.

0

1

Disabled.

Enabled.

Rev. 0 | Page 44 of 51

Data Sheet

AD4115

Bits

Bit Name

Settings

Description

Reset

Access

5

REG_CHECK

This bit enables a register integrity checker that can be used to monitor

any change in the value of the user registers. To use this feature, configure all

other registers as desired with this bit cleared. Then, write to this register to

set the REG_CHECK bit to 1. If the contents of any of the registers change,

the REG_ERROR bit is set in the status register. To clear the error, set the

REG_CHECK bit to 0. Neither the interface mode register nor the ADC data

or status register is included in the registers that are checked. If a register must

have a new value written, this bit must first be cleared. Otherwise, an error

is flagged when the new register contents are written.

0x0

R/W

0

1

Disabled.

Enabled.

4

Reserved

CRC_EN

This bit is reserved. Set this bit to 0.

0x0

R

[3:2]

These bits enable CRC protection of register reads/writes. CRC increases

the number of bytes in a serial interface transfer by one.

0x00

R/W

00 Disabled.

01 XOR checksum enabled for register read transactions. Register writes still

use CRC with these bits set.

10 CRC checksum enabled for read and write transactions.

This bit is reserved. Set this bit to 0.

1

0

Reserved

WL16

0x0

R

This bit changes the ADC data register to 16 bits. The ADC is not reset by a 0x0

write to the interface mode register. Therefore, the ADC result is not

rounded to the correct word length immediately after writing to these

bits. The first new ADC result is correct.

R/W

0

1

24-bit data.

16-bit data.

REGISTER CHECK

Address: 0x03, Reset: 0x000000, Name: REGCHECK

The register check register is a 24-bit checksum calculated by exclusively OR'ing the contents of the user registers. The REG_CHECK bit

in the interface mode register must be set for this checksum to operate. Otherwise, the register reads 0.

Table 24. Bit Descriptions for REGCHECK

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

REGISTER_CHECK

This register contains the 24-bit checksum of user registers when the

REG_CHECK bit is set in the interface mode register.

0x000000

R

DATA REGISTER

Address: 0x04, Reset: 0x000000, Name: Data

The data register contains the ADC conversion result. The encoding is offset binary, or it can be changed to unipolar by the

RDY RDY

output high if it is low.

BI_UNIPOLARx bits in the setup configuration registers. Reading the data register brings the

bit and the

output is brought high, it is not possible to determine if another

RDY

The ADC result can be read multiple times. However, because the

ADC result is imminent. After the command to read the ADC register is received, the ADC does not write a new result into the data register.

Table 25. Bit Descriptions for Data

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

Data

This register contains the ADC conversion result. If DATA_STAT is set in

the interface mode register, the status register is appended to this

register when read, making this a 32-bit register.

0x000000

R

Rev. 0 | Page 45 of 51

AD4115

Data Sheet

GPIO CONFIGURATION REGISTER

Address: 0x06, Reset: 0x0800, Name: GPIOCON

The GPIO configuration register controls the general-purpose I/O pins of the ADC.

Table 26. Bit Descriptions for GPIOCON

Bits

Bit Name

Settings Description

Reset Access

[15:14] Reserved

Reserved.

0x0

R

R/W

13

12

OP_EN2_3

MUX_IO

GPO2/GPO3 output enable. This bit enables the GPO2 and GPO3 pins. The outputs

are referenced between AVDD and AVSS.

Disabled.

Enabled.

This bit allows the ADC to control an external multiplexer, using GPIO0, GPIO1,

GPO2, and GPO3 in sync with the internal channel sequencing. The analog input

pins used for a channel can still be selected on a per channel basis. Therefore, it is

possible to have a 16-channel multiplexer in front of each analog input pair

(VIN0/VIN1 to VIN14/VIN15), giving a total of 128 differential channels. However,

only 16 channels at a time can be automatically sequenced. Following the sequence

of 16 channels, the user changes the analog input to the next pair of input channels,

and it sequences through the next 16 channels. There is a delay function that allows

extra time for the analog input to settle, in conjunction with any switching of an

external multiplexer (see the delay bits in the ADC mode register).

0

1

0x0

R

11

SYNC_EN

SYNC input enable. This bit enables the SYNC pin as a sync input. When set low, the

SYNC pin holds the ADC and filter in reset until SYNC goes high. An alternative

operation of the SYNC pin is available when the ALT_SYNC bit in the interface mode

register is set. This mode works only when multiple channels are enabled. In such cases, a

low on the SYNC pin does not immediately reset the filter/modulator. Instead, if the

SYNC pin is low when the channel is due to be switched, the modulator and filter are

prevented from starting a new conversion. Bringing SYNC high begins the next

conversion. This alternative sync mode allows SYNC to be used while cycling

through channels.

0x1

R/W

0

1

Disabled.

Enabled.

[10:9]

ERR_EN

ERROR pin mode. These bits enable the ERROR pin as an error input/output.

0x0

R/W

00 Disabled.

01 Enable error input (active low). ERROR is an error input. The inverted readback state

is OR'ed with other error sources and is available in the ADC_ERROR bit in the status

register. The ERROR pin state can also be read from the ERR_DAT bit in this register.

10 Enable open-drain error output (active low). ERROR is an open-drain error output.

The status register error bits are OR'ed, inverted, and mapped to the ERROR pin.

ERROR pins of multiple devices can be wired together to a common pull-up resistor

so that an error on any device can be observed.

11 General-purpose output (active low). ERROR is a general-purpose output. The status

of the pin is controlled by the ERR_DAT bit in this register. This output is referenced

between IOVDD and DGND, as opposed to the AVDD and AVSS levels used by the

GPIOx and GPOx pins. The output has an active pull-up resistor in this case.

8

ERR_DAT

ERROR pin data. This bit determines the logic level at the ERROR pin if the pin is

enabled as a general-purpose output. This bit reflects the readback status of the pin

if the pin is enabled as an input.

0x0

R/W

0

1

Logic 0.

Logic 1.

7

6

GP_DATA3

GP_DATA2

GPIO1 data. This bit is the write data for GPIO1.

GPIO1 = 0.

GPIO1 = 1.

0x0

R/W

0

1

GPIO0 data. This bit is the write data for GPIO0.

0

1

GPIO0 = 0.

GPIO0 = 1.

Rev. 0 | Page 46 of 51

Data Sheet

AD4115

Bits

5

Bit Name

IP_EN1

Settings Description

This bit runs GPIO1 into an input. Input is equal to AVDD and AVSS.

Disabled.

Reset Access

0x0

R/W

0

1

Enabled.

4

3

2

IP_EN0

This bit runs GPIO0 into an input. Input is equal to AVDD and AVSS.

0

1

Disabled.

Enabled.

OP_EN1

OP_EN0

This bit runs GPIO1 into an output. Outputs are referenced between AVDD and AVSS.

0

1

Disabled.

Enabled.

This bit runs GPIO0 into an output. Outputs are referenced between AVDD and AVSS.

0

1

Disabled.

Enabled.

1

0

GP_DATA1

GP_DATA0

This bit is the readback or write data for GPIO1.

This bit is the readback or write data for GPIO0.

0x0

R/W

ID REGISTER

Address: 0x07, Reset: 0x38DX, Name: ID

The ID register returns a 16-bit ID. For the AD4115, this value is 0x38DX, where x is don’t care.

Table 27. Bit Descriptions for ID

Bits

Bit Name

Settings

Description

Reset

Access

[15:0] ID

Product ID. The ID register returns a 16-bit ID code that is specific to the ADC.

0x38DX

R

CHANNEL REGISTER 0 TO CHANNEL REGISTER 15

Address: 0x10 to 0x1F, Reset: 0x8001, Name: CH0 to CH15

The channel registers are 16-bit registers that select the currently active channels, the selected inputs for each channel, and the setup to

be used to configure the ADC for that channel. The layout for CH0 to CH15 is identical.

Table 28. Bit Descriptions for CH0 to CH15

Bits

Bit Name

Settings

Description

Reset Access

15

CH_ENx

This bit enables Channel x. If more than one channel is enabled, the ADC

automatically sequences between them.

0x1

R/W

0

1

Disabled.

Enabled.

[14:12] SETUP_SELx

These bits identify which of the eight setups is used to configure the ADC for

this channel. A setup comprises a set of four registers: a setup configuration register,

a filter configuration register, an offset register, and a gain register. All channels can

use the same setup, in which case the same 3-bit value must be written to these

bits on all active channels, or up to eight channels can be configured differently.

0x0

R/W

000 Setup 0.

001 Setup 1.

010 Setup 2.

011 Setup 3.

100 Setup 4.

101 Setup 5.

110 Setup 6.

111 Setup 7.

Reserved.

[11:10] Reserved

[9:0] INPUTx

0x0

0x1

R

R/W

These bits select which input pair is connected to the input of the ADC for this

channel.

0000000001 VIN0, VIN1.

0000010000 VIN0, VINCOM.

Rev. 0 | Page 47 of 51

AD4115

Data Sheet

Bits

Bit Name

Settings

Description

Reset Access

0000100000 VIN1, VIN0.

0000110000 VIN1, VINCOM.

0001000011 VIN2, VIN3.

0001010000 VIN2, VINCOM.

0001100010 VIN3, VIN2.

0001110000 VIN3, VINCOM.

0010000101 VIN4, VIN5.

0010010000 VIN4, VINCOM.

0010100100 VIN5, VIN4.

0010110000 VIN5, VINCOM.

0011000111 VIN6, VIN7.

0011010000 VIN6, VINCOM.

0011100110 VIN7, VIN6.

0011110000 VIN7, VINCOM.

0100001001 VIN8, VIN9.

0100010000 VIN8, VINCOM.

0100101000 VIN9, VIN8.

0100110000 VIN9, VINCOM.

0101001011 VIN10, VIN11.

0101010000 VIN10, VINCOM.

0101101010 VIN11, VIN10.

0101110000 VIN11, VINCOM.

0110001101 VIN12, VIN13.

0110010000 VIN12, VINCOM.

0110101100 VIN13, VIN12.

0110110000 VIN13, VINCOM.

0111001111 VIN14, VIN15.

0111010000 VIN14, VINCOM.

0111101110 VIN15, VIN14.

0111110000 VIN15, VINCOM.

1000110010 Temperature sensor.

1010110110 Reference.

SETUP CONFIGURATION REGISTER 0 TO SETUP CONFIGURATION REGISTER 7

Address: 0x20 to 0x27, Reset: 0x1000 Name: SETUPCON0 to SETUPCON7

The setup configuration registers are 16-bit registers that configure the reference selection, input buffers, and output coding of the ADC.

The layout for SETUPCON0 to SETUPCON7 is identical.

Table 29. Bit Descriptions for SETUPCON0 to SETUPCON7

Bits

Bit Name

Settings Description

Reset Access

[15:13] Reserved

These bits are reserved. Set these bits to 0.

Bipolar/unipolar. This bit sets the output coding of the ADC for Setup x.

Unipolar coded output.

Bipolar coded output.

REF+ buffer. This bit enables or disables the REF+ input buffer.

Disabled.

Enabled.

0x0

0x1

R

R/W

12

11

10

BI_UNIPOLARx

0

1

REFBUFx+

REFBUFx−

0x0

R/W

0

1

REF− buffer. This bit enables or disables the REF− input buffer.

0

1

Disabled.

Enabled.

Rev. 0 | Page 48 of 51

Data Sheet

AD4115

Bits

[9:8]

Bit Name

INBUFx

Settings Description

Input buffer. This bit enables or disables input buffers.

Reset Access

0x0

R/W

00 Disabled.

01 Reserved.

10 Reserved.

11 Enabled.

[7:6]

[5:4]

Reserved

REF_SELx

These bits are reserved. Set these bits to 0.

These bits allow the user to select the reference source for ADC conversion on

Setup 0.

0x0

R

R/W

00 External reference, REF .

10 Internal 2.5 V reference, must be enabled via ADCMODE (see Table 22).

11 AVDD − AVSS.

[3:0]

Reserved

These bits are reserved. Set these bits to 0.

0x0

R

FILTER CONFIGURATION REGISTER 0 TO FILTER CONFIGURATION REGISTER 7

Address: 0x28 to 0x2F, Reset: 0x0500, Name: FILTCON0 to FILTCON7

The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets

any active ADC conversion and restarts converting at the first channel in the sequence. The layout for FILTCON0 to FILTCON7 is identical.

Table 30. Bit Descriptions for FILTCON0 to FILTCON7

Bits

Bit Name

Settings

Description

Reset

Access

15

SINC3_MAPx

If this bit is set, the mapping of the filter register changes to directly

program the decimation rate of the sinc3 filter for Setup x. All other

options are eliminated. This bit allows fine tuning of the output data

rate and filter notch for rejection of specific frequencies. The data

rate when on a single channel equals f_MOD/(32 × FILTCON0[14:0]).

0x0

R/W

[14:12]

11

Reserved

These bits are reserved. Set these bits to 0.

0x0

R

ENHFILTENx

This bit enables various postfilters for enhanced 50 Hz/60 Hz

rejection for Setup x. The ORDERx bits must be set to 00 to select the

sinc5 + sinc1 filter for this function to work.

R/W

0

1

Disabled.

Enabled.

[10:8]

ENHFILTx

These bits select between various postfilters for enhanced 50 Hz/

60 Hz rejection for Setup x.

0x5

R/W

010 27 SPS, 47 dB rejection, 36.7 ms settling.

011 25 SPS, 62 dB rejection, 40 ms settling.

101 20 SPS, 86 dB rejection, 50 ms settling.

110 16.67 SPS, 92 dB rejection, 60 ms settling.

This bit is reserved. Set this bit to 0.

7

Reserved

ORDERx

0x0

R

[6:5]

These bits control the order of the digital filter that processes the

modulator data for Setup x.

R/W

00 Sinc5 + sinc1 (default).

11 Sinc3.

[4:0]

ODRx

These bits control the output data rate of the ADC and, therefore, the 0x0

settling time and noise for Setup x. Rates shown are for a single-channel

enabled sinc5 + sinc 1 filter. See Table 16 for multiple channels

enabled.

R/W

00000 125,000 SPS.

00001 125,000 SPS.

00010 62,500 SPS.

00011 62,500 SPS.

00100 31,250 SPS.

00101 25,000 SPS.

00110 15,625 SPS.

00111 10,417 SPS.

Rev. 0 | Page 49 of 51

AD4115

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

01000 5000 SPS.

01001 2500 SPS (3906 SPS for sinc3).

01010 1000 SPS (1157 SPS for sinc3).

01011 500 SPS (539 SPS for sinc3).

01100 395.6 SPS (401 SPS for sinc3).

01101 200 SPS (206 SPS for sinc3).

01110 100 SPS (102 SPS for sinc3).

01111 59.89 SPS (59.98 SPS for sinc3).

10000 49.92 SPS (50 SPS for sinc3).

10001 20 SPS.

10010 16.66 SPS (16.67 SPS for sinc3).

10011 10 SPS.

10100 5 SPS.

10101 2.5 SPS.

10110 2.5 SPS.

OFFSET REGISTER 0 TO OFFSET REGISTER 7

Address: 0x30 to 0x37, Reset: 0x800000, Name: OFFSET0 to OFFSET7

The offset (zero-scale) registers are 16-bit registers that can be used to compensate for any offset error in the ADC or in the system. The

layout for OFFSET0 to OFFSET7 is identical.

Table 31. Bit Descriptions for OFFSET0 to OFFSET7

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

OFFSETx

Offset calibration coefficient for Setup x.

0x800000 R/W

GAIN REGISTER 0 TO GAIN REGISTER 7

Address: 0x38 to0x3F, Reset: 0x5XXXX0, Name: GAIN0 to GAIN7

The full-scale gain registers are 16-bit registers that can be used to compensate for any gain error in the ADC or in the system. The layout

for GAIN0 to GAIN7 is identical.

Table 32. Bit Descriptions for GAIN0 to GAIN7

Bits

Bit Name

Settings

Description

Reset¹

0x5XXXX0 R/W

Access

[23:0]

GAINx

Gain calibration coefficient for Setup x.

¹X means don’t care.

Rev. 0 | Page 50 of 51

Data Sheet

AD4115

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

6.10

6.00 SQ

5.90

0.30

0.25

0.18

PIN 1

INDICATOR

AREA

PIN 1

IONS

INDICATOR AR EA OP T

(SEE DETAIL A)

31

40

30

1

0.50

BSC

4.70

EXPOSED

PAD

4.60 SQ

4.50

21

10

20

11

0.45

0.40

0.35

0.20 MIN

TOP VIEW

SIDE VIEW

BOTTOM VIEW

1.00

0.95

0.85

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5

Figure 45. 40-Lead Lead Frame Chip Scale Package [LFCSP]

6 mm × 6 mm Body and 0.95 mm Package Height

(CP-40-15)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

AD4115BCPZ

AD4115BCPZ-RL7

EVAL-AD4115SDZ

EVAL-SDP-CB1Z

−40°C to +105°C

40-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

CP-40-15

Evaluation Controller Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D023874-7/20(0)

Rev. 0 | Page 51 of 51


型号：	AD4115BCPZ-RL7
厂家：	ADI
描述：	Single-Supply, Multichannel, 125 kSPS, 24-Bit, Sigma-Delta ADC with Â±10 V Inputs
文件：	总51页 (文件大小：841K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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