AD4116_技术文档

Single Supply, 24-Bit, Sigma-Delta ADC with ± ±0 V,

±0 MΩ Inputs and Buffered Low Level Inputs

Data Sheet

AD4±±6

On-chip 2.5 V reference

FEATURES

0.12% accuracy at 25°C, 5 ppm/°C (typical) drift

Internal or external clock

Power supplies

AVDD to AVSS = 4.5 V to 5.5 V

IOVDD to DGND = 2 V to 5.5 V

Total I_DD(AVDD + IOVDD) = 6.15 mA

Temperature range: −40°C to +105°C

3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK)

SPI, QSPI, MICROWIRE, and DSP compatible

24-bit ADC with integrated analog front end

Fast and flexible output rate: 1.25 SPS to 62.5 kSPS

Channel scan data rate

12,422 SPS per channel (80 µs settling, sinc5 + sinc1)

20,618 SPS per channel (48 µs settling, sinc3)

85 dB rejection of 50 Hz and 60 Hz at 20 SPS per channel

10 V inputs, 6 differential or 11 single-ended

Pin absolute maximum rating: 65 V

Absolute input pin voltage up to 20 V

≥10 MΩ impedance

APPLICATIONS

Low level direct ADC input

Process control

PLC and DCS modules

Instrumentation and measurement

VREF inputs, 2 differential or 4 single-ended

Absolute input pin voltage, AVDD to AVSS

True rail-to-rail analog input buffers

FUNCTIONAL BLOCK DIAGRAM

AVDD REGCAPA

REF– REF+ REFOUT

IOVDD REGCAPD

BUFFERED

PRECISION

REFERENCE

1.8V

LDO

1.8V

LDO

VIN0

VIN1

INTERNAL

REFERENCE

VIN2

PRECISION

VOLTAGE

DIVIDER

VIN3

RAIL-TO-RAIL

VIN4

REFERENCE

VIN5

INPUT BUFFERS

CS

VIN6

>10MΩ

VIN7

SCLK

VIN8

VIN9

SERIAL

INTERFACE

DIGITAL

FILTER

DIN

VIN10

VINCOM

Σ-Δ ADC

DOUT/RDY

MUX

VBIAS–

SYNC

ERROR

ADCIN11

ADCIN12

ADCIN13

ADCIN14

ADCIN15

CRYSTAL AND INTERNAL

CLOCK OSCILLATOR

CIRCUITRY

GPIO CONTROL

TEMPERATURE

SENSOR

AVSS

DGND

GPIO0 GPIO1 GPO2 GPO3

XTAL1

CLKIO/XTAL2

Figure 1.

Rev. 0

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Technical Support

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AD4±±6

Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Calibration .................................................................................. 39

Digital Interface.............................................................................. 40

Checksum Protection ................................................................ 40

CRC Calculation......................................................................... 41

Integrated Functions...................................................................... 43

General-Purpose I/O ................................................................. 43

External Multiplexer Control................................................... 43

Delay ............................................................................................ 43

16-Bit/24-Bit Conversion.......................................................... 43

DOUT_RESET ........................................................................... 43

Synchronization ......................................................................... 43

Error Flags................................................................................... 44

DATA_STAT.............................................................................. 44

IOSTRENGTH ........................................................................... 44

Internal Temperature Sensor ................................................... 45

Applications Information ............................................................. 46

Grounding and Layout.............................................................. 46

Register Summary .......................................................................... 47

Register Details ............................................................................... 49

Communications Register ........................................................ 49

Status Register............................................................................. 50

ADC Mode Register................................................................... 51

Interface Mode Register ............................................................ 52

Register Check............................................................................ 53

Data Register............................................................................... 53

GPIO Configuration Register................................................... 54

ID Register .................................................................................. 55

Channel Register 0 to Channel Register 15............................ 55

Applications ...................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications .................................................................................... 4

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings ........................................................... 9

Thermal Resistance...................................................................... 9

Electrostatic Discharge (ESD) Ratings...................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions .......................... 10

Typical Performance Characteristics........................................... 13

Noise Performance and Resolution ............................................. 18

Theory of Operation ...................................................................... 21

Power Supplies............................................................................ 22

Digital Communication ............................................................ 22

AD4116 Reset.............................................................................. 22

Configuration Overview............................................................ 24

Circuit Description......................................................................... 27

Muliplexer ................................................................................... 27

Voltage Inputs............................................................................. 28

Low Level Inputs ........................................................................ 28

Absolute Input Pin Voltages..................................................... 28

Data Output Coding .................................................................. 29

AD4116 Reference...................................................................... 29

Buffered Reference Input .......................................................... 30

Clock Source ............................................................................... 30

Digital Filter .................................................................................... 32

Sinc5 + Sinc1 Filter .................................................................... 32

Sinc3 Filter................................................................................... 32

Single Cycle Settling................................................................... 33

Enhanced 50 Hz and 60 Hz Rejection Filters......................... 33

Operating Modes............................................................................ 36

Continuous Conversion Mode................................................. 36

Continuous Read Mode ............................................................ 37

Single Conversion Mode ........................................................... 38

Standby and Power-Down Modes........................................... 39

Setup Configuration Register 0 to Setup Configuration

Regsiter 7 ..................................................................................... 56

Filter Configuration Register 0 to Filter Configuration

Register 7 ..................................................................................... 57

Offset Register 0 to Offset Register 7....................................... 58

Gain Register 0 to Gain Register 7........................................... 58

Outline Dimensions....................................................................... 59

Ordering Guide .......................................................................... 59

REVISION HISTORY

12/2021—Revision 0: Initial Version

Rev. 0 | Page 2 of 59

Data Sheet

AD4±±6

GENERAL DESCRIPTION

The AD4116 is a low power, low noise, 24-bit, Σ-Δ analog-to-

digital converter (ADC) that integrates an analog front end

(AFE) for six fully differential or eleven single-ended, high

impedance (≥10 MΩ) bipolar, 10 V voltage inputs. The

additional two differential or four single-ended/pseudo

differential direct ADC inputs provides excellent performance

at lower input ranges.

The embedded 2.5 V, low drift (5 ppm/°C), band gap internal

reference (with output reference buffer) reduces the external

component count.

The digital filter allows flexible settings, including simultaneous

50 Hz and 60 Hz rejection at a 27.27 SPS output data rate. The

user can select between the different filter settings depending

on the demands of each channel in the application. The

automatic channel sequencer enables the ADC to switch

through each enabled channel.

The AD4116 also integrates key analog and digital signal

conditioning blocks to configure eight individual setups for

each analog input channel in use. As many as 16 channels can

be enabled at any time. A channel is defined as any of the standard

analog voltage inputs or a low level direct ADC input. The

AD4116 features a maximum channel scan rate of 12,422 SPS

(80 µs) using a sinc5 + sinc1 filter and 20,618 SPS per channel

(48 µs) using a sinc3 filter.

The precision performance of the AD4116 is achieved by

integrating the proprietary iPassives® technology from Analog

Devices, Inc.

The AD4116 operates with a single power supply, making it

easy to use in galvanically isolated applications. The specified

operating temperature range is −40°C to +105°C. The AD4116

is housed in a 40-lead, 6 mm × 6 mm LFCSP.

Rev. 0 | Page 3 of 59

AD4±±6

Data Sheet

SPECIFICATIONS

Single-supply: AVDD = 4.5 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = 0 V, DGND = 0 V, and VBIAS− = 0 V, unless otherwise noted.

Split-supply: AVDD = 2.5 V, IOVDD = 2 V to 3.6 V, AVSS = −2.5 V, DGND = 0 V, and VBIAS− = AVSS, unless otherwise noted.

Internal reference, internal master clock (MCLK) = 4 MHz, and T_A= T_MINto T_MAX(−40°C to +105°C), unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

VOLTAGE INPUTS (VINx)

Differential Input Voltage Range¹

Specified performance

Functional

−10

−V_REF× 10

−20

+10

+V_REF× 10

+20

V

MΩ

Absolute (Pin) Input Voltage

Input Impedance

Offset Error²

Offset Drift

Gain Error

Gain Drift

Integral Nonlinearity (INL)

Total Unadjusted Error (TUE)³

10

25°C, 192.5 µs settling

192.5 µs settling

25°C, 192.5 µs settling

192.5 µs settling

96.5 µs settling⁴

3

30

0.05

5

mV

µV/°C

% of FS

ppm/°C

% of FSR

0.02

25°C, internal reference

−40°C to +105°C, internal reference

192.5 µs settling

0.1

0.2

% of FSR

25°C, internal reference

−40°C to +105°C, internal reference

AVDD for input voltage (V_IN) = 1 V

V_IN= 1 V

0.1

0.15

% of FSR

dB

Power Supply Rejection

Common-Mode Rejection

At DC

70

80

120

dB

At 50 Hz, 60 Hz

20 Hz output data rate (post filter),

50 Hz 1 Hz and 60 Hz 1 Hz

Internal clock, 20 SPS ODR (post filter)

External clock, 20 SPS ODR (post filter)

See Table 7 and Table 8

Normal Mode Rejection⁴

71

85

90

dB

Resolution

Noise

See Table 7 and Table 8

LOW LEVEL INPUTS (ADCINx)

Differential Input Voltage Range

Absolute (Pin) Input Voltage

Input Buffers Disabled

Input Buffers Enabled

Analog Input Current

Input Buffers Disabled

Input Buffers Enabled

Offset Error²

Reference voltage (V_REF) = (REF+) − (REF−)

V_REF

V

AVSS − 0.05

AVSS

AVDD + 0.05

AVDD

V

12

2.7

60

µA/V

nA

µV

Offset Drift

Gain Error

Gain Drift

Integral Nonlinearity (INL)

Total Unadjusted Error (TUE)^{3, 4}

300

0.01

5

nV/°C

% of FS

ppm/°C

ppm of FSR

Internal full-scale calibration⁵, 25°C

15

Internal calibration

25°C, internal reference

−40°C to +105°C, internal reference

AVDD for V_IN= 1 V

0.03

0.06

90

% of FSR

dB

Power Supply Rejection

Common-Mode Rejection

At DC

V_IN= 0.1 V

85

120

dB

At 50 Hz, 60 Hz

20 Hz output data rate (post filter),

50 Hz 1 Hz and 60 Hz 1 Hz

Rev. 0 | Page 4 of 59

Data Sheet

AD4±±6

Parameter

Normal Mode Rejection⁴

Test Conditions/Comments

50 Hz 1 Hz and 60 Hz 1 Hz

Internal clock, 20 SPS ODR (post filter)

External clock, 20 SPS ODR (post filter)

See Table 9 and Table 10

Min

Typ

Max

Unit

71

85

90

dB

Resolution

Noise

See Table 9 and Table 10

ADC SPEED AND PERFORMANCE

ADC Output Data Rate (ODR)

No Missing Codes⁴

INTERNAL REFERENCE

Output Voltage

One channel, see Table 7

1.25

24

62,500

SPS

Bits

Excluding sinc3 filter ≥ 31.25 kHz notch

100 nF external capacitor to AVSS

REFOUT with respect to AVSS

REFOUT, T_A= 25°C

2.5

5

V

Initial Accuracy^{4, 6}

−0.12

−10

+0.12

+12

+10

% of V

ppm/°C

mA

Temperature Coefficient

Reference Load Current, I_LOAD

Power Supply Rejection

Load Regulation

AVDD (line regulation)

∆V_OUT/∆I_LOAD

e_N, 0.1 Hz to 10 Hz, 2.5 V reference

e_N, 1 kHz, 2.5 V reference

100 nF REFOUT capacitor

95

32

4.5

215

200

25

dB

ppm/mA

µV rms

nV/√Hz

µs

Voltage Noise

Voltage Noise Density

Turn On Settling Time

Short-Circuit Current, I_SC

EXTERNAL REFERENCE INPUTS

Differential Input Range

Absolute Voltage Limits

Buffers Disabled

mA

V_REF= (REF+) − (REF−)

1

2.5

AVDD

V

AVSS − 0.05

AVSS

AVDD + 0.05

AVDD

V

Buffers Enabled

REF Input Current

Buffers Disabled

Input Current

18

1.2

6

µA/V

Input Current Drift

External clock

Internal clock

nA/V/°C

Buffers Enabled

Input Current

Input Current Drift

Normal Mode Rejection

400

0.6

nA

nA/°C

See previous normal mode rejection

parameters within this table

Common-Mode Rejection

TEMPERATURE SENSOR

Accuracy

95

dB

After user calibration at 25°C

With respect to AVSS

2

477

°C

µV/K

Sensitivity

GENERAL-PURPOSE OUTPUTS

(GPIO0, GPIO1, GPO2, AND GPO3)

Floating State Output Capacitance

Output Voltage⁴

High, V_OH

5

pF

Source current (I_SOURCE) = 200 µA

Sink current (I_SINK) = 800 µA

AVDD − 1

V

Low, V_OL

AVSS + 0.4

CLOCK

Internal Clock

Frequency

Accuracy

Duty Cycle

Output Low Voltage, V_OL

Output High Voltage, V_OH

4

MHz

%

V

−2.5%

+2.5%

0.4

50

0.8 × IOVDD

Rev. 0 | Page 5 of 59

AD4±±6

Data Sheet

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Crystal

Frequency

14

16

10

4

16.384

MHz

µs

MHz

%

Start-Up Time

External Clock (CLKIO)

Duty Cycle

4.096

70

30

50

LOGIC INPUTS

Input Voltage⁴

High, V_INH

2 V ≤ IOVDD < 2.3 V

2.3 V ≤ IOVDD ≤ 5.5 V

2 V ≤ IOVDD < 2.3 V

2.3 V ≤ IOVDD ≤ 5.5 V

IOVDD ≥ 2.7 V

0.65 × IOVDD

0.7 × IOVDD

V

Low, V_INL

0.35 × IOVDD

0.7

0.25

0.2

+10

Hysteresis

0.08

0.04

−10

IOVDD < 2.7 V

V

µA

Leakage Current

LOGIC OUTPUT (DOUT/RDY)

Output Voltage⁴

High, V_OH

IOVDD ≥ 4.5 V, I_SOURCE= 1 mA

2.7 V ≤ IOVDD < 4.5 V, I_SOURCE= 500 µA

IOVDD < 2.7 V, I_SOURCE= 200 µA

IOVDD ≥ 4.5 V, I_SINK= 2 mA

2.7 V ≤ IOVDD < 4.5 V, I_SINK= 1 mA

IOVDD < 2.7 V, I_SINK= 400 µA

Floating state

0.8 × IOVDD

V

µA

pF

Low, V_OL

0.4

+10

Leakage Current⁴

Output Capacitance

POWER REQUIREMENTS

Power Supply Voltage

AVDD to AVSS

AVSS to DGND

IOVDD to DGND

IOVDD to AVSS

−10

Floating state

10

4.5

−2.75

2

5.5

0

5.5

6.35

V

For AVSS < DGND

POWER SUPPLY CURRENTS⁷

All outputs unloaded, digital inputs

connected to IOVDD or DGND

Full Operating Mode

AVDD Current

IOVDD Current

Including internal reference

Internal clock

All V_IN= 0 V

5.3

0.85

45

6.63

1.12

mA

µA

Standby Mode

Power-Down Mode

POWER DISSIPATION

Full Operating Mode

Standby Mode

All V_IN= 0 V

20

µA

31

223

100

mW

µW

Power-Down Mode

¹The full specification is guaranteed for a differential input signal of 10 V. The device is functional up to a differential input signal of V_REF× 10. However, the specified

absolute (pin) voltage must not be exceeded for proper function.

²Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. An internal zero-scale calibration

at low level inputs reduces the offset error in the order of the noise for the programmed output data rate selected.

³To improve performance, use an external reference with better accuracy and lower temperature coefficient.

⁴Specification is not production tested but is supported by characterization data at the initial product release.

⁵Following a system full-scale calibration, the gain error is reduced to the order of the noise for the programmed output data rate.

⁶This specification includes moisture sensitivity level (MSL) preconditioning effects.

⁷This specification is with no load on the REFOUT pin and the digital output pins.

Rev. 0 | Page 6 of 59

Data Sheet

AD4±±6

TIMING CHARACTERISTICS

IOVDD = 2 V to 5.5 V (single-supply), IOVDD = 2 V to 3.6V (split-supply), Input Logic 0 = 0 V, Input Logic 1 = IOVDD, and capacitive

load (C_LOAD) = 20 pF, unless otherwise noted.

Table 2.

Parameter

Limit at T_MIN, T_MAX

Unit

Description^{1, 2}

SCLK

t₃

t₄

25

ns min

SCLK high pulse width

SCLK low pulse width

READ OPERATION

t₁

0

ns min

ns max

ns min

ns max

ns min

ns max

ns min

CS falling edge to DOUT/RDY active time

IOVDD = 4.75 V to 5.5 V

IOVDD = 2 V to 3.6 V

SCLK active edge to data valid delay⁴

IOVDD = 4.75 V to 5.5 V

IOVDD = 2 V to 3.6 V

Bus relinquish time after CS inactive edge

15

40

0

12.5

25

2.5

20

0

3

t₂

5

t₅

t₆

t₇

SCLK inactive edge to CS inactive edge

10

SCLK inactive edge to DOUT/RDY high/low

WRITE OPERATION

t₈

0

8

5

ns min

CS falling edge to SCLK active edge setup time⁴

Data valid to SCLK edge setup time

Data valid to SCLK edge hold time

CS rising edge to SCLK edge hold time

t₉

t₁₀

t₁₁

¹Sample tested during initial release to ensure compliance.

²See Figure 2 and Figure 3.

³This parameter is defined as the time required for the output to cross the V_OLor V_OHlimits.

⁴The SCLK active edge is the falling edge of SCLK.

5

RDY

DOUT/

while DOUT/

enabled, the digital word can be read only once.

returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required,

RDY

is high. However, care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is

Rev. 0 | Page 7 of 59

AD4±±6

Data Sheet

Timing Diagrams

CS (I)

t₆

t₁

t

5

MSB

LSB

t₇

DOUT/RDY (O)

t₂

t₃

SCLK (I)

t

4

I = INPUT, O = OUTPUT

Figure 2. Read Cycle Timing Diagram

CS (I)

t

8

11

SCLK (I)

DIN (I)

t

9

t

10

MSB

LSB

I = INPUT, O = OUTPUT

Figure 3. Write Cycle Timing Diagram

Rev. 0 | Page 8 of 59

Data Sheet

AD4±±6

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Table 3.

Parameter

Rating

AVDD to AVSS

AVDD to DGND

IOVDD to DGND

IOVDD to AVSS

AVSS to DGND

VINx to AVSS

ADCINx to AVSS

Reference Input Voltage to AVSS

Digital Input Voltage to DGND

Digital Output Voltage to DGND

Digital Input Current

Temperature

−0.3 V to +6.5 V

−0.3 V to +7.5 V

−3.25 V to +0.3 V

−65 V to +65 V

−0.3 V to AVDD + 0.3 V

−0.3 V to IOVDD + 0.3 V

10 mA

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

θ_JCis the thermal resistance from the junction to the package case.

Table 4. Thermal Resistance

Package Type¹

θ_JA

θ_JC

2.63

Unit

2

3

CP-40-15

34

°C/W

¹4-layer JEDEC PCB.

²Thermal impedance simulated values are based on JEDEC 2S2P thermal test

PCB with 16 thermal vias. θ_JAis specified for a device soldered on a JEDEC

test PCB for surface-mount packages. See JEDEC JESD-51.

³A cold plate is attached to the PCB bottom and measured at the exposed paddle.

Operating Range

Storage Range

Maximum Junction

Lead Soldering, Reflow

−40°C to +105°C

−65°C to +150°C

150°C

ELECTROSTATIC DISCHARGE (ESD) RATINGS

260°C

The following ESD information is provided for handling of

ESD-sensitive devices in an ESD protected area only.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.

Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.

ESD Ratings for AD4116

Table 5. AD4116, 40-Lead LFCSP

ESD Model

Withstand Threshold (V)

Class

1C

C3

HBM

CDM

1000

1250

ESD CAUTION

Rev. 0 | Page 9 of 59

AD4±±6

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VINCOM

VIN0

1

2

3

4

5

6

7

8

9

30 VIN8

29 VIN7

VIN1

28 VIN6

VIN2

VIN3

REFOUT

REGCAPA

AVSS

27 VIN5

AD4116

26 VIN4

TOP VIEW

25 GPO2

24 GPIO1

23 GPIO0

22 REGCAPD

21 DGND

(Not to Scale)

AVDD

DNC 10

NOTES

1. DO NOT CONNECT. DO NOT CONNECT ANYTHING TO THIS PIN.

2. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A SIMILAR PAD

ON THE PCB UNDER THE EXPOSED PAD TO CONFER MECHANICAL

STRENGTH TO THE PACKAGE AND FOR HEAT DISSIPATION. THE

EXPOSED PAD MUST BE CONNECTED TO AVSS THROUGH THIS PAD

ON THE PCB.

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Mnemonic¹

Type²Description

Pin No.

1

VINCOM

AI

Voltage Input Common. Voltage inputs are referenced to the VINCOM pin when configured as single-

ended (connect the VINCOM pin to analog ground), or a negative input of an input pair with VIN10 in

differential configuration.

2

3

4

5

6

7

VIN0

AI

Voltage Input 0. Input referenced to VINCOM in single-ended configuration, or a positive input of an

input pair with VIN1 in differential configuration.

Voltage Input 1. Input referenced to VINCOM in single-ended configuration, or a negative input of an

input pair with VIN0 in differential configuration.

Voltage Input 2. Input referenced to VINCOM in single-ended configuration, or a positive input of an

input pair with VIN3 in differential configuration.

Voltage Input 3. Input referenced to VINCOM in single-ended configuration, or a negative input of an

input pair with VIN2 in differential configuration.

Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS. Decouple the REFOUT

pin to AVSS using a 0.1 µF capacitor.

Analog Low Dropout (LDO) Regulator Output. Decouple the REGCAPA pin to AVSS using a 1 µF

capacitor and a 0.1 µF capacitor.

VIN1

AI

VIN2

AI

VIN3

AI

REFOUT

REGCAPA

AO

8

9

10

11

AVSS

AVDD

DNC

P

N/A

AI

Negative Analog Supply. This supply ranges from −2.75 V to 0 V and is nominally set to 0 V.

Analog Supply Voltage. This voltage ranges from 4.5 V to 5.5 V with respect to AVSS.

Do Not Connect. Do not connect anything to this pin.

Voltage Bias Negative. The VBIAS− pin is setting the bias voltage for the voltage input analog front-end.

Connect the VBIAS− pin to AVSS.

VBIAS−

12

13

XTAL1

XTAL2/CLKIO AI/DI

AI

Input 1 for Crystal.

Input 2 for Crystal/Clock Input or Output. See the CLOCKSEL bit settings in the ADCMODE register for

more information.

14

DOUT/RDY

DO

Serial Data Output/Data Ready Output. This pin serves a dual purpose. It functions as a serial data

output pin to access the output shift register of the ADC. The output shift register can contain data

from any of the on-chip data or control registers. The data-word/control word information is placed on

the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the

DOUT/RDY output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as

a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the

conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used

as an interrupt to a processor, indicating that valid data is available.

Rev. 0 | Page 10 of 59

Data Sheet

AD4±±6

Mnemonic¹

Type²Description

Pin No.

15

DIN

DI

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the

control registers in the ADC, with the register address (RA) bits of the communications register

identifying the appropriate register. Data is clocked in on the rising edge of SCLK.

16

17

SCLK

CS

DI

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. SCLK has a Schmitt

triggered input.

Chip Select Input. The CS pin is an active low logic input used to select the ADC. Use CS to select the

ADC in systems with more than one device on the serial bus. CS can be hardwired low, allowing the

ADC to operate in 3-wire mode with SCLK, DIN, and DOUT/RDY used to interface with the device. When

CS is high, the DOUT/RDY output is tristated.

18

ERROR

DI/O

Error Input/Output or General-Purpose Output. The ERROR pin can be used in one of the following

three modes:

Active low error input mode. This mode sets the ADC_ERROR bit in the status register.

Active low, open-drain error output mode. The status register error bits are mapped to the ERROR pin.

The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error

on any device can be observed.

General-purpose output mode. The status of the pin is controlled by the ERR_DAT bit in the GPIOCON

register. The pin is referenced between IOVDD and DGND.

19

20

SYNC

DI

P

Synchronization Input. Allows synchronization of the digital filters and analog modulators when using

multiple AD4116 devices.

Digital I/O Supply Voltage. The IOVDD voltage ranges from 2 V to 5.5 V (nominal). IOVDD is

independent of AVDD. For example, IOVDD can be operated at 3.3 V when AVDD equals 5 V, or vice

versa. If AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V.

IOVDD

21

22

DGND

REGCAPD

P

AO

Digital Ground.

Digital LDO Regulator Output. The REGCAPD pin is for decoupling purposes only. Decouple the

REGCAPD pin to DGND using a 1 µF capacitor.

23

24

GPIO0

GPIO1

DI/O

General-Purpose Input and Output 0. Logic input and output on the GPIO0 pin is referred to the AVDD

and AVSS supplies.

General-Purpose Input and Output 1. Logic input and output on the GPIO1 pin is referred to the AVDD

and AVSS supplies.

25

26

GPO2

VIN4

DO

AI

General-Purpose Output 2. Logic output on the GPIO2 pin is referred to the AVDD and AVSS supplies.

Voltage Input 4. Input referenced to VINCOM in single-ended configuration, or a positive input of an

input pair with VIN5 in differential configuration.

27

28

29

30

31

32

33

34

35

36

37

VIN5

AI

Voltage Input 5. Input referenced to VINCOM in single ended configuration, or a negative input of an

input pair with VIN4 in differential configuration.

Voltage Input 6. Input referenced to VINCOM in single-ended configuration, or a positive input of an

input pair with VIN7 in differential configuration.

Voltage Input 7. Input referenced to VINCOM in single-ended configuration, or a negative input of an

input pair with VIN6 in differential configuration.

Voltage Input 8. Input referenced to VINCOM in single-ended configuration, or a positive input of an

input pair with VIN9 in differential configuration.

Voltage Input 9. Input referenced to VINCOM in single-ended configuration, or a negative input of an

input pair with VIN8 in differential configuration.

Voltage Input 10. Input referenced to VINCOM in single-ended configuration, or a positive input of an

input pair with VINCOM in differential configuration.

Low Level ADC Input 11. Input referenced to ADCIN15 in pseudo differential input, or a positive input of

an input pair with ADCIN12 in differential configuration.

Low Level ADC Input 12. Input referenced to ADCIN15 in pseudo differential input, or a negative input

of an input pair with ADCIN11 in differential configuration.

Low Level ADC Input 13. Input referenced to ADCIN15 in pseudo differential input, or a positive input of

an input pair with ADCIN14 in differential configuration.

Low Level ADC Input 14. Input referenced to ADCIN15 in pseudo differential input, or a negative input

of an input pair with ADCIN13 in differential configuration.

Low Level ADC Input 15. Low level inputs are referenced to the ADCIN15 pin when configured as

pseudo differential input, or a negative input of an input pair with any of the low level input pins in a

differential input.

VIN6

VIN7

VIN8

VIN9

VIN10

ADCIN11

ADCIN12

ADCIN13

ADCIN14

ADCIN15

38

GPO3

DO

General-Purpose Output 3. Logic output on the GPO3 pin is referred to the AVDD and AVSS supplies.

Rev. 0 | Page 11 of 59

AD4±±6

Data Sheet

Mnemonic¹

Type²Description

Pin No.

39

REF−

AI

Reference Input Negative Terminal. REF− can span from AVSS to AVDD − 1 V. Reference can be selected

through the REF_SELx bits in the setup configuration registers.

40

REF+

AI

Reference Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+

can span from AVDD to AVSS + 1 V. Reference can be selected through the REF_SELx bits in the setup

configuration registers.

EP

P

Exposed Pad. Solder the exposed pad to a similar pad on the PCB under the exposed pad to confer

mechanical strength to the package and for heat dissipation. The exposed pad must be connected to

AVSS through this pad on the PCB.

¹Note that, throughout this data sheet, the dual function pin mnemonics are referenced by the relevant function only.

²AI means analog input, AO means analog output, P means power supply, N/A means not applicable, DI means digital input, DO means digital output, and DI/O means

bidirectional digital input and output.

Rev. 0 | Page 12 of 59

Data Sheet

AD4±±6

TYPICAL PERFORMANCE CHARACTERISTICS

8389012

180

160

140

120

100

80

8389010

8389008

8389006

8389004

8389002

8389000

8388998

8388996

60

40

20

0

8388997 8388999 8389001 8389003 8389005 8389007 8389009 8389011

200

400

600

800

1000

0

SAMPLE NUMBER

ADC CODE

Figure 5. Noise (Voltage Input, Output Data Rate = 1.25 SPS)

Figure 8. Histogram (Voltage Input, Output Data Rate = 1.25 SPS)

8388000

300

250

200

150

100

50

8387950

8387900

8387850

8387800

8387750

8387700

8387650

8387600

0

200

400

600

800

1000

0

SAMPLE NUMBER

ADC CODE

Figure 6. Noise (Voltage Input, Output Data Rate = 5.194 kSPS)

Figure 9. Histogram (Voltage Input, Output Data Rate = 5.194 kSPS)

8391000

160

140

120

100

80

8390900

8390800

8390700

8390600

8390500

8390400

8390300

8390200

8390100

60

40

20

0

200

400

600

800

1000

0

SAMPLE NUMBER

ADC CODE

Figure 10. Histogram (Voltage Input, Output Data Rate = 62.5 kSPS)

Figure 7. Noise (Voltage Input, Output Data Rate = 62.5 kSPS)

Rev. 0 | Page 13 of 59

AD4±±6

Data Sheet

8388428

900

800

700

600

500

400

300

200

100

0

8388427

8388426

8388425

0

200

400

600

800

1000

8388424 8388425 8388426 8388427 8388428 8388429

SAMPLE NUMBER

ADC CODE

Figure 11. Noise (Low Level Input, Output Data Rate = 1.25 SPS)

Figure 14. Histogram (Low Level Input,

Output Data Rate = 1.25 SPS)

8388480

8388460

8388440

8388420

8388400

8388380

8388360

40

35

30

25

20

15

10

5

0

200

400

600

800

1000

SAMPLE NUMBER

ADC CODE

Figure 12. Noise (Low Level Input, Output Data Rate = 5.194 kSPS)

Figure 15. Histogram (Low Level Input, Output Data Rate = 5.194 kSPS)

8388520

8388500

8388480

8388460

8388440

8388420

8388400

8388380

8388360

8388340

8388320

18

16

14

12

10

8

6

4

2

0

200

400

600

800

1000

SAMPLE NUMBER

ADC CODE

Figure 16. Histogram (Low Level Input, Output Data Rate = 62.5 kSPS)

Figure 13. Noise (Low Level Input, Output Data Rate = 62.5 kSPS)

Rev. 0 | Page 14 of 59

Data Sheet

AD4±±6

–60

0

–2

–70

–80

–90

–4

–100

–110

–120

–130

–140

–6

–8

–10

–12

–150

10

–2.5 –2.0 –1.5 –1.0 –0.5

0

0.5

1.0

1.5

2.0

2.5

20

30

40

50

60

ADCIN (V)

V

FREQUENCY (Hz)

IN

Figure 20. INL vs ADCIN (Low Level Input)

Figure 17. Common-Mode Rejection (CMR) vs. V_INFrequency (V_IN= 1 V,

10 Hz to 70 Hz, Output Data Rate = 20 SPS Enhanced Filter)

25

20

15

10

5

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

0

3.9981

3.9993

4.0005

4.0018

4.0030

4.0042

1

10

100

1k

10k

100k

1M

10M 100M

V

FREQUENCY

IN

FREQUENCY (MHz)

Figure 18. ADC PSRR vs. V_INFrequency

Figure 21. Internal Oscillator Frequency and

Accuracy Distribution Histogram

70

60

50

40

30

20

10

0

4.04

4.02

4.00

3.98

3.96

3.94

3.92

3.90

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

–10

–8

–6

–4

–2

0

2

4

6

8

10

V

(V)

IN

Figure 19. INL vs. V_IN(Voltage Input at 192.5 µs Settling)

Figure 22. Internal Oscillator Frequency vs. Temperature

Rev. 0 | Page 15 of 59

AD4116

Data Sheet

60

50

40

30

20

10

9

8

7

6

5

4

3

2

1

0

–10

–8

–6

–4

–2

0

2

4

6

8

0.02

0.10

0.18

0.26

0.34

0.42

0.50

0.58

OFFSET ERROR (mV)

OFFSET ERROR DRIFT (µV/°C)

Figure 23. Offset Error Distribution Histogram

(Voltage Input at 192.5 μs Settling)

Figure 26. Offset Error Drift Distribution Histogram

(Low Level Input)

10

9

8

7

6

5

4

3

2

1

0

100

90

80

70

60

50

40

30

20

10

0

–80

–60

–40

–20

0

20

–0.07 –0.05 –0.03 –0.01

0.01

0.03

0.05

0.07

OFFSET ERROR (µV)

GAIN ERROR (% of FS)

Figure 24. Offset Error Distribution Histogram

(Low Level Input)

Figure 27. Gain Error Distribution Histogram

(Voltage Input at 192.5 μs Settling)

120

100

80

60

40

20

0

8

7

6

5

4

3

2

1

0

0.02

0.04

0.06

0.08

0.10

0.12

0.14

–0.005

0

0.005

0.010

0.015

0.020

OFFSET ERROR DRIFT (mV/°C)

GAIN ERROR (% of FS)

Figure 28. Gain Error Distribution Histogram

(Low Level Input)

Figure 25. Offset Error Drift Distribution Histogram

(Voltage Input at 192.5 μs Settling)

Rev. 0 | Page 16 of 59

Data Sheet

AD4±±6

60

50

40

30

20

10

0

10

9

8

7

6

5

4

3

2

1

0

2

3

4

5

6

7

1

2

3

4

5

6

7

8

9

10

GAIN ERROR DRIFT (ppm/°C)

Figure 29. Gain Error Drift Distribution Histogram

(Voltage Input at 192.5 µs Settling)

Figure 31. Gain Error Drift Distribution Histogram

(Low Level Input)

90

80

70

60

50

40

30

20

10

0

20

18

16

14

12

10

8

–40°C

+25°C

+105°C

–40°C

+25°C

+105°C

6

4

2

0

–0.10

–0.07

–0.04

–0.01

0.02

0.05

0.08

–0.01

0

0.01

0.02

0.03

0.04

TUE (%FSR)

Figure 30. TUE Distribution Histogram (Voltage Input at 96.5 µs Settling)

Figure 32. TUE Distribution Histogram (Low Level Input)

Rev. 0 | Page 17 of 59

AD4116

Data Sheet

NOISE PERFORMANCE AND RESOLUTION

Table 7 to Table 10 show the rms noise, peak-to-peak noise,

effective resolution, and the noise free (peak-to-peak)

resolution of the AD4116 for various ODRs. These values are

typical and are measured with an external 2.5 V reference,

analog input buffers enabled and with the ADC continuously

converting on multiple channels. The values in Table 7 and

Table 8 are generated for the 10 V voltage input range, with a

differential input voltage of 0 V. The values in Table 9 and

Table 10 are generated for the V_REFinput range, with a

differential input voltage of 0 V. It is important to note that the

peak-to-peak resolution is calculated based on the peak-to-peak

noise. The peak-to-peak resolution represents the resolution for

which there is no code flicker.

Table 7. 10 V Voltage Input RMS Noise Resolution vs. ODR Using a Sinc5 + Sinc1 Filter

Default ODR (SPS);

SING_CYC = 0 and

Single Channel Enabled

ODR (SPS per Channel);

SING_CYC = 1 or Multiple

Channels Enabled

Notch

Frequency Noise

(Hz)

Effective

Peak-to-Peak

Resolution

(μV p-p) (Bits)

Settling

Time¹

Resolution Noise

(μV rms)²(Bits)

62,500

31,250

15,625

10,416.7

5,194.8

2,496.9

1007.6

499.9

390.6

200.3

100.0

59.75

49.84

20.00

16.65

10.00

5.00

12,422.36

10,362.69

7,782.1

6,230.53

5,194.8

2,496.9

1007.6

499.9

390.6

200.3

100.0

59.75

49.84

20.00

16.65

10.00

5.00

2.50

1.25

80.5 μs

96.5 μs

62,500

31,250

15,625

10,416.7

7,812.5

2,976.19

1077.59

516.53

400.64

202.92

100.6

59.98

50

20.03

16.67

10.01

5

2.5

1.25

326.60

271.80

209.60

171.80

151.40

95.46

56.48

39.56

35.82

25.72

19.08

15.22

14.07

10.32

9.62

15.90

16.17

16.54

16.83

17.01

17.68

18.43

18.95

19.09

19.57

20.00

20.33

20.44

20.89

20.99

21.14

21.29

21.55

21.61

2038.60 13.26

1778.01 13.46

1360.18 13.84

1093.80 14.16

1006.20 14.28

128.5 μs

160.5 μs

192.5 μs

400.5 μs

992.50 μs

2.00 ms

585.80

373.60

247.80

235.80

163.40

116.00

98.16

76.89

51.85

50.66

42.32

38.74

32.78

31.59

15.06

15.71

16.30

16.37

16.90

17.40

17.64

17.99

18.56

18.59

18.85

18.98

19.22

19.27

2.56 ms

4.99 ms

10.00 ms

16.74 ms

20.06 ms

50.00 ms

60.06 ms

100.00 ms

200.00 ms

400.00 ms

800.00 ms

8.67

7.78

6.52

6.23

2.50

1.25

¹The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.

²Based on 1000 samples for data rates ≥ 59.75 SPS per channel, and based on 100 samples for data rates ≤ 49.84 SPS per channel.

Table 8. 10 V Voltage Input RMS Noise Resolution vs. ODR Using a Sinc3 Filter

Default ODR (SPS);

SING_CYC = 0 and

Single Channel Enabled

ODR (SPS per Channel);

SING_CYC = 1 or

Multiple Channels Enabled

Notch

Frequency Noise

(Hz)

Effective

Peak-to-Peak

Resolution

(μV p-p) (Bits)

Settling

Time¹

Resolution Noise

(μV rms)²(Bits)

62,500

31,250

15,625

10,416.7

5,208.3

2,500

1008.1

500

400.64

200.32

100.0

59.98

50

20,618.56

10,362.69

5,194.81

3,466.2

1,734.61

832.99

335.97

166.65

133.54

66.77

48.5 μs

96.5 μs

62,500

31,250

15,625

10,416.7

5,208.3

2,500

1008.1

500

400.64

200.32

100.0

1213.00

279.20

163.40

133.38

95.20

64.90

41.82

30.12

27.68

20.22

15.30

12.88

12.40

8.64

14.01

16.13

16.90

17.19

17.68

18.23

18.87

19.34

19.46

19.92

20.32

20.57

20.62

21.14

21.20

7641.80 11.35

1748.20 13.49

1031.76 14.24

192.5 μs

288.5 μs

576.5 μs

1.20 ms

2.98 ms

6.00 ms

7.49 ms

14.98 ms

30.00 ms

50.02 ms

60.00 ms

891.69

608.60

435.00

260.80

205.40

179.60

140.00

96.46

87.62

60.79

42.91

14.46

15.01

15.49

16.23

16.57

16.77

17.12

17.67

17.81

18.34

18.83

18.79

33.3

19.99

16.67

6.67

59.98

50.00

20

16.67

150.00 ms 20.00

180.00 ms 16.67

5.56

8.34

Rev. 0 | Page 18 of 59

Data Sheet

AD4116

Default ODR (SPS);

SING_CYC = 0 and

Single Channel Enabled

ODR (SPS per Channel);

SING_CYC = 1 or

Multiple Channels Enabled

Notch

Frequency Noise

(Hz)

Effective

Peak-to-Peak

Resolution

(μV p-p) (Bits)

Settling

Time¹

Resolution Noise

(μV rms)²(Bits)

10

5

2.5

1.25

3.33

1.67

0.83

0.42

300.00 ms 10.00

600.00 ms 5.00

8.25

8.13

6.68

21.20

21.23

21.51

42.91

41.72

33.38

18.80

18.85

18.88

19.20

1.20 sec

2.4 sec

2.50

1.25

¹The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.

²Based on 1000 samples for data rates ≥ 59.98 SPS per channel, and based on 100 samples for data rates ≤ 50 SPS per channel.

Table 9. VRꢀF Low-level Input RMS Noise Resolution vs. ODR Using a Sinc5 + Sinc1 Filter

Default ODR (SPS);

SING_CYC = 0 and

Single Channel Enabled

ODR (SPS per Channel);

SING_CYC = 1 or Multiple

Channels Enabled

Notch

Frequency Noise

(Hz)

Effective

Peak-to-Peak

Resolution

(μV p-p) (Bits)

Settling

Time¹

Resolution Noise

(μV rms)²(Bits)

62,500

31,250

15,625

10,416.7

5,194.8

2,496.9

1007.6

499.9

390.6

200.3

100.0

59.75

49.84

20.00

16.65

10.00

5.00

12,422.36

10,362.69

7,782.1

6,230.53

5,194.8

2,496.9

1007.6

499.9

390.6

200.3

100.0

59.75

49.84

20.00

16.65

10.00

5.00

2.50

1.25

80.5 μs

96.5 μs

62,500

31,250

15,625

10,416.7

7,812.5

2,976.19

1077.59

516.53

400.64

202.92

100.6

9.6

8.3

6.3

6.1

4.9

3.2

1.95

1.3

1.2

0.85

0.6

0.45

0.4

0.26

0.23

0.18

0.13

0.09

0.07

18.99

19.20

19.60

19.79

19.96

20.58

21.29

21.87

21.99

22.49

22.99

23.41

23.58

24

63.36

54.78

41.58

36.3

32.34

21.12

12.87

8.58

7.92

5.61

3.96

2.97

16.27

16.48

16.88

17.07

17.24

17.85

18.57

19.15

19.27

19.77

20.27

20.68

20.85

21.47

21.65

22.00

22.47

23.00

23.37

128.5 μs

160.5 μs

192.5 μs

400.5 μs

992.50 μs

2.00 ms

2.56 ms

4.99 ms

10.00 ms

16.74 ms

20.06 ms

50.00 ms

60.06 ms

59.98

50

20.03

16.67

2.64

1.716

1.518

1.188

0.858

0.594

0.462

24

100.00 ms 10.01

200.00 ms

400.00 ms 2.5

800.00 ms 1.25

5

2.50

1.25

24

¹The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.

²Based on 1000 samples for data rates ≥ 59.98 SPS per channel, and based on 100 samples for data rates ≤ 50 SPS per channel.

Table 10. V_RꢀFLow Level Input RMS Noise Resolution vs. ODR Using a Sinc3 Filter

Default ODR (SPS);

SING_CYC = 0 and

Single Channel Enabled

ODR (SPS per Channel);

SING_CYC = 1 or Multiple

Channels Enabled

Notch

Frequency Noise

(Hz)

Effective

Peak-to-Peak

Resolution

(μV p-p) (Bits)

Settling

Time¹

Resolution Noise

(μV rms)²(Bits)

62,500

31,250

15,625

10,416.7

5,208.3

2,500

1008.1

500

400.64

200.32

100.0

20,618.56

10,362.69

5,194.81

3,466.2

1,734.61

832.99

335.97

166.65

133.54

66.77

48.5 μs

96.5 μs

62,500

31,250

15,625

10,416.7

5,208.3

2,500

1008.1

500

400.64

200.32

100.0

105

14

5.8

4.7

3.2

1.95

1.45

0.98

0.9

0.64

0.45

0.33

15.54

18.45

19.72

20.02

20.58

21.29

21.72

22.28

22.41

22.90

23.41

23.85

693

92.4

12.82

15.72

16.99

17.30

17.85

18.57

18.99

19.56

19.68

20.17

20.68

21.13

192.5 μs

288.5μs

576.5 μs

1.20 ms

2.98 ms

6.00 ms

7.49 ms

14.98 ms

30.00 ms

50.02 ms

38.28

31.02

21.12

12.87

9.57

6.468

5.94

4.224

2.97

33.3

19.99

59.98

2.178

Rev. 0 | Page 19 of 59

AD4116

Data Sheet

Default ODR (SPS);

SING_CYC = 0 and

Single Channel Enabled

ODR (SPS per Channel);

SING_CYC = 1 or Multiple

Channels Enabled

Notch

Frequency Noise

(Hz)

Effective

Peak-to-Peak

Resolution

(μV p-p) (Bits)

Settling

Time¹

Resolution Noise

(μV rms)²(Bits)

50

20

16.67

10

5

16.67

6.67

5.56

3.33

1.67

0.83

0.42

60.00 ms

50.00

0.3

0.2

23.99

24

1.98

1.32

21.27

21.85

22.09

22.37

22.88

23.41

23.59

150.00 ms 20.00

180.00 ms 16.67

300.00 ms 10.00

600.00 ms 5.00

1.20 sec

2.4 sec

0.17

0.14

0.098

0.068

0.06

1.122

0.924

0.6468

0.4488

0.396

2.5

1.25

2.50

1.25

24

¹The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.

²Based on 1000 samples for data rates ≥ 59.98 SPS per channel, and based on 100 samples for data rates ≤ 50 SPS per channel.

Rev. 0 | Page 20 of 59

Data Sheet

AD4±±6

THEORY OF OPERATION

The AD4116 offers the user a fast settling, high resolution,

multiplexed ADC with high levels of configurability, including

the following features:

the external circuitry and must be connected to a 0.1 μF

decoupling capacitor.

The AD4116 includes two separate linear regulator blocks for

both the analog and digital circuitry. The analog LDO regulator

regulates the AVDD supply to 1.8 V.

•

Six fully differential or eleven single-ended voltage inputs.

A high impedance voltage divider with integrated

precision matched resistors

The linear regulator for the digital IOVDD supply performs a

similar function, regulating the input voltage applied at the

IOVDD pin to 1.8 V. The serial interface signals always operate

from the IOVDD supply seen at the pin; meaning that, if 3.3 V

is applied to the IOVDD pin, the interface logic inputs and

outputs operate at this level.

•

Embedded proprietary iPassives technology within a small

device footprint.

Two differential or four single-ended low level direct ADC

inputs.

Per channel configurability—up to eight different setups

can be defined. A separate setup can be mapped to each of

the channels. Each setup allows the user to configure whether

the buffers are enabled or disabled, gain and offset correction,

filter type, ODR, and reference source selection.

Highly configurable digital filter enabling conversion rates

up to 62.5 kSPS on a single channel and 12.422 kSPS

switching using sinc5 + sinc1 filter.

The AD4116 is designed for a multitude of factory automation

and process control applications, such as programmable logic

controller (PLC) and distributed control system (DCS) modules.

The AD4116 reduces overall system cost and design burden

while maintaining a high level of accuracy. The AD4116 offers

the following system benefits:

•

A single 5 V power supply.

The AD4116 includes a precision, 2.5 V, low drift (5 ppm/°C),

band gap internal reference. This reference can be selected for

use in ADC conversions, reducing the external component

count. When enabled, the internal reference is output to the

REFOUT pin. It can be used as a low noise biasing voltage for

A guaranteed minimum 10 MΩ input impedance.

An overrange voltage greater than 10 V.

A buffered low level input voltage.

A high channel count

Reduced calibration costs.

16MHz

CX2

CX1

OPTIONAL EXTERNAL

CRYSTAL CIRCUITRY

CAPACITORS

12

13

2

3

VIN0

VIN1

XTAL1

±10V

CLKIN

XTAL2/CLKIO

DOUT/RDY

OPTIONAL

EXTERNAL

CLOCK

14

DOUT/RDY

DIN

INPUT

15

16

17

DIN

SCLK

CS

SCLK

CS

32

VIN10

IOVDD

0.1µF

20

21

22

IOVDD

DGND

AD4116

1

VINCOM

ADCIN11

REGCAPD

0.1µF

1µF

AVDD

33

±VREF

9

AVDD

REFOUT

34 ADCIN12

0.1µF

6

7

37

11

ADCIN15

VBIAS–

0.1µF

REGCAPA

0.1µF

1µF

AVSS

8

Figure 33. Typical Connection Diagram

Rev. 0 | Page 21 of 59

AD4±±6

Data Sheet

determine the specific register to which the read or write

operation applies.

POWER SUPPLIES

The AD4116 has two independent power supply pins: AVDD

and IOVDD. The AD4116 has no specific requirements for a

power supply sequence. However, when all power supplies are

stable, a device reset is required. See the AD4116 Reset section

for details on how to reset the device.

When the read or write operation to the selected register is

complete, the interface returns to its default state, where it

expects a write operation to the communications register.

In situations where interface synchronization is lost, a write

operation of at least 64 serial clock cycles with DIN high returns

the ADC to its default state by resetting the entire device,

CS

AVDD powers the internal 1.8 V analog LDO regulator, which

powers the ADC core. AVDD also powers the crosspoint

multiplexer and integrated input buffers. AVDD is referenced to

AVSS, and AVDD − AVSS = 5 V. AVDD and AVSS can be a

single 5 V supply or 2.5 V split supply. When using split

supplies, consider the absolute maximum ratings (see the

Absolute Maximum Ratings section).

including the register contents. Alternatively, if

is being used

CS

with the digital interface, returning

high resets the digital

interface to its default state and aborts any current operation.

Figure 35 and Figure 36 show writing to and reading from a

register by first writing the 8-bit command to the communications

register followed by the data for the addressed register.

IOVDD powers the internal 1.8 V digital LDO regulator. This

regulator powers the digital logic of the ADC. IOVDD sets the

voltage levels for the serial peripheral interface (SPI) of the

ADC. IOVDD is referenced to DGND, and IOVDD to DGND

can vary from 2 V (minimum) to 5.5 V (maximum).

Reading the ID register is the recommended method for verifying

correct communication with the device. The ID register is a

read only register and contains the value 0x34Dx for the

AD4116

Single-Supply Operation (AVSS = DGND)

8 BITS, 16 BITS,

OR 24 BITS OF DATA

8-BIT COMMAND

When the AD4116 is powered from a single supply connected

to AVDD, the supply must be 5 V. In this configuration, AVSS

and DGND can be shorted together on one single ground

plane.

CS

CMD

DATA

DIN

IOVDD can range from 2 V to 5.5 V in this unipolar input

configuration.

SCLK

Figure 35. Writing to a Register (8-Bit Command with Register Address

Followed by Data of 8 Bits, 16 Bits, or 24 Bits; Data Length Is Dependent on

the Register Selected)

DIGITAL COMMUNICATION

The AD4116 has a 3-wire or 4-wire SPI that is compatible with

QSPI™, MICROWIRE®, and DSPs. The interface operates in SPI

8 BITS, 16 BITS,

24 BITS, OR

CS

Mode 3 and can be operated with tied low. In SPI Mode 3,

8-BIT COMMAND

32 BITS OF DATA

SCLK idles high, the falling edge of SCLK is the drive edge, and

the rising edge of SCLK is the sample edge. Data is clocked out

on the falling and drive edge and data is clocked in on the rising

and sample edge.

CS

CMD

DIN

DOUT/

RDY

DATA

DRIVE EDGE

SAMPLE EDGE

SCLK

Figure 36. Reading from a Register (8-Bit Command with Register Address

Followed by Data of 8 Bits, 16 Bits, 24, or 32 Bits; Data Length on DOUT Is

Dependent on the Register Selected)

Figure 34. SPI Mode 3 SCLK Edges

Accessing the ADC Register Map

AD4116 RESET

The communications register controls access to the full register

map of the ADC. This register is an 8-bit write only register. On

power-up or after a reset, the digital interface defaults to a state

where it is expecting a write to the communications register.

Therefore, all communication begins by writing to the

communications register.

After a power-up cycle and when the power supplies are

stable, a device reset is required. In situations where interface

synchronization is lost, a device reset is also required. A write

operation of at least 64 serial clock cycles with DIN high returns

the ADC to the default state by resetting the entire device,

CS

including the register contents. Alternatively, if is being used

The data written to the communications register determines

which register is being accessed and if the next operation is a

read or write. The RA bits (Bits[5:0] in Register 0x00)

CS

with the digital interface, returning

high sets the digital

interface to the default state and halts any serial interface operation.

Rev. 0 | Page 22 of 59

Data Sheet

AD4±±6

Table 11. Communications Register Bit Map

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x00

RW

0x00

COMMS

[7:0]

WEN

R/W

RA

W

Table 12. ID Register Bit Map

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

ID[15:8]

ID[7:0]

Bit 2

Bit 1

Bit 0

Reset

0x34DX¹

RW

0x07

ID

[15:8]

[7:0]

R

¹X means don’t care.

Rev. 0 | Page 23 of 59

AD4±±6

Data Sheet

Channel Configuration

CONFIGURATION OVERVIEW

The AD4116 has 16 independent channels and 8 independent

setups. The user can select any of the input pairs on any

channel, as well as any of the eight setups for any channel, giving

the user full flexibility in the channel configuration. This flexibility

also allows per channel configuration when using differential

inputs and single-ended inputs because each channel can have

its own dedicated setup.

After power-on or reset, the AD4116 default configuration is as

follows:

•

Channel configuration: Channel 0 is enabled, and the

VIN0 and VIN1 pair is selected as the input. Setup 0 is

selected.

•

Setup configuration: the analog input buffers are disabled, and

the reference input buffers are also disabled. The REF pins

are selected as the reference source. Note that for this

setup, the default channel does not operate correctly

because the input buffers need to be enabled for a V_IN

input.

Channel Registers

The channel registers select which of the voltage inputs is used

for that channel. This register also contains a channel enable and

disable bit and the setup selection bits, which are used to select

which of the eight available setups to use for this channel.

•

Filter configuration: the sinc5 + sinc1 filter is selected and

the maximum output data rate of 62.5 kSPS is selected.

ADC mode: continuous conversion mode and the internal

oscillator are enabled. The internal reference is disabled.

Interface mode: CRC and the data and status output are

disabled.

When the AD4116 is operating with more than one channel

enabled, the channel sequencer cycles through the enabled

channels in sequential order, from Channel 0 to Channel 15. If

a channel is disabled, it is skipped by the sequencer. Details of

the channel register for Channel 0 are shown in Table 13.

Note that only a few of the register setting options are shown.

This list is only an example. For full register information, see

the Register Details section.

Figure 37 shows an overview of the suggested flow for changing

the ADC configuration, divided into the following three blocks:

•

Channel configuration (see Box A in Figure 37)

Setup configuration (see Box B in Figure 37)

ADC mode and interface mode configuration (see Box C

in Figure 37)

A

CHANNEL CONFIGURATION

SELECT INPUT AND SETUP FOR EACH ADC CHANNEL

B

C

SETUP CONFIGURATION

8 POSSIBLE ADC SETUPS

SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE

ADC MODE AND INTERFACE MODE CONFIGURATION

SELECT ADC OPERATING MODE, CLOCK SOURCE,

ENABLE CRC, DATA AND STATUS, AND MORE

Figure 37. Suggested ADC Configuration Flow

Table 13. Channel Register 0

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Reserved

Bit 1

Bit 0

Reset

RW

0x10

CH0

[15:8] CH_EN0

[7:0]

SETUP_SEL0

INPUT[9:8]

0x8001

RW

INPUT[7:0]

Rev. 0 | Page 24 of 59

Data Sheet

AD4±±6

ADC Setups

Setup Configuration Registers

The AD4116 has eight independent setups. Each setup consists

of the following four registers:

The setup configuration registers allow the user to select the output

coding of the ADC by selecting between bipolar mode and

unipolar mode. The user can select the reference source using

these registers. Three options are available: a reference connected

between the REF+ and REF− pins, the internal reference, or using

AVDD − AVSS. The input and reference buffers can also be

enabled or disabled using these registers.

•

Setup configuration registers

Filter configuration registers

Gain registers

Offset registers

For example, Setup 0 consists of Setup Configuration Register 0,

Filter Configuration Register 0, Gain Register 0, and Offset

Register 0. Figure 38 shows the grouping of these registers. The

setup is selectable from the channel registers (see the Channel

Configuration section), which allows each channel to be assigned

to one of eight separate setups. Table 14 through Table 17 show

the four registers that are associated with Setup 0. This

structure is repeated for Setup 1 to Setup 7.

Filter Configuration Registers

The filter configuration registers select which digital filter is

used at the output of the ADC modulator. The order of the

filter and the output data rate are selected by setting the bits in

these registers. For more information, see the Digital Filter

section.

SETUP CONFIGURATION

REGISTERS

FILTER CONFIGURATION

REGISTERS

GAIN REGISTERS*

OFFSET REGISTERS

SETUPCON0

SETUPCON1

SETUPCON2

SETUPCON3

SETUPCON4

SETUPCON5

FILTCON0

FILTCON1

FILTCON2

FILTCON3

FILTCON4

FILTCON5

GAIN0

GAIN1

GAIN2

GAIN3

GAIN4

GAIN5

OFFSET0

0x30

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

OFFSET1

0x31

OFFSET2

0x32

OFFSET3

0x33

OFFSET4

0x34

OFFSET5

0x35

SETUPCON6

SETUPCON7

FILTCON6

FILTCON7

GAIN6

GAIN7

OFFSET6

0x36

OFFSET7

0x37

SELECT PERIPHERAL

FUNCTIONS FOR

ADC CHANNEL

SELECT DIGITAL

FILTER TYPE

AND OUTPUT DATA RATE

GAIN CORRECTION

OPTIONALLY

OFFSET CORRECTION

OPTIONALLY PROGRAMMED

PER SETUP AS REQUIRED

PROGRAMMED

PER SETUP AS REQUIRED

INPUT BUFFERS

REFERENCE INPUT BUFFERS

REFERENCE SOURCE

125kSPS TO 2.5SPS

SINC5 + SINC1

SINC3

SINC3 MAP

ENHANCED 50Hz/60Hz

Figure 38. ADC Setup Register Grouping

Table 14. Setup Configuration Register 0

Reg. Name

0x20 SETUPCON0 [15:8]

[7:0] Reserved

Bits

Bit 7

Bit 6

Reserved

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INBUF0

Reset

RW

BI_UNIPOLAR0 REFBUF0+ REFBUF0−

0x1000

RW

REF_SEL0

Reserved

Table 15. Filter Configuration Register 0

Reg. Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x28 FILTCON0 [15:8] SINC3_MAP0

[7:0] Reserved

Reserved

ORDER0

ENHFILTEN0

ENHFILT0

0x0500

RW

ODR0

Table 16. Gain Register 0

Reg. Name

Bits

Bits[23:0]

Reset

RW

0x38 GAIN0

[23:0]

GAIN0[32:0]

0x5XXXX0 RW

Table 17. Offset Register 0

Reg. Name

Bits

Bits[15:0]

Reset

RW

0x30 OFFSET0

[23:0]

OFFSET0[23:0]

0x800000 RW

Rev. 0 | Page 25 of 59

AD4±±6

Data Sheet

Gain Registers

ADC Mode Register

The gain registers are 24-bit registers that hold the gain

calibration coefficient for the ADC. The gain registers are read

and write registers. The power-on reset value of the gain registers

is 0x5XXXX0. The gain registers are 24-bit read and write

registers.

The ADC mode register primarily sets the conversion mode of

the ADC to either continuous or single conversion. The user

can also select the standby and power-down modes, as well as

any of the calibration modes. In addition, this register contains

the clock source select bits and internal reference enable bit. The

reference select bits are contained in the setup configuration

registers (see the ADC Setups section for more information).

The details of this register are shown in Table 18.

Offset Registers

The offset registers hold the offset calibration coefficient for the

ADC. The power-on reset value of the offset registers is 0x800000.

The offset registers are 24-bit read and write registers.

Interface Mode Register

The interface mode register configures the digital interface

operation. This register allows the user to control data-word

length, CRC enable, data plus status read, and continuous read

mode. The details of this register are shown in Table 19. For more

information, see the Digital Interface section.

ADC Mode and Interface Mode Configuration

The ADC mode register and the interface mode register configure

the core peripherals for use by the AD4116 and the mode for

the digital interface.

Table 18. ADC Mode Register

Reg.

0x01 ADCMODE [15:8] REF_EN

[7:0] Reserved

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Reserved

Bit 2

CLOCKSEL

Bit 1

Delay

Reserved

Bit 0

Reset

RW

Reserved

SING_CYC

Mode

0x2000 RW

Table 19. Interface Mode Register

Reg. Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

IOSTRENGTH

CRC_EN

Bit 2

Bit 1

Reserved

Bit 0

Reset

RW

0x02 IFMODE

[15:8]

[7:0]

Reserved

ALT_SYNC

Reserved

DOUT_RESET

0x0000

RW

CONTREAD

DATA_

STAT

REG_

CHECK

Reserved WL16

Rev. 0 | Page 26 of 59

Data Sheet

AD4±±6

CIRCUIT DESCRIPTION

AVDD

MULTIPLEXER

MULIPLEXER

ADCIN11

ADCIN12

There are 12 standard voltage VIN pins and five low level voltage

ADCIN pins: VIN0 to VIN10, VINCOM, ADCIN11 to ADCIN15.

Each of these pins connects to the internal multiplexer. The

multiplexer enables these inputs to be configured as input pairs

(see the Voltage Inputs section and the Low Level Inputs section

for more information on how to setup these inputs). The

AD4116 can have up to 16 active channels. When more than

one channel is enabled, the channels are automatically sequenced

in order from the lowest enabled channel number to the highest

enabled channel number. The output of the multiplexer is

connected to the input of the integrated true rail-to-rail buffers.

These buffers can be bypassed, and the multiplexer output can

be directly connected to the switched capacitor input of the

ADC. The simplified input circuits are shown in Figure 39 and

Figure 40.

+IN

AVSS

AVDD

AVSS

AVDD

–IN

ADCIN15

AVSS

Figure 39. Simplified Low Level Input Circuit

AVDD

AVSS

MULTIPLEXER

2.2MΩ

9.9MΩ

2.2MΩ 2.2MΩ

VIN0

VIN1

+IN

AVDD

AVSS

9.9MΩ

AVDD

AVSS

–IN

9.9MΩ

2.2MΩ

VINCOM

VBIAS–

2.2MΩ 2.2MΩ

Figure 40. Simplified Voltage Input Circuit

Rev. 0 | Page 27 of 59

AD4±±6

Data Sheet

Fully Differential Inputs

VOLTAGE INPUTS

The differential low level inputs are paired together in the

following pairs: ADCIN11 and ADCIN12, ADCIN13 and

ADCIN14.

The unique integrated AFE of the AD4116 allows the user to

configure for eleven single-ended inputs or six fully differential

inputs. The integrated precision voltage divider on the analog

front end has a division ratio of 10 and contains Analog Devices

unique and patented iPassives technology to provide high

impedance precision matched resistors that enable an input

range of 20 V from a single +5 V power supply. Due to the

high input impedance on the analog front end, the conversion

accuracy of the voltage inputs may be dependent on the selected

output data rate when switching between channels or when

SING_CYC is enabled. For high output data rates, the settling

time is short; therefore, the large input impedance can influence

the accuracy. If a slower output data rate is selected, the error is

reduced as the ADC takes more time to process the analog

input, which allows sufficient time for the front end to settle.

Therefore, performing conversions at longer settling time

minimizes the error.

Single-Ended or Pseudo Differential Inputs

The user can measure up to four different single-ended or

pseudo differential, low level voltage inputs. In this case, each

voltage input must be paired with the ADCIN15 pin as the

input common pin. An example is to connect the ADCIN15

pin externally to the AVSS pin in a single-ended configuration,

meaning that the ADC can only convert positive input voltages.

Another example is to connect ADCIN15 to the REFOUT voltage

(that is, AVSS + 2.5 V) in a pseudo differential configuration,

and then differential voltages from −2.5 V to +2.5 V can be

converted.

ABSOLUTE INPUT PIN VOLTAGES

Voltage Inputs

Enable the input buffers in the corresponding setup configuration

register for the voltage input channels (see Table 34).

The AD4116 voltage input pins are specified for an accuracy of

10 V, specifically for the differential voltage between any two

voltage input pins.

Fully Differential Inputs

The voltage input pins have separate specifications for the absolute

voltage that can be applied, and the unique design of the voltage

divider network of the analog front end enables overvoltage

robustness on the AD4116, meaning that the allowed overvoltages

vary depending on the AVDD supply. Figure 41 shows the

different degrees of robustness that can be achieved for AVDD =

5 V. Figure 41 provides a visual representation and guidance on

how an overvoltage on a voltage pin can affect the overall device

accuracy.

The differential inputs are paired together in the following

pairs: VIN0 and VIN1, VIN2 and VIN3, VIN4 and VIN5, VIN6

and VIN7, VIN8 and VIN9, VIN10 and VINCOM.

Single-Ended Inputs

The user can measure up to 11 different single-ended voltage

inputs. In this case, each voltage input must be paired with the

VINCOM pin. Connect the VINCOM pin externally to the

AVSS pin.

LOW LEVEL INPUTS

The guaranteed accuracy section of Figure 41 shows the voltage

range that can be applied to a voltage input pin and achieve

guaranteed accuracy.

There are five low level input pins: ADCIN11, ADCIN12,

ADCIN13, ADCIN14, and ADCIN15. Each of these pins

connects to the internal crosspoint multiplexer. The crosspoint

multiplexer enables any of these inputs to be configured as an

input pair, either single-ended or fully differential.

AVDD = 5V

ABSOLUTE MAXIMUM RATING

+65V

NO DAMAGE TO DEVICE

+30V

+20V

The output of the multiplexer is connected to the input of the

integrated true rail-to-rail buffers. These buffers can be bypassed,

and the multiplexer output can be directly connected to the

switched capacitor input of the ADC. In buffered mode, the

input channel feeds into a high impedance input stage of the

buffer amplifier. Therefore, the input can tolerate significant

source impedances and is tailored for direct connection to external

resistive input protection or EMC filtering. When operating the

device in unbuffered mode, the device has a higher analog input

current. Note that this unbuffered input path provides a

dynamic load to the driving source. Therefore, RC combinations

on the input pins can cause gain errors, depending on the

output impedance of the source that is driving the ADC input.

NO LOSS OF ACCURACY ON OTHER CHANNELS

GUARANTEED ACCURACY

–20V

–25V

NO LOSS OF ACCURACY ON OTHER CHANNELS

NO DAMAGE TO DEVICE

–65V

ABSOLUTE MAXIMUM RATING

Figure 41. Absolute Input Pin Voltages, AVDD = 5 V

The no loss of accuracy sections show the voltage levels that can

be applied without degrading the accuracy of other channels.

Rev. 0 | Page 28 of 59

Data Sheet

AD4±±6

The no damage to device sections show the allowable positive

and negative voltages that can be applied to a voltage input pin

without exceeding the absolute maximum. The performance of

other channels is degraded, but the performance recovers when

the overvoltage is removed. This voltage range is specified as an

absolute maximum rating of 65 V. Operation beyond the

maximum operating conditions for extended periods can affect

product reliability.

in a code of 000 … 000, a zero differential input voltage resulting in

a code of 100 … 000, and a positive full-scale input voltage

resulting in a code of 111 … 111. The output code for any low-

level input voltage is represented as

Code = 2^{N – 1}× ((V_ADCIN/V_REF) + 1)

where:

N = 24.

V_REFis the reference voltage.

Low Level Inputs

V

_ADCINis the low level input voltage.

The absolute, low level, input voltage in unbuffered mode

includes the range between AVSS − 50 mV and AVDD + 50 mV.

The absolute input voltage range in buffered mode is restricted

to a range between AVSS and AVDD. This low level input

voltage is specified with an absolute maximum rating of

AVSS − 0.3 V to AVDD1 + 0.3 V.

AD4116 REFERENCE

The AD4116 offers the user the option of either supplying an

external reference to the REF+ and REF− pins of the device,

using AVDD − AVSS, or by allowing the use of the internal

2.5 V, low noise, low drift reference. Select the reference source

to be used by the analog input by setting the REF_SELx bits,

Bits[5:4], in the setup configuration registers appropriately. By

default, the AD4116 uses an external reference on power-up.

DATA OUTPUT CODING

Voltage Inputs

When the ADC is configured for unipolar operation, the

output code is natural (straight) binary with a zero differential

input voltage resulting in a code of 00 … 00, a midscale voltage

resulting in a code of 100 … 000, and a full-scale input voltage

resulting in a code of 111 … 111.

Internal Reference

The AD4116 includes a low noise, low drift voltage reference.

The internal reference has a 2.5 V output. The internal

reference is output on the REFOUT pin after the REF_EN bit in

the ADC mode register is set and is decoupled to AVSS with a

0.1 μF capacitor. The AD4116 internal reference is disabled by

default on power-up.

The output code for any input voltage is represented as

Code = (2^N× V_IN× 0.1)/V_REF

External Reference

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage resulting

in a code of 000 … 000, a zero differential input voltage resulting in

a code of 100 … 000, and a positive full-scale input voltage

resulting in a code of 111 … 111. The output code for any

analog input voltage can be represented as

The AD4116 has a fully differential reference input applied

through the REF+ and REF− pins. Standard low noise, low drift

voltage references, such as the ADR4525, are recommended for

use. Apply the external reference to the AD4116 reference pins

as shown in Figure 42. Decouple the output of any external

reference to AVSS. As shown in Figure 42, the ADR4525

output is decoupled with a 0.1 μF capacitor at the output for

stability purposes. The output is then connected to a 4.7 μF

capacitor, which acts as a reservoir for any dynamic charge

required by the ADC and is followed by a 0.1 μF decoupling

capacitor at the REF+ input. This capacitor is placed as close as

possible to the REF+ and REF− pins.

Code = 2^{N − 1}× ((V_IN× 0.1/V_REF) + 1)

where:

N = 24.

V

_INis the input voltage.

_REFis the reference voltage.

Low Level Inputs

When the ADC is configured for unipolar operation, the

output code is natural (straight) binary with a zero differential

input voltage resulting in a code of 00 … 00, a midscale voltage

resulting in a code of 100 … 000, and a full-scale input voltage

resulting in a code of 111 … 111. The output code for any low-

level input voltage is represented as

The REF− pin is connected directly to the AVSS potential. When

an external reference is used instead of the internal reference

to supply the AD4116, attention must be paid to the output of

the REFOUT pin. The internal reference is controlled by the

REF_EN bit (Bit 15) in the ADC mode register. If the internal

reference is not being used elsewhere in the application, ensure

that the REF_EN bit is disabled.

Code = (2^N× V_ADCIN)/V_REF

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage resulting

Rev. 0 | Page 29 of 59

AD4±±6

Data Sheet

AD4116

3V TO 18V

40

39

REF+

REF–

ADR4525²

2.5V VREF

0.1µF

4.7µF

1

2

ALL DECOUPLING IS TO AVSS.

ANY OF THEADR452x FAMILY REFERENCES CAN BE USED.

ADR4525 ENABLES REUSE OF THE 5V ANALOG SUPPLY

NEEDED FOR AVDD TO POWER THE REFERENCE V

.

IN

Figure 42. ADR4525 Connected to AD4116 REF Pins

Table 20. Setup Configuration 0 Register

Reg. Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INBUF0

Reset

RW

0x20 SETUPCON0 [15:8]

[7:0]

Reserved

BI_UNIPOLAR0 REFBUF0+ REFBUF0−

0x1000 RW

Reserved

REF_SEL0

Reserved

Table 21. ADC Mode Register

Reg.

Name

Bits

Bit 7

Bit 6

Reserved

Bit 5

Bit 4

Bit 3

Bit 2

CLOCKSEL

Bit 1

Bit 0

Reset

0x2000

RW

0x01

ADCMODE [15:8]

[7:0]

REF_EN

Reserved

SING_CYC

Mode

Reserved

Delay

RW

Reserved

Internal Oscillator

BUFFERED REFERENCE INPUT

The internal oscillator runs at 16 MHz and is internally divided

down to 4 MHz for the modulator and can be used as the ADC

master clock. The internal oscillator is the default clock source for

the AD4116 and is specified with an accuracy of −2.5% to +2.5%.

The AD4116 has true rail-to-rail, integrated, precision unity

gain buffers on both ADC reference inputs. The buffers provide

the benefit of providing high input impedance and allowing

high impedance external sources to be directly connected to the

reference inputs. The integrated reference buffers can fully

drive the internal reference switch capacitor sampling network,

simplifying the reference circuit requirements. Each reference

input buffer amplifier is fully chopped, meaning that it minimizes

the offset error drift and 1/f noise of the buffer. When using a

reference, such as the ADR4525, these buffers are not required

because these references, with proper decoupling, can drive the

reference inputs directly.

There is an option to allow the internal clock oscillator to be output

on the XTAL2/CLKIO pin. The clock output is driven to the

IOVDD logic level. This option can affect the dc performance of

the AD4116 due to the disturbance introduced by the output

driver. The extent to which the performance is affected depends

on the IOVDD voltage supply. Higher IOVDD voltages create a

wider logic output swing from the driver and affect performance

to a greater extent. This effect is further exaggerated if the

IOSTRENGTH bit is set at higher IOVDD levels.

CLOCK SOURCE

The AD4116 uses a nominal master clock of 4 MHz. The AD4116

can source its sampling clock from one of three sources:

•

An internal oscillator

An external crystal (use a 16 MHz crystal automatically

divided internally to set the 4 MHz clock)

An external clock source

•

All output data rates listed in this data sheet relate to a master

clock rate of 4 MHz. Using a lower clock frequency from, for

instance, an external source scales any listed data rate

proportionally. To achieve the specified data rates, particularly

rates for rejection of 50 Hz and 60 Hz, use a 4 MHz clock. The

source of the master clock is selected by setting the CLOCKSEL bits

(Bits[3:2]) in the ADC mode register. The default operation on

power-up and reset of the AD4116 is to operate with the internal

oscillator. It is possible to fine tune the output data rate and

filter notch at low output data rates using the SINC3_MAPx bits.

Rev. 0 | Page 30 of 59

Data Sheet

AD4±±6

The external crystal circuitry can be sensitive to the SCLK

External Crystal

edges, depending on the SCLK frequency, IOVDD voltage,

crystal circuitry layout, and the crystal used. During crystal startup,

any disturbances caused by the SLCK edges may cause double

edges on the crystal input, resulting in invalid conversions until

the crystal voltage has reached a high enough level such that

any interference from the SCLK edges is insufficient to cause

double clocking. This double clocking can be avoided by

ensuring that the crystal circuitry has reached a sufficient

voltage level after startup before applying any SCLK.

If higher precision, lower jitter clock sources are required, the

AD4116 can use an external crystal to generate the master clock.

The crystal is connected to the XTAL1 and XTAL2/CLKIO pins.

A recommended crystal for use is the FA-20H, a 16 MHz,

10 ppm, 9 pF crystal from Epson-Toyocom that is available in a

surface-mount package. As shown in Figure 43, insert two

capacitors (CX1 and CX2) from the traces connecting the

crystal to the XTAL1 and XTAL2/CLKIO pins. These capacitors

allow circuit tuning. Connect these capacitors to the DGND pin.

The value for these capacitors depends on the length and

capacitance of the trace connections between the crystal and

the XTAL1 and XTAL2/CLKIO pins. Therefore, the values of

these capacitors differ depending on the PCB layout and the

crystal used.

Because of the nature of the crystal circuitry, it is recommended

that empirical testing of the circuit be performed under the

required conditions, with the final PCB layout and crystal, to

ensure correct operation.

External Clock

The AD4116 can also use an externally supplied clock. In

systems where an externally supplied clock is used, the external

clock is routed to the XTAL2/CLKIO pin. In this configuration,

the XTAL2/ CLKIO pin accepts the externally sourced clock

and routes it to the modulator. The logic level of this clock

input is defined by the voltage applied to the IOVDD pin.

AD4116

1

CX1

XTAL1

XTAL2/CLKIO

CX2

1

DECOUPLE TO DGND

Figure 43. External Crystal Connections

Rev. 0 | Page 31 of 59

AD4±±6

Data Sheet

DIGITAL FILTER

The AD4116 has three flexible filter options to allow

optimization of noise, settling time, and rejection:

SINC3 FILTER

The sinc3 filter achieves the best single-channel noise performance

at lower rates and is, therefore, most suitable for single-channel

applications. The sinc3 filter always has a settling time equal to

•

The sinc5 + sinc1 filter.

The sinc3 filter.

Enhanced 50 Hz and 60 Hz rejection filters.

t

_SETTLE= 3/Output Data Rate

Figure 46 shows the frequency domain filter response for the

sinc3 filter. The sinc3 filter has good roll-off over frequency and

has wide notches for good notch frequency rejection.

50Hz AND 60Hz

POSTFILTER

SINC1

SINC5

SINC3

0

–10

Figure 44. Digital Filter Block Diagram

–20

–30

The filter and output data rate are configured by setting the

appropriate bits in the filter configuration register for the selected

setup. Each channel can use a different setup and therefore, a

different filter and output data rate. See the Register Details for

more information.

–40

–50

–60

–70

–80

SINC5 + SINC1 FILTER

–90

–100

–110

–120

The sinc5 + sinc1 filter is targeted at multiplexed applications

and achieves single cycle settling at output data rates of 5.195 kSPS

and less. The sinc5 block output is fixed at the maximum rate of

62.5 kSPS, and the sinc1 block output data rate can be varied to

control the final ADC output data rate. Figure 45 shows the

frequency domain response of the sinc5 + sinc1 filter at a 50 SPS

output data rate. The sinc5 + sinc1 filter has a slow roll-off over

frequency and narrow notches.

0

50

100

FREQUENCY (Hz)

150

Figure 46. Sinc3 Filter Response

The output data rates with the accompanying settling time and

rms noise for the sinc3 filter are shown in Table 8 and Table 10.

It is possible to fine tune the output data rate for the sinc3 filter by

setting the SINC3_MAPx bit in the filter configuration registers.

If this bit is set, the mapping of the filter register changes to directly

program the decimation rate of the sinc3 filter. All other options

are eliminated. The data rate when on a single channel can be

calculated using the following equation:

0

–20

–40

–60

Output Data Rate = f_MOD/(32 × FILTCONx[14:0])

where:

–80

f

_MODis the modulator rate (MCLK/2) and is equal to 2 MHz.

FILTCONx[14:0] are the contents on the filter configuration

–100

–120

registers, excluding the MSB.

For example, an output data rate of 50 SPS can be achieved with

SINC3_MAPx enabled by setting the FILTCONx[14:0] bits to a

value of 1,250.

0

50

100

FREQUENCY (Hz)

150

Figure 45. Sinc5 + Sinc1 Filter Response at 50 SPS ODR

The output data rates with the accompanying settling time and

rms noise for the sinc5 + sinc1 filter are shown in in Table 7

and Table 9.

Rev. 0 | Page 32 of 59

Data Sheet

AD4±±6

Figure 48 shows the same step on the analog input but with

single cycle settling enabled. The analog input requires at least a

single cycle for the output to be fully settled. The output data

SINGLE CYCLE SETTLING

The AD4116 can be configured by setting the SING_CYC bit in

the ADC mode register so that only fully settled data is output, thus

effectively putting the ADC into a single cycle settling mode. This

mode achieves single cycle settling by reducing the output data

rate to be equal to the settling time of the ADC for the selected

output data rate. This bit has no effect with the sinc5 + sinc1 filter

at output data rates of 5.195 kSPS and less or when multiple

channels are enabled.

RDY

rate, as indicated by the

signal, is now reduced to equal

the settling time of the filter at the selected output data rate.

ANALOG

INPUT

FULLY

SETTLED

ADC

OUTPUT

t_SETTLE

Figure 47 shows a step on the analog input with single cycle

settling mode disabled and the sinc3 filter selected. The analog

input requires at least three cycles after the step change for the

output to reach the final settled value.

Figure 48. Step Input with Single Cycle Settling

ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS

The enhanced filters provide rejection of 50 Hz and 60 Hz

simultaneously and allow the user to trade off settling time and

rejection. These filters can operate at up to 27.27 SPS or can

reject up to 90 dB of 50 Hz 1 Hz and 60 Hz 1 Hz interference.

These filters are operated by post filtering the output of the

sinc5 + sinc1 filter. For this reason, the sinc5 + sinc1 filter must

be selected when using the enhanced filters to achieve the

specified settling time and noise performance.

ANALOG

INPUT

FULLY

SETTLED

ADC

OUTPUT

1/ODR

Figure 47. Step Input Without Single Cycle Settling

Table 22. Enhanced Filter Output Data Rate, Settling Time, Rejection, and Voltage Input Noise

Output Data

Rate (SPS)

Settling

Time (ms)

Simultaneous Rejection of

Noise

(µV rms)

Peak-to-Peak

Resolution (Bits)

50 Hz 1 Hz and 60 Hz 1 Hz (dB)¹

Comments

27.27

25

20

36.67

40

50

47

62

85

90

13.24

12.81

12.48

11.99

17.72

17.87

17.86

17.91

See Figure 49 and Figure 52

See Figure 50 and Figure 53

See Figure 51 and Figure 54

See Figure 55 and Figure 56

16.667

60

¹Master clock = 4.00 MHz.

Table 23. Enhanced Filter Output Data Rate, Settling Time, Rejection, and Low Level Input Noise

Output Data

Rate (SPS)

Settling

Time (ms)

Simultaneous Rejection of

Noise

(µV rms)

Peak-to-Peak

Resolution (Bits)

50 Hz 1 Hz and 60 Hz 1 Hz (dB)¹

Comments

27.27

25

20

36.67

40

50

47

62

85

90

0.34

0.3

21.19

21.42

See Figure 49 and Figure 52

See Figure 50 and Figure 53

See Figure 51 and Figure 54

See Figure 55 and Figure 56

16.667

60

0.3

¹Master clock = 4.00 MHz.

Rev. 0 | Page 33 of 59

AD4±±6

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

40

45

50

55

60

65

70

100

200

300

400

500

600

FREQUENCY (Hz)

Figure 52. 27.27 SPS ODR, 36.67 ms Settling Time (40 Hz to 70 Hz)

Figure 49. 27.27 SPS ODR, 36.67 ms Settling Time

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

40

45

50

55

60

65

70

100

200

300

400

500

600

FREQUENCY (Hz)

Figure 53. 25 SPS ODR, 40 ms Settling Time (40 Hz to 70 Hz)

Figure 50. 25 SPS ODR, 40 ms Settling Time

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

40

45

50

55

60

65

70

100

200

300

400

500

600

FREQUENCY (Hz)

Figure 54. 20 SPS ODR, 50 ms Settling Time (40 Hz to 70 Hz)

Figure 51. 20 SPS ODR, 50 ms Settling Time

Rev. 0 | Page 34 of 59

Data Sheet

AD4±±6

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

100

200

300

400

500

600

40

45

50

55

60

65

70

FREQUENCY (Hz)

Figure 55. 16.667 SPS ODR, 60 ms Settling Time

Figure 56. 16.667 SPS ODR, 60 ms Settling Time (40 Hz to 70 Hz)

Rev. 0 | Page 35 of 59

AD4±±6

Data Sheet

OPERATING MODES

The AD4116 has a number of operating modes that can be set

from the ADC mode register and interface mode register. These

modes are as follows:

RDY

the DOUT/

pin goes high. The user can read this register

additional times, if required. However, ensure that the data

register is not being accessed at the completion of the next

conversion. Otherwise, the new conversion word is lost.

•

Continuous conversion mode

Continuous read mode

Single conversion mode

Standby mode

Power-down mode

Calibration modes (four)

When several channels are enabled, the ADC automatically

sequences through the enabled channels, performing one

conversion on each channel. When all the channels are

converted, the sequence starts again with the first channel. The

channels are converted in order from the lowest enabled channel

to the highest enabled channel. The data register is updated as

CONTINUOUS CONVERSION MODE

RDY

soon as each conversion is available. The

output pulses

low each time a conversion is available. The user can then read

the conversion while the ADC converts the next enabled channel.

Continuous conversion mode is the default power-up mode.

RDY

The AD4116 converts continuously, and the

status register goes low each time a conversion is complete. If

RDY

bit in the

CS

If the DATA_STAT bit in the interface mode register is set to 1,

the contents of the status register, along with the conversion data,

are output each time the data register is read. The four LSBs of

the status register indicates the channel to which the conversion

corresponds.

is low, the

output also goes low when a conversion is

complete. To read a conversion, write to the communications

register to indicate that the next operation is a read of the data

register. When the data-word has been read from the data register,

CS

0x44

DIN

DATA

DOUT/RDY

SCLK

Figure 57. Continuous Conversion Mode

Rev. 0 | Page 36 of 59

Data Sheet

AD4±±6

the CONTREAD bit in the interface mode register. When this bit

is set, the only serial interface operations possible are reads from

the data register. To exit continuous read mode, issue a dummy

CONTINUOUS READ MODE

In continuous read mode, it is not required to write to the

communications register before reading ADC data. Apply only

RDY

read of the ADC data register command (0x44) while the

output is low. Alternatively, apply a software reset (that is, 64

CS

RDY

the required number of SCLKs after the

to indicate the end of a conversion. When the conversion is

RDY

output goes low

SCLKs with

= 0 and DIN = 1) to reset the ADC and all

read, the

output returns high until the next conversion is

register contents. The dummy read and the software reset are

the only commands that the interface recognizes after it is

placed in continuous read mode. Hold DIN low in continuous

read mode until an instruction is to be written to the device.

available. In this mode, the data can be read only once. Ensure

that the data-word is read before the next conversion is complete.

If the user has not read the conversion before the completion of

the next conversion or if insufficient serial clocks are applied to

the AD4116 to read the data-word, the serial output register is

reset shortly before the next conversion is complete, and the

new conversion is placed in the output serial register. The ADC

must be configured for continuous conversion mode to use

continuous read mode. To enable continuous read mode, set

If multiple ADC channels are enabled, each channel is output

in turn, with the status bits being appended to the data if the

DATA_STAT bit is set in the interface mode register. The four

LSBs of the status register indicates the channel to which the

conversion corresponds.

CS

0x02

0x0080

DIN

DATA

DOUT/RDY

SCLK

Figure 58. Continuous Read Mode

Rev. 0 | Page 37 of 59

AD4±±6

Data Sheet

RDY

output goes low. The ADC then selects the next channel and

SINGLE CONVERSION MODE

begins a conversion. The user can read the present conversion

while the next conversion is being performed. When the next

conversion is complete, the data register is updated; therefore,

the user has a limited period in which to read the conversion.

When the ADC has performed a single conversion on each of

the selected channels, it returns to standby mode.

In single conversion mode, the AD4116 performs a single

conversion and is placed in standby mode after the conversion

RDY

is complete. The

of a conversion. When the data-word has been read from the

RDY

output goes low to indicate the completion

data register, the

output goes high. The data register can

RDY

be read several times, if required, even when the

high.

output goes

If the DATA_STAT bit in the interface mode register is set to 1, the

contents of the status register, along with the conversion, are

output each time the data register is read. The four LSBs of the

status register indicate the channel to which the conversion

corresponds.

If several channels are enabled, the ADC automatically sequences

through the enabled channels and performs a conversion on

RDY

each channel. When the first conversion is started, the

output goes high and remains high until a valid conversion is

CS

available and is low. When the conversion is available, the

CS

0x01

0x8010

0x44

DIN

DATA

DOUT/RDY

SCLK

Figure 59. Single Conversion Mode

Rev. 0 | Page 38 of 59

Data Sheet

AD4±±6

To start a calibration, write the relevant value to the mode bits

STANDBY AND POWER-DOWN MODES

RDY

in the ADC mode register. The DOUT/

pin and the

bit

In standby mode, most blocks are powered down. The LDO

regulators remain active so that the registers maintain their

contents. The crystal oscillator remains active if selected. To

power down the clock in standby mode, set the CLOCKSEL bits

in the ADC mode register to 00 (internal oscillator mode).

in the status register go high when the calibration initiates. When

the calibration is complete, the contents of the corresponding

RDY

offset or gain register are updated, the

bit in the status

RDY

CS

is low),

register is reset, the

output pin returns low (if

and the AD4116 reverts to standby mode.

In power-down mode, all blocks are powered down, including

the LDO regulators. All registers lose their contents, and the GPIO

outputs are placed in three-state. To prevent accidental entry to

power-down mode, the ADC must first be placed in standby

During an internal offset calibration, both modulator inputs are

connected internally to the selected negative analog input pin.

Therefore, it is necessary to ensure that the voltage on the selected

negative analog input pin does not exceed the allowed limits

and is free from excessive noise and interference. A full-scale,

low level, input voltage automatically connects to the ADC

input to perform an internal full-scale calibration.

CS

mode. Exiting power-down mode requires 64 SCLKs with

=

0 and DIN = 1, that is, a serial interface reset. A delay of 500 µs is

recommended before issuing a subsequent serial interface

command to allow the LDO regulator to power up.

However, for system calibrations, the system zero-scale (offset)

and system full-scale (gain) voltages must be applied to the

input pins before initiating the calibration modes. As a result,

errors external to the AD4116 are removed.

CALIBRATION

The AD4116 allows a 2-point calibration to be performed to

eliminate any offset and gain errors. The following four calibration

modes are used to eliminate these offset and gain errors on a per

setup basis:

The calibration range of the ADC gain for a system full-scale

calibration on a voltage input is from 3.75 × V_REFto 10.5 × V_REF

However, if 10.5 × V_REFis greater than the absolute input voltage

specification for the applied AVDD, use the specification as the

.

•

Internal zero-scale calibration mode

Internal full-scale calibration mode

System zero-scale calibration mode

System full-scale calibration mode

upper limit instead of 10.5 × V_REF(see the Specifications section).

The calibration range of the ADC gain for a system full-scale

calibration on a low level input is from 0.4 × V_REFto 1.05 × V_REF

.

Only one channel can be active during calibration. After each

conversion, the ADC conversion result is scaled using the ADC

calibration registers before being written to the data register.

An internal zero-scale calibration only removes the offset error

of the ADC core. It does not remove error from the resistive

front end. A system zero-scale calibration reduces the offset

error to the order of the noise on that channel.

The default value of the offset register is 0x800000, and the

default value of the gain register is 0x5XXXX0. The following

equations show the calculations that are used. In unipolar mode,

the ideal relationship (that is, not taking into account the ADC

gain error and offset error) is as follows:

From an operational point of view, treat a calibration like

another ADC conversion. An offset calibration, if required,

must always be performed before a full-scale calibration. Set the

RDY

For the voltage inputs,

system software to monitor the

bit in the status register or

output to determine the end of a calibration via a

Data = ((0.075 × V_IN/V_REF) × 2²³− (Offset − 0x800000)) ×

(Gain/0x400000) × 2

RDY

the

polling sequence or an interrupt driven routine. All calibrations

require a time equal to the settling time of the selected filter and

output data rate to be completed.

For the low level inputs,

Data = ((0.75 × V_ADCIN/V_REF) × 2²³− (Offset − 0x800000)) ×

(Gain/0x400000) × 2

Any calibration can be performed at any output data rate.

Using lower output data rates results in better calibration

accuracy and is accurate for all output data rates. A new offset

calibration is required for a given channel if the reference

source for that channel is changed.

In bipolar mode, the ideal relationship (that is, not taking into

account the ADC gain error and offset error) is as follows:

For the voltage inputs,

Data = ((0.075 × V_IN/V_REF) × 2²³− (Offset − 0x800000)) ×

(Gain/0x400000) + 0x800000

The AD4116 provides the user with access to the on-chip

calibration registers, allowing the microprocessor to read the

calibration coefficients of the device and to write its own

calibration coefficients. A read or write of the offset and gain

registers can be performed at any time except during an internal or

self calibration.

For the low level inputs,

Data = ((0.75 × V_ADCIN/V_REF) × 2²³− (Offset − 0x800000)) ×

(Gain/0x400000) + 0x800000

Rev. 0 | Page 39 of 59

AD4±±6

Data Sheet

DIGITAL INTERFACE

The programmable functions of the AD4116 are accessible via

CRC_ERROR bit is set in the status register. However, to

CS

ensure that the register write is completed. It is important to

read back the register and verify the checksum.

the SPI. The SPI of the AD4116 consists of four signals:

RDY

,

DIN, SCLK, and DOUT/

. The DIN line transfers data into

the on-chip registers. The DOUT output accesses data from the

on-chip registers. SCLK is the serial clock input for the device. All

data transfers (either on DIN or on DOUT) occur with respect to

the SCLK signal.

For CRC checksum calculations during a write operation, the

following polynomial is always used:

x⁸+ x²+ x + 1

During read operations, the user can select between this

polynomial and a similar exclusive OR (XOR) function. The

XOR function requires less time to process on the host

microcontroller than the polynomial-based checksum. The

CRC_EN bits in the interface mode register enable and disable

the checksum and allow the user to select between the polynomial

check and the simple XOR check.

RDY

The DOUT/

the line going low if

in the data register. The DOUT/

read operation from the data register is complete. The

pin also functions as a data ready signal, with

CS

is low when a new data-word is available

RDY

pin is reset high when a

RDY

output also goes high before updating the data register to

indicate when not to read from the device to ensure that a data

read is not attempted while the register is being updated. Take

The checksum is appended to the end of each read and write

transaction. The checksum calculation for the write transaction

is calculated using the 8-bit command word and the 8-bit to 24-bit

data. For a read transaction, the checksum is calculated using

the command word and the 8-bit to 32-bit data output. Figure 60

and Figure 61 show SPI write and read transactions, respectively.

RDY

care to avoid reading from the data register when

to go low. The best method to ensure that no data read occurs is to

RDY

is about

always monitor the

output. Start reading the data register

goes low, and ensure a sufficient SCLK rate,

such that the read is completed before the next conversion result.

CS CS

RDY

as soon as

is used to select a device.

can be used to decode the

8-BIT COMMAND

UP TO 24-BIT INPUT

8-BIT CRC

AD4116 in systems where several components are connected to

the serial bus.

CS

Figure 2 and Figure 3 show timing diagrams for interfacing to

CMD

DATA

CRC

DIN

CS

the AD4116 using

to decode the device. Figure 2 shows the

timing for a read operation from the AD4116, and Figure 3

shows the timing for a write operation to the AD4116. It is

possible to read from the data register several times, even though

SCLK

Figure 60. SPI Write Transaction with CRC

RDY

the

output returns high after the first read operation.

UP TO 32-BIT

However, take care to ensure that the read operations are

completed before the next output update occurs. In continuous

read mode, the data register can be read only once.

8-BIT COMMAND

OUTPUT

8-BIT CRC

CS

CMD

DIN

CS

The serial interface can operate in 3-wire mode by tying

RDY

low. In this case, the SCLK, DIN, and DOUT/

lines are

used to communicate with the AD4116. The end of the

DOUT/

RDY

DATA

CRC

RDY

conversion can also be monitored using the

status register.

bit in the

SCLK

CS

The SPI can be reset by writing 64 SCLKs with

= 0 and

DIN = 1. A reset returns the SPI to the state in which it expects a

write to the communications register. This operation resets the

contents of all registers to their power-on values. Following a

reset, allow a period of 500 µs before addressing the SPI.

Figure 61. SPI Read Transaction with CRC

If checksum protection is enabled when continuous read mode

is active, there is an implied read data command of 0x44 before

every data transmission that must be accounted for when

calculating the checksum value. The checksum protection ensures

a nonzero checksum value even if the ADC data equals 0x000000.

CHECKSUM PROTECTION

The AD4116 has a checksum mode that can improve interface

robustness. Using the checksum mode ensures that only valid

data is written to a register and allows data read from a register

to be validated. If an error occurs during a register write, the

Rev. 0 | Page 40 of 59

Data Sheet

AD4±±6

so that its MSB is adjacent to the leftmost Logic 1 of the new

CRC CALCULATION

result, and the procedure is repeated. This process is repeated

until the original data is reduced to a value less than the

polynomial. This value is the 8-bit checksum.

Polynomial

The checksum, which is eight bits wide, is generated using the

following polynomial:

Example of a Polynomial CRC Calculation—24-Bit Word:

0x654321 (Eight Command Bits and 16-Bit Data)

x⁸+ x²+ x + 1

To generate the checksum, the data is left shifted by eight bits

to create a number ending in eight Logic 0s. The polynomial is

aligned so that its MSB is adjacent to the leftmost Logic 1 of the

data. An exclusive OR (XOR) function is applied to the data to

produce a new, shorter number. The polynomial is again aligned

An example of generating the 8-bit checksum using the

polynomial based checksum follows:

Initial value

011001010100001100100001

01100101010000110010000100000000

100000111

left shifted eight bits

polynomial

x⁸+ x²+ x + 1 =

100100100000110010000100000000

100000111

XOR result

polynomial

100011000110010000100000000

100000111

XOR result

polynomial

11111110010000100000000

100000111

XOR result

polynomial value

XOR result

1111101110000100000000

100000111

polynomial value

XOR result

111100000000100000000

100000111

polynomial value

XOR result

11100111000100000000

100000111

polynomial value

XOR result

1100100100100000000

100000111

polynomial value

XOR result

100101010100000000

100000111

polynomial value

XOR result

101101100000000

100000111

polynomial value

XOR result

1101011000000

100000111

polynomial value

XOR result

101010110000

100000111

polynomial value

XOR result

1010001000

100000111

polynomial value

checksum = 0x86.

10000110

Rev. 0 | Page 41 of 59

AD4±±6

Data Sheet

XOR Calculation

The checksum, which is eight bits wide, is generated by splitting

the data into bytes and then performing an XOR of the bytes.

Example of an XOR Calculation—24-Bit Word: 0x654321

(Eight Command Bits and 16-Bit Data)

Using the previous polynomial example, divide the checksum

into three bytes (0x65, 0x43, and 0x21) which results in the

following XOR calculation:

01100101

01000011

00100110

00100001

00000111

0x65

0x43

XOR result

0x21

CRC

Rev. 0 | Page 42 of 59

Data Sheet

AD4±±6

INTEGRATED FUNCTIONS

The AD4116 has a number of integrated functions.

DOUT_RESET

RDY

pin. By default, this pin

GENERAL-PURPOSE I/O

The SPI uses a shared DOUT/

RDY

outputs the

the data from the register being read. After the read is

RDY

signal. During a data read, this pin outputs

The AD4116 has two general-purpose digital input and output

pins (GPIO0 and GPIO1) and two general-purpose digital

output pins (GPO2 and GPO3). As the naming convention

suggests, the GPIO0 and GPIO1 pins can be configured as

inputs or outputs, but the GPO2 and GPO3 pins are outputs

only. The GPIOx and GPOx pins are enabled using the

following bits in the GPIOCON register: IP_EN0 and IP_EN1

(or OP_EN0 and OP_EN1) for GPIO0 and GPIO1 and

OP_EN2_3 for GPO2 and GPO3.

complete, the pin reverts to outputting the

short, fixed period of time (t₇). However, this time may be too

short for some microcontrollers and can be extended until the

pin is brought high by setting the DOUT_RESET bit in the

interface mode register to 1. This setting means that

signal after a

CS

must

frame each read operation and complete the SPI transaction.

SYNCHRONIZATION

When the GPIO0 or GPIO1 pin is enabled as an input, the logic

level at the pin is contained in the GP_DATA0 or GP_DATA1

bit, respectively. When the GPIO0, GPIO1, GPO2, or GPO3

pin is enabled as an output, the GP_DATA0, GP_DATA1,

GP_DATA2, or GP_DATA3 bit, respectively, determines the

logic level output at the pin. The logic levels for these pins are

referenced to AVDD and AVSS; therefore, outputs have an

amplitude of either 5 V or depending on the AVDD − AVSS

voltage.

Normal Synchronization

When the SYNC_EN bit in the GPIOCON register is set to 1,

SYNC

the

pin functions as a synchronization pin. The

input allows the user to reset the modulator and the digital filter

without affecting any of the setup conditions on the device. This

reset allows the user to start gathering samples of the analog

input from a known point in time, that is, the rising edge of

SYNC

. This pin must be low for at least one master clock cycle

to ensure that synchronization occurs. If multiple channels are

enabled, the sequencer is reset to the first enabled channel.

ERROR

The

pin can also be used as a general-purpose output if

the ERR_EN bits in the GPIOCON register are set to 11. In this

configuration, the ERR_DAT bit in the GPIOCON register

If multiple AD4116 devices are operated from a common

master clock, they can be synchronized so that their data registers

are updated simultaneously. Synchronization is normally done

after each AD4116 has performed its own calibration or has

calibration coefficients loaded into its calibration registers. A

ERROR

determines the logic level output at the

level for the pin is referenced to IOVDD and DGND, and the

ERROR

pin. The logic

pin has an active pull-up.

EXTERNAL MULTIPLEXER CONTROL

SYNC

falling edge on the

analog modulator and places the AD4116 into a consistent

SYNC

pin resets the digital filter and the

If an external multiplexer is used to increase the channel count,

the multiplexer logic pins can be controlled using the AD4116

GPIOx and GPOx pins. When the MUX_IO bit is set in the

GPIOCON register (Address 0x06, Bit 12), the timing of the

GPIOx pins is controlled by the ADC; therefore, the channel

change is synchronized with the ADC, eliminating any need for

external synchronization.

known state. While the

maintained in this state. On the

pin is low, the AD4116 is

SYNC

rising edge, the modulator

and filter are taken out of this reset state, and on the next master

clock edge, the device starts to gather input samples again.

The device is taken out of reset on the master clock falling edge

SYNC

following the

multiple devices are being synchronized, take the

high on the master clock rising edge to ensure that all devices

SYNC

low-to-high transition. Therefore, when

DELAY

SYNC

It is possible to insert a programmable delay before the AD4116

begins to take samples. This delay allows an external amplifier

or multiplexer to settle and can also alleviate the specification

requirements for the external amplifier or multiplexer. Eight

programmable settings, ranging from 0 µs to 4 ms, can be set using

the delay bits in the ADC mode register (Register 0x01, Bits[10:8]).

begin sampling on the master clock falling edge. If the

pin is not taken high in sufficient time, it is possible to have a

difference of one master clock cycle between the devices, that is,

the instant at which conversions are available differs from

device to device by a maximum of one master clock cycle.

SYNC

The

for a single channel when in normal synchronization mode. In

SYNC

input can also be used as a start conversion command

16-BIT/24-BIT CONVERSION

By default, the AD4116 generates 24-bit conversions. However,

the width of the conversions can be reduced to 16 bits. Setting

Bit WL16 in the interface mode register to 1 rounds all data

conversions to 16 bits. Clearing this bit sets the width of the

data conversions to 24 bits.

this mode, the rising edge of the

RDY

input starts a conversion,

output indicates when the

and the falling edge of the

conversion is complete. The settling time of the filter is required

for each data register update. After the conversion is complete,

SYNC

bring the

input low in preparation for the next

conversion start signal.

Rev. 0 | Page 43 of 59

AD4±±6

Data Sheet

Alternate Synchronization

ERROR

Input/Output

SYNC

In alternate synchronization mode, the

input operates as

ERROR

The

pin functions as an error input and output pin or

a start conversion command when several channels of the

AD4116 are enabled. Setting the ALT_SYNC bit in the interface

mode register to 1 enables an alternate synchronization scheme.

as a general-purpose output pin. The ERR_EN bits in the

GPIOCON register determine the function of the pin.

ERROR

When the ERR_EN bits are set to 10, the

pin functions

SYNC

When the

conversion on the enabled channel, selects the next channel in

SYNC

input is taken low, the ADC completes the

as an open-drain error output. The three error bits in the status

register (ADC_ERROR, CRC_ERROR, and REG_ERROR) are

the sequence, and then waits until the

to start the conversion. The

input is taken high

output goes low when the

ERROR

OR’ed, inverted, and mapped to the

output. Therefore,

output indicates that an error has occurred. The

status register must be read to identify the error source.

ERROR

RDY

ERROR

the

conversion is complete on the current channel, and the data

register is updated with the corresponding conversion. Therefore,

When the ERR_EN bits are set to 01, The

as an error input. The error output of another component can

ERROR

pin functions

SYNC

the

input does not interfere with the sampling on the

currently selected channel but allows the user to control the

instant at which the conversion begins on the next channel in

the sequence.

be connected to the AD4116

indicates when an error occurs on either itself or the external

ERROR

input so that the AD4116

component. The value on the

input is inverted and

Alternate synchronization mode can be used only when several

channels are enabled. It is not recommended to use this mode

when a single channel is enabled.

OR’ed with the errors from the ADC conversion, and the result

is indicated via the ADC_ERROR bit in the status register. The

ERROR

value of the

the GPIOCON register.

ERROR

input is reflected in the ERR_DAT bit in

ERROR FLAGS

The status register contains three error bits (ADC_ERROR,

CRC_ERROR, and REG_ERROR) that flag errors with the

ADC conversion, errors with the CRC check, and errors caused

by changes in the registers, respectively. In addition, the

The

bits are set to 00. When the ERR_EN bits are set to 11, the

ERROR

input and output is disabled when the ERR_EN

pin operates as a general-purpose output where the

ERR_DAT bit is used to determine the logic level of the pin.

ERROR

output can indicate that an error has occurred.

DATA_STAT

ADC_ERROR

The contents of the status register can be appended to each

conversion on the AD4116 using the DATA_STAT bit in the

IFMODE register. This function is useful if several channels are

enabled. Each time a conversion is output, the contents of the

status register are appended. The four LSBs of the status register

indicate to which channel the conversion corresponds. In

addition, the user can determine if any errors are being flagged

by the error bits.

The ADC_ERROR bit in the status register flags any errors that

occur during the conversion process. The flag is set when an

overrange or underrange result is output from the ADC. The

ADC also outputs all 0s or all 1s when an undervoltage or

overvoltage occurs. This flag is reset only when the overvoltage or

undervoltage is removed. This flag is not reset by a read of the

data register.

CRC_ERROR

IOSTRENGTH

If the CRC value that accompanies a write operation does not

correspond with the information sent, the CRC_ERROR flag is

set. The flag is reset as soon as the status register is explicitly read.

The SPI can operate with a power supply as low as 2 V.

RDY

However, at this low voltage, the DOUT/

pin may not

have sufficient drive strength if there is moderate parasitic

capacitance on the board or if the SCLK frequency is high. The

IOSTRENGTH bit in the interface mode register increases the

REG_ERROR

The REG_ERROR flag is used in conjunction with the

REG_CHECK bit in the interface mode register. When the

REG_CHECK bit is set, the AD4116 monitors the values in

the on-chip registers. If a bit changes, the REG_ERROR bit is

set to 1. Therefore, for writes to the on-chip registers, set the

REG_CHECK bit to 0. When the registers are updated, the

REG_CHECK bit can be set to 1. The AD4116 calculates a

checksum of the on-chip registers. If one of the register values

has changed, the REG_ERROR bit is set to 1. If an error is

flagged, the REG_CHECK bit must be set to 0 to clear the

REG_ERROR bit in the status register. The register check

function does not monitor the data register, status register, or

interface mode register.

RDY

drive strength of the DOUT/

pin.

Rev. 0 | Page 44 of 59

Data Sheet

AD4±±6

The temperature sensor requires that the input buffers be enabled

on both inputs and the internal reference be enabled.

INTERNAL TEMPERATURE SENSOR

The AD4116 has an integrated temperature sensor. The

temperature sensor can be used as a guide for the ambient

temperature at which the device is operating. The ambient

temperature can be used for diagnostic purposes or as an

indicator of when the application circuit must rerun a

calibration routine to take into account a shift in operating

temperature. The temperature sensor is selected using the

multiplexer and is selected in the same way as an input channel.

To use the temperature sensor, the first step is to calibrate the

device in a known temperature (25°C) and take a conversion as a

reference point. The temperature sensor has a nominal sensitivity

of 477 μV/K. The difference in this ideal slope and the slope

measured can calibrate the temperature sensor. The temperature

sensor is specified with a 2°C typical accuracy after calibration

at 25°C. To calculate the temperature, use the following equation:

Temperature (°C) = (Conversion Result ÷ 477 µV) − 273.15

Rev. 0 | Page 45 of 59

AD4±±6

Data Sheet

APPLICATIONS INFORMATION

to run under the AD4116 to prevent noise coupling. The power

supply lines to the AD4116 must use as wide a trace as possible

to provide low impedance paths and reduce glitches on the

power supply line. Shield fast switching signals like clocks with

digital ground to prevent radiating noise to other sections of

the board and never run clock signals near the inputs. Avoid

crossover of digital and analog signals. Run traces on opposite

sides of the board at right angles to each other. This layout

reduces the effects of feedthrough on the board. A microstrip

technique is by far the best but is not always possible with a

double-sided board. In this technique, the component side of

the board is dedicated to ground planes, whereas signals are

placed on the solder side.

GROUNDING AND LAYOUT

The inputs and reference inputs are differential and, therefore,

most of the voltages in the analog modulator are common-mode

voltages. The high common-mode rejection of the device removes

common-mode noise on these inputs. The analog and digital

supplies to the AD4116 are independent and separately pinned

out to minimize coupling between the analog and digital sections

of the device. The digital filter provides rejection of broadband

noise on the power supplies, except at integer multiples of the

master clock frequency.

The digital filter also removes noise from the analog inputs

and reference inputs, provided that these noise sources do not

saturate the analog modulator. As a result, the AD4116 is more

immune to noise interference than a conventional high

resolution converter. However, because the resolution of the

AD4116 is high and the noise levels from the converter are so

low, take care with regard to grounding and layout.

Proper decoupling is important when using high resolution ADCs.

The AD4116 has two power supply pins: AVDD and IOVDD.

The AVDD pin is referenced to AVSS, and the IOVDD pin is

referenced to DGND. Decouple AVDD with a 10 µF tantalum

capacitor in parallel with a 0.1 µF capacitor to AVSS on each

pin. Place the 0.1 µF capacitor as near as possible to the device

on each supply, ideally right up against the device. Decouple

IOVDD with a 10 µF tantalum capacitor, in parallel with a 0.1 µF

capacitor to DGND. Decouple all inputs to AVSS. If an external

reference is used, decouple the REF+ and REF− pins to AVSS.

The PCB that houses the ADC must be designed so that the

analog and digital sections are separated and confined to

certain areas of the board. A minimum etch technique is

generally best for ground planes because it results in the best

shielding.

In any layout, the user must keep in mind the flow of currents

in the system, ensuring that the paths for all return currents are as

close as possible to the paths the currents took to reach their

destinations.

The AD4116 also has two on-board LDO regulator outputs:

one that regulates the AVDD supply, and one that regulates the

IOVDD supply. For the REGCAPA pin, it is recommended that

1 µF and 0.1 µF capacitors to AVSS be used. Similarly, for the

REGCAPD pin, it is recommended that 1 µF and 0.1 µF

capacitors to DGND be used.

Avoid running digital lines under the device because this

couples noise onto the die and allows the analog ground plane

Rev. 0 | Page 46 of 59

Data Sheet

AD4±±6

REGISTER SUMMARY

Table 24. Register Summary

Register Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset¹

0x00

R/W

W

0x00

0x01

COMMS

Status

[7:0] WEN

[7:0] RDY

W

R/

RA

ADC_ERROR CRC_ERROR REG_ERROR

Channel

0x80

R

ADCMODE [15:8] REF_EN

[7:0] Reserved

Reserved

Mode

SING_CYC

Reserved

CLOCKSEL

IOSTRENGTH

Delay

Reserved

0x2000 R/W

0x02

0x03

IFMODE

[15:8]

Reserved

ALT_SYNC

DOUT_

RESET

0x0000 R/W

[7:0] CONTREAD DATA_STAT REG_CHECK Reserved

CRC_EN

Reserved

WL16

REGCHECK [23:16]

REGISTER_CHECK[23:16]

REGISTER_CHECK[15:8]

REGISTER_CHECK[7:0]

Data[23:16]

0x000000 R

0x0800 R/W

[15:8]

[7:0]

0x04

Data

[23:0]

[15:8]

[7:0]

Data[15:8]

Data[7:0]

0x06

0x07

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

GPIOCON [15:8]

[7:0] GP_DATA3

[15:8]

Reserved

OP_EN2_3 MUX_IO

IP_EN0

SYNC_EN

OP_EN1

ERR_EN

ERR_DAT

GP_DATA2 IP_EN1

OP_EN0 GP_DATA1 GP_DATA0

ID

ID[15:8]

ID[7:0]

0x34DX

R

[7:0]

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH9

CH10

CH11

CH12

CH13

CH14

CH15

[15:8] CH_EN0

[7:0]

SETUP_SEL0

Reserved

INPUT0[9:8]

INPUT1[9:8]

INPUT2[9:8]

INPUT3[9:8]

INPUT4[9:8]

INPUT5[9:8]

INPUT6[9:8]

INPUT7[9:8]

INPUT8[9:8]

INPUT9[9:8]

INPUT10[9:8]

INPUT11[9:8]

INPUT12[9:8]

INPUT13[9:8]

INPUT14[9:8]

INPUT15[9:8]

0x8001 R/W

0x0001 R/W

INPUT0[7:0]

INPUT1[7:0]

INPUT2[7:0]

INPUT3[7:0]

INPUT4[7:0]

INPUT5[7:0]

INPUT6[7:0]

INPUT7[7:0]

INPUT8[7:0]

INPUT9[7:0]

Input10[7:0]

INPUT11[7:0]

INPUT12[7:0]

INPUT13[7:0]

INPUT14[7:0]

INPUT15[7:0]

[15:8] CH_EN1

[7:0]

SETUP_SEL1

SETUP_SEL2

SETUP_SEL3

SETUP_SEL4

SETUP_SEL5

SETUP_SEL6

SETUP_SEL7

SETUP_SEL8

SETUP_SEL9

SETUP_SEL10

SETUP_SEL11

SETUP_SEL12

SETUP_SEL13

SETUP_SEL14

SETUP_SEL15

Reserved

[15:8] CH_EN2

[7:0]

[15:8] CH_EN3

[7:0]

[15:8] CH_EN4

[7:0]

[15:8] CH_EN5

[7:0]

[15:8] CH_EN6

[7:0]

[15:8] CH_EN7

[7:0]

[15:8] CH_EN8

[7:0]

[15:8] CH_EN9

[7:0]

[15:8] CH_EN10

[7:0]

[15:8] CH_EN11

[7:0]

[15:8] CH_EN12

[7:0]

[15:8] CH_EN13

[7:0]

[15:8] CH_EN14

[7:0]

[15:8] CH_EN15

[7:0]

Rev. 0 | Page 47 of 59

AD4±±6

Data Sheet

Register Name

Bits

Bit 7

Bit 6

Reserved

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset¹

R/W

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

SETUPCON0 [15:8]

[7:0]

BI_UNIPOLAR0 REFBUF0+ REFBUF0−

INBUF0

INBUF1

INBUF2

INBUF3

INBUF4

INBUF5

INBUF6

INBUF7

0x1000 R/W

0x0500 R/W

REF_SEL0

Reserved

SETUPCON1 [15:8]

[7:0]

BI_UNIPOLAR1 REFBUF1+ REFBUF1−

REF_SEL1

Reserved

SETUPCON2 [15:8]

[7:0]

BI_UNIPOLAR2 REFBUF2+ REFBUF2−

REF_SEL2

REF_SEL3

Reserved

SETUPCON3 [15:8]

[7:0]

BI_UNIPOLAR3 REFBUF3+ REFBUF3−

Reserved

SETUPCON4 [15:8]

[7:0]

BI_UNIPOLAR4 REFBUF4+ REFBUF4−

REF_SEL4

Reserved

SETUPCON5 [15:8]

[7:0]

BI_UNIPOLAR5 REFBUF5+ REFBUF5−

REF_SEL5

Reserved

SETUPCON6 [15:8]

[7:0]

BI_UNIPOLAR6 REFBUF6+ REFBUF6−

REF_SEL6

Reserved

SETUPCON7 [15:8]

[7:0]

BI_UNIPOLAR7 REFBUF7+ REFBUF7−

REF_SEL7

Reserved

ENHFILT0

FILTCON0 [15:8] SINC3_MAP0

[7:0] Reserved

Reserved

ORDER0

Reserved

ORDER1

Reserved

ORDER2

Reserved

ORDER3

Reserved

ORDER4

Reserved

ORDER5

Reserved

ORDER6

Reserved

ORDER7

ENHFILTEN0

ENHFILTEN1

ENHFILTEN2

ENHFILTEN3

ENHFILTEN4

ENHFILTEN5

ENHFILTEN6

ENHFILTEN7

ODR0

ODR1

ODR2

ODR3

ODR4

ODR5

ODR6

ODR7

FILTCON1 [15:8] SINC3_MAP1

[7:0] Reserved

ENHFILT1

ENHFILT2

ENHFILT3

ENHFILT4

ENHFILT5

ENHFILT6

ENHFILT7

FILTCON2 [15:8] SINC3_MAP2

[7:0] Reserved

FILTCON3 [15:8] SINC3_MAP3

[7:0] Reserved

FILTCON4 [15:8] SINC3_MAP4

[7:0] Reserved

FILTCON5 [15:8] SINC3_MAP5

[7:0] Reserved

FILTCON6 [15:8] SINC3_MAP6

[7:0] Reserved

FILTCON7 [15:8] SINC3_MAP7

[7:0] Reserved

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

OFFSET0

OFFSET1

OFFSET2

OFFSET3

OFFSET4

OFFSET5

OFFSET6

OFFSET7

GAIN0

[23:0]

OFFSET0[23:0]

0x800000 R/W

0x5XXXX0 R/W

OFFSET1[23:0]

OFFSET2[23:0]

OFFSET3[23:0]

OFFSET4[23:0]

OFFSET5[23:0]

OFFSET6[23:0]

OFFSET7[23:0]

GAIN0[23:0]

GAIN1[23:0]

GAIN2[23:0]

GAIN3[23:0]

GAIN4[23:0]

GAIN5[23:0]

GAIN6[23:0]

GAIN7[23:0]

GAIN1

GAIN2

GAIN3

GAIN4

GAIN5

GAIN6

GAIN7

¹X means don’t care.

Rev. 0 | Page 48 of 59

Data Sheet

AD4±±6

REGISTER DETAILS

COMMUNICATIONS REGISTER

Address: 0x00, Reset: 0x00, Name: COMMS

All access to the on-chip registers must start with a write to the communications register. This write determines which register is

accessed next and whether that operation is a write or a read.

Table 25. Bit Descriptions for COMMS

Bits Bit Name

Settings Description

Reset Access

7

6

WEN

R/W

This bit must be low to begin communications with the ADC.

0x0

W

This bit determines if the command is a read or write operation.

0

1

Write command.

Read command.

[5:0] RA

The register address bits determine the register to be read from or written to as part

of the current communication.

0x00

W

000000 Status register.

000001 ADC mode register.

000010 Interface mode register.

000011 Register checksum register.

000100 Data register.

000110 GPIO configuration register.

000111 ID register.

010000 Channel 0 register.

010001 Channel 1 register.

010010 Channel 2 register.

010011 Channel 3 register.

010100 Channel 4 register.

010101 Channel 5 register.

010110 Channel 6 register.

010111 Channel 7 register.

011000 Channel 8 register.

011001 Channel 9 register.

011010 Channel 10 register.

011011 Channel 11 register.

011100 Channel 12 register.

011101 Channel 13 register.

011110 Channel 14 register.

011111 Channel 15 register.

100000 Setup Configuration 0 register.

100001 Setup Configuration 1 register.

100010 Setup Configuration 2 register.

100011 Setup Configuration 3 register.

100100 Setup Configuration 4 register.

100101 Setup Configuration 5 register.

100110 Setup Configuration 6 register.

100111 Setup Configuration 7 register.

101000 Filter Configuration 0 register.

101001 Filter Configuration 1 register.

101010 Filter Configuration 2 register.

101011 Filter Configuration 3 register.

101100 Filter Configuration 4 register.

101101 Filter Configuration 5 register.

101110 Filter Configuration 6 register.

101111 Filter Configuration 7 register.

Rev. 0 | Page 49 of 59

AD4±±6

Data Sheet

Bits Bit Name

Settings Description

110000 Offset 0 register.

110001 Offset 1 register.

110010 Offset 2 register.

110011 Offset 3 register.

110100 Offset 4 register.

110101 Offset 5 register.

110110 Offset 6 register.

110111 Offset 7 register.

111000 Gain 0 register.

111001 Gain 1 register.

111010 Gain 2 register.

111011 Gain 3 register.

111100 Gain 4 register.

111101 Gain 5 register.

111110 Gain 6 register.

111111 Gain 7 register.

Reset Access

STATUS REGISTER

Address: 0x00, Reset: 0x80, Name: Status

The status register is an 8-bit register that contains ADC and serial interface status information. The register can optionally be appended

to the data register by setting the DATA_STAT bit in the interface mode register.

Table 26. Bit Descriptions for Status

Bits Bit Name

Settings Description

Reset Access

7

RDY

The status of RDY is output to the DOUT/RDY pin when CS is low and a register is not

0x1

R

being read. This bit goes low when the ADC writes a new result to the data register. In

ADC calibration modes, this bit goes low when the ADC writes the calibration result.

RDY is brought high automatically by a read of the data register.

0

1

New data result available.

Awaiting new data result.

6

ADC_ERROR

By default, this bit indicates if an ADC overrange or underrange occurred. The ADC

result is clamped to 0xFFFFFF for overrange errors and 0x000000 for underrange

errors. This bit is updated when the ADC result is written and is cleared at the next

update after removing the overrange or underrange condition.

0x0

R

0

1

No error.

Error.

5

4

CRC_ERROR

REG_ERROR

This bit indicates if a CRC error occurred during a register write. For register reads, the

host microcontroller determines if a CRC error occurred. This bit is cleared by a read of

this register.

No error.

CRC error.

0x0

R

0

1

This bit indicates if the content of one of the internal registers changes from the value

calculated when the register integrity check is activated. The check is activated by

setting the REG_CHECK bit in the interface mode register. This bit is cleared by

clearing the REG_CHECK bit.

0

1

No error.

Error.

Rev. 0 | Page 50 of 59

Data Sheet

AD4±±6

Bits Bit Name

Settings Description

These bits indicate which channel was active for the ADC conversion whose result is

Reset Access

[3:0] Channel

0x0

R

currently in the data register, which may be different from the channel currently being

converted. The mapping is a direct map from the channel register; therefore, Channel 0

results in 0x0 and Channel 15 results in 0xF.

0000 Channel 0.

0001 Channel 1.

0010 Channel 2.

0011 Channel 3.

0100 Channel 4.

0101 Channel 5.

0110 Channel 6.

0111 Channel 7.

1000 Channel 8.

1001 Channel 9.

1010 Channel 10.

1011 Channel 11.

1100 Channel 12.

1101 Channel 13.

1110 Channel 14.

1111 Channel 15.

ADC MODE REGISTER

Address: 0x01, Reset: 0x2000, Name: ADCMODE

The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets

RDY

the filter and the

bits and starts a new conversion or calibration.

Table 27. Bit Descriptions for ADCMODE

Bits

Bit Name

Settings Description

This bit enables the internal reference and outputs a buffered 2.5 V to the REFOUT pin.

Disabled.

Reset Access

15

REF_EN

0x0

R/W

0

1

Enabled.

Reserved

14

13

This bit is reserved. Set this bit to 0.

0x0

0x1

R/W

SING_CYC

This bit can be used when only a single channel is active to set the ADC to only

output at the settled filter data rate.

0

1

Disabled.

Enabled.

[12:11] Reserved

These bits are reserved. Set these bits to 0.

0x0

R

[10:8]

Delay

These bits allow a programmable delay to be added after a channel switch to allow

the settling of the external circuitry before the ADC starts processing its input.

R/W

000 0 µs.

001 16 µs.

010 64 µs.

011 160 µs.

100 400 µs.

101 800 µs.

110 3 ms.

111 4 ms.

7

Reserved

This bit is reserved. Set this bit to 0.

0x0

R

Rev. 0 | Page 51 of 59

AD4±±6

Data Sheet

Bits

Bit Name

Settings Description

These bits control the operating mode of the ADC. See the Operating Modes section

Reset Access

[6:4]

Mode

0x0

R/W

for more information.

000 Continuous conversion mode.

001 Single conversion mode.

010 Standby mode.

011 Power-down mode.

100 Internal offset calibration.

101 Internal gain calibration

110 System offset calibration.

111 System gain calibration.

[3:2]

[1:0]

CLOCKSEL

Reserved

These bits select the ADC clock source. Selecting the internal oscillator also enables

the internal oscillator.

00 Internal oscillator

01 Internal oscillator output on the XTAL2/CLKIO pin.

10 External clock input on the XTAL2/CLKIO pin.

11 External crystal on the XTAL1 pin and the XTAL2/CLKIO pin.

These bits are reserved. Set these bits to 0.

0x0

R/W

R

INTERFACE MODE REGISTER

Address: 0x02, Reset: 0x0000, Name: IFMODE

The interface mode register configures various serial interface options.

Table 28. Bit Descriptions for IFMODE

Bits

Bit Name

Settings Description

Reset Access

[15:13] Reserved

These bits are reserved Set these bits to 0.

0x0

R

12

11

ALT_SYNC

This bit enables a different behavior of the SYNC pin to allow the use of SYNC as a

control for conversions when cycling channels.

Disabled.

Enabled.

R/W

0

1

IOSTRENGTH

This bit controls the drive strength of the DOUT/RDY pin. Set this bit when reading

0x0

R/W

from the SPI at high speed with a low IOVDD supply and moderate capacitance.

0

1

Disabled (default).

Enabled.

[10:9]

8

Reserved

These bits are reserved. Set these bits to 0.

See the DOUT_RESET section.

Disabled.

0x0

R

DOUT_RESET

R/W

0

1

Enabled.

7

6

CONTREAD

DATA_STAT

This bit enables the continuous read mode of the ADC data register. The ADC must be

configured in continuous conversion mode to use continuous read mode. For

more details, see the Operating Modes section.

Disabled.

Enabled.

0x0

R/W

0

1

This bit enables the status register to be appended to the data register when read

so that channel and status information are transmitted with the data, which is the

only way to be sure that the channel bits read from the status register correspond

to the data in the data register.

0

1

Disabled.

Enabled.

Rev. 0 | Page 52 of 59

Data Sheet

AD4±±6

Bits

Bit Name

Settings Description

This bit enables a register integrity checker, which can be used to monitor any change

Reset Access

5

REG_CHECK

0x0

R/W

in the value of the user registers. To use this feature, configure all other registers as

desired with this bit cleared. Then, write to this register to set the REG_CHECK bit to 1.

If the contents of any of the registers change, the REG_ERROR bit is set in the status

register. To clear the error, set the REG_CHECK bit to 0. Neither the interface mode

register nor the ADC data or status registers are included in the registers that are

checked. If a register must have a new value written, this bit must first be cleared.

Otherwise, an error is flagged when the new register contents are written.

0

1

Disabled.

Enabled.

4

Reserved

CRC_EN

This bit is reserved. Set this bit to 0.

0x0

R

[3:2]

These bits enable CRC protection of register reads and writes. CRC increases the

number of bytes in a SPI transfer by one.

0x00

R/W

00 Disabled.

01 XOR checksum enabled for register read transactions. Note that register writes still

use CRC with these bits set.

10 CRC checksum enabled for read and write transactions.

This bit is reserved. Set this bit to 0.

1

0

Reserved

WL16

0x0

R

This bit changes the ADC data register to 16 bits. The ADC is not reset by a write to

the interface mode register. Therefore, the ADC result is not rounded to the correct

word length immediately after writing to these bits. The first new ADC result is correct.

R/W

0

1

24-bit data.

16-bit data.

REGISTER CHECK

Address: 0x03, Reset: 0x000000, Name: REGCHECK

The register check register is a 24-bit checksum calculated by exclusively OR’ing the contents of the user registers. The REG_CHECK bit

in the interface mode register must be set for this checksum to operate. Otherwise, the register reads 0.

Table 29. Bit Descriptions for REGCHECK

Bits

Bit Name

Settings Description

This register contains the 24-bit checksum of user registers when the

REG_CHECK bit is set in the interface mode register.

Reset

Access

[23:0] REGISTER_CHECK

0x000000

R

DATA REGISTER

Address: 0x04, Reset: 0x000000, Name: Data

The data register contains the ADC conversion result. The encoding is offset binary, or it can be changed to unipolar by the

RDY RDY

output high if it is

BI_UNIPOLARx bits in the setup configuration registers. Reading the data register brings the

bit and the

output is brought high, it is not possible to determine if

RDY

low. The ADC result can be read multiple times. However, because the

another ADC result is imminent. After the command to read the ADC register is received, the ADC does not write a new result into the data

register.

Table 30. Bit Descriptions for Data

Bits

Bit Name

Settings Description

Reset

Access

[23:0]

Data

This register contains the ADC conversion result. If DATA_STAT is set in the

0x000000

R

interface mode register, the status register is appended to this register when

read, making this a 32-bit register.

Rev. 0 | Page 53 of 59

AD4±±6

Data Sheet

GPIO CONFIGURATION REGISTER

Address: 0x06, Reset: 0x0800, Name: GPIOCON

The GPIO configuration register controls the general-purpose input and output pins of the ADC.

Table 31. Bit Descriptions for GPIOCON

Bits

Bit Name

Settings Description

Reset Access

[15:14] Reserved

Reserved.

0x0

R

R/W

13

12

OP_EN2_3

MUX_IO

GPO2/GPO3 Output Enable. This bit enables the GPO2 and GPO3 pins. The outputs

are referenced between AVDD and AVSS.

Disabled.

Enabled.

This bit allows the ADC to control an external multiplexer, using GPIO0/GPIO1/

GPO2/GPO3 in sync with the internal channel sequencing. The analog input pins used

for a channel can still be selected on a per channel basis. Therefore, it is possible to

have a 16-channel multiplexer in front of each analog input pair (VIN0/VIN1 to

VIN10/VINCOM and ADCIN11/ADCIN12 to ADCIN13/ADCIN14), giving a total of 128

differential channels. However, only 16 channels at a time can be automatically

sequenced. Following the sequence of 16 channels, the user changes the analog input

to the next pair of input channels, and it sequences through the next 16 channels.

There is a delay function that allows extra time for the analog input to settle, in

conjunction with any switching of an external multiplexer (see the delay bits in the

ADC Mode Register section).

0

1

0x0

R

11

SYNC_EN

SYNC Input Enable. This bit enables the SYNC pin as a sync input. When set low, the

SYNC pin holds the ADC and filter in reset until SYNC goes high. An alternative

operation of the SYNC pin is available when the ALT_SYNC bit in the interface mode

register is set. This mode works only when multiple channels are enabled. In such

cases, a low on the SYNC pin does not immediately reset the filter and modulator.

Instead, if the SYNC pin is low when the channel is due to be switched, the

modulator and filter are prevented from starting a new conversion. Bringing SYNC

high begins the next conversion. This alternative sync mode allows SYNC to be used

while cycling through channels.

0x1

R/W

0

1

Disabled.

Enabled.

[10:9]

ERR_EN

ERROR Pin Mode. These bits enable the ERROR pin as an error input and output.

Disabled.

Enables error input (active low). ERROR is an error input. The (inverted) readback

state is OR'ed with other error sources and is available in the ADC_ERROR bit in the

status register. The ERROR pin state can also be read from the ERR_DAT bit in this

register.

0x0

R/W

00

01

10

11

Enables open-drain error output (active low). ERROR is an open-drain error output.

The status register error bits are OR'ed, inverted, and mapped to the ERROR pin.

ERROR pins of multiple devices can be wired together to a common pull-up resistor

so that an error on any device can be observed.

General-purpose output (active low). ERROR is a general-purpose output. The status

of the pin is controlled by the ERR_DAT bit in this register. This output is referenced

between IOVDD and DGND, as opposed to the AVDD and AVSS levels used by the

GPIOx pins. The output has an active pull-up resistor in this case.

8

ERR_DAT

ERROR Pin Data. This bit determines the logic level at the ERROR pin if the pin is

enabled as a general-purpose output. This bit reflects the readback status of the pin

if the pin is enabled as an input.

0x0

R/W

0

1

Logic 0.

Logic 1.

7

6

GP_DATA3

GP_DATA2

GPO1 Data. This bit is the write data for GPO1.

GPO1 = 0.

GPO1 = 1.

GPO0 Data. This bit is the write data for GPO0.

GPO0 = 0.

GPO0 = 1.

0x0

R/W

0

1

0

1

Rev. 0 | Page 54 of 59

Data Sheet

AD4±±6

Bits

5

Bit Name

IP_EN1

Settings Description

This bit runs GPIO1 into an input. Input must be equal to AVDD or AVSS.

Disabled.

Reset Access

0x0

R/W

0

1

Enabled.

4

3

2

IP_EN0

This bit runs GPIO0 into an input. Input must be equal to AVDD or AVSS.

0

1

Disabled.

Enabled.

OP_EN1

OP_EN0

This bit runs GPIO1 into an output. Outputs are referenced between AVDD or AVSS.

0

1

Disabled.

Enabled.

This bit runs GPIO0 into an output. Outputs are referenced between AVDD or AVSS.

0

1

Disabled.

Enabled.

1

0

GP_DATA1

GP_DATA0

This bit is the readback or write data for GPIO1.

This bit is the readback or write data for GPIO0.

0x0

R/W

ID REGISTER

Address: 0x07, Reset: 0x34DX, Name: ID

The ID register returns a 16-bit ID. For the AD4116, this value is 0x34Dx.

Table 32. Bit Descriptions for ID

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

ID

Product ID. The ID register returns a 16-bit ID code that is specific to the ADC.

0x34DX

R

CHANNEL REGISTER 0 TO CHANNEL REGISTER 15

Address: 0x10 to Address 0x1F, Reset: 0x8001, Name: CH0 to CH15

The channel registers are 16-bit registers that select the currently active channels, the selected inputs for each channel, and the setup to

be used to configure the ADC for that channel. The layout for CH0 to CH15 is identical except that the default CH_ENx bit for CH1 to

CH15 is 0x0.

Table 33. Bit Descriptions for CH0 to CH15

Bits

Bit Name

Settings

Description

Reset Access

15

CH_ENx

This bit enables Channel 0. If more than one channel is enabled, the ADC

automatically sequences between them.

0x1

R/W

0

1

Disabled.

Enabled.

[14:12] SETUP_SELx

These bits identify which of the eight setups is used to configure the ADC for

this channel. A setup comprises a set of four registers: a setup configuration

register, a filter configuration register, an offset register, and a gain register. All

channels can use the same setup, in which case, the same 3-bit value must be

written to these bits on all active channels, or up to eight channels can be

configured differently.

0x0

R/W

000 Setup 0.

001 Setup 1.

010 Setup 2.

011 Setup 3.

100 Setup 4.

101 Setup 5.

110 Setup 6.

111 Setup 7.

Reserved.

[11:10] Reserved

0x0

R

Rev. 0 | Page 55 of 59

AD4±±6

Data Sheet

Bits

[9:0]

Bit Name

INPUTx

Settings

Description

Reset Access

These bits select which input pair is connected to the input of the ADC for this

channel.

0x1

R/W

0000000001 VIN0 and VIN1.

0000010000 VIN0 and VINCOM.

0000100000 VIN1 and VIN0.

0000110000 VIN1 and VINCOM.

0001000011 VIN2 and VIN3.

0001010000 VIN2 and VINCOM.

0001100010 VIN3 and VIN2.

0001110000 VIN3 and VINCOM.

0010000101 VIN4 and VIN5.

0010010000 VIN4 and VINCOM.

0010100100 VIN5 and VIN4.

0010110000 VIN5 and VINCOM.

0011000111 VIN6 and VIN7.

0011010000 VIN6 and VINCOM.

0011100110 VIN7 and VIN6.

0011110000 VIN7 and VINCOM.

0100001001 VIN8 and VIN9.

0100010000 VIN8 and VINCOM.

0100101000 VIN9 and VIN8.

0100110000 VIN9 and VINCOM.

0101010000 VIN10, VINCOM (single-ended or differential pair)

0101101100 ADCIN11, ADCIN12.

0110001011 ADCIN12, ADCIN11.

0110101110 ADCIN13, ADCIN14.

0111001101 ADCIN14, ADCIN13.

0101101111 ADCIN11, ADCIN15. (pseudo differential or differential pair)

0110001111 ADCIN12, ADCIN15. (pseudo differential or differential pair)

0110101111 ADCIN13, ADCIN15. (pseudo differential or differential pair)

0111001111 ADCIN14, ADCIN15. (pseudo differential or differential pair)

1000110010 Temperature sensor.

1010110110 Reference.

SETUP CONFIGURATION REGISTER 0 TO SETUP CONFIGURATION REGSITER 7

Address: 0x20 to 0x27, Reset: 0x1000 Name: SETUPCON0 to SETUPCON7

The setup configuration registers are 16-bit registers that configure the reference selection, input buffers, and output coding of the ADC.

The layout for SETUPCON0 to SETUPCON7 is identical.

Table 34. Bit Descriptions for SETUPCON0 to SETUPCON7

Bits

Bit Name

Settings Description

Reset Access

[15:13] Reserved

These bits are reserved. Set these bits to 0.

Bipolar and Unipolar Output. This bit sets the output coding of the ADC for

Setup 0.

0x0

0x1

R

12

BI_UNIPOLARx

R/W

0

1

Unipolar coded output.

Bipolar coded output.

11

10

REFBUFx+

REFBUFx−

REF+ Buffer. This bit enables or disables the REF+ input buffer.

Disabled.

Enabled.

0x0

R/W

0

1

REF− Buffer. This bit enables or disables the REF− input buffer.

0

1

Disabled.

Enabled.

Rev. 0 | Page 56 of 59

Data Sheet

AD4±±6

Bits

[9:8]

Bit Name

INBUFx

Settings Description

Input Buffer. This bit enables or disables input buffers.

Reset Access

0x0

R/W

00 Disabled.

01 Reserved.

10 Reserved.

11 Enabled.

[7:6]

[5:4]

Reserved

REF_SELx

This bit is reserved. Set this bit to 0.

These bits allow the user to select the reference source for ADC conversion on

Setup 0.

0x0

R

R/W

00 External reference − REF .

10 Internal 2.5 V reference must be enabled via ADCMODE (see Table 27).

11 AVDD − AVSS.

[3:0]

Reserved

These bits are reserved. Set these bits to 0.

0x0

R

FILTER CONFIGURATION REGISTER 0 TO FILTER CONFIGURATION REGISTER 7

Address: 0x28 to 0x2F, Reset: 0x0500, Name: FILTCON0 to FILTCON7

The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets

any active ADC conversion and restarts converting at the first channel in the sequence. The layout for FILTCON0 to FILTCON7 is identical.

Table 35. Bit Descriptions for FILTCON0 to FILTCON7

Bits

Bit Name

Settings Description

Reset Access

15

SINC3_MAPx

If this bit is set, the mapping of the filter register changes to directly program the

0x0

R/W

decimation rate of the sinc3 filter for Setup 0. All other options are eliminated. This bit

allows fine tuning of the output data rate and filter notch for rejection of specific

frequencies. The data rate when on a single channel equals f_MOD/(32 × FILTCON0[14:0]).

[14:12] Reserved

These bits are reserved. Set these bits to 0.

0x0

R

11

ENHFILTENx

This bit enables various post filters for enhanced 50 Hz/60 Hz rejection for Setup 0. The

ORDER0 bits must be set to 00 to select the sinc5 + sinc1 filter for this function to work.

R/W

0

1

Disabled.

Enabled.

[10:8]

ENHFILTx

These bits select between various post filters for enhanced 50 Hz/60 Hz rejection

for Setup 0.

0x5

R/W

010 27 SPS, 47 dB rejection, and 36.7 ms settling.

011 25 SPS, 62 dB rejection, and 40 ms settling.

101 20 SPS, 86 dB rejection, and 50 ms settling.

110 16.67 SPS, 92 dB rejection, and 60 ms settling.

This bit is reserved. Set this bit to 0.

7

Reserved

ORDERx

0x0

R

[6:5]

These bits control the order of the digital filter that processes the modulator data for

Setup 0.

R/W

00 Sinc5 + sinc1 (default).

11 Sinc3.

[4:0]

ODRx

These bits control the output data rate of the ADC and, therefore, the settling time

and noise for Setup x. Rates shown are for single channel enabled sinc5 + sinc 1 filter.

See Table 7 for multiple channels enabled.

0x0

R/W

62500 SPS.

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

62500 SPS.

31250 SPS.

15625 SPS.

10416.7 SPS.

5194.8 SPS (5208.3 SPS for sinc3).

2496.9 SPS (2500 SPS for sinc3).

1007.6 SPS (1008.1 SPS for sinc3).

499.9 SPS (500 SPS for sinc3).

Rev. 0 | Page 57 of 59

AD4±±6

Data Sheet

Bits

Bit Name

Settings Description

Reset Access

390.6 SPS (400.64 SPS for sinc3).

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

200.3 SPS (200.32 SPS for sinc3).

100.0 SPS.

59.75 SPS (59.98 SPS for sinc3).

49.84 SPS (50 SPS for sinc3).

20.00 SPS.

16.65 SPS (16.67 SPS for sinc3).

10.00 SPS.

5.00 SPS.

2.50 SPS.

1.25 SPS.

OFFSET REGISTER 0 TO OFFSET REGISTER 7

Address: 0x30 to 0x37, Reset: 0x800000, Name: OFFSET0 to OFFSET7

The offset (zero-scale) registers are 16-bit registers that can be used to compensate for any offset error in the ADC or in the system. The

layout for OFFSET0 to OFFSET7 is identical.

Table 36. Bit Descriptions for OFFSET0 to OFFSET7

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

OFFSETx

Offset calibration coefficient for Setup 0.

0x800000

R/W

GAIN REGISTER 0 TO GAIN REGISTER 7

Address: 0x38 to 0x3F, Reset: 0x5XXXX0, Name: GAIN0 to GAIN7

The gain (full-scale) registers are 16-bit registers that can be used to compensate for any gain error in the ADC or in the system. The

layout for GAIN0 to GAIN7 is identical.

Table 37. Bit Descriptions for GAIN0 to GAIN7

Bits

Bit Name

Settings

Description

Reset¹

Access

[23:0]

GAINx

Gain calibration coefficient for Setup 0.

0x5XXXX0

R/W

¹X means don’t care.

Rev. 0 | Page 58 of 59

Data Sheet

AD4±±6

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

6.10

6.00 SQ

5.90

0.30

0.25

0.18

PIN 1

INDICATOR

AREA

PIN 1

IONS

INDICATOR AR EA OP T

(SEE DETAIL A)

31

40

30

1

0.50

BSC

4.70

EXPOSED

PAD

4.60 SQ

4.50

21

10

20

11

0.45

0.40

0.35

0.20 MIN

TOP VIEW

SIDE VIEW

BOTTOM VIEW

1.00

0.95

0.85

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5

Figure 62. 40-Lead Lead Frame Chip Scale Package [LFCSP]

6 mm × 6 mm Body and 0.95 mm Package Height

(CP-40-15)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

AD4116BCPZ

−40°C to +105°C

40-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

CP-40-15

AD4116BCPZ-RL7

EVAL-AD4116ASDZ

EVAL-SDP-CB1Z

Evaluation Controller Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D25501-12/21(0)

Rev. 0 | Page 59 of 59


型号：	AD4116
厂家：	ADI
描述：	Single Supply, 24-Bit, Sigma-Delta ADC with Â±10 V, 10 MÎ© Inputs and Buffered Low Level Inputs
文件：	总59页 (文件大小：1046K)
中文：	中文翻译
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AD4116 [ADI]

相关型号：

AD4116BCPZ

AD4116BCPZ-RL7

AD412

AD4134

AD4134BCPZ

AD4134BCPZ-RL7

AD420

AD420AN

AD420AN-32

AD420ANZ-32

AD420AR

AD420AR-32