AD1953YSTRL_技术文档

SigmaDSP^™3-Channel, 26-Bit

Signal Processing DAC

a

AD1953

FEATURES

APPLICATIONS

5 V 3-Channel Audio DAC System

Digital Audio Output (2-Channel or 6-Channel

Packed Mode)

2.0/2.1 Channel Audio Systems (2 Main Channels

Plus Subwoofer)

Multichannel Automotive Sound Systems

Multimedia Audio

Mini Component Stereo

Home Theater Systems (AC-3 Postprocessor)

Musical Instruments

Accepts Sample Rates up to 48 kHz

7 Biquad Filter Sections per Channel

Dual Dynamic Processor with Arbitrary Input/Output

Curve and Adjustable Time Constants

0 ms to 6 ms Variable Delay/Channel for Speaker Alignment

Stereo Spreading Algorithm for Phat Stereo™ Effect

Program RAM Allows Complete New Program Download

via SPI Port

Parameter RAM Allows Complete Control of More Than

200 Parameters via SPI Port

SPI Port Features Safe-Upload Mode for Transparent

Filter Updates

In-Seat Sound Systems (Aircraft, Motor Coaches)

PRODUCT OVERVIEW

The AD1953 is a complete 26-bit, single-chip, 3-channel digital

audio playback system with built-in DSP functionality for speaker

equalization, dual-band compression/limiting, delay compensa-

tion, and image enhancement. These algorithms can be used to

compensate for real-world limitations of speakers, amplifiers,

and listening environments, resulting in a dramatic improvement

of perceived audio quality.

2 Control Registers Allow Complete Control of Modes

and Memory Transfers

Differential Output for Optimum Performance

112 dB Signal-to-Noise (Not Muted) at 48 kHz Sample

Rate (A-Weighted Stereo)

70 dB Stop-Band Attenuation

On-Chip Clickless Volume Control

Hardware and Software Controllable Clickless Mute

Digital De-emphasis Processing for 32 kHz, 44.1 kHz, 48 kHz

Sample Rates

The signal processing used in the AD1953 is comparable to that

found in high end studio equipment. Most of the processing is

done in full 48-bit double-precision mode, resulting in very good

low level signal performance and the absence of limit cycles or

idle tones. The compressor/limiter uses a sophisticated two-band

algorithm often found in high end broadcast compressors.

(continued on page 9)

Flexible Serial Data Port with Right-Justified, Left-Justified,

I²S Compatible, and DSP Serial Port Modes

Auxiliary Digital Input

Graphical Custom Programming Tools

48-Lead LQFP Plastic Package

FUNCTIONAL BLOCK DIAGRAM

SERIAL DATA

OUTPUT

3

AD1953

3

AUDIO DATA

MUX

SERIAL DATA

INPUTS

DAC – L

26 ꢀ 22

DSP CORE

MASTER CLOCK

OUTPUT

ANALOG

OUTPUTS

DATA FORMAT:

3.23 (SINGLE PRECISION)

3.45 (DOUBLE PRECISION)

DAC – R

MCLK

GENERATOR

(256/512 f )

MASTER

CLOCK INPUTS

MCLK

MUX

DAC – SW

S

AUX SERIAL

DATA INPUT

DIGITAL

OUTPUT

DATA CAPTURE

OUT/TDM OUT

SPI DATA

OUTPUT

SERIAL CONTROL

INTERFACE

3

SPI INPUT

RAM

ROM

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

AD1953

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 7

TYPICAL PERFORMANCE CHARACTERISTICS . . . . . 8

PERFORMANCE PLOTS . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SIGNAL PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Signal Processing Overview . . . . . . . . . . . . . . . . . . . . . . . 12

Numeric Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Coefficient Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Internal DSP Signal Data Format . . . . . . . . . . . . . . . . . . 13

High-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Biquad Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Stereo Image Expander . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Main Compressor/Limiter . . . . . . . . . . . . . . . . . . . . . . . . 15

RMS Time Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

RMS Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

RMS Release Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Look-Ahead Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Post-Compression Gain . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Subwoofer Compressor/Limiter . . . . . . . . . . . . . . . . . . . . 17

De-Emphasis Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Using the Sub Reinjection Paths for Systems with No

Subwoofer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Interpolation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SPI PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SPI Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Volume Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Parameter RAM Contents . . . . . . . . . . . . . . . . . . . . . . . . 23

Options for Parameter Updates . . . . . . . . . . . . . . . . . . . . 24

Soft Shutdown Mechanism . . . . . . . . . . . . . . . . . . . . . . . 25

Safeload Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Summary of RAM Modes . . . . . . . . . . . . . . . . . . . . . . . . 25

SPI READ/WRITE DATA FORMATS . . . . . . . . . . . . . . . 26

INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Setting the Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Setting the Data and MCLK Input Selectors . . . . . . . . . . 28

DATA CAPTURE REGISTERS AND OUTPUTS . . . . . . 28

SERIAL DATA INPUT/OUTPUT PORTS . . . . . . . . . . . . 30

Serial Data Input/Output Modes . . . . . . . . . . . . . . . . . . . 30

DIGITAL CONTROL PIN . . . . . . . . . . . . . . . . . . . . . . . . 31

Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

ANALOG OUTPUT SECTION . . . . . . . . . . . . . . . . . . . . 31

GRAPHICAL CUSTOM PROGRAMMING TOOLS . . . . 32

APPENDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 34

REV. 0

–2–

AD1953

SPECIFICATIONS

TEST CONDITIONS, UNLESS OTHERWISE NOTED.

Supply Voltages (AVDD, DVDD) 5.0 V

Ambient Temperature

Input Clock

Input Signal

Input Sample Rate

Measurement Bandwidth

Word Width

25°C

12.288 MHz

1.000 kHz 0 dB Full Scale

48 kHz

20 Hz to 20 kHz

24 Bits

Load Capacitance

Load Impedance

Input Voltage High

Input Voltage Low

2200 pF

2.74 kΩ

2.1 V

0.8 V

ANALOG PERFORMANCE*

Parameter

Min

Typ

Max

Unit

RESOLUTION

24

Bits

SIGNAL-TO-NOISE RATIO (20 Hz to 20 kHz) (Left/Right Output)

No Filter (Stereo)

With A-Weighted Filter

109

112

dB

DYNAMIC RANGE (20 Hz to 20 kHz, –60 dB Input) (Left/Right Output)

No Filter

With A-Weighted Filter

109

112

dB

108

–93

TOTAL HARMONIC DISTORTION PLUS NOISE (Left/Right Output)

V_O= –0.5 dB

–100

dB

SIGNAL-TO-NOISE RATIO (20 Hz to 20 kHz) (Subwoofer Output)

No Filter (Stereo)

With A-Weighted Filter

104

107

dB

DYNAMIC RANGE (20 Hz to 20 kHz, –60 dB Input) (Subwoofer Output)

No Filter

With A-Weighted Filter

104

107

dB

104

–90

TOTAL HARMONIC DISTORTION PLUS NOISE (Subwoofer Output)

V_O= –0.5 dB

–96

dB

ANALOG OUTPUTS

Differential Output Range ( Full Scale) (Left/Right Output)

Differential Output Range ( Full Scale) (Subwoofer Output)

2.72

2.79

V p-p

CMOUT

2.50

V

DC ACCURACY

Gain Error (Left/Right Channel)

Gain Error (Subwoofer Channel)

Interchannel Gain Mismatch

Gain Drift

–5

–8

–0.250

+5

+8

+0.250

%

dB

ppm/°C

mV

150

DC Offset

–35

+35

INTERCHANNEL CROSSTALK (EIAJ Method)

INTERCHANNEL PHASE DEVIATION

MUTE ATTENUATION

–120

0.1

dB

Degrees

dB

–107

DE-EMPHASIS GAIN ERROR

0.1

dB

*Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).

Specifications subject to change without notice.

–3–

REV. 0

AD1953

DIGITAL I/O

Parameter

Min

Typ

Max

Unit

Input Voltage High (V_IH)

Input Voltage High (V_IH) – RESETB

Input Voltage Low (V_IL)

Input Leakage (I_IH@ V_IH= 2.1 V)

Input Leakage (I_IL@ V_IL= 0.8 V)

High Level Output Voltage (V_OH), I_OH= 2 mA

Low Level Output Voltage (V_OL), I_OL= 2 mA

Input Capacitance

2.1

2.25

V

µA

V

pF

0.8

10

DVDD – 0.5

0.4

20

Specifications subject to change without notice.

POWER

Parameter

Min

Typ

Max

Unit

SUPPLIES*

Voltage: Analog, and Digital

Analog Current

Analog Current, Power-Down

Digital Current

Digital Current, SPI Power-Down

Digital Current, Reset Power-Down

4.5

5

5.5

48

46

76

10

62

V

42

40

66

6

mA

54

DISSIPATION

Operation, Both Supplies

Operation, Analog Supplies

Operation, Digital Supplies

SPI Power-Down, Both Supplies

Reset Power-Down, Both Supplies

540

210

330

230

470

mW

POWER SUPPLY REJECTION RATIO

1 kHz 300 mV p-p Signal at Analog Supply Pins

20 kHz 300 mV p-p Signal at Analog Supply Pins

–80

dB

*ODVDD current is dependent on load capacitance and clock rate.

Specifications subject to change without notice.

TEMPERATURE RANGE

Parameter

Min

Typ

Max

Unit

Specifications Guaranteed

Functionality Guaranteed

Storage

25

°C

–40

–55

ꢁ105

ꢁ125

Specifications subject to change without notice.

REV. 0

–4–

AD1953

DIGITAL TIMING

Parameter

Min

Typ

Max

Unit

t_DMDMCLK Recommended Duty Cycle @ 12.288 MHz (256 f_SMode)

t_DMDMCLK Recommended Duty Cycle @ 24.576 MHz (512 f_SMode)

t_DMDMCLK Delay (All Mode)

45

40

55

60

25

%

ns

t_DBH

t_DBD

t_DLS

t_DLH

t_DLD

t_DDS

t_DDH

t_DDD

t_TFS

BCLK Low Pulsewidth

BCLK High Pulsewidth

BCLK Delay (to BCLKO)

LRCLK Setup

LRCLK Hold

LRCLK Delay (to LRCLKO)

SDATA Setup

10

25

0

10

0

10

SDATA Hold

SDATA Delay (to SDATAO)

TDMFS Delay (from MCLK)

TDMBC Delay (from MCLK)

TDMO Delay (from TDMBC)

CCLK Low Pulsewidth

CCLK High Pulsewidth

CLATCH Setup

25

35

5

t_TBS

t_TOS

t_CCL

t_CCH

t_CLS

12

10

0

t_CLH

t_CLD

t_CDS

t_CDH

t_COD

t_COH

t_DCD

t_DCH

CLATCH Hold

CLATCH High Pulsewidth

CDATA Setup

CDATA Hold

COUT Delay

COUT Hold

DCSOUT Delay

DCSOUT Hold

10

35

2

5

t_PDRPPD/RST Low Pulsewidth

Specifications subject to change without notice.

DIGITAL FILTER CHARACTERISTICS at 44.1 kHz

Parameter

Min

Typ

Max

Unit

Pass-Band Ripple

Stop-Band Attenuation

Pass Band

0.01

dB

kHz

70

20

0.4535 ϫ f_S

24

0.5442 ϫ f_S

24.625/f_S

Stop Band

kHz

sec

Group Delay

Specifications subject to change without notice.

–5–

REV. 0

AD1953

ABSOLUTE MAXIMUM RATINGS

*

Package Characteristics (48-Lead LQFP)

DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

ODVDD to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

Digital Inputs . . . . . . . . . . DGND – 0.3 V to DVDD + 0.3 V

Analog Inputs . . . . . . . . . . AGND – 0.3 V to AVDD + 0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Reference Voltage . . . . . . . . . . . . . . . . . . . (AVDD + 0.3)/2 V

Maximum Junction Temperature . . . . . . . . . . . . . . . . 125∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Min

Typ

Max

Unit

␪

_JA(Thermal Resistance

[Junction-to-Ambient])

_JC(Thermal Resistance

[Junction-to-Case])

76

∞C/W

17

∞C/W

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300∞C/10 sec

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model

Temperature Range Package Description

Package Option

AD1953YST

–40∞C to +105∞C

48-Lead LQFP

Evaluation Board

ST-48

ST-48 on 13" Reel

ST-48 on 7" Reel

AD1953YSTRL

AD1953YSTRL7

EVAL-AD1953EB

PIN CONFIGURATION

48-Lead LQFP

TCAP

FIL

48 47 46 45 44 43 42 41 40 39 38 37

1

2

NC

MCLK2

MCLK1

MCLK0

AUXDATA

MUTE

36

35

34

33

32

31

30

29

28

NC

PIN 1

IDENTIFIER

AGND

3

VOUTL–

VOUTL+

AVDD

4

5

AD1953

6

AGND

TOP VIEW

7

DVDD

AVDD

(Not to Scale)

8

SDATA2

BCLK2

LRCLK2

SDATA1

BCLK1

VOUTR+

VOUTR–

9

10

11

12

27 AGND

26 VOUTS+

25 VOUTS–

13 14 15 16 17 18 19 20 21 22 23 24

NC = NO CONNECT

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD1953 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

REV. 0

–6–

AD1953

PIN FUNCTION DESCRIPTIONS

Description

Input/

Output

Pin No.

Mnemonic

1

2

3

4

5

6

7

8

9

NC

No Connect

MCLK2

MCLK1

MCLK0

AUXDATA

MUTE

DVDD

SDATA2

BCLK2

IN

Master Clock Input 2 256/512 f_S

Master Clock Input 1 256/512 f_S

Master Clock Input 0 256/512 f_S

Auxiliary Serial Data Input

Mute Signal, Initiates Volume Ramp-Down

Digital Supply for DSP Core, 4.5 V to 5.5 V

Serial Data Input 2

Bit Clock 2

Left/Right Clock 2

Serial Data Input 1

Bit Clock 1

Digital Ground

Left/Right Clock 1

Serial Data Input 0

Bit Clock 0

Left/Right Clock 0

SPI Data Input

SPI Data Bit Clock

SPI Data Framing Signal

Reset Signal, Active Low

Analog 5 V Supply

Analog GND

No Connect

Negative Sub Analog DAC Output

Positive Sub Analog DAC Output

Analog GND

Negative Left Analog DAC Output

Positive Left Analog DAC Output

Analog 5 V Supply

Analog GND

Analog 5 V Supply

Positive Left Analog DAC Output

Negative Left Analog DAC Output

Analog GND

No Connect

Connection for Filtered AVDD/2

Connection for Noise Reduction Capacitor

IN

10

LRCLK2

SDATA1

BCLK1

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

DGND

LRCLK1

SDATA0

BCLK0

LRCLK0

CDATA

CCLK

CLATCH

RESETB

AVDD

IN

AGND

NC

VOUTS–

VOUTS+

AGND

VOUTR–

VOUTR+

AVDD

AGND

AVDD

VOUTL+

VOUTL–

AGND

NC

VREF

FILTCAP

ZEROFLAG

DMUXO/TDMO

BMUXO/TDMBC

OUT

IN

OUT

Zero Flag Output. High when both left and right channels are 0 for 1024 frames.

Dual-function Pin: Serial Data MUX Output/TDM Mode Output Data

Dual-function Pin: Bit Clock MUX Output/TDM Mode Bit Clock Output (256 f_S)

Dual-function Pin: Left/Right Clock MUX Output/TDM Mode Frame Sync

Clock Output

LRMUXO/TDMFS OUT

44

45

ODVDD

DCSOUT

Digital Supply Pin for Output Drivers, 2.5 V to 5.5 V

Data Capture Serial Output for Data Capture Registers. Use in conjunction

with selected LRCLK and BCLK to form a 3-wire output.

SPI Data Output, Three-Stated when Inactive

Master Clock Output 512/256 f_S(Frequency Selected by SPI Register)

Digital Ground

OUT

46

47

48

COUT

MCLKOUT

DGND

OUT

–7–

REV. 0

AD1953–Typical Performance Characteristics

PERFORMANCE PLOTS

The following plots demonstrate the performance achieved on the

actual silicon. TPC 1 shows an FFT of a full-scale 1 kHz signal

with a THD+N of –100 dB, which is dominated by a second

harmonic. TPC 2 shows an FFT of a –60 dB sine wave, demon-

strating the lack of low level artifacts. TPC 3 shows a frequency

response plot with the seven equalization biquads set to an alter-

nating pattern of 6 dB boosts and cuts. TPC 4 shows a linearity

plot, where the measurement was taken with the same equaliza-

tion curve used to make TPC 3. When the biquad filters are not

in use, the signal passes through the filters with no quantization

effects. TPC 4 therefore demonstrates that using double-precision

math in the biquad filters has virtually eliminated any quantization

artifacts. TPC 5 shows a tone-burst applied to the compressor,

with the attack and recovery characteristics plainly visible. The

rms detector was programmed for normal rms time constants;

the hold/decay feature was not used for this plot.

0

–2

–4

–6

–8

–10

–12

–14

–16

–18

–20

20

50

100

200

500

1k

5k

10k

Hz

TPC 3. Frequency Response of EQ Biquad Filters

0

–20

3.0

2.5

2.0

–40

1.5

1.0

–60

0.5

–80

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–100

–120

–140

–160

0

2

4

6

8

10

12

14

16

18

20

–120

–100

–80

–60

–40

–20

0

kHz

dBFS

TPC 1. FFT of Full-Scale Sine Wave (32k Points)

TPC 4. Linearity Plot

2.0

0

–20

1.5

1.0

–40

0.5

–60

0

–80

–0.5

–1.0

–1.5

–2.0

–100

–120

–140

–160

–120

–100

–80

–60

–20

0

2

4

6

8

10

12

14

16

18

20

ms

kHz

TPC 2. FFT of –60 dB Sine Wave (32k Points)

TPC 5. Tone-Burst Response with Compressor

Threshold Set to –20 dB

–8–

REV. 0

AD1953

PRODUCT OVERVIEW (continued from page 1)

An extensive SPI port allows click-free parameter updates, along

with readback capability from any point in the algorithm flow.

The AD1953 has a very sophisticated SPI port that supports

complete read/write capability of both the program RAM and

the parameter RAM. Two control registers are also provided to

control the chip serial modes and various other optional fea-

tures. Handshaking is included for ease of memory uploads/

downloads.

The AD1953 also includes ADI’s patented multibit Σ-∆ DAC

architecture. This architecture provides 112 dB SNR and dynamic

range and THD+N of –100 dB. These specifications allow the

AD1953 to be used in applications ranging from low end

boom-boxes to high end professional mixing/editing systems.

The AD1953 contains eight independent data-capture circuits

that can be programmed to tap the signal flow of the processor

at any point in the DSP algorithm flow. Two of these data-

capture circuits can be read back over the SPI port, and the

other six are fed to a serial output pin operating either in TDM

mode (for all six channels) or 2-channel mode for simple con-

nection to an external DAC. This allows the basic functionality

of the AD1953 to be easily extended.

The AD1953 has a digital output that allows it to be used purely

as a DSP. This digital output can also be used to drive an exter-

nal DAC to extend the number of channels beyond the three

that are provided on the chip. This chip can be used with either

its default signal processing program or with a custom user-

designed program. Graphical programming tools are available

from ADI for custom programming.

The processor core in the AD1953 has been designed from the

ground up for straightforward coding of sophisticated compres-

sion/limiting algorithms. The AD1953 contains two independent

compressor/limiters with rms based amplitude detection and

attack/hold/release controls, together with an arbitrary compres-

sion curve that is loaded by the user into a lookup table that

resides in the parameter RAM. The compressor also features

look-ahead compression, which prevents compressor overshoots.

Features

The AD1953 is comprised of a 26-bit DSP (48-bit with double-

precision) for interpolation and audio processing, three multibit

Σ-∆ modulators, and analog output drive circuitry. Other features

include an on-chip parameter RAM using a “safe-upload” feature

for transparent and simultaneous updates of filter coefficients.

Digital de-emphasis filters are also included. On-chip input

selectors allow up to three sources of serial data and master

clock to be selected. The 3-channel configuration is especially

useful for 2.1 playback systems that include two satellite speakers

and a subwoofer. The default program allows for independent

equalization and compression/limiting for the satellite and

subwoofer outputs. Figure 1 shows the block diagram of the device.

The AD1953 has a very flexible serial data input port that allows

for glueless interconnection to a variety of ADCs, DSP chips,

AES/EBU receivers, and sample rate converters. The AD1953

can be configured in left-justified, I²S, right-justified, or DSP

serial port compatible modes. It can support 16, 20, and 24 bits

in all modes. The AD1953 accepts serial audio data in MSB

first, twos complement format. The part can also be set up in a

4-channel serial input mode by simultaneously using the serial

input mux and the auxiliary serial input.

The AD1953 contains a program RAM that is booted from an

internal program ROM on power-up. Signal-processing param-

eters are stored in a 256-location parameter RAM, which is

initialized on power-up by an internal boot ROM. New values

are written to the parameter RAM using the SPI port. The

values stored in the parameter RAM control the IIR equalization

filters, the dual-band compressor/limiter, the delay values, and

the settings of the stereo spreading algorithm.

The AD1953 operates from a single 5 V power supply. It is

fabricated on a single monolithic integrated circuit and is housed

in a 48-lead LQFP package for operation over the temperature

range –40°C to +105°C.

VREF

ZEROFLAG

RESETB MUTE

DE-EMPHASIS

DVDD AVDD ODVDD

3

VOLTAGE

3

REFERENCE

DATA MEMORY, 512 ꢀ 26

DAC – L

3:1

AUDIO

DATA

SERIAL DATA I/O

GROUP

3

SERIAL

IN

ANALOG

OUTPUTS

DAC – R

26 ꢀ 22

DSP CORE

1

(2-CHANNEL

AND TDM)

1

MUX

2

DAC –SW

AUX SERIAL

DATA INPUT

DATA FORMAT:

3.23 (SINGLE PRECISION)

3.45 (DOUBLE PRECISION)

ANALOG

BIAS

MCLK

MASTER

CLOCK I/O

GROUP

3:1

1

GENERATOR

MCLK

(256/512 f IN)

S

1

MUX

256/512 f OUT

S

CONTROL

COEFFICIENT

ROM

64 ꢀ 22

PROGRAM

RAM

512 ꢀ 35

PARAMETER

RAM

256 ꢀ 22

REGISTERS

SPI I/O

GROUP

TRAP REG.

SPI PORT

3

2

(I S, SPI)

SAFELOAD

REGISTERS

DCSOUT

MEMORY CONTROLLERS

DCSOUTTRAP

FILTCAP

AGND

3

DGND

2

NOTES

1

CONTROLLEDTHROUGH SPI CONTROL REGISTERS

2

DAC DOES NOT USE DIGITAL INTERPOLATION

Figure 1. Block Diagram

–9–

REV. 0

AD1953

Pin Functions

MCLKO—Master Clock Output.

All input pins have a logic threshold compatible with TTL input

levels, and may therefore be used in systems with 3.3 V logic.

All digital output levels are controlled by the ODVDD pin,

which may range from 2.7 V to 5.5 V, for compatibility with a

wide range of external devices. (See Pin Function Descriptions.)

The master clock output pin may be programmed to produce

either 256 × f_S, 512 × f_S, or a copy of the selected MCLK input

pin. This pin is programmed by writing to Bits <1:0> of Control

Register 2. The default is 00, which disables the MCLKO pin.

CDATA—Serial Data In for the SPI Control Port.

SDATA0, 1, 2—Serial Data Inputs.

See SPI Port section for more information on SPI port timing.

One of these three inputs is selected by an internal MUX, set by

writing to Bits <7:6> in Control Register 2. Default is 00, which

selects SDATA0. The serial format is selected by writing to Bits

<3:0> of Control Register 0. See SPI Read/Write Data Formats

section for recommendations on how to change input sources

without causing a click or pop noise.

COUT—Serial Data Output.

This is used for reading back registers and memory locations. It

is three-stated when an SPI read is not active. See SPI Port

section for more information on SPI port timing.

CCLK—SPI Bit Rate Clock.

This pin either may run continuously or be gated off between

SPI transactions. See SPI Port section for more information on

SPI port timing.

LRCLK0, 1, 2—Left/Right Clocks for Framing the Input Data.

The active LRCLK input is selected by writing to Bits <7:6>

in Control Register 2. Default is 00, which selects LRCLK0.

The interpretation of the LRCLK changes according to the serial

mode, set by writing to Control Register 0.

CLATCH—SPI Latch Signal.

This pin must go LOW at the beginning of an SPI transaction,

and HIGH at the end of a transaction. Each SPI transaction

may take a different number of CCLKs to complete, depending

on the address and read/write bit that are sent at the beginning

of the SPI transaction. Detailed SPI timing information is given

in the SPI Port section.

BCLK0, 1, 2—Serial Bit Clocks for Clocking in the Serial Data.

The active BCLK input is selected by writing to Bits <7:6> in

Control Register 2. Default is 00, which selects BCLK0. The

interpretation of BCLK changes according to the serial mode,

which is set by writing to Control Register 0.

RESETB—Active-Low Reset Signal.

After RESETB goes HIGH, the AD1953 goes through an ini-

tialization sequence where the program and parameter RAMs

are initialized with the contents of the on-board boot ROMs. All

SPI registers are set to 0, and the data RAMs are also zeroed.

The initialization is complete after 1024 MCLK cycles. Since

the MCLK IN FREQ SELECT (Bit <2> in Control Register 2)

defaults to 512 × f_Sat power-up, this initialization will proceed

at the external MCLK rate and will take 1024 MCLK cycles to

complete, regardless of the absolute frequency of the external

MCLK. New values should not be written to the SPI port until

the initialization is complete.

DMUXO/TDMO, LRMUXO/TDMFS, BMUXO/TDMBC

Dual-function pins:

•

Function 1: Outputs of 3:1 MUX that selects one of the

three serial input groups.

•

Function 2: Used for 6-channel data capture outputs in

TDM Data Capture Mode.

These three pins operate as MUX outputs when Bit <8> of

Control Register 2 is a 1 and Bits <13:12> of Control Register 1

are 00. These pins may be used to send the selected serial input

signals to other external devices. The default is OFF.

In TDM mode, TDMBC provides a 256

× f_Sclock signal,

ZEROFLAG—Zero-Input Indicator.

TDMFS provides a frame sync signal, and TDMO provides the

TDM data for an external multichannel DAC or CODEC, such

as the AD1833 or AD1836 respectively. These output pins are

enabled by writing a 01 to Bits <13:12> of Control Register 1.

The default mode is 00, or OFF.

This pin will go HIGH if both serial inputs have been inactive

(zero data) for 1024 LRCLK cycles. This pin may be used to

drive an external mute FET for reduced noise during digital

silence. This pin also functions as a test out pin, controlled by

the test register at SPI address 511. While most test modes are

not useful to the end user, one may be of some use. If the test

register is programmed with the number 7 (decimal), the

ZEROFLAG output will be switched to the output of the inter-

nal pseudo-random noise generator. This noise generator

operates at a bit rate of 128 × f_S, and has a repeat time of once

per 2²⁴cycles. This mode may be used to generate white noise

(or, with appropriate filtering, pink noise) to be used as a test

signal for measuring speakers or room acoustics.

In TDM mode, the internal signals that are captured are con-

trolled by writing Program Counter Trap numbers to SPI

addresses 268 to 273. When the internal Program Counter

contents are equal to the Trap values written to the SPI port, the

selected DSP register is transferred to parallel-to-serial registers

and shifted out of the TDMO pin.

MCLK0, 1, 2—Master Clock Inputs.

Active input selected by writing to Bits <5:4> of Control Regis-

ter 2. The default is 00, which selects MCLK0. The master clock

frequency must be either 256 × f_Sor 512 × f_S, where f_Sis the input

sampling rate. The master clock frequency is programmed by

writing to Bit <2> of Control Register 2. The default is 0, (512

× f_S). See Initialization section for recommendations concerning

how to change clock sources without causing an audio click or

pop. Note that since the default MCLK source pin is MCLK0,

there must be a clock signal present on this pin on power-up so

that the AD1953 can complete its initialization routine.

DCSOUT—Data Capture Serial Out.

This pin will output the DSP’s internal signals, which can be

used by external DACs or other signal-processing devices. The

signals that are captured and output on the DCSOUT pin are

controlled by writing Program Counter Trap numbers to SPI

addresses 263 (for the left output) and 264 (for the right output).

When the internal Program Counter contents are equal to the

Trap values written to the SPI port, the selected DSP register is

transferred to the DCSOUT parallel-to-serial registers and

REV. 0

–10–

AD1953

shifted out on the DCSOUT pin. Table XXI shows the Pro-

gram Counter Trap values and register-select values that should

be used to tap various internal points of the algorithm flow.

VOUTS+, VOUTS– —Sub Channel Differential Outputs.

These outputs are designed to drive loads of 10 kΩ or greater,

with a peak current capability of 250 µA. This output does not

use digital interpolation, as it is intended for low frequency

application. An external third-order filter with a cutoff frequency

< 2 kHz is recommended.

The DCSOUT pin is meant to be used in conjunction with the

LRCLK and BCLK signals that are provided to the serial input

port. The format of DCSOUT is the same as the format used

for the serial port. In other words, if the serial port is running in

I²S mode, then the DCSOUT pin, together with the LRCLK0

and BCLK0 pins (assuming input 0 is selected), will form a

valid 3-wire I²S output.

VREF—Analog Reference Voltage Input.

The nominal VREF input voltage is 2.5 V; the analog gain

scales directly with the voltage on this pin. When using the

AD1953 to drive a power amplifier, it is recommended that the

VREF voltage be derived by dividing down and heavily filtering

the supply to the power amplifier. This provides a benefit if the

compressor/limiter in the AD1953 is used to prevent amplifier

clipping. In this case, if the DAC output voltage is scaled to the

amplifier power supply, a fixed compressor threshold can be

used to protect an amplifier whose supply may vary over a wide

range. Any ac signal on this pin will cause distortion, and a large

decoupling capacitor may therefore be necessary to ensure that

the voltage on VREF is clean. The input impedance of VREF is

greater than 1 MΩ.

The DCSOUT pin can be used for a variety of purposes. If the

DCSOUT pin is used to drive another external DAC, then a 4.1

system is possible using a new program downloaded into the

program RAM.

AUXDATA—Auxiliary Serial Data Input.

The AUXDATA pin may be used in conjunction with a custom

program to access two extra channels of serial input data, allow-

ing for a total of four input channels. The serial format is identical

to the selected format of SDATA0, 1, 2. The AUXDATA pin is

synchronous to the selected LRCLK and BCLK signal, and there-

fore should have the same timing as the main serial input signal.

FILTCAP—Filter Capacitor Point.

This pin is used to reduce the noise on an internal biasing point

in order to provide the highest performance. It may not be nec-

essary to connect this pin, depending on the quality of the layout

and grounding used in the application circuit.

MUTE—Mute Output Signal.

When this pin is asserted HIGH, a ramp sequence is started that

gradually reduces the volume to zero. When deasserted, the

volume ramps from zero back to the original volume setting.

The ramp speed is timed so that it takes 10 ms to reach zero

volume when starting from the default 0 dB volume setting.

DVDD—Digital VDD for Core.

5 V nominal.

ODVDD—Digital VDD for All Digital Outputs.

Variable from 2.7 V to 5.5 V.

VOUTL+, VOUTL– —Left-Channel Differential Analog Out-

puts. Full-scale outputs correspond to 1 V rms on each output pin,

or 2 V rms differential, assuming a VREF input voltage of 2.5 V. The

full-scale swing scales directly with VREF. These outputs are

capable of driving a load of > 5 kΩ, with a maximum peak current

of 1 mA from each pin. An external third-order filter is recom-

mended for filtering out-of-band noise.

DGND (2)—Digital Ground.

AVDD (3)—Analog VDD.

5 V nominal. For best results, use a separate regulator for AVDD.

Bypass capacitors should be placed close to the pins and con-

nected directly to the analog ground plane.

VOUTR+, VOUTR– —Right Channel Differential Outputs.

Output characteristics are the same as for VOUTL+ and VOUTL–.

AGND (3)—Analog Ground.

For best performance, separate nonoverlapping analog and

digital ground planes should be used.

–11–

REV. 0

AD1953

L/R DYNAMICS PROCESSOR

EQ AND CROSSOVER FILTERS

8ꢀ

OUT

DELAY

DAC

INTERPOLATION

LEFT

(0ms–2.3ms)

IN

LEFT

7 BIQUAD

FILTERS

CROSSOVER

(2 FILTERS)

DELAY

(0ms–3.7ms)

HPF/

DE-EMPHASIS

LEVEL DETECT,

LOOK-UP TABLE

HPF/

DE-EMPHASIS

IN

RIGHT

7 BIQUAD

FILTERS

CROSSOVER

(2 FILTERS)

DELAY

(0ms–3.7ms)

DELAY

(0ms–2.3ms)

8ꢀ

OUT

RIGHT

INTERPOLATION

L/R REINJECTION

LEVEL

1 BIQUAD

FILTER

LEVEL DETECT,

LOOK-UP TABLE

SUB CHANNEL

L/R MIX

SUBWOOFER

OUTPUT

DELAY

(0ms–3.7ms)

CROSSOVER

(3 FILTERS)

MONO DAC

SUB DYNAMICS PROCESSOR

Figure 2. Signal Processing Flow

Figure 3. Graphical User Interface

quality of compressed audio. In addition, the main channels

have a stereo widening algorithm that increases the perceived

spread of the stereo image.

SIGNAL PROCESSING

Signal Processing Overview

Figure 2 shows the signal processing flow diagram of the AD1953.

The AD1953 is designed to provide all common signal-processing

functions commonly used in 2.0 or 2.1 playback systems. A

7-biquad equalizer operates on the stereo input signal. The

output of this equalizer is fed to a 2-biquad crossover filter for

the main channels, and the mono sum of the left and right equalizer

outputs is fed to a 3-biquad crossover filter for the Sub channel.

Each of the three channels has independent delay compensa-

tion. There are two high quality compressor/limiters available:

one operating on the left/right outputs and one operating on the

subwoofer channel. The subwoofer output may be blended back

into the left/right outputs for 2.0 playback systems. In this

configuration, the two independent compressor/limiters provide

2-band compression, which significantly improves the sound

Most of the signal processing functions are coded using full 48-bit

double-precision arithmetic. The input word length is 24 bits,

with two extra headroom bits added in the processor to allow

internal gains up to 12 dB without clipping (additional gains can

be accommodated by scaling down the input signal in the first

biquad filter section).

A graphical user interface (GUI) is available for evaluation of

the AD1953 (Figure 3). This GUI controls all of the functions

of the chip in a very straightforward and user-friendly interface.

No code needs to be written to use the GUI to control the chip.

For more information on AD1953 software tools, send an email to

SigmaDSP@analog.com.

REV. 0

–12–

AD1953

0.75

2-BIT SIGN EXTENTION

DIGITAL ꢂ-ꢃ

MODULATORS

(1.23 FORMAT)

DIGITAL

CLIPPER

SIGNAL PROCESSING

(3.23 FORMAT)

DAC INTERPOLATION

FILTERS (3.23 FORMAT)

DATA IN

SERIAL PORT

1.23

3.23

Figure 4. Numeric Precision and Clipping Structure

Each section of this flow diagram will be explained in detail on

the following pages.

A digital clipper circuit is used between the output of the DSP

core and the input to the DAC Σ-∆ modulators to prevent over-

loading the DAC circuitry (see Figure 4). Note that there is a

gain factor of 0.75 used in the DAC interpolation filters, and

therefore signal values of up to 1/0.75 will pass through the DSP

without clipping. Since the DAC is designed to produce an

analog output of 2 V rms (differential) with a 0 dB digital input,

signals between 0 dB and 1/0.75 (approximately 3 dB) will produce

larger analog outputs and result in slightly degraded analog per-

formance. This extra analog range is necessary in order to pass 0

dBFS square waves through the system, as these square waves

cause overshoots in the interpolation filters that would otherwise

briefly clip the digital DAC circuitry.

Numeric Formats

It is common in DSP systems to use a standardized method of

specifying numeric formats. To better comprehend issues relat-

ing to precision and overflow, it is helpful to think in terms of

fractional twos complement number systems. Fractional

number systems are specified by an A.B format, where A is the

number of bits to the left of the decimal point and B is the

number of bits to the right of the decimal point. In a twos

complement system, there is also an implied offset of one-half of

the binary range; for example, in a twos complement 1.23 sys-

tem, the legal signal range is –1.0 to (+1.0 – 1 LSB).

A separate digital clipper circuit is used in the DSP core to

ensure that any accumulator values that exceed the numeric

3.23 format range are clipped when taken from the accumulator.

The AD1953 uses two different numeric formats; one for the

coefficient values (stored in the parameter RAM) and one for

the signal data values. The coefficient format is as follows:

High-Pass Filter

Coefficient Format

The high-pass filter is a first-order double-precision design. The

purpose of the high-pass filter is to remove digital dc from the

input. If this dc were allowed to pass, the detectors used in the

compressor/limiter would give an incorrect reading for low

signal levels.

Coefficient format: 2.20

Range: –2.0 to (+2.0 – 1 LSB)

Examples:

1000000000000000000000 = –2.0

1100000000000000000000 = –1.0

1111111111111111111111 = (1 LSB below 0.0)

0000000000000000000000 = 0.0

0100000000000000000000 = 1.0

0111111111111111111111 = (2.0 – 1 LSB)

The high-pass filter is controlled by a single parameter

(alpha_HPF), which is programmed by writing to SPI location

180 in 2.20 twos complement format. The following equation

can be used to calculate the parameter Alpha_HPF from the –3 dB

point of the filter:

This format is used because standard biquad filters require

coefficients that range between +2.0 and –2.0. It also allows

gain to be inserted at various places in the signal path.





–2.0 × π × HPF _CUTOFF

Alpha_ HPF = 1.0 – EXP









f_S

Internal DSP Signal Data Format

Input data format: 1.23

This is sign-extended when written to the data memory of the

AD1953.

where EXP is the exponential operator, HPF_CUTOFF is the

high-pass cutoff in Hz, and f_Sis the audio sampling rate.

The default value for the –3 dB cutoff of the high-pass filter is

2.75 Hz at a sampling rate of 44.1 kHz.

Internal DSP signal data format: 3.23

Range: –4.0 to (+4.0 – 1 LSB)

Examples:

b0

OUT

IN

10000000000000000000000000 = –4.0

11000000000000000000000000 = –2.0

11100000000000000000000000 = –1.0

11111111111111111111111111 = (1 LSB below 0.0)

00000000000000000000000000 = 0.0

00100000000000000000000000 = 1.0

01000000000000000000000000 = 2.0

01111111111111111111111111 = (4.0 – 1 LSB).

b1

b2

a1

a2

–1

Z

–1

Z

Figure 5. Biquad Filter

The sign-extension between the serial port and the DSP core

allows for up to 12 dB of gain in the signal path without internal

clipping. Gains greater than 12 dB can be accommodated by

scaling the input down in the first biquad filter, and scaling the

signal back up at the end of the biquad filter section.

Biquad Filters

Each of the two input channels has seven second-order biquad

sections in the signal path. In addition, the left and right chan-

nels have two additional biquad filters that may be used either

as crossover filters or as additional equalization filters. The sub

channel has three additional biquad filters, also to be used as

equalization and/or crossover filters. In a typical scenario, the

–13–

REV. 0

AD1953

first seven biquads would be used for speaker equalization and/

or tone controls, and the remaining filters would be programmed

to function as crossover filters. Note that there is a common

equalization section used for both the main and sub channels,

followed by crossover filters. This arrangement prevents any

interaction from occurring between the crossover filters and the

equalization filters. One section of the biquad IIR filter is shown

in Figure 5.

If gains larger than 12 dB cannot be avoided, then the coeffi-

cients b0 through b2 of the first biquad section may be scaled

down to fit the signal into the 12 dB maximum signal range, and

then scaled back up at the end of the filter chain.

Volume

Eight separate SPI registers are available to control the volume.

Three registers are used by the on-board program—one each for

the Left, Right, and Sub channels. These registers are special in

that they include automatic digital ramp circuitry for clickless

volume adjustment. The volume control word is in 2.20 format,

and gains from +2.0 to –2.0 are possible. The default value is

1.0. It takes 1024 audio frames to adjust the volume from 2.0

down to 0; in the normal case where the max volume is set to

1.0, it will take 512 audio frames for this ramp to reach zero.

Note that a Mute command is the same as setting the volume to

zero, except that when the part is unmuted, the volume returns to

its original value. These volume ramp times assume that the

AD1953 is set for the fast volume ramp speed. If the slow

setting is selected, it will take 8192 audio frames to reach zero

from a setting of 2.0. Correspondingly, it will take 4096 frames

to reach 0 volume from the normal setting of 1.0.

This section implements the transfer function:

b0 + b1× Z^–1+ b2 × Z^–2

(

)

H Z =

( )

1− a1× Z^–1– a2 × Z^–2

(

)

The coefficients a1, a2, b0, b1, and b2 are all in twos comple-

ment 2.20 format with a range from –2 to (+2 – 1 LSB). The

negative sign on the a1 and a2 coefficients is the result of adding

both the feed-forward “b” terms as well as the feedback “a” terms.

Some digital filter packages automatically produce the correct

a1 and a2 coefficients for the topology of Figure 5, while others

assume a denominator of the form 1 + a1 × Z^–1+ a2 × Z^–1. In this

case, it may be necessary to invert the a1 and a2 terms for

proper operation.

The volume blocks are placed after the biquad filter sections to

maximize the level of the signal that is passed through the filter

sections. In a typical situation, the nominal volume setting might be

–15 dB, allowing a substantial increase in volume when the user

increases the volume. The AD1953 was designed with an analog

dynamic range of > 112 dB, so that in the typical situation with

the volume set to –15 dB, the signal-to-noise ratio at the output

will still exceed 97 dB. Greater output dynamic ranges are possible

if the compressor/limiter is used, as the post-compression gain

parameter can boost the signal back up to a higher level. In this

case, the compressor will prevent the output from clipping when

the volume is turned up and the input signal is large.

The biquad structure shown in Figure 5 is coded using double-

precision math to avoid limit cycles from occurring when low

frequency filters are used. The coefficients are programmed by

writing to the appropriate location in the parameter RAM through

the SPI port (see Table VI). There are two possible scenarios

for controlling the biquad filters:

1. Dynamic Adjustment (for example, Bass/Treble control or Para-

metric Equalizer)

When using dynamic filter adjustment, it is highly recommended

that the user employ the safeload mechanism to avoid temporary

instability when the filters are dynamically updated. This can

occur if some, but not all, of the coefficients are updated to new

values when the DSP calculates the filter output. The operation

of the Safeload registers is detailed in the Options for Parameter

Updates section.

Stereo Image Expander

The image-enhancement processing is based on ADI’s patented

Phat Stereo algorithm. The block diagram is shown in Figure 6.

LEFT OUT

LEFT IN

+

–

2. Setting Static EQ Curve after Power-Up

–

If many of the biquad filters need to be initialized after power-

up (for example, to implement a static speaker-correction

curve), the recommended procedure is to set the processor

shutdown bit, wait for the volume to ramp down (about 20 ms),

and then write directly to the parameter RAM in Burst

Mode. After the RAM is loaded, the shutdown bit can be

deasserted, causing the volume to ramp back up to the initial

value. This entire procedure is click-free and faster than using

the Safeload mechanism.

+

–

1kHz

FIRST-ORDER LPF

LEVEL

RIGHT OUT

RIGHT IN

Figure 6. Stereo Image Expander

The algorithm works by increasing the phase shift for low

frequency signals that are panned left or right in the stereo mix.

Since the ear is responsive to interaural phase shifts below 1 kHz,

this increase in phase shifts results in a widening of the stereo

image. Note that signals panned to the center are not processed,

resulting in a more natural sound. There are two parameters

that control the Phat Stereo algorithm: the Level variable,

which controls how much out-of-phase information is added to

the left and right channels, and the cutoff frequency of the

first-order low-pass filter, which determines the frequency range

of the added out-of-phase signals. For best results, the cutoff

frequency should be in the range of 500 Hz to 2 kHz. These

parameters are controlled by altering the parameter RAM locations

that store the parameters spread_level and alpha_spread.

The datapaths of the AD1953 contain an extra two bits on top

of the 24 bits that are input to the serial port. This allows up to

12 dB of boost without clipping. However, it is important to

remember that it is possible to design a filter that has less than

12 dB of gain at the final filter output, but more than 12 dB of

gain at the output of one or more intermediate biquad filter

sections. For this reason, it is important to cascade the filter

sections in the correct order, putting the sections with the

largest peak gains at the end of the chain rather than at the

beginning. This is standard practice when coding IIR filters and

is covered in basic books on DSP coding.

REV. 0

–14–

AD1953

The spread_level is a linear number in 2.20 format that multiplies

the processed left-right signal before it is added to or subtracted

from the main channels. The parameter alpha_spread is related to

the cutoff frequency of the first-order low-pass filter by the equation

For example, if the input to a 2:1 compressor is increased by

2 dB, the output will rise by 1 dB for signals above the threshold.

A single “hard” threshold results in more audible behavior than

a so-called “soft-knee” compressor, where the compression is

introduced more gradually. In an analog compressor, the soft-knee

characteristic is usually made by using diodes in their exponential

turn-on region.

 –2.0 × π × spread _ freq 

Alpha _spread = 1.0 – EXP





f_S





where EXP is the exponential operator, spread_freq is the low-pass

cutoff in Hz, and f_Sis the audio sampling rate.

OUT

VCA WITH EXP

CONTROL

THRESHOLD

SLOPE

Note that the stereo spreading algorithm assumes that frequencies

below 1 kHz are present in the main satellite speakers. In some

systems, the crossover frequency between the satellite and

subwoofer speakers is quite high (> 500 Hz). In this case, the

stereo spreading algorithm will not be effective, as the frequencies

that contribute to the spreading effect will be coming mostly from

the subwoofer, which is a mono source.

COMPRESSION

CURVE NON-

RMS DETECTOR

WITH dB OUT

FILTER

LINEAR CIRCUITS

Figure 7. Analog Compressor

The best analog compressors use rms detection as the signal

amplitude detector. RMS detectors are the only class of detec-

tors that are not sensitive to the phase of the harmonics in a

complex signal. The ear also bases its loudness judgment on the

overall signal power. Using an rms detector therefore results in

the best audible performance. Compressors that are based on

peak detection, while good for preventing clipping, are generally

quite poor when it comes to audible performance.

Delay

Each of the three DAC channels has a delay block that allows

the user to introduce a delay of up to 165 audio samples. The

delay values are programmed by entering the delay (in samples)

into the appropriate location of the parameter RAM. With a

44.1 kHz sample rate, a delay of 165 samples corresponds to a

time delay of 3.74 ms. Since sound travels at approximately

1 foot/ms, this can be used to compensate for speaker place-

ments that are off by as much as 3.74 feet.

RMS detectors have a certain time constant that determines

how rapidly they can respond to transient signals. There is always

a trade-off between speed of response and distortion. Figure 8

shows this trade-off.

An additional 100 samples of delay are used in the look-ahead

portion of the compressor/limiter, but only for the main two

channels. This can be used to increase the total delay for the left

and right channels to 265 samples, or 6 ms at 44.1 kHz.

INPUTWAVEFORM

Main Compressor/Limiter

The compressor used in the AD1953 is quite sophisticated and

is comparable in many ways to professional compressor/limiters

used in the professional audio and broadcast fields. It uses rms/

peak detection with adjustable attack/hold/release, look-ahead

compression, and table-based entry of the input/output curve for

complete flexibility.

The AD1953 uses two compressor/limiters, one in the subwoofer

DAC and one in the main left/right DAC. It is well known that

having independent compressors operating over different frequency

ranges results in a superior perceived sound. With a single-band

compressor, loud bass information will modulate the gain of the

entire audio signal, resulting in suboptimal maximum perceived

loudness as well as gain pumping or modulation effects. With

independent compressors operating separately on the low and

high frequencies, this problem is dramatically reduced. If the

AD1953 is being operated in 2-channel mode, an extra path is

added so that the subwoofer channel can be added back into the

main channel. This maintains the advantage of using a 2-band

compressor, even in a 2.0 system configuration.

COMPRESSOR ENVELOPE –

FASTTIME CONSTANT

COMPRESSOR ENVELOPE –

SLOWTIME CONSTANT

Figure 8. Effect of RMS Time Constant on Distortion

In the case of a fast-responding rms detector, the detector enve-

lope will have a signal component in addition to the desired dc

component. This signal component (which, for an rms detector,

is at twice the input frequency) will result in harmonic distortion

when multiplied by this detector signal.

Figure 7 shows the traditional basic analog compressor/limiter.

It uses a voltage controlled amplifier to adjust gain and a feed-

forward detector path using an rms detector with adjustable

time constants, followed by a nonlinear circuit to implement the

desired input/output relationship. A simple compressor will have

a single threshold above which the gain is reduced. The amount

of compression above the threshold is called the compression

ratio and is defined as dB change in input/dB change in output.

The AD1953 uses a modified rms algorithm to improve the

relationship between acquisition time and distortion. It uses a

peak-riding circuit together with a hold circuit to modify the rms

signal, as shown in Figure 9. Figure 8 shows two envelopes—one

with the harmonic distortion and another, flatter envelope,

which is produced by the AD1953.

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AD1953

INPUTWAVEFORM

DESIRED

COMPRESSION

CURVE

RELEASETIME, SPI-

PROGRAMMABLE

HOLDTIME, SPI-

PROGRAMMABLE

INPUT LEVEL – 3dB/TABLE ENTRY

1.0

Figure 9. Using the Hold and Release Time Feature

Using this idea of a modified rms algorithm, the true rms value

is still obtained for all but the lowest frequency signals, while the

distortion due to rms ripple is reduced. It also allows the user to

set the hold and release times of the compressor independently.

The detector path of the AD1953 is shown in Figure 10. The rms

detector is controlled by three parameters stored in parameter

RAM: the rms time constant, the hold time, and the release rate.

The log output of the rms detector is applied to a look-up table

with interpolation. The higher bits of the rms output form an

offset into this table, and the lower bits are used to interpolate

between the table entries to form a high precision gain word.

The look-up table resides in the parameter RAM and is loaded

by the user to give the desired curve. The look-up table contains

33 data locations, and the LSB of the address into the look-up

table corresponds to a 3 dB change in the amplitude of the detec-

tor signal. This gives the user the ability to program an input/

output curve over a 99 dB range. For the main compressor, the

table resides in locations 110 to 142 in the SPI parameter RAM.

INPUT LEVEL – 3dB/TABLE ENTRY

Figure 11. Example of Table Entry for a Given

Compression Curve

Note that the maximum gain that can be entered in the table is 2.0

(minus 1 LSB). If more gain is required, the entire compression

curve may be shifted upward by using the post-compression gain

block following the compressor/limiter.

The AD1953 compressor/limiter also includes a look-ahead

compression feature. The idea behind look-ahead compression

is to prevent compressor overshoots by applying some digital

delay to the signal before the gain-control multiplier, but not to

the detector path. In this way, the detector can acquire the new

amplitude of the input signal before the signal actually reaches

the multiplier. A comparison of a tone burst fed to a conventional

compressor versus a look-ahead compressor is shown in Figure 12.

HIGH BITS (1LSB = 3dB)

MODIFIED RMS

DETECTOR WITH

LOG OUTPUT

OUTPUT TO

GAIN STAGE

LOOK-UP TABLE

LOW BITS

LINEAR

INTERPOLATION

RELEASE

HOLD

TIME

CONSTANT

CONVENTIONAL COMPRESSOR GAIN

Figure 10. Gain Derived from Interpolated Look-Up Table

One subtlety of the table look-up involves the difference between

the rms value of a sine wave and that of a square wave. If a

full-scale square wave is applied to the AD1953, the rms value of

this signal will be 3 dB higher than the rms value of a 0 dBFS sine

wave. Therefore, the table will range from +9 dB (location 142)

to –87 dB (location 110).

The entries in the table are linear gain words in 2.20 format.

Figure 11 shows an example of the table entries for a simple

above-threshold compressor.

LOOK-AHEAD COMPRESSOR GAIN

HOLDTIME

Figure 12. Conventional Compression vs. Look-Ahead

Compression

REV. 0

–16–

AD1953

In the look-ahead compressor, the gain has already been reduced

by the time the tone-burst signal arrives at the multiplier input.

Note that when using a look-ahead compressor, it is impor-

tant to set the detector hold time to a value that is at least the

same as the look-ahead delay time, or else the compressor

release will start too soon, resulting in an expanded “tail” of a

tone burst signal. The complete flow of the left/right dynamics

processor is shown in Figure 13.

f_S= audio sample rate

Hold_time = absolute time to wait before starting the release

ramp-down of the detector output

int() = integer part of expression

RMS Release Rate

rms_ decay _ parameter = int rms_ decay /1.096

(

)

Where rms_decay_parameter = decimal integer number to enter

into the SPI RAM

DELAY

POST-COMPRESSION

SPI-PROGRAMMABLE

GAIN, SPI-

LOOK-AHEAD DELAY

rms_decay = decay rate in dB/sec

int() = integer part of expression

Look-Ahead Delay

PROGRAMMABLE

UP TO 30dB

DELAY

(L+R)

2

Lookahead _delay _ parameter = Lookahead _delay × f_S

HIGH BITS (1LSB = 3dB)

Where Lookahead_delay = predictive compressor delay in abso-

lute time

MODIFIED RMS

DETECTOR WITH

LOG OUTPUT

LOOK-UP

TABLE

LINEAR

INTERPOLATION

LOW BITS

f_S= audio sample rate

RELEASE

HOLD

TIME

CONSTANT

The maximum Lookahead_delay_parameter value is 100.

Post-Compression Gain

Figure 13. Complete Dynamics Flow, Main Channels

Post _ compression_ gain _ parameter =

Post _ compression_ gain _ linear^∧1 5

The detector path works from a sum of left and right channels

((L+R)/2). This is the normal way that compressors are built,

and it counts on the fact that the main instruments in any stereo

mix are seldom recorded deliberately out of phase, especially in

the lower frequencies, which tend to dominate the energy spectrum

of real music.

(

)

Where Post_compression gain_linear is the linear post-compression

gain

^ = raise to the power

The compressor is followed by a block known as post-compression

gain. Most compressors are used to reduce the dynamic range of

music by lowering the gain during loud signal passages. This

results in an overall loss of volume. This loss can be made up by

introducing gain after the compressor. In the AD1953, the

coefficient format used is 2.20, which has a maximum floating-

point representation of slightly less than 2.0. This means the

maximum gain that can be achieved in a single instruction is 6 dB.

To get more gain, the program in the AD1953 uses a cascade

of five multipliers to achieve up to 30 dB of post-compression gain.

Subwoofer Compressor/Limiter

The subwoofer compressor/limiter differs from the left/right

compressor in the following ways:

1. The subwoofer compressor operates on a weighted sum of left

and right inputs (aa × Left + bb × Right), where aa and bb are

both programmable.

2. The detector input has a biquad filter in series with the input

in order to implement frequency-dependent compression

thresholds.

3. There is no predictive compression, as presumably the input

signals are filtered to pass only low frequencies, and therefore

transient overshoots are not a problem.

To program the compressor/limiter, the following formulas may

be used to determine the 22-bit numbers (in 2.20 format) to be

entered into the parameter RAM.

The subwoofer compressor signal flow is shown in Figure 14.

RMS Time Constant

V

_SUB = K1 ꢀ LEFT_IN + K2 ꢀ RIGHT_IN

IN

This can be best expressed by entering the time constant in

terms of dB/sec “raw” release rate (without the peak-riding circuit).

The attack rate is a rather complicated formula that depends on

the change in amplitude of the input sine wave.

POST-COMPRESSION

GAIN, SPI-

PROGRAMMABLE

UP TO 30dB

HIGH BITS (1LSB = 3dB)

 release rate 

MODIFIED RMS

DETECTOR WITH

LOG OUTPUT





BIQUAD

FILTER

10.0 × f _S



rms _tconst _ parameter = 1.0 –10^

LOOK-UP

TABLE

LINEAR

INTERPOLATION

LOW BITS

where

RELEASE

HOLD

TIME

CONSTANT

rms_tconst_parameter = fractional number to enter into the

SPI RAM (after converting to 22-bit 2.20 format)

Figure 14. Signal Flow for Subwoofer Compressor

release_rate = release rate of the raw rms detector in dB/sec. This

must be negative. f_S= audio sampling rate.

The biquad filter before the detector can be used to implement

a frequency-dependent compression threshold. For example,

assume that the overload point of the woofer is strongly fre-

quency-dependent. In this case, one would have to set the

compressor threshold to a value that corresponded to the most

sensitive overload frequency of the woofer. If the input signal

happened to be mostly in a frequency range where the woofer

RMS Hold Time

rms_holdtime_ parameter = int f × hold _time

(

)

S

where

rms_holdtime_parameter = integer number to enter into the SPI RAM

–17–

REV. 0

AD1953

was not so sensitive to overload, then the compressor would be

too pessimistic and the volume of the woofer would be reduced.

If, on the other hand, the biquad filter were designed to follow

the woofer excursion curve of the speaker, then the volume of

the woofer could be maximized under all conditions. This is

illustrated in Figure 15.

the sum is done in voltage mode. The user must take care to

design an appropriate set of crossover filters.

Interpolation Filters

The left and right channels have a 128:1 interpolation filter

with 70 dB stop-band attenuation that precedes the digital Σ-∆

modulator. This filter has a group delay of approximately 24.185/f_S,

where f_Sis the sampling rate. The sub channel does not use an

interpolation filter. The reason for this (besides saving valuable

MIPS) is that it is expected that the bandwidth of the sub output

will be limited to less than 1 kHz. With no interpolation filter, the

first “image” will therefore be at 43.1 kHz (which is f_S– 1 kHz,

for CD audio). The standard external filter used for both the

main and sub channels is a third-order, single op amp filter. If

the cutoff frequency of the external subwoofer filter is 2 kHz,

then there are more than four octaves between 2 kHz and the

first image at 43.1 kHz. A third-order filter will roll off by

approximately 18 dB/oct × 4 octaves = 72 dB attenuation. This is

approximately the same as the digital attenuation used in the main

channel filters, so no internal interpolation filter is required to remove

the out-of-band images.

20Hz

200Hz

20Hz

200Hz

FREQ

Figure 15. Optimizing Woofer Loudness Using the

Subwoofer RMS Biquad Filter

When using a filter in front of the detector, a confusing side-

effect occurs. If one measures the frequency response by using a

swept sine wave with an amplitude large enough to be above the

compressor threshold, the resulting frequency response will not

look flat. However, this is not real in the sense that, as the sine

wave is swept through the system, the gain is being slowly

modulated up and down according to the response of the biquad

filter in front of the detector. If one measures the response using a

pink-noise generator, the result will look much better, as the

detector will settle on only one gain value. The perceptual effect

of the swept-sine-wave test is not at all what would be pre-

dicted by simply looking at the frequency response curve; it is

only the signal-path filters that will affect the perception of fre-

quency response, not the detector-path filters.

Note that by having interpolation filters in the main channels but

not the subwoofer channel, there is a potential time-delay mis-

match between the main and sub channels. The group delay of

the digital interpolation filters used in the main left/right channels

is about 0.5 ms. This must be compared to the group delay of

the external analog filter used in the subwoofer path. If the

group delay mismatch causes a frequency response error (when the

two signals are “acoustically added”), the programmable delay

feature can be used to put extra delay in either the subwoofer path

or the main left/right path.

SPI PORT

Overview

De-emphasis Filtering

The standard for encoding CDs allows the use of a pre-emphasis

curve during encoding, which must be compensated for by a

de-emphasis curve during playback. The de-emphasis curve is

defined as a first-order shelving filter with a single pole at

(1/(2 × π × 50 µs)) followed by a single zero at (1/(2 × π × 15 µs)).

This curve may be accurately modeled using a first-order digital

filter. This filter is included in the AD1953; it is not part of the

bank of biquad filters, and so does not take away from the num-

ber of available filters.

The AD1953 has many different control options. Most signal-

processing parameters are controlled by writing new values to

the parameter RAM using the SPI port. Other functions such as

volume and de-emphasis filtering are programmed by writing to

SPI control registers.

The SPI port uses a 4-wire interface, consisting of CLATCH,

CCLK, CDATA, and COUT signals. The CLATCH signal

goes LOW at the beginning of a transaction and HIGH at the

end of a transaction. The CCLK signal latches the serial input

data on a low-to-high transition. The CDATA signal carries the

serial input data, and the COUT signal is the serial output data.

The COUT signal remains three-stated until a read operation is

requested. This allows other SPI compatible peripherals to

share the same readback line.

Since the specification of the de-emphasis filter is based on an

analog filter, the response of the filter should not depend on the

incoming sampling rate. However, when the de-emphasis filter is

implemented digitally, the response will scale with the sampling rate

unless the filter coefficients are altered to suit each possible input

sampling rate. For this reason, the AD1953 includes three separate

de-emphasis curves; one each for sampling rates of 32 kHz, 44.1 kHz,

and 48 kHz. These curves are selected by writing to Bits <5:4> of

Control Register 1 over the SPI port.

The SPI port is capable of full read/write operation for all of the

memories (parameter and program) and some of the SPI registers

(Control Register 1 and data capture registers). The memories

may be accessed in both a single-address mode or in burst mode.

All SPI transactions follow the same basic format, shown in Table I.

Using the Sub Reinjection Paths for Systems with No Subwoofer

Many systems will not use a subwoofer, but would still benefit

from 2-band compression/limiting. This can be accommodated

by using sub reinjection paths in the program flow. These

parameters are programmed by entering two numbers (in 2.20

format) into the parameter RAM. Note that if the biquad filters

are not properly designed, the frequency response at the cross-

over point may not be flat. Many crossover filters are designed to

be flat in the sense of adding the powers together, but nonflat if

The Wb/R bit is low for a write, and high for a read operation.

The 10-bit address word is decoded into a location in one of the

two memories (parameter or program) or one of the SPI regis-

ters. The number of data bytes varies according to the register

or memory being accessed. In burst-write mode (available for

loading the RAMs only), an initial address is given followed by a

continuous sequence of data for consecutive RAM locations.

REV. 0

–18–

AD1953

The detailed data format diagram for continuous-mode opera-

tion is given in SPI Read/Write data formats.

clicks. In cases where large blocks of data need to be downloaded,

the DSP core can be shut down and new data loaded, and the

core can then be restarted. The shutdown and restart mecha-

nisms employ a gradual volume ramp to prevent clicks and pops.

In cases where only a few parameters need to be changed (for

example, a single biquad filter), a safeload mechanism is used

that allows a block of SPI registers to be transferred to the

parameter RAM within a single audio frame while the core is

running. The safeload mode uses internal logic to prevent con-

tention between the DSP core and the SPI port.

A sample timing diagram for a single SPI WRITE operation to

the parameter RAM is shown in Figure 16.

Table I. SPI Word Format

Byte 0

Byte 1

Byte 2 Byte 3 Byte 4

Data Data

00000, R/Wb, adr[9:8] Adr[7:0] Data

A sample timing diagram of a single SPI READ operation is

shown in Figure 17. The COUT pin goes from three-state to

driven at the beginning of Byte 2. Bytes 0 and 1 contain the

address and R/W bit, and Bytes 2 to 4 carry the data. The exact

format is shown in Tables VIII to XIX.

SPI Address Decoding

Table II shows the address decoding used in the SPI port. The

SPI address space encompasses a set of registers and two RAMs,

one for holding signal-processing parameters and one for holding

the program instructions. Both of the RAMs are loaded on

power-up from on-board boot ROMs.

The AD1953 has several mechanisms for updating signal-

processing parameters in real time without causing loud pops or

CLATCH

CCLK

BYTE 0

CDATA

BYTE 1

BYTE 4

Figure 16. Sample of SPI WRITE Format (Single-Write Mode)

CLATCH

CCLK

BYTE 1

XXX

BYTE 0

CDATA

COUT

HI-Z

DATA

Figure 17. Sample of SPI READ Format (Single-Read Mode)

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REV. 0

AD1953

Table II. SPI Port Address Decoding

Read/Write Word Length

SPI Address

Register Name

0–255

Parameter RAM

Write: 22 Bits

Read: 22 Bits

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

SPI Control Register 1

SPI Control Register 2

Volume 0

Write: 14 Bits

Read: 2 Bits

Write: 10 Bits

Read: N/A

Write: 22 Bits

Read: N/A

Write: 22 Bits

Read: N/A

Write: 22 Bits

Read: N/A

Write: 22 Bits

Read: N/A

Write: 22 Bits

Read: N/A

Write: 22 Bits

Read: N/A

Volume 1

Volume 2

Volume 3

Volume 4

Volume 5

Volume 6

Write: 22 Bits

Read: N/A

Write: 22 Bits

Read: N/A

Volume 7

Data Capture (SPI Out) #1

Data Capture (SPI Out) #2

Data Capture (Serial Out) Slot 0

Data Capture (Serial Out) Slot 1

Data Capture (Serial Out) Slot 2

Data Capture (Serial Out) Slot 3

Data Capture (Serial Out) Slot 4

Data Capture (Serial Out) Slot 5

Parameter RAM Safeload Register 0

Parameter RAM Safeload Register 1

Parameter RAM Safeload Register 2

Parameter RAM Safeload Register 3

Parameter RAM Safeload Register 4