AD1954YSTRL [ADI]
SigmaDSP⑩ 3-Channel, 26-Bit Signal Processing DAC; SigmaDSP⑩ 3通道， 26比特信号处理DAC
| 型号： | AD1954YSTRL |
| 厂家： | 
ADI |
| 描述： | SigmaDSP⑩ 3-Channel, 26-Bit Signal Processing DAC |
| 文件： | 总36页 (文件大小：1445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SigmaDSP
Signal Processing DAC
Graphical Custom ProgrammingTools
5V 3-Channel Audio DAC System
44-Lead MQFP or 48-Lead LQFP Plastic Package
Accepts Sample Rates up to 48 kHz
7 Biquad Filter Sections per Channel
Dual Dynamic Processor with Arbitrary Input/Output Curve
and AdjustableTime Constants
0 ms to 6 msVariable Delay/Channel for Speaker Alignment
Stereo Spreading Algorithm for Phat Stereo™ Effect
Program RAM Allows Complete New Program Download
2.0/2.1 Channel Audio Systems (Two Main Channels plus
Subwoofer)
Automotive Sound Systems
Minicomponent Stereo
HomeTheater Systems (AC-3 Postprocessor)
In-Seat Sound Systems (Aircraft, Motor Coaches)
Parameter RAM Allows Complete Control of MoreThan
SPI Port Features Safe-Upload Mode forTransparent Filter
Updates
2 Control Registers Allow Complete Control of Modes and
MemoryTransfers
Differential Output for Optimum Performance
112 dB Signal-to-Noise (Not Muted) at 48 kHz Sample Rate
(A-Weighted Stereo)
The AD1954 is a complete 26-bit single-chip 3-channel digital
audio playback system with built-in DSP functionality for speaker
equalization, dual-band compression/limiting, delay compensa-
tion, and image enhancement.These algorithms can be used to
compensate for real-world limitations of speakers, amplifiers, and
listening environments, resulting in a dramatic improvement of
perceived audio quality.
70 dB Stop-Band Attenuation
On-Chip ClicklessVolume Control
The signal processing used in the AD1954 is comparable to that
found in high-end studio equipment. Most of the processing is
done in full 48-bit double-precision mode, resulting in very good
low-level signal performance and the absence of limit cycles or
idle tones.The compressor/limiter uses a sophisticated two-band
algorithm often found in high-end broadcast compressors.
Digital De-emphasis Processing for 32 kHz, 44.1 kHz, and
48 kHz Sample Rates
Flexible Serial Data Port with Right-Justified, Left-Justified,
2S Compatible, and DSP Serial Port Modes
Auxiliary Digital Input
()
SERIAL DATA
OUTPUT
3
3
AD1954
26 22
DSP CORE
3
3
AUDIO DATA
MUX
SERIAL DATA
INPUTS
DAC – L
DAC – R
DATA FORMAT:
3.23 (SINGLE PRECISION)
3.45 (DOUBLE PRECISION)
MASTER CLOCK
OUTPUT
ANALOG
OUTPUTS
MCLK
GENERATOR
MASTER
CLOCK INPUTS
MCLK
MUX
DAC – SW
(256f /512f )
S
S
AUX SERIAL
DATA INPUT
DATA CAPTURE
OUT
DIGITAL
OUTPUT
SPI DATA
OUTPUT
SERIAL CONTROL
INTERFACE
3
SPI INPUT
RAM
ROM
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed byAnalog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or other-
wise under any patent or patent rights ofAnalog Devices.Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
GENERAL DESCRIPTION (continued from page 1)
Internal DSP Signal Data Format
High-Pass Filter
Biquad Filters
Look-Ahead Delay
De-emphasis Filtering
Using the Sub Reinjection Paths for Systems with
Interpolation Filters
SPI Address Decoding
Vo
Power-Up Sequence
Setting the Clock Mode
Serial Data Input Modes
Cookbook Formulae for Audio EQ Biquad Coefficients
REV. A
Test conditions, unless otherwise noted.
SupplyVoltages (AVDD, DVDD
AmbientTemperature
Input Clock
)
Input Signal
Input Sample Rate
Load Capacitance
Load Impedance
InputVoltage High
InputVoltage Low
2200 pF
Typ
SIGNAL-TO-NOISE RATIO (20 Hz to 20 kHz) (Left/Right Output)
No Filter (Stereo)
With A-Weighted Filter
DYNAMIC RANGE (20 Hz to 20 kHz, –60 dB Input) (Left/Right Output)
With A-Weighted Filter
TOTAL HARMONIC DISTORTION PLUS NOISE (Left/Right Output)
O
SIGNAL-TO-NOISE RATIO (20 Hz to 20 kHz) (Subwoofer Output)
No Filter (Stereo)
With A-Weighted Filter
DYNAMIC RANGE (20 Hz to 20 kHz, –60 dB Input) (Subwoofer Output)
With A-Weighted Filter
TOTAL HARMONIC DISTORTION PLUS NOISE (Subwoofer Output)
O
Differential Output Range (± Full Scale) (Left/Right Output)
Differential Output Range (± Full Scale) (Subwoofer Output)
V p-p
V p-p
Gain Error (Left/Right Channel)
Gain Error (Subwoofer Channel)
ppm/°C
Degrees
INTERCHANNEL CROSSTALK (EIAJ Method)
Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
REV. A
(continued)
Typ
InputVoltage High (VIH)
InputVoltage High (VIH) – RESETB
InputVoltage Low (VIL)
Input Leakage (IIH @VIH = 2.1V)
Input Leakage (IIL @VIL = 0.8V)
High Level OutputVoltage (VOH), IOH
Low Level OutputVoltage (VOL), I
Input Capacitance
µA
µA
pF
Specifications subject to change without notice.
Typ
Voltage, Analog and Digital
Analog Current
Analog Current, Power-Down
Digital Current
Digital Current, SPI Power-Down
Digital Current, Reset Power-Down
Operation, Both Supplies
Operation, Analog Supplies
Operation, Digital Supplies
SPI Power-Down, Both Supplies
Reset Power-Down, Both Supplies
POWER SUPPLY REJECTION RATIO
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
ODVDD current is dependent on load capacitance and clock rate.
Specifications subject to change without notice.
Parameter
Typ
Max
Unit
Specifications Guaranteed
Functionality Guaranteed
Storage
25
°C
°C
°C
–40
–55
+105
+125
Specifications subject to change without notice.
REV. A
Typ
DMDC MCLK Recommended Duty Cycle @ 12.288 MHz (256 fS Mode)
DMDC MCLK Recommended Duty Cycle @ 24.576 MHz (512 fS Mode)
DMD MCLK Delay (All Mode)
DBH
DBH BCLK High Pulsewidth
DBD BCLK Delay (to BCLKO)
DLS LRCLK Setup
DLH
DLD LRCLK Delay (to LRCLKO)
DDS SDATA Setup
%
%
DDH
DDD SDATA Delay (to SDATAO)
CCL
CCH CCLK High Pulsewidth
CLS CLATCH Setup
CLH
CLD CLATCH High Pulsewidth
CDS CDATA Setup
CDH
COD COUT Delay
COH
DCD DCSOUT Delay
DCH
PDRP
Specifications subject to change without notice.
Typ
Pass-Band Ripple
Stop-Band Attenuation
S
S
S
Stop Band
Group Delay
Specifications subject to change without notice.
Package Characteristics (44-Lead MQFP)
Digital Inputs
ReferenceVo(AVDD + 0.3)/2V
Maximum JunctionTemperature
StorageTemperature Range
Typ
JA (Thermal Resistance—
Junction to Ambient)
JC (Thermal Resistance—
Junction to Ambient)
Package Characteristics (48-Lead LQFP)
Typ
JA (Thermal Resistance—
Junction to Ambient)
JC (Thermal Resistance—
Junction to Ambient)
Stresses above those listed underAbsolute Maximum Ratings may cause permanent
damage to the device.This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD1954YS
AD1954YSRL
AD1954YST
AD1954YSTRL
AD1954YSTRL7
EVAL-AD1954EB
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
44-Lead MQFP
44-Lead MQFP
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
Evaluation Board
S-44
S-44 on 13" Reel
ST-48
ST-48 on 13" Reel
ST-48 on 7" Reel
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on
the human body and test equipment and can discharge without detection. Although the AD1954 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATIONS
44-LEAD MQFP
48-LEAD LQFP
F
C
42
48 47 46 45 44 43 42 41 40 39 38 37
44 43
PIN 1
41 40 39 38 37 36 35 34
1
2
NC
MCLK2
36
35
34
33
32
31
30
29
28
27
26
25
NC
1
2
33
32
31
30
29
28
27
26
25
24
23
MCLK2
MCLK1
AGND
PIN 1
IDENTIFIER
AGND
IDENTIFIER
VOUTL–
VOUTL+
AVDD
3
MCLK1
VOUTL–
VOUTL+
AVDD
3
MCLK0
4
MCLK0
5
DEEMP/SDATA_AUX
MUTE
4
DEEMP/SDATA_AUX
MUTE
AD1954
6
AGND
5
AGND
TOP VIEW
AD1954
7
DVDD
AVDD
(Not to Scale)
6
DVDD
TOP VIEW
AVDD
8
SDATA2
VOUTR+
VOUTR–
AGND
(Not to Scale)
7
SDATA2
VOUTR+
VOUTR–
AGND
9
BCLK2
10
11
12
LRCLK2
8
BCLK2
LRCLK2
SDATA1
BCLK1
SDATA1
VOUTS+
VOUTS–
9
BCLK1
10
11
VOUTS+
VOUTS–
13 14 15 16 17 18 19 20 21 22 23 24
13
20
12
14 15 16 17 18 19
21 22
NC = NO CONNECT
REV. A
Input/
(44-MQFP) (48-LQFP) Mnemonic Output Description
SDATA_AUX
Master Clock Input 2 256 fSS
Master Clock Input 1 256 fSS
Master Clock Input 0 256 fSS
Enables 44.1 kHz De-emphasis Filter (Others Available through SPI Control)
Auxiliary Serial Data Input
6
DVDD
Mute Signal. Initiates volume ramp-down.
Digital Supply for DSP Core, 4.5V to 5.5V
Serial Data Input 2
Left/Right Clock 2
Serial Data Input 1
Digital Ground
Left/Right Clock 1
Serial Data Input 0
Left/Right Clock 0
SPI Data Input
LRCLK0
AGND
37
16
IN
SPI Data Framing Signal
Reset Signal, Active Low
Analog 5V Supply
Analog GND
Negative Sub Analog DAC Output
Positive Sub Analog DAC Output
Analog GND
Negative Left Analog DAC Output
Positive Left Analog DAC Output
Analog 5V Supply
Analog GND
Analog 5V Supply
Positive Left Analog DAC Output
Negative Left Analog DAC Output
Analog GND
25
No Connect
NC
Connection for Noise Reduction Capacitor
Zero Flag Output. High when both left and right channels are 0 for 1024 frames.
Serial Data Mux Output
Bit Clock Mux Output
Left/Right Clock Mux Output
Digital Supply Pin for Output Drivers, 2.5V to 5.5V
Data Capture Serial Output for Data Capture Registers. Use in conjunction with
selected LRCLK and BCLK to form a 3-wire output.
43
MCLKOUT OUT
SPI Data Output.Three-stated when inactive.
Master Clock Output 512 fS/256 fS (Frequency Selected by SPI Register)
Digital Ground
For a complete description of the pins, refer to the Pin Functions section.
REV. A
AD1954–Typical Performance Characteristics
0
–2
The following plots demonstrate the performance achieved on the
actual silicon.TPC 1 shows an FFT of a full-scale 1 kHz signal,
with aTHD+N of –100 dB, which is dominated by a second
harmonic.TPC 2 shows an FFT of a –60 dB sine wave, demon-
strating the lack of low-level artifacts.TPC 3 shows a frequency
response plot with the seven equalization biquads set to an alter-
nating pattern of 6 dB boosts and cuts.TPC 4 shows a linearity
plot, where the measurement was taken with the same equalization
curve used to makeTPC 3.When the biquad filters are not in use,
the signal passes through the filters with no quantization effects.
TPC 4 therefore demonstrates that using double-precision math
in the biquad filters has virtually eliminated any quantization
artifacts.TPC 5 shows a tone-burst applied to the compressor,
with the attack and recovery characteristics plainly visible.The
rms detector was programmed for normal rms time constants;
the hold/decay feature was not used for this plot.
–4
–6
–8
–10
–12
–14
–16
–18
–20
20
50
100
200
500
1k
2k
5k
10k
Hz
TPC 3. Frequency Response of EQ Biquad Filters
0
–20
3.0
2.5
2.0
1.5
–40
1.0
–60
0.5
–80
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–100
–120
–140
–160
0
2
4
6
8
10
12
14
16
18
20
–120
–100
–80
–60
–40
–20
0
kHz
dBFS
TPC 1. FFT of Full-Scale Sine Wave (32k Points)
TPC 4. Linearity Plot
0
–20
2.0
1.5
1.0
0.5
0
–40
–60
–80
–100
–120
–140
–160
–0.5
–1.0
–1.5
–2.0
0
2
4
6
8
10
12
14
16
18
20
–120
–100
–80
–60
–20
0
kHz
ms
TPC 5. Tone-Burst Response with Compressor
Threshold Set to –20 dB
TPC 2. FFT of –60 dB Sine Wave (32k Points)
REV. A
(continued from page 1)
An extensive SPI port allows click-free parameter updates, along
with read-back capability from any point in the algorithm flow.
The AD1954 contains a program RAM that boots from an internal
program ROM on power-up. Signal processing parameters are
stored in a 256-location parameter RAM, which is initialized on
power-up by an internal boot ROM. New values are written to
the parameter RAM using the SPI port.The values stored in the
parameter RAM control the IIR equalization filters, the dual-
band compressor/limiter, the delay values, and the settings of the
stereo spreading algorithm.
The AD1954 includes ADI’s patented multibit
ture.This architecture provides 112 dB SNR and dynamic range
andTHD+N of –100 dB.These specifications allow the AD1954
to be used in applications ranging from low-end boom boxes to
high-end professional mixing/editing systems.
The AD1954 has a very sophisticated SPI port that supports
complete read/write capability of both the program and the para-
meter RAM.Two control registers are also provided to control
the chip serial modes and various other optional features. Hand-
shaking is also included for ease of memory uploads/downloads.
The AD1954 also has a digital output that allows it to be used
purely as a DSP.This digital output can also be used to drive an
external DAC to extend the number of channels beyond the three
that are provided on the chip.
This chip can be used with either its default signal processing
program or with a custom user-designed program. Graphical pro-
gramming tools are available from ADI for custom programming.
The AD1954 contains four independent data capture circuits,
which can be programmed to tap the signal flow of the processor
at any point in the DSP algorithm flow.These captured signals
can be accessed either through a separate serial out pin (i.e., that
can be connected to an external DAC or DSP) or by reading from
the data capture SPI registers.This allows the basic functionality
of the AD1954 to be easily extended.
The AD1954 is comprised of a 26-bit DSP (48 bits with double
precision) for interpolation and audio processing, three multibit
modulators, and analog output drive circuitry. Other features
include an on-chip parameter RAM that uses a safe-upload feature
for transparent and simultaneous updates of filter coefficients and
digital de-emphasis filters. Also, on-chip input selectors allow up
The 3-channel configuration is especially useful for 2.1 playback
systems that include two satellite speakers and a subwoofer.
The default program allows for independent equalization and
compression/limiting for the satellite and subwoofer outputs.
Figure 1 shows the block diagram of the device.
The processor core in the AD1954 has been designed from the
ground up for straightforward coding of sophisticated compres-
sion/limiting algorithms.The AD1954 contains two independent
compressor/limiters with rms based amplitude detection and
attack/hold/release controls, together with an arbitrary compression
curve that is loaded by the user into a look-up table that resides
in the parameter RAM.The compressor also features look-ahead
compression that prevents compressor overshoots.
VREF
ZEROFLAG
RESETB
MUTE DE-EMPHASIS
DVDD
AVDD
3
ODVDD
VOLTAGE
3
DATA MEMORY, 512 26
REFERENCE
3
DAC – L
DAC – R
3:1
SERIAL DATA I/O
GROUP
3
3
AUDIO
SERIAL
IN
ANALOG
OUTPUTS
26 22
DSP CORE
DATA
MUX
1
1
2
DAC – SW
AUX SERIAL
DATA INPUT
DATA FORMAT:
3.23 (SINGLE PRECISION)
ANALOG
BIAS GROUP
BIAS
3.45 (DOUBLE PRECISION)
MCLK
GENERATOR
(256 fS/512 fS IN)
256 fS/512 fS OUT
MASTER
CLOCK I/O
GROUP
3:1
1
MCLK
1
MUX
CONTROL
COEFFICIENT
ROM
64 22
PROGRAM
RAM
512 35
PARAMETER
RAM
256 22
REGISTERS
SPI I/O
GROUP
TRAP REG.
SPI PORT
FILTCAP
3
2
(I S, SPI)
SAFELOAD
REGISTERS
DCSOUT
MEMORY CONTROLLERS
DCSOUTTRAP
AGND
3
DGND
2
NOTES
1
CONTROLLEDTHROUGH SPI CONTROL REGISTERS.
2
DAC DOES NOT USE DIGITAL INTERPOLATION.
Figure 1. Block Diagram
REV. A
—Master Clock Output
The AD1954 has a very flexible serial data input port, which
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers, and sample rate converters. The
AD1954 can be configured in left-justified, I2S, right-justified, or
DSP serial port compatible modes. It can support 16 bits, 20 bits,
and 24 bits in all modes. The AD1954 accepts serial audio data
in MSB first, twos complement format. The part can also be set
up in a 4-channel serial input mode by simultaneously using the
serial input mux and the auxiliary serial input.
The master clock output pin may be programmed to produce
S, 512 S, or a copy of the selected MCLK input
pin.This pin is programmed by writing to Bits 1 and 0 of Control
Register 2.The default is 00, which disables the MCLKO pin.
See SPI Port section for more information on SPI port timing.
—Serial Data Output
The AD1954 operates from a single 5V power supply. It is fabri-
cated on a single monolithic integrated circuit and is housed in a
44-lead MQFP or 48-lead LQFP package for operation over the
temperature range –40°C to +105°C.
This is used for reading back registers and memory locations. It
for more information on SPI port timing.
PIN FUNCTIONS
This pin either may run continuously or be gated off in between
SPI port timing.
All input pins have a logic threshold compatible withTTL input
levels and can therefore be used in systems with 3.3V logic. All
digital output levels are controlled by the ODVDD pin, which
may range from 2.7V to 5.5V, for compatibility with a wide
range of external devices. (See Pin Function Descriptions table.)
—SPI Latch Signal
It must go low at the beginning of an SPI transaction and high at the
end of a transaction. Each SPI transaction may take a different
number of CCLKs to complete, depending on the address and
read/write bit that are sent at the beginning of the SPI transaction.
Detailed SPI timing information is given in SPI Port section.
SDATA0, SDATA1, SDATA2—Serial Data Inputs
One of these three inputs is selected by an internal mux, set by
writing to Bits 7 and 6 in Control Register 2. Default is 00, which
selects SDATA0.The serial format is selected by writing to Bits 3–0
of Control Register 0. See SPI Read/Write Data Formats section
for recommendations on how to change input sources without
causing a click or pop noise.
—Active Low Reset Signal
After RESETB goes high, the AD1954 goes through an initial-
ization sequence where the program and parameter RAMs are
SPI registers are set to 0, and the data RAMs are also zeroed.The
initialization is complete after 1024 MCLK cycles. Since the
MCLK IN FREQ SELECT (Bit 2 in Control Register 2) defaults
S at power-up, this initialization will proceed at the
external MCLK rate and will take 1024 MCLK cycles to com-
plete, regardless of the absolute frequency of the external MCLK.
New values should not be written to the SPI port until the initial-
ization is complete.
LRCLK0, LRCLK1, LRCLK2—Left/Right Clocks for Framing the
Input Data
The active LRCLK input is selected by writing to Bits 7 and 6
in Control Register 2.The default is 00, which selects LRCLK0.
The interpretation of the LRCLK changes according to the serial
mode, set by writing to Control Register 0.
BCLK0, BCLK1, BCLK2—Serial Bit Clocks for Clocking in the
Serial Data
The active BCLK input is selected by writing to Bits 7 and 6 in
Control Register 2. Default is 00, which selects BCLK0.The
interpretation of BCLK changes according to the serial mode,
which is set by writing to Control Register 0.
—Zero-Input Indicator
This pin will go high if both serial inputs have been inactive (zero
data) for 1024 LRCLK cycles.This pin may be used to drive an
external mute FET for reduced noise during digital silence.This
pin also functions as a test out pin, controlled by the test register
end user, one may be of some use. If theTest Register is pro-
grammed with the number 7 (decimal), the ZEROFLAG output
will be switched to the output of the internal pseudo-random noise
generator.This noise generator operates at a bit rate of 128 S
and has a repeat time of once per 224 cycles.This mode may be
used to generate white noise (or, with appropriate filtering, pink
noise) to be used as a test signal for measuring speakers or room
LRCLKOUT, BCLKOUT, SDATAOUT—Output of Mux that
Selects One of theThree Serial Input Groups
These pins may be used to send the selected serial input signals
to other external devices.This output pin is enabled by writing a
1 to Bit 8 of Control Register 2.The default mode is 0 or Off.
MCLK0, MCLK1, MCLK2—Master Clock Inputs
Active input selected by writing to Bits 5 and 4 of Control Regis-
ter 2.The default is 00, which selects MCLK0.The master clock
frequency must be either 256 S S, where fS is the input
sampling rate.The master clock frequency is programmed by
writing to Bit 2 of Control Register 2.The default is 0 (512 S).
See the Initialization section for recommendations concerning
how to change clock sources without causing an audio click or pop.
Note that since the default MCLK source pin is MCLK0, there
must be a clock signal present on this pin on power-up so that
the AD1954 can complete its initialization routine.
REV. A
—Data Capture Serial Out
The full-scale swing scales directly withVREF.These outputs are
capable of driving a load of >5 k, with a maximum peak current
of 1 mA from each pin. An external third order filter is recom-
mended for filtering out-of-band noise.
This pin will output the DSP’s internal signals, which can be used
by external DACs or other signal processing devices.The signals
that are captured and output on the DCSOUT pin are controlled
by writing program counter trap numbers to SPI Addresses 263
(for the left output) and 264 (for the right output).When the inter-
nal program counter contents are equal to the trap values written
to the SPI port, the selected DSP register is transferred to the
DCSOUT parallel-to-serial registers and shifted out on the
DCSOUT pin.Table XX shows the program counter trap values
and register-select values that should be used to tap various inter-
nal points of the algorithm flow.
VOUTR+,VOUTR2 —Right Channel Differential Outputs
left channel VOUTL+,VOUTL–.
VOUTS+,VOUTS2 —Subchannel Differential Outputs
These outputs are designed to drive loads of 10 k or greater,
with a peak current capability of 250 µA.This output does not
use digital interpolation, since it is intended for low frequency
applications. An external third order filter with a cutoff frequency
The DCSOUT pin is meant to be used in conjunction with the
LRCLK and BCLK signals that are provided to the serial input
port.The format of DCSOUT is the same as the format used
for the serial port. In other words, if the serial port is running in
2S mode, then the DCSOUT pin, together with the LRCLK0
and BCLK0 pins (assuming input 0 is selected), will form a valid
2S output.
VREF—Analog ReferenceVoltage Input
The nominalVREF input voltage is 2.5V; the analog gain scales
directly with the voltage on this pin.When using the AD1954 to
drive a power amplifier, it is recommended that theVREF voltage
be derived by dividing down and heavily filtering the supply to the
power amplifier.This provides a benefit if the compressor/limiter
in the AD1954 is used to prevent amplifier clipping. In this case, if
the DAC output voltage is scaled to the amplifier power supply, a
fixed compressor threshold can be used to protect an amplifier
whose supply may vary over a wide range. Any ac signal on this
pin will cause distortion, and therefore, a large decoupling capaci-
tor may be necessary to ensure that the voltage onVREF is clean.
The input impedance ofVREF is greater than 1 M
The DCSOUT pin can be used for a variety of purposes. If the
DCSOUT pin is used to drive another external DAC, then a
4.1 system is possible using a new program downloaded into the
program RAM.
DEEMP/SDATA_AUX—De-emphasis Input Pin/Auxiliary Serial
Data Input
In de-emphasis mode, if this pin is asserted high, then a digital
de-emphasis filter will be inserted into the signal flow.The
de-emphasis curve is valid only for a sample rate of 44.1 kHz;
curves for 32 kHz and 48 kHz may be programmed using the
SPI port.This pin can also be used as an auxiliary 2-channel serial
data input.This function is set by writing a 1 to Bit 11 of Control
Register 1.The same clocks are used for this serial input as are
used for the SDATA0, SDATA1, and SDATA2 signals.This serial
input can only be used in the signal processing flow when using
Analog Devices’ custom programming tools; see the Graphical
Custom ProgrammingTools section.The use of de-emphasis is
still available while this pin is used as a serial input but only
through SPI control.
FILTCAP—Filter Capacitor Point
This pin is used to reduce the noise on an internal biasing point
in order to provide the highest performance. It may not be neces-
sary to connect this pin, depending on the quality of the layout
and the grounding used in the application circuit.
DVDD—DigitalVDD for Core
ODVDD—DigitalVDD for All Digital Outputs
—Mute Output Signal
DGND (2)—Digital Ground
When this pin is asserted high, a ramp sequence is started, which
gradually reduces the volume to zero.When de-asserted, the volume
ramps from zero back to the original volume setting.The ramp
speed is timed so that it takes 10 ms to reach 0 volume when starting
from the default 0 dB volume setting.
AVDD (3)—AnalogVDD
5V nominal. For best results, use a separate regulator for AVDD.
Bypass capacitors should be placed close to the pins and connected
directly to the analog ground plane.
VOUTL+,VOUTL2—Left Channel Differential Analog Outputs
Full-scale outputs correspond to 1Vrms on each output pin or
2V rms differential, assuming aVREF input voltage of 2.5V.
AGND (3)—Analog Ground
For best performance, separate nonoverlapping analog and digital
ground planes should be used.
REV. A
–11
L/R DYNAMICS PROCESSOR
EQ AND CROSSOVER FILTERS
8
DELAY
(0ms–2.3ms)
OUT
DAC
DAC
INTERPOLATION
LEFT
DELAY
(0ms–3.7ms)
CROSSOVER
7 BIQUAD
(2 FILTERS)
FILTERS
HPF/
DEEMPH
IN
LEFT
LEVEL DETECT,
LOOK-UP TABLE
DELAY
(0ms–3.7ms)
HPF/
DEEMPH
CROSSOVER
(2 FILTERS)
7 BIQUAD
FILTERS
IN
RIGHT
8
DELAY
(0ms–2.3ms)
OUT
RIGHT
INTERPOLATION
L/R REINJECTION
LEVEL
LEVEL DETECT,
LOOK-UP TABLE
1 BIQUAD
FILTER
SUB CHANNEL
L/R MIX
DELAY
(0ms–3.7ms)
SUBWOOFER
OUTPUT
CROSSOVER
(3 FILTERS)
MONO DAC
SUB DYNAMICS PROCESSOR
Figure 2. Signal Processing Flow
Signal Processing Overview
coefficient values (stored in the parameter RAM) and one for the
signal data values.The coefficient format is as follows:
Figure 2 shows the signal processing flow diagram of the AD1954.
The AD1954 is designed to provide all the signal processing
functions commonly used in 2.0 or 2.1 playback systems. A seven-
biquad equalizer operates on the stereo input signal.The output of
this equalizer is fed to a two-biquad crossover filter for the main
channels, and the mono sum of the left and right equalizer outputs
is fed to a three-biquad crossover filter for the subchannel. Each
of the three channels has independent delay compensation.There
are two high quality compressor/limiters available: one operating
on the left/right outputs and one operating on the subwoofer chan-
nel.The subwoofer output may be blended back into the left/right
outputs for 2.0 playback systems. In this configuration, the two
independent compressor/limiters provide two-band compression,
which significantly improves the sound quality of compressed
audio. In addition, the main channels have a stereo widening
algorithm that increases the perceived spread of the stereo image.
Coefficient Format
Range: –2.0 to +(2.0 – 1 LSB)
Examples:
1111111111111111111111 = (1 LSB below 0.0)
0111111111111111111111 = (2.0 – 1 LSB)
This format is used because standard biquad filters require
coefficients that range between +2.0 and –2.0. It also allows gain
to be inserted at various places in the signal path.
Internal DSP Signal Data Format
Input Data Format: 1.23
This is sign extended when written to the data memory of the
Internal DSP Signal Data Format: 3.23
Range: –4.0 to +(4.0 – 1 LSB)
Examples:
Most of the signal processing functions are coded using full 48-bit
double-precision arithmetic.The input word length is 24 bits, with
two extra headroom bits added in the processor to allow internal
gains up to 12 dB without clipping (additional gains can be
accommodated by scaling down the input signal in the first biquad
filter section).
11111111111111111111111111 = (1 LSB below 0.0)
01111111111111111111111111 = (4.0 – 1 LSB).
A graphical user interface (GUI) is available for evaluation of
the AD1954 (Figure 3).This GUI controls all of the functions of
the chip in a very straightforward and user friendly interface. No
code needs to be written to use the GUI to control the chip. For
more information on AD1954 software tools, send an e-mail to
SigmaDSP@analog.com.
Each section of this flow diagram will be explained in detail on
the following pages.
The sign extension between the serial port and the DSP core
allows for up to 12 dB of gain in the signal path without internal
clipping. Gains greater than 12 dB can be accommodated by
scaling the input down in the first biquad filter and scaling the
signal back up at the end of the biquad filter section.
It is common in DSP systems to use a standardized method of
specifying numeric formats.To better comprehend issues relating to
precision and overflow, it is helpful to think in terms of fractional
twos complement number systems. Fractional number systems
are specified by an A.B format, where A is the number of bits to
the left of the decimal point, and B is the number of bits to the
right of the decimal point. In a twos complement system, there is
also an implied offset of one-half of the binary range; for example,
in a twos complement 1.23 system, the legal signal range is
–1.0 to +(1.0 – 1 LSB).
A digital clipper circuit is used between the output of the DSP
core and the input to the DAC modulators to prevent over-
loading the DAC circuitry (see Figure 4). Note that there is a gain
factor of 0.75 used in the DAC interpolation filters, and therefore
signal values of up to 1/0.75 will pass through the DSP without
clipping. Since the DAC is designed to produce an analog output
of 2V rms (differential) with a 0 dB digital input, signals between
REV. A
Figure 3. Graphical User Interface
0.75
2-BIT SIGN EXTENTION
DIGITAL -
DIGITAL
CLIPPER
SIGNAL PROCESSING
(3.23 FORMAT)
DAC INTERPOLATION
FILTERS (3.23 FORMAT)
MODULATORS
DATA IN
SERIAL PORT
(1.23 FORMAT)
1.23
3.23
Figure 4. Numeric Precision and Clipping Structure
0 dB and 1/0.75 (approximately 3 dB) will produce larger analog
outputs and result in slightly degraded analog performance.This
extra analog range is necessary in order to pass 0 dBFS square
waves through the system, since these square waves cause over-
shoots in the interpolation filters, which would otherwise briefly
clip the digital DAC circuitry.
is the exponential operator, HPF_cutoff is the high-
pass cutoff in Hz, and fS is the audio sampling rate.The default
value for the –3 dB cutoff of the high-pass filter is 2.75 Hz at a
sampling rate of 44.1 kHz.
Biquad Filters
Each of the two input channels has seven second order biquad
sections in the signal path. In addition, the left and right channels
have two additional biquad filters that may be used either as
crossover filters or as additional equalization filters.The subchan-
nel has three additional biquad filters that are also to be used
as equalization and/or crossover filters. In a typical scenario, the
first seven biquads would be used for speaker equalization and/or
tone controls, and the remaining filters would be programmed to
function as crossover filters. Note that there is a common equal-
ization section used for both the main and sub channels, followed
by the crossover filters.This arrangement prevents any interaction
from occurring between the crossover filters and the equalization
filters. One section of the biquad IIR filter is shown in Figure 5.
A separate digital clipper circuit is used in the DSP core to ensure
that any accumulator values that exceed the numeric 3.23 format
range are clipped when taken from the accumulator.
High-Pass Filter
The high-pass filter is a first order double-precision design.The pur-
pose of the high-pass filter is to remove digital dc from the input. If
this dc were allowed to pass, the detectors used in the compressor/
limiter would give an incorrect reading for low signal levels.The
high-pass filter is controlled by a single parameter (alpha_HPF),
which is programmed by writing to SPI location 180 in 2.20 twos
complement format.The following equation can be used to calcu-
late the parameter alpha_HPF from the –3 dB point of the filter:
–2.0 × p × HPF_Cutoff
Alpha_HPF = 1.0 – EXP
fS
REV. A
b0
to fit the signal into the 12 dB maximum signal range and then
scaled back up at the end of the filter chain.
OUT
IN
Volume
b1
b2
a1
a2
–1
–1
Three separate SPI registers are used to control the volume—one
each for the left, right, and sub channels.These registers are
special in that they include automatic digital ramp circuitry for
clickless volume adjustment.The volume control word is in 2.20
format and therefore gains from +2.0 to –2.0 are possible.The
default value is 1.0. It takes 1024 audio frames to adjust the vol-
ume from 2.0 down to 0; in the normal case where the maximum
volume is set to 1.0, it will take 512 audio frames for this ramp to
reach zero. Note that a mute command is the same as setting the
volume to zero, except that when the part is unmuted, the vol-
ume returns to its original value.
Z
Z
–1
–1
Z
Z
Figure 5. Biquad Filter
This section implements the transfer function:
b0 + b1× Z–1 + b2 × Z–2
1− a1× Z–1 – a2 × Z–2
(
)
H Z =
( )
These volume ramp times assume that the AD1954 is set for
the fast volume ramp speed. If the slow setting is selected, it will
take 8192 audio frames to reach zero from a setting of 2.0. Cor-
respondingly, it will take 4096 frames to reach 0 volume from the
normal setting of 1.0.
The coefficients a1, a2, b0, b1, and b2 are all in twos comple-
ment 2.20 format with a range from –2 to +2 (minus 1 LSB).
The negative sign on the a1 and a2 coefficients is the result of
adding both the feed-forward b terms as well as the feedback a
terms. Some digital filter packages automatically produce the
correct a1 and a2 coefficients for the topology of Figure 5, while
others assume a denominator of the form 1 + a1 × Z–1 + a2
–1. In this case, it may be necessary to invert the a1 and a2
terms for proper operation.
The volume blocks are placed after the biquad filter sections to
maximize the level of the signal that is passed through the filter
sections. In a typical situation, the nominal volume setting might
be –15 dB, allowing a substantial increase in volume when the user
increases the volume.The AD1954 was designed with an analog
dynamic range of >112 dB, so that in the typical situation with
the volume set to –15 dB, the signal-to-noise ratio at the output
will still exceed 97 dB. Greater output dynamic ranges are pos-
sible if the compressor/limiter is used, since the post-compression
gain parameter can boost the signal back up to a higher level. In
this case, the compressor will prevent the output from clipping
when the volume is turned up and the input signal is large.
The biquad structure shown in Figure 5 is coded using double-
precision math to avoid limit cycles from occurring when low
frequency filters are used.The coefficients are programmed
by writing to the appropriate location in the parameter RAM,
through the SPI port (seeTableVI).There are two possible sce-
narios for controlling the biquad filters:
1. Dynamic Adjustment (e.g., Bass/Treble Control or Parametric
Equalizer).
Stereo Image Expander
The image enhancement processing is based on ADI’s patented
Phat Stereo algorithm.The block diagram is shown in Figure 6.
When using dynamic filter adjustment, it is highly recom-
mended that the user employ the safeload mechanism to avoid
temporary instability when the filters are dynamically updated.
This could occur if some, but not all, of the coefficients were
updated to new values when the DSP calculates the filter
output.The operation of the safeload registers is detailed in
the Options for Parameter Updates section.
LEFT OUT
LEFT IN
+
–
–
+
–
1kHz
FIRST ORDER LPF
2. Setting Static EQ Curve after Power-Up.
LEVEL
If many of the biquad filters need to be initialized after power-
up (e.g., to implement a static speaker correction curve), the
recommended procedure is to set the processor shutdown bit,
wait for the volume to ramp down (about 20 ms), and then
write directly to the parameter RAM in burst mode. After the
RAM is loaded, the shutdown bit can be de-asserted, causing
the volume to ramp back up to the initial value.This entire proce-
dure is click-free and faster than using the safeload mechanism.
RIGHT OUT
RIGHT IN
Figure 6. Stereo Image Expander
The algorithm works by increasing the phase shift for low frequency
signals that are panned left or right in the stereo mix. Since the ear
is responsive to interaural phase shifts below 1 kHz, this increase in
phase shifts results in a widening of the stereo image. Note that
signals panned to the center are not processed, resulting in a more
natural sound.There are two parameters that control the Phat
Stereo algorithm: the level variable, which controls how much out-
of-phase information is added to the left and right channels, and
the cutoff frequency of the first order low-pass filter, which deter-
mines the frequency range of the added out-of-phase signals. For
best results, the cutoff frequency should be in the range of 500 Hz
to 2 kHz.These parameters are controlled by altering the param-
eter RAM locations that store the parameters spread_level and
alpha_spread.The spread_level is a linear number in 2.20 format
that multiplies the processed left-right signal before it is added to or
subtracted from the main channels.The parameter alpha_spread
The data paths of the AD1954 contain an extra two bits on top of
the 24 bits that are input to the serial port.This allows up to 12 dB
of boost without clipping. However, it is important to remember
that it is possible to design a filter that has less than 12 dB of gain
at the final filter output, but more than 12 dB of gain at the output
of one or more intermediate biquad filter sections. For this reason,
it is important to cascade the filter sections in the correct order,
putting the sections with the largest peak gains at the end of the
chain rather than at the beginning.This is standard practice when
coding IIR filters and is covered in basic books on DSP coding.
If gains larger than 12 dB cannot be avoided, then the coefficients
b0 through b2 of the first biquad section may be scaled down
REV. A
is related to the cutoff frequency of the first order low-pass filter
by the equation:
A single hard threshold results in more audible behavior than a
so-called soft-knee compressor, where the compression is in-
troduced more gradually. In an analog compressor, the soft-knee
characteristic is usually made by using diodes in their exponential
turn-on region.
–2.0 × p × Spread_Freq
Alpha_Spread = 1.0 – EXP
fS
is the exponential operator, Spread_Freq is the low-pass
cutoff in Hz, and fS is the audio sampling rate.
OUT
VCA WITH EXP
CONTROL
THRESHOLD
SLOPE
Note that the stereo spreading algorithm assumes that frequencies
below 1 kHz are present in the main satellite speakers. In some
systems, the crossover frequency between the satellite and sub-
woofer speakers is quite high (>500 Hz). In such a case, the stereo
spreading algorithm will not be effective, since the frequencies
that contribute to the spreading effect will come mostly from the
subwoofer, which is a mono source.
COMPRESSION
CURVE
NONLINEAR
CIRCUITS
RMS DETECTOR
WITH DB OUT
FILTER
Figure 7. Analog Compressor
Delay
The best analog compressors use rms detection as the signal
amplitude detector.The only class of detectors that is not sensi-
tive to the phase of the harmonics in a complex signal are rms
detectors.The ear also bases its loudness judgment on the overall
signal power and therefore using an rms detector results in the
best audible performance. Compressors that are based on peak
detection, while good for preventing clipping, are generally quite
poor for audible performance.
Each of the three DAC channels has a delay block that allows the
user to introduce a delay of up to 165 audio samples.The delay
values are programmed by entering the delay (in samples) into
the appropriate location of the parameter RAM.With a 44.1 kHz
sample rate, a delay of 165 samples corresponds to a time delay
of 3.74 ms. Since sound travels at approximately 1 foot/ms, this
can be used to compensate for speaker placements that are off by
rapidly they can respond to transient signals.There is always a
trade-off between speed of response and distortion. Figure 8
An additional 100 samples of delay are used in the look-ahead
portion of the compressor/limiter but only for the main two chan-
nels.This can be used to increase the total delay for the left and
right channels to 265 samples or 6 ms at 44.1 kHz.
INPUTWAVEFORM
Main Compressor/Limiter
The compressor used in the AD1954 is quite sophisticated and is
comparable in many ways to the professional compressor/limiters
used in the professional audio and broadcast fields. It uses rms/
peak detection with adjustable attack/hold/release, look-ahead
compression, and table-based entry of the input/output curve for
complete flexibility.
The AD1954 uses two compressor/limiters: one in the subwoofer
DAC and one in the main left/right DAC. It is well known that
having independent compressors operating over different fre-
quency ranges results in a superior perceived sound.With a
single-band compressor, loud bass information will modulate the
gain of the entire audio signal, resulting in suboptimal maximum
perceived loudness as well as gain pumping or modulation effects.
With independent compressors operating separately on the low
and high frequencies, this problem is dramatically reduced. If the
AD1954 is being operated in two-channel mode, an extra path is
main channel.This maintains the advantage of using a two-band
compressor, even in a 2.0 system configuration.
COMPRESSOR ENVELOPE—
FASTTIME CONSTANT
COMPRESSOR ENVELOPE—
SLOWTIME CONSTANT
In the case of a fast-responding rms detector, the detector envelope
will have a signal component in addition to the desired dc com-
ponent.This signal component (which, for an rms detector, is
at twice the input frequency) will result in harmonic distortion
when multiplied by this detector signal.
Figure 7 shows the traditional basic analog compressor/limiter.
It uses a voltage controlled amplifier to adjust gain and a feed-
forward detector path using an rms detector with adjustable time
constants, followed by a nonlinear circuit, to implement the
desired input/output relationship. A simple compressor will have
a single threshold above which the gain is reduced.The amount of
compression above the threshold is called the compression ratio
and is defined as dB change in input/dB change in output. For
example, if the input to a 2:1 compressor is increased by 2 dB,
the output will rise by 1 dB for signals above the threshold.
The AD1954 uses a modified rms algorithm to improve the relation-
ship between acquisition time and distortion. It uses a peak-riding
circuit together with a hold circuit to modify the rms signal, as
shown in Figure 9.This figure shows two envelopes. One has the
harmonic distortion, as seen in the previous figure, and the other,
flatter envelope is the one produced by the AD1954.
REV. A
INPUTWAVEFORM
DESIRED
COMPRESSION
CURVE
RELEASETIME, SPI-
PROGRAMMABLE
HOLDTIME, SPI-
PROGRAMMABLE
INPUT LEVEL – 3dB/TABLE ENTRY
Figure 9. Using the Hold and ReleaseTime Feature
Using this idea of a modified rms algorithm, the true rms value
is still obtained for all but the lowest frequency signals, while the
distortion due to rms ripple is reduced. It also allows the user to
set the hold and release times of the compressor independently.
The detector path of the AD1954 is shown in Figure 10.The rms
detector is controlled by three parameters stored in the parameter
RAMs: the rms time constant, the hold time, and the release rate.
The log output of the rms detector is applied to a look-up table
with interpolation.The higher bits of the rms output form an
offset into this table, and the lower bits are used to interpolate
between the table entries to form a high-precision gain word.The
look-up table resides in the parameter RAM and is loaded by
the user to give the desired curve.The look-up table contains 33
data locations, and the LSB of the address into the look-up table
corresponds to a 3 dB change in the amplitude of the detector
signal.This gives the user the ability to program an input/output
curve over a 99 dB range. For the main compressor, the table
resides in Locations 110 to 142 in the SPI parameter RAM.
INPUT LEVEL – 3dB/TABLE ENTRY
Figure 11. Example ofTable Entry for a Given
Compression Curve
Note that the maximum gain that can be entered in the table is
2.0 (minus 1 LSB). If more gain is required, the entire compres-
sion curve may be shifted upward by using the post-compression
gain block following the compressor/limiter.
The AD1954 compressor/limiter also includes a look-ahead com-
pression feature.The idea behind look-ahead compression is to
prevent compressor overshoots by applying some digital delay to
the signal before the gain-control multiplier but not to the detec-
tor path. In this way, the detector can acquire the new amplitude
of the input signal before the signal actually reaches the multiplier.
A comparison of a tone burst fed to a conventional compressor
versus a look-ahead compressor is shown in Figure 12.
HIGH BITS (1LSB = 3dB)
MODIFIED RMS
DETECTOR WITH
LOG OUTPUT
OUTPUT TO
GAIN STAGE
LOOK-UP TABLE
LOW BITS
LINEAR
INTERPOLATION
RELEASE
HOLD
TIME
CONSTANT
CONVENTIONAL COMPRESSOR GAIN
Figure 10. Gain Derived from Interpolated Look-UpTable
One subtlety of the look-up table involves the difference between
the rms value of a sine wave and that of a square wave. If a full-
scale square wave is applied to the AD1954, the rms value of this
signal will be 3 dB higher than the rms value of a 0 dBFS sine
wave.Therefore, the table ranges from +9 dB (Location 142) to
–87 dB (Location 110).
LOOK-AHEAD COMPRESSOR GAIN
The entries in the table are linear gain words in 2.20 format.
Figure 11 shows an example of the table entries for a simple
above-threshold compressor.
HOLDTIME
Figure 12. Conventional Compression vs. Look-Ahead
Compression
REV. A
In the look-ahead compressor, the gain has already been reduced
by the time that the tone-burst signal arrives at the multiplier input.
Note that when using a look-ahead compressor, it is important to
the look-ahead delay time or the compressor release will start too
soon, resulting in an expanded tail of a tone-burst signal.The
complete flow of the left/right dynamics processor is shown in
Figure 13.
rms_hold_time_parameter = int f × hold_time
S
rms_holdtime_parameter = the integer number to enter into
the SPI RAM, fS = the audio sample rate, hold_time
lute time to wait before starting the release ramp-down of the
detector output, and () = the integer part of the expression.
rms_decay_parameter = int rms_decay /0.137
(
)
DELAY
POSTCOMPRESSION
rms_decay_parameter = the decimal integer number to enter
into the SPI RAM, rms_decay = the decay rate in dB/sec, and
() = the integer part of the expression.
SPI-PROGRAMMABLE
LOOK-AHEAD DELAY
GAIN, SPI-
PROGRAMMABLE
UP TO 30dB
DELAY
(L+R)
2
Look-Ahead Delay
lookahead_delay_parameter = lookahead_delay × fS
HIGH BITS (1LSB = 3dB)
MODIFIED RMS
DETECTOR WITH
LOG OUTPUT
lookahead_delay = the predictive compressor delay in
absolute time, fS = the audio sample rate, and the maximum
lookahead_delay_parameter
LOOK-UP
TABLE
LINEAR
INTERPOLATION
LOW BITS
RELEASE
HOLD
TIME
CONSTANT
Postcompression Gain
post_compression_gain_parameter =
Figure 13. Complete Dynamics Flow, Main Channels
post_compression_gain_linear∧ 1/5
The detector path works from the sum of the left and right channels
((L + R)/2).This is the normal way that compressors are built and
counts on the fact that the main instruments in any stereo mix are
seldom recorded deliberately out of phase, especially in the lower
frequencies that tend to dominate the energy spectrum of real music.
post_compression_gain_linear is the linear post-compression
gain and ^ = the raise to the power.
Subwoofer Compressor/Limiter
The subwoofer compressor/limiter differs from the left/right
compressor in the following ways:
The compressor is followed by a block known as post-compression
gain. Most compressors are used to reduce the dynamic range
of music by lowering the gain during loud signal passages.This
results in an overall loss of volume.This loss can be made up by
introducing gain after the compressor. In the AD1954, the coef-
ficient format used is 2.20, which has a maximum floating-point
representation of slightly less than 2.0.This means that the maxi-
mum gain that can be achieved in a single instruction is 6 dB.To
get more gain, the program in the AD1954 uses a cascade of five
multipliers to achieve up to 30 dB of post-compression gain.
1. The subwoofer compressor operates on a weighted sum of the
left and right inputs (aa Right), where aa and
bb are both programmable.
2. The detector input has a biquad filter in series with the input
in order to implement frequency-dependent compression
3. There is no predictive compression since presumably the input
signals are filtered to pass only low frequencies and therefore
transient overshoots are not a problem.
To program the compressor/limiter, the following formulas may
be used to determine the 22-bit numbers (in 2.20 format) to be
entered into the parameter RAM.
The subwoofer compressor signal flow is shown in Figure 14.
V
_SUB = k1 LEFT_IN + K2 RIGHT_IN
IN
RMSTime Constant
This can be best expressed by entering the time constant in terms
of dB/sec raw release rate (without the peak-riding circuit).The
attack rate is a rather complicated formula that depends on the
change in amplitude of the input sine wave.
POSTCOMPRESSION
PROGRAMMABLE
UP TO 30dB
HIGH BITS (1LSB = 3dB)
MODIFIED RMS
DETECTOR WITH
LOG OUTPUT
BIQUAD
FILTER
LOOK-UP
TABLE
LINEAR
INTERPOLATION
release_rate
LOW BITS
10.0 × fS
)
rms_tconst_parameter = 1.0 – 10 (
RELEASE
HOLD
TIME
CONSTANT
the SPI RAM (after converting to 22-bit 2.20 format), and the
release_rate = the
This must be negative, and fS = the audio sample rate.
Figure 14. Signal Flow for Subwoofer Compressor
REV. A
The biquad filter before the detector can be used to implement a
frequency-dependent compression threshold. For example, assume
that the overload point of the woofer is very frequency depen-
dent. In this case, one would have to set the compressor threshold
to a value that corresponded to the most sensitive overload fre-
quency of the woofer. If the input signal happened to be mostly
in a frequency range where the woofer was not so sensitive to
overload, then the compressor would be too pessimistic and the
volume of the woofer would be reduced. If, on the other hand,
the biquad filter were designed to follow the woofer excursion
curve of the speaker, then the volume of the woofer could be
maximized under all conditions.This is illustrated in Figure 15.
incoming sampling rate. However, when the de-emphasis filter is
implemented digitally, the response will scale with the sampling
rate unless the filter coefficients are altered to suit each possible
input sampling rate. For this reason, the AD1954 includes three
separate de-emphasis curves: one each for sampling rates of
32 kHz, 44.1 kHz, and 48 kHz.These curves are selected by
writing to Bits 5 and 4 of Control Register 1 over the SPI port.
Alternatively, the 44.1 kHz curve can be called upon using the
DEEMP/SDATA_AUX pin.This pin is included for compatibility
with CD decoder chips that have a de-emphasis output pin.
Using the Sub Reinjection Paths for Systems with No Subwoofer
Many systems will not use a subwoofer but would still benefit
from two-band compression/limiting.This can be accommodated
by using sub reinjection paths in the program flow.These param-
eters are programmed by entering two numbers (in 2.20 format)
into the parameter RAM. Note that if the biquad filters are not
properly designed, the frequency response at the crossover point
may not be flat. Many crossover filters are designed to be flat in
the sense of adding the powers together, but nonflat if the sum is
done in voltage mode.The user must take care to design an appro-
priate set of crossover filters.
20Hz
200Hz
20Hz
200Hz
FREQUENCY
FREQUENCY
Figure 15. Optimizing Woofer Loudness Using the
Subwoofer rms Biquad Filter
Interpolation Filters
The left and right channels have a 128:1 interpolation filter with
70 dB stop-band attenuation that precedes the digital
lator.This filter has a group delay of approximately 24.1875/fS
taps, where fS is the sampling rate.The sub channel does not use
an interpolation filter.The reason for this (besides saving valuable
MIPS) is that it is expected that the bandwidth of the sub output
will be limited to less than 1 kHz.With no interpolation filter, the
first image will therefore be at 43.1 kHz (which is fS
CD audio).The standard external filter used for both the main
and sub channels is a third order, single op amp filter. If the cut-
off frequency of the external subwoofer filter is 2 kHz, then there
are more than four octaves between 2 kHz and the first image
at 43.1 kHz. A third order filter will roll off by approximately
4 octaves = 72 dB attenuation.This is approximately
the same as the digital attenuation used in the main channel
filters, so no internal interpolation filter is required to remove the
out-of-band images.
When using a filter in front of the detector, a confusing side effect
occurs. If one measures the frequency response by using a swept
sine wave with an amplitude large enough to be above the com-
pressor threshold, the resulting frequency response will not look
flat. However, this is not real in the sense that, as the sine wave is
swept through the system, the gain is being slowly modulated up
and down according to the response of the biquad filter in front of
the detector. If one measures the response using a pink noise gen-
erator, the result will look much better, since the detector will settle
on only one gain value.The perceptual effect of the swept sine wave
test is not at all what would be predicted by simply looking at the
frequency response curve; it is only the signal path filters that will
affect the perception of the frequency response, not the detector
path filters.
De-emphasis Filtering
The standard for encoding CDs allows the use of a pre-emphasis
curve during encoding, which must be compensated for by a
de-emphasis curve during playback. The de-emphasis curve
is defined as a first order shelving filter with a single pole at
(1/(2 50 µs)) followed by a single zero at (1/(2 15 µs)).
This curve may be accurately modeled using a first order digital
filter. This filter is included in the AD1954; it is not part of the
bank of biquad filters and so does not take away from the num-
Note that by having interpolation filters in the main channels
but not the subwoofer channel, there is a potential time-delay
mismatch between the main and sub channels. The group delay
of the digital interpolation filters used in the main left/right
channels is about 0.5 ms. This must be compared to the group
delay of the external analog filter used in the subwoofer path. If
the group-delay mismatch causes a frequency response error
(when the two signals are acoustically added), then the pro-
grammable delay feature can be used to put extra delay in either
the subwoofer path or the main left/right path.
Since the specification of the de-emphasis filter is based on an
analog filter, the response of the filter should not depend on the
REV. A
bit is low for a write and high for a read operation.
of the two memories (parameter or program) or one of the SPI
registers.The number of data bytes varies according to the regis-
ter or memory being accessed. In burst-write mode (available for
loading the RAMs only), an initial address is given followed by a
continuous sequence of data for consecutive RAM locations.The
detailed data format diagram for continuous-mode operation is
given in SPI read/write data formats.
The AD1954 has many different control options. Most signal
processing parameters are controlled by writing new values to
the parameter RAM using the SPI port. Other functions, such as
volume and de-emphasis filtering, are programmed by writing to
the SPI control registers.
The SPI port uses a 4-wire interface, consisting of CLATCH,
CCLK, CDATA, and COUT signals.The CLATCH signal goes
low at the beginning of a transaction and high at the end of a
transaction.The CCLK signal latches the serial input data on a
low-to-high transition.The CDATA signal carries the serial input
data, and the COUT signal is the serial output data.The COUT
signal remains three-stated until a read operation is requested.
This allows other SPI compatible peripherals to share the same
A sample timing diagram for a single SPI write operation to the
parameter RAM is shown in Figure 16.
A sample timing diagram of a single SPI read operation is shown
in Figure 17.The COUT pin goes from three-state to driven at
the beginning of Byte 2. Bytes 0 and 1 contain the address and
bit, and Bytes 2 through 4 carry the data.The exact format
The SPI port is capable of full read/write operation for all of the
memories (parameter and program) and some of the SPI registers
(Control Register 1 and the data capture registers).The memories
may be accessed in both a single address mode or in burst mode.
The AD1954 has several mechanisms for updating signal-processing
parameters in real time without causing loud pops or clicks. In
cases where large blocks of data need to be downloaded, the DSP
core can be shut down and new data loaded, and then the core
can be restarted.The shutdown and restart mechanisms employ a
gradual volume ramp to prevent clicks and pops. In cases where
only a few parameters need to be changed (e.g., a single biquad
filter), a safeload mechanism is used, which allows a block of SPI
registers to be transferred to the parameter RAM within a single
audio frame while the core is running.The safeload mode uses
internal logic to prevent contention between the DSP core and
the SPI port.
Byte 0
Byte 1
Byte 2 Byte 3 Byte 4
, Addr[9:8]
CLATCH
CCLK
BYTE 0
BYTE 1
BYTE 4
CDATA
Figure 16. Sample of SPI Write Format (Single-Write Mode)
CLATCH
CCLK
BYTE 1
XXX
BYTE 0
CDATA
COUT
HI-Z
HI-Z
DATA
DATA
DATA
REV. A
Table II. SPI Port Address Decoding
Read/WriteWord Length
Register Name
SPI Control Register 1
SPI Control Register 2
Volume Right
Data Capture (SPI Out) #1
Data Capture (SPI Out) #2
Data Capture (Serial Out) Left
Data Capture (Serial Out) Right
Parameter RAM Safe Load Register 0
Parameter RAM Safe Load Register 1
Parameter RAM Safe Load Register 2
Parameter RAM Safe Load Register 3
Parameter RAM Safe Load Register 4
Write: 9-Bit Program CounterValue, 2-Bit Register Address
Write: 9-Bit Program CounterValue, 2-Bit Register Address
Write: 9-Bit Program CounterValue, 2-Bit Register Address
Write: 9-Bit Program CounterValue, 2-Bit Register Address
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Test Register
Program RAM
SPI Address Decoding
Bits 3:2 select one of four serial modes, which are discussed in
the Serial Data Input Port section.
Table II shows the address decoding used in the SPI port.The
SPI address space encompasses a set a registers and two RAMs,
one for holding signal processing parameters and one for hold-
ing the program instructions. Both of the RAMs are loaded on
power-up from on-board boot ROMs.
The de-emphasis curve selection Bits 5:4 turn on the internal
de-emphasis filter for one of three possible sample rates.
Bit 6, the soft power-down bit, stops the internal clocks to the DSP
core, but does not reset the part.The digital power consumption
is reduced to a low level when this bit is asserted. Reset can only
be asserted using the external reset pin.
Control Register 1
Control Register 1 is an 11-bit register that controls data capture,
serial modes, de-emphasis, mute, power-down, and SPI-to-
memory transfers.Table III documents the contents of this register.
Table IV details the two bits in the register’s read operation.
Soft mute (Bit 7) is used to initiate a volume ramp-down sequence.
If the initial volume was set to 1.0, this operation will take 512
audio frames to complete.When this bit is de-asserted, a ramp-up
sequence is initiated until the volume returns to its original setting.
Bits 1:0 set the word length, which is used in right-justified serial
When set, Bit 8 enables the DCSOUT pin.This must be set in
order to read from the data capture serial out registers.
REV. A
TableV. Control Register 2Write Definition
The initiate-safe-transfer Bit 9 will request a data transfer from
the SPI safeload registers to the parameter RAM.The safeload
registers contain address-data pairs, and only those registers
that have been written to since the last transfer operation will be
uploaded.The user may poll for this operation to complete by
reading Bit 0 of Control Register 1.The Safeload Mechanism
section goes into more detail on this feature.
Register Bits
Volume Ramp Speed
1 = 160 ms Full RampTime
0 = 20 ms Full RampTime
Serial Port Output Enable
Serial Port Input Select
Bit 10, the halt program bit, is used to initiate a volume ramp-down
followed by a shutdown of the DSP core.The user may poll for
this operation to complete by reading Bit 1 of Control Register 1.
MCLK Input Select
Bit 11 sets the function of the de-emphasis/auxiliary serial input
pin.When this bit is set to 1, the pin will function as an auxiliary
serial input that is clocked by the input mux’s selected clocks.
When set to 0, this pin enables the 44.1 kHz de-emphasis curve.
Table III. Control Register 1Write Definition
MCLK in Frequency Select
S
S
MCLK Out Frequency Select
S
S
Register Bits
De-emphasis/Auxiliary Serial Input Pin Select
(1 = Auxiliary Serial Input)
Halt Program (1 = Halt)
Initiate SafeTransfer (1 =Transfer)
Enable DCSOUT Output Pin (1 = Enable)
Soft Mute (1 = Start Mute Sequence)
Soft Power-Down (1 = Power-Down)
De-emphasis Curve Select
11 = MCLK_Out = MCLK_In (Feedthrough)
Control Register 2
TableV documents the contents of Control Register 2. Bits 1 and 0
set the frequency of the MCLKOUT pin. If these bits are set to
00, then the MCLKOUT pin is disabled (default).When set to
01, the MCLKOUT pin is set to 512 S, which is the same as
the internal master clock used by the DSP core.When set to 10,
this pin is set to 256 S, derived by dividing the internal DSP
clock by 2. In this mode, the output 256 fS
with respect to the input 256 fS
feedthrough mode.When set to 11, the MCLKOUT pin mirrors
the selected MCLK input pin (it’s the output of the MCLK mux
selector). Note that the internal DSP master clock may either be
the same as the selected MCLK pin (when MCLK frequency
S mode) or may be derived from the MCLK
pin using an internal clock doubler (when MCLK frequency
S).
2
01 = Right-Justified
11 = Left-Justified
Word Length
Table IV. Control Register 1 Read Definition
Register Bits
Bit 2 selects one of two possible MCLK input frequencies.When
set to 0 (default), the MCLK frequency is set to 512 S
mode, the internal DSP clock and the external MCLK are at the
same frequency.When set to 1, the MCLK frequency is set to
S, and an internal clock doubler is used to generate the
DSP Core Shutdown Complete
1 = Shutdown Complete
Safe Memory Load Complete
1 = Complete (Note: Cleared after Read)
0 = Not Complete
Bits 5 and 4 select one of three clock input sources using an inter-
nal mux.To avoid click and pop noises when switching MCLK
sources, it is recommended that the user put the DSP core in
shutdown before switching MCLK sources.
Bit 0 is asserted when all requested safeload registers have been
transferred to the parameter RAM. It is cleared after the read
operation is complete.
Bit 1 is asserted after the requested shutdown of the DSP is com-
pleted.When this bit is set, the user is free to write or read any
RAM location without causing an audio pop or click.
Bits 7 and 6 select one of three serial input sources using an
internal mux. Each source selection includes a separate SDATA,
LRCLK, and BCLK input.To avoid click and pop noises when
switching serial sources, it is recommended that the user put the
DSP core in shutdown before writing to these bits.
REV. A
Bit 8 is used to enable the three serial output pins.These pins are
connected to the output of the serial input mux, which is set by
Bits 7 and 6.The default is 0 (disabled).
RAMs. Since the RAMs are also being used during real-time
DSP operation, a glitch will likely occur at the output.This
Bit 9 changes the default setting of the volume ramp speed.When
set to 0, it will take 1024 LRCLK periods to go from full volume
(6 dB) to infinite attention.When set to 1, the same operation
will take 8192 LRCLK periods.
the glitch while accessing the internal RAMs by first shutting
down the core.This is recommended for transferring large
amounts of data, such as initializing the parameter RAM at
power-up or downloading a completely new program.These
transfers can be sped up by using burst mode, where an initial
address followed by blocks of data are sent to the RAM.
Volume Registers
The AD1954 contains three 22-bit volume registers: one each for
the left, right, and subwoofer channels.These registers are special
because when the volume is changed from an initial value to a
new value, a linear ramp is used to interpolate between the two
values.This feature prevents audible clicks and pops when chang-
ing volume.The ramp is set so that it takes 512 audio frames to
decrement from a volume of 1.0 (default) down to 0 (muted).
The volume registers are formatted in 2.20 twos complement,
meaning that 0100000000000000000000 is interpreted as 1.0.
Negative values can also be written to the volume register, caus-
ing an inversion of the signal. Negative values work as expected
with the ramp feature; to go from +1.0 to –1.0 will take 1024
LRCLKs, and the volume will pass through 0 on the way.
3. Safeload writes.This is where up to five SPI registers are loaded
with address/data intended for the parameter RAM.The data
is then transferred to the requested address when the RAM is
not busy.This method can be used for dynamic updates while
live program material is playing through the AD1954. For
example, a complete update of one biquad section can occur in
one audio frame while the RAM is not busy.This method is not
available for writing to the program RAM or control registers.
The next section discusses these options in more detail.
Soft Shutdown Mechanism
Parameter RAM Contents
When writing large amounts of data to the program or parameter
RAM, the processor core should be halted to prevent unpleasant
noises from appearing at the audio output. Figure 18 shows a
graphical representation of this mechanism’s volume envelope.
Points A through D are referenced in the following description.
Bit 10 in Serial Control Register 0 (processor shutdown bit) will
shut down the processor core.When the processor shutdown bit
is asserted (A), an automatic volume ramp-down sequence
(B) lasting from 10 ms to 20 ms will occur, followed by a shut-
down of the core.This method of shutting down the core
prevents pops or clicks from occurring. After the shutdown is
complete, Bit 1 in Control Register 1 will be set.The user can
either poll for this bit to be set or just wait for a period longer
TableVI shows the contents of the parameter RAM for the AD1954’s
default program.The parameter RAM is 22 bits wide and occupies
SPI Addresses 0 through 255.The low addresses of the RAM are
used to control the biquad filters.There are 22 biquad filters in all,
and each biquad has five coefficients, resulting in a total memory
usage of 110 coefficients.There are also two tables of 33 coeffi-
cients, each that define the main and subcompressor input/output
characteristics.These are loaded with 1.0 on power-up, resulting
in no compression. Other RAM entries control other compressor
characteristics, as well as delay and spatialization settings.
The parameter RAM is initialized on power-up by an on-board
boot ROM.The default values yield no equalization, no com-
pression, no spatialization, no delay, and normal detector time
constants in the compressor sections.The functionality of the
AD1954 on power-up is basically that of a normal audio DAC
with no signal processing capability.
Once the core is shut down (C), the parameter or program RAMs
may be written or read freely.To facilitate the transfer of large
blocks of sequential data, a block transfer mode is supported
where a starting address followed by a stream of data is sent to the
memory.The address into the memory will be automatically
The data format of the parameter RAM is twos complement
2.20 format.This means that the coefficients may range from
+2.0 (–1 LSB) to –2.0, with 1.0 represented by the binary word
Options for Parameter Updates
The parameter and program RAMs can be written and read using
Once the data has been written, the shutdown bit can be cleared
(D).The processor then will initiate a volume ramp-up sequence
A
B
C
D
Figure 18. Recommended Sequences for Complete Parameter or Program RAM Uploaded Using Shutdown Mechanism
REV. A
TableVI. Parameter RAM Contents—Default Program
IIR3 Right a2
Main Compressor
Look-UpTable Base
Main Compressor
Compressor Gain
IIR4 Right b0
IIR4 Right b1
IIR4 Right b2
IIR4 Right a1
IIR4 Right a2
IIR5 Right b0
IIR5 Right b1
IIR5 Right b2
IIR5 Right a1
IIR5 Right a2
IIR6 Right b0
IIR6 Right b1
IIR6 Right b2
IIR6 Right a1
IIR6 Right a2
1.0 (all)
4
(120 dB/sec)
Compressor
Look-UpTable Base
Sub Compressor
Post-Compressor
Gain (Sub)
High-Pass Filter
Cutoff Frequency
Main Compressor
Look-Ahead Delay
Delay Left
Delay Right
Delay Sub
Stereo Spreading
Stereo Spreading
Frequency Control
4
(120 dB/sec)
IIR0 Xover Right b0
IIR0 Xover Right b1
IIR0 Xover Right b2
IIR0 Xover Right a1
IIR0 Xover Right a2
Reinjection
Reinjection
IIR1 Xover Right b0
IIR1 Xover Right b1
IIR1 Xover Right b2
IIR1 Xover Right a1
IIR1 Xover Right a2
to Main Right
Input Gain from
IIR0 Right b0
IIR0 Right b1
IIR0 Right b2
IIR0 Right a1
IIR0 Right a2
Input Gain from
Right In
IIR1 Right b0
1
Time, Samples
IIR1 Right b1
IIR1 Right b2
IIR1 Right a1
IIR1 Right a2
(4095 Max)
Time, Samples
(4095 Max)
DecayTime
DecayTime
1
IIR2 Right b0
IIR2 Right b1
IIR2 Right b2
IIR2 Right a1
IIR2 Right a2
(10000 dB/sec)2
(10000 dB/sec)2
IIR3 Right b0
IIR3 Right b1
IIR3 Right b2
IIR3 Right a1
NOTES
1The detector hold and decay times are integer values, while the rest of the parameters are fractional twos complement values.
2The default decay time of the hold/release circuit is set fast enough so that the decay is dominated by the time constant of the rms detector.
REV. A
that lasts for 10 ms to 20 ms. Again, this reduces the chance of
any pop or click noise from occurring.
example, if only two parameters are to be sent, then it is neces-
sary to write to only two of the five safeload registers.When the
request safe transfer bit is asserted, only those two registers will
be sent; the other three registers are not sent and can still hold
Note that this shutdown sequence assumes that the part is set
to the fast volume ramp speed (Control Register 2, Bit 9). If the
slow ramp speed is set, the volume may not reach zero before the
part enters shutdown and a click or pop may be heard.
The safeload mechanism is not limited to uploading biquad
coefficients; any set of five values in the parameter RAM may be
updated in the same way.This allows real-time adjustment of the
compressor/limiter, delay, or stereo spreading blocks.
Safeload Mechanism
Many applications require real-time control of filter characteristics,
such as bass/treble controls and parametric or graphic equalization.
To prevent instability from occurring, all of the parameters of a
particular biquad filter must be updated at the same time; other-
wise, the filter could execute for one or two audio frames with a
could cause temporary instability, leading to transients that could
take a long time to decay.
Summary of RAM Modes
TableVII shows the sizes and available modes of the parameter
RAM and the program RAM.
SPI READ/WRITE DATA FORMATS
The read/write formats of the SPI port are designed to be byte-
oriented.This allows for easy programming of common microcon-
troller chips.To fit into a byte-oriented format, 0s are appended
to the data fields to extend the data-word to the next multiple of
8 bits. For example, 22-bit words written to the SPI parameter
RAM are appended with two leading zeroes to reach 24 bits
(3 bytes), and 35-bit words written to the program RAM are
appended with five zeros to reach 40 bits (5 bytes).These zero-
extended data fields are appended to a 2-byte field consisting of a
read/write bit and a 10-bit address.The SPI port knows how many
data bytes to expect based on the address that is received in the
first two bytes.
The method used in the AD1954 to eliminate this problem is to
load a set of five registers in the SPI port with the desired param-
eter RAM address and data. Five registers are used because each
biquad filter has five coefficients. Once these registers are loaded,
the initiate safe transfer bit in Control Register 1 should be set.
Once this bit is set, the processor waits for a period of time in
the program sequence where the parameter RAM is not being
accessed for at least five consecutive instruction cycles.When the
program counter reaches this point, the parameter RAM is writ-
ten with five new data values at addresses corresponding to those
that were entered in the safeload registers.When the operation is
complete, Bit 0 of Control Register 1 (read) is set.This bit may
be polled by the external microprocessor until a 1 is read and
will be reset on a read operation.The polling operation is not
required; the safeload mechanism guarantees that the transfer will
be complete within one audio frame.
The total number of bytes for a single-location SPI write command
can vary from 4 bytes (for a control register write) to 7 bytes (for
a program RAM write). Block writes may be used to fill contiguous
locations in program RAM or parameter RAM.
The read and write formats of the parameter RAM, program RAM
and registers are detailed inTablesVIII to XIX.
The safeload logic automatically sends only those safeload registers
that have been written to since the last safeload operation. For
Range
Memory
Direct write, write after core shutdown, safeload write
Direct write, write after core shutdown
Program RAM
TableVIII. Parameter RAM Read/Write Format (Single Address)
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
, Addr[9:8]
Addr[7:0]
00, Param[21:16]
Param[15:8]
Param[7:0]
Table IX. Parameter RAM Block Read/Write Format (Burst Moded)
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9
Byte 10
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
, Addr[9:8]
Addr[7:0]
00, Param[21:16]
Param[15:8]
Param[7:0]
Table X. Program RAM Read/Write Format (Single Address)
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Prog[15:8]
Byte 6
, Addr[9:8]
Addr[7:0]
00000, Prog[34:32]
Prog[31:24]
Prog[23:16]
Prog[7:0]
REV. A
Byte 7
Byte 8
Byte 9
Byte 10
Byte 11
Byte 12
Byte 13
Byte 14
Byte 15
Byte 16
Table XI. Program RAM Read/Write Format (Burst Address)
Byte 2 Byte 3 Byte 4 Byte 5 Byte 6
Byte 0
Byte 1
, Addr[9:8] Addr[7:0] 00000, Prog[34:32] Prog[31:24] Prog[23:16] Prog[15:8] Prog[7:0]
Table XII. SPI Control Register 1Write Format
Byte 0
Byte 1
Byte 2
Byte 3
, Addr[9:8]
Addr[7:0]
0000, Bit[11:8]
Bit[7:0]
Table XIII. SPI Control Register 1 Read Format
Byte 0
Byte 1
Byte 2
, Addr[9:8]
Addr[7:0]
000000, Bit[1:0]
Table XIV. SPI Control Register 2Write Format
Byte 0
Byte 1
Addr[7:0]
Byte 2
Byte 3
, Addr[9:8]
000000, Bit[9:8]
Bit[7:0]
Volume RegisterWrite Format
Byte 0
Byte 1
Byte 2
Byte 3
Volume[15:8]
Byte 4
000000, Addr[9:8]
Addr[7:0]
00,Volume[21:16]
Volume[7:0]
Table XVI. Data Capture RegisterWrite Format
Byte 2
Byte 0
Byte 1
Addr[7:0]
Byte 3
ProgCount[5:0], RegSel[1:0]1, 2
, Addr[9:8]
00000, ProgCount[8:6]1
1ProgCount[8:0] = value of program counter where trap occurs (seeTable XX).
2RegSel[1:0] selects one of four registers (see Data Capture Register section).
Table XVII. Data Capture Serial Out Register (Address and Register Select)Write Format
Byte 0
Byte 1
Byte 2
Byte 3
, Addr[9:8]
Addr[7:0]
00000, ProgCount[8:6]1
ProgCount[5:0], RegSel[1:0]1, 2
1ProgCount[8:0] = value of program counter where trap occurs (seeTable XX).
2RegSel[1:0] selects one of four registers (see Data Capture Register section).
Table XVIII. Data Capture Read Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
, Addr[9:8]
Addr[7:0]
Data[23:16]
Data[15:8]
Data[7:0]
Table XIX. Safeload RegisterWrite Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
, Addr[9:8]
Addr[7:0]
ParamAddr[7:0]
00, Param[21:16]
Param[15:8]
Param[7:0]
REV. A
Setting the Data and MCLK Input Selectors
Power-Up Sequence
The AD1954 contains input selectors for both serial data inputs
and the MCLK input.This allows the AD1954 to select a variety
of input and clock sources with no external hardware required.
These input selectors are controlled by writing to SPI Control
Register 2.
The AD1954 has a built-in power-up sequence that initializes the
contents of the internal RAMs. During this time, the contents
of the internal program boot ROM are copied to the internal
program RAM memory, and likewise, the SPI parameter RAM is
ries are also cleared during this time.
When the data source or MCLK source is changed by writing
to the SPI port, it is possible that a pop or click will occur in the
audio.To prevent this noise, the core should be shut down by
writing a 1 to the halt program bit in Control Register 1.This
initiates a volume ramp-down sequence followed by a shutdown
of the DSP core. Once the core is shut down (which can be veri-
fied by reading Bit 1 from Control Register 1 or by waiting at
least 20 ms after the halt program command is issued), the new
data or MCLK source can be programmed by writing to Control
Register 2.The DSP core can then be restarted by clearing the
halt program bit in Control Register 1.
The boot sequence lasts for 1024 MCLK cycles and starts on the
rising edge of the RESETB pin. Since the boot sequence requires
a stable master clock, the user should avoid writing to or reading
from the SPI registers during this period of time. Note that the
default power-on state of the internal clock mode circuitry is 512
S, or about 24 MHz for normal audio sample rates.This mode
bypasses all the internal clock doublers and allows the external
master clock to directly operate the DSP core. If the external
S, then the boot sequence will operate at
this reduced clock rate and will take slightly longer to complete.
After the boot sequence has finished, the clock modes may be
set via the SPI port. For example, if the external master clock
frequency is 256 S clock, the boot sequence would take 1024
S clock cycles to complete, after which an SPI write could
occur to put the AD1954 in 256 S
The AD1954 incorporates a feature called data capture. Using
this feature, any node in the signal processing flow may be sent
to either an SPI readable register or a dedicated serial output
pin.This allows the basic functionality of the AD1954 to be
extended to a larger number of channels. Alternatively, it can be
used to monitor and display information about signal levels or
compressor/limiter activity.
The default state of the MCLK input selector is MCLK0. Since
this input selector is controlled using the SPI port, and the SPI port
cannot be written to until the boot sequence is complete, there
must be a stable master clock signal present on the MCLK0 pin at
startup.
The AD1954 contains four independent data capture registers.
Two of these registers transfer their data to the data capture serial
output (DCSOUT) pin.The serial data format of this pin is the
same as the serial data format used for the main digital inputs,
and the LRCLK and BCLK signals can therefore be used as
frame sync and bit clock signals.This pin is primarily intended
to feed signals to an external DAC or DSP chip to extend the
two registers may be read back over the SPI port and can be used
for a variety of purposes. One example might be to access the dB
output of the internal rms detector to run a front-panel signal
level display. A sample system is shown in Figure 19. For each
of the four data capture registers, a capture count and a register
select must be set.The capture count is a number between 0 and
511 that corresponds to the program step number where the
capture will occur.The register select field programs one of four
registers in the DSP core that will be transferred to the data cap-
ture register when the program counter equals the capture count.
The register select field is decoded as follows:
Setting the Clock Mode
The AD1954 contains a clock doubler circuit that is used to gener-
S S
The clock mode is set by writing to Bit 2 of Control Register 2.
When the clock mode is changed, it is possible that a glitch will
occur on the internal MCLK signal.This may cause the proces-
sor to inadvertently write an incorrect value into the data RAM,
which could cause an audio pop or click sound.To prevent this
the following procedure is recommended:
1. Assert the soft power-down bit (Bit 6 in Control Register 1) to
stop the internal MCLK.
2. Write the desired clock mode into Bit 2 of Control Register 2.
4. De-assert the soft power-down bit.
An alternative procedure is to initiate a soft shutdown of the pro-
cessor core by writing a 1 to the halt program bit in Control
Register 1.This initiates a volume ramp-down sequence followed
by a shutdown of the DSP core. Once the core is shut down (which
can be verified by reading Bit 1 from Control Register 1 or by
waiting at least 20 ms), the new clock mode can be programmed
by writing to Bit 2 of Control Register 2.The DSP core can then
be restarted by clearing the halt program bit in Control Register 1.
00: Multiplier Output (Mult_Out)
01: Output of dB Conversion Block (DB_OUT)
10: Multiplier Data Input (MDI)
11: Multiplier Coefficient Input (MCI)
The capture count and register select bits are set by writing to one
of the four data capture registers at the following SPI addresses:
261: SPI Data Capture Setup Register 1
262: SPI Data Capture Setup Register 2
263: Data Capture Serial Out Setup Register 1
264: Data Capture Serial Out Setup Register 2
REV. A
The format of the captured data varies according to the register
select fields. Data captured from the mult_out setting is in 1.23
twos complement format so that a full-scale input signal will
produce a full-scale digital output (assuming no processing). If
the parameters are set such that the input-to-output gain is more
than 0 dB, then the digital output will be clipped.
The SPI capture registers can be accessed by reading from SPI
Locations 261 (for SPI Capture Register 1) or 262 (for SPI Cap-
ture Register 2).The other two data capture registers (data capture
serial out) automatically transfer their data to the data capture
serial out (DCSOUT) pin. DCSOUT Capture Register 1 is pres-
ent in the left data slot (as defined by the serial input format), and
DCSOUT Capture Register 2 is present in the right data slot.The
format for writing to the SPI data capture setup registers is given
Data captured from the DB_OUT setting is in 5.19 format, where
the actual rms dB level is equal to –87 + (3 DB_OUT). In this
equation, DB_OUT is the value that is captured. It follows that in
this data format, the actual output readings will range from –87 dB
value of the full-scale digital signal.
dB LEVEL METERS
LRCLK
EXT DACs
BCLK
Data captured using the MDI setting is in 3.21 format. A 0 dB
digital input will produce a –12 dB digital output, assuming the
AD1954 is set for no processing.
Data captured using the MCI setting is in 2.20 format.This data
is generally a signal gain or filter coefficient, and therefore it does
not make sense to talk about the input-to-output gain. A coeffi-
cient of 01000000000000000000 corresponds to a gain of 1.0.
DCSOUT
5.1
CHANNEL
OUTPUT
The data that must be written to set up the data capture is a
concatenation of the 9-bit program count index with the 2-bit
register select field. Refer toTable XX to find the capture count
and register select numbers that correspond to the desired point
to be monitored in the default signal processing flow.
MICRO-
CONTROLLER
AD1954
Figure 19. Typical Application of Data Capture Feature
REV. A
Table XX. Data CaptureTrap Indexes and Register Select—Default Program
Program Count
Index (9 Bits)
Register
Select (2 Bits)
Signal Description
HPF Out Right
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
DB_Out
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
24-Bit Positive Binary, Bit 19
Corresponds to a 3 dB Change
2.22, 2 LSBs = 0
De-emphasis Out Left
De-emphasis Out Right
Left Biquad 0 Output
Left Biquad 1 Output
Left Biquad 2 Output
Left Biquad 3 Output
Left Biquad 4 Output
Left Biquad 5 Output
Left Biquad 6 Output
Right Biquad 0 Output
Right Biquad 1 Output
Right Biquad 2 Output
Right Biquad 3 Output
Right Biquad 4 Output
Right Biquad 5 Output
Right Biquad 6 Output
Volume Out Right
Phat Stereo Out Right
Delay Output Left
Delay Output Right
Main Compressor rms Out (dB)
Main Compressor Gain Reduction
(Linear)
Look-Ahead Delay Output Left
Look-Ahead Delay Output Right
Main Compressor Out Left
Main Compressor Out Right
Interpolator Input Left
Mult_Out
Mult_Out
Mult_Out
3.21, 2 LSBsTruncated
3.21, 2 LSBsTruncated
1.23, Clipped
1.23, Clipped
1.23, Clipped
(Includes Sub Reinject)
Interpolator Input Right
(Includes Sub Reinject)
Mult_Out
1.23, Clipped
Subchannel Filter Input
Sub Xover Biquad 0 Output
Sub Xover Biquad 1 Output
Sub Xover Biquad 2 Output
Left Xover Biquad 0 Output
Left Xover Biquad 1 Output
Right Xover Biquad 0 Output
Right Xover Biquad 1 Output
Sub Delay Output
99
108
349
358
511
467
489
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
DB_Out
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
24-Bit Positive Binary, Bit 19
Corresponds to a 3 dB Change
2.22, 2 LSBs = 0
1.23, Clipped
Sub rms Biquad Output
Sub rms Output (dB)
Sub Compressor Gain (Linear)
Subchannel Output
495
511
MCI
Mult_Out
REV. A
LRCLK
BCLK
RIGHT CHANNEL
LEFT CHANNEL
SDATA
MSB
LSB
MSB
LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL
LSB
LRCLK
BCLK
SDATA
LSB
I S MODE – 16 BITS TO 24 BITS PER CHANNEL
LSB
MSB
MSB
2
RIGHT CHANNEL
LRCLK
BCLK
LEFT CHANNEL
SDATA
LSB
MSB
MSB
LSB
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
SDATA
LSB
LSB
MSB
MSB
DSP MODE – 16 BITS TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOESN’T IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT DSP MODE, WHICH IS 2 fS.
3. BCLK FREQUENCY IS NORMALLY 64 LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 20. Serial Input Modes
clock period before the MSB of the right channel is valid. Data is
sampled on the falling edge of BCLK.The DSP serial port mode
can be used with any word length up to 24 bits. In this mode,
it is the responsibility of the DSP to ensure that the left data is
transmitted with the first LRCLK pulse and that synchronism is
maintained from that point forward.
The AD1954’s flexible serial data input port accepts data in twos
complement, MSB first format.The left channel data field always
precedes the right channel data field.The serial mode is set by
using mode select bits in the SPI control register. In all modes
except for the right-justified mode, the serial port will accept an
arbitrary number of bits up to a limit of 24 (extra bits will not
cause an error, but they will be truncated internally). In the right-
justified mode, SPI control register bits are used to set the word
length to 16 bits, 20 bits, or 24 bits.The default on power-up is
24-bit mode. Proper operation of the right-justified mode requires
exactly 64 BCLKs per audio frame.
DIGITAL CONTROL PINS
Mute
The AD1954 offers two methods of muting the analog output.
By asserting the mute signal high, the left, right, and subchan-
nels are muted. As an alternative, the user can assert the mute
bit in the serial control register high. The AD1954 has been
designed to minimize pops and clicks when muting and unmut-
ing the device by automatically ramping the gain up or down.
When the device is unmuted, the volume returns to the value
set in the volume register.
Serial Data Input Modes
Figure 20 shows the serial input modes. For the left-justified
mode, LRCLK is high for the left channel and low for the right
channel. Data is sampled on the rising edge of BCLK.The MSB
is left-justified to an LRCLK transition, with no MSB delay.The
left-justified mode can accept any word length up to 24 bits.
De-emphasis
The AD1954 has a built-in de-emphasis filter that can be used to
50 µs/15 µs emphasis response curve.This feature may be acti-
vated by the pin or by an SPI write to the control register.When
activating with the pin, only the 44.1 kHz sample rate curve is
available.When using the SPI port, curves for 44.1 kHz, 32 kHz,
and 48 kHz are supported.
2S mode, LRCLK is low for the left channel and high for
the right channel. Data is valid on the rising edge of BCLK.The
MSB is left-justified to an LRCLK transition but with a single
BCLK period delay.The I2S mode can be used to accept any
number of bits up to 24.
In right-justified mode, LRCLK is high for the left channel and low
for the right channel. Data is sampled on the rising edge of BCLK.
The start of data is delayed from the LRCLK edge by 16 BCLK,
12 BCLK, or 8 BCLK intervals, depending on the selected word
length.The default word length is 24 bits; other word lengths are set
by writing to Bits 1 and 0 of Control Register 1. In right-justified
mode, it is assumed that there are 64 BCLKs per frame.
For the DSP serial port mode, LRCLK must pulse high for at
least one bit clock period before the MSB of the left channel
is valid, and LRCLK must pulse high again for at least one bit
REV. A
3.01k
1.50k
270pF
Figure 21 shows the block diagram of the analog output section.
A series of current sources are controlled by a digital
lator. Depending on the digital code from the modulator, each
current source is connected to the summing junction of either a
positive I-to-V converter or a negative I-to-V converter.Two extra
current sources that push instead of pull are added to set the
midscale common-mode voltage.
2.80k
1nF
– INPUT
+ INPUT
549
OUT
2.7nF
806
2.2nF
499
820pF
1.00k
Figure 22. Recommended External Analog Filter
for Main Channel
I
I
REF
REF
11k
6.8nF
68pF
11k
3.01k
– INPUT
+ INPUT
OUT+
OUT–
270nF
27nF
56nF
604
VREF IN
OUT
560nF
2.2nF
I
+ DIG_IN
I
– DIG_IN
220nF
REF
REF
BIAS
5.62k
1.5k
15nF
150pF
5.62k
FROM DIGITAL
SWITCHED CURRENT
SOURCES
- MODULATOR
(DIG_IN)
Figure 23. Recommended External Analog Filter
for Subchannel
Figure 21. Internal DAC Analog Architecture
The lower frequency filter is used on the subwoofer output because
there is no digital interpolation filter used in the subwoofer signal
path.When calculating the resistor values for the filter, it is impor-
tant to take into account the output resistance of the AD1954,
which is nominally 60 . For best distortion performance, 1% resis-
tors should be used.The reason for this is that the single-ended
performance of the AD1954 is about 80 dB.The degree to which
the single-ended distortion cancels in the final output is determined
by the common-mode rejection of the external analog filter, which in
turn depends on the tolerance of the components used in the filter.
All current sources are derived from theVREF input pin.The
gain of the AD1954 is directly proportional to the magnitude of
the current sources, and therefore the gain of the AD1954 is pro-
portional to the voltage on theVREF pin.WithVREF set to 2.5V,
the gain of the AD1954 is set to provide signal swings of 2V rms
differential (1V rms from each pin).This is the recommended
operating condition.
When the AD1954 is used to drive an audio power amplifier and
the compression feature is being used, theVREF voltage should
then be derived by dividing down the supply of the amplifier.
This sets a fixed relationship between the digital signal level
(which is the only information available to the digital compres-
sor) and the full-scale output of the amplifier (just prior to the
onset of clipping). For example, if the amplifier power supply
drops by 10%, then theVREF input to the amplifier will also
drop by 10%, which will reduce the analog output signal swing
by 10%.The compressor will therefore be effective in preventing
clipping, regardless of any variation in amplifier supply voltage.
The sub output of the AD1954 has a lower drive strength than
the left and right output pins (±0.25 mA peak versus ±0.5 mA
peak for the left and right outputs). For this reason, it is best to
use higher resistor values in the external sub filter.
Figure 24 shows a recommended filter design for the subwoofer
pins used as a full bandwidth channel in a custom designed pro-
gram.This design is also a 100 kHz Bessel filter.
11k
68pF
Since theVREF input effectively multiplies the signal, care must
be taken to ensure that no ac signals appear on this pin.This
can be accomplished by using a large decoupling capacitor in
theVREF external resistive divider circuit. If theVREF signal is
derived by dividing the 5V analog supply, then the time constant
of the divider must effectively filter any noise on the supply. If
theVREF signal is derived from an unregulated power amplifier
supply, then the time constant must be longer, since the ripple on
the amplifier supply voltage will presumably be greater than in
the case of the 5V supply.
11k
– INPUT
3.01k
27nF
604
OUT
56nF
2.2nF
1.5k
5.62k
+ INPUT
5.62k
150pF
Figure 24. Recommended External Analog Filter for
Full Bandwidth Signals on the Subchannel Output
on each output channel.The circuit shown in Figures 22, 23, and
24 combine a third order filter and a single-ended-to-differential
(Figure 22) are for a 100 kHz Bessel filter, and those used in the
subwoofer channel (Figure 23) result in a 10 kHz Bessel filter.
For best performance, a large (>10 µF) capacitor should be con-
nected between the FILTCAP pin and analog ground.This pin is
connected to an internal node in the bias generator, and by add-
ing an external capacitance to this pin, the thermal noise of the
left/right channels is minimized.The sub channel is not affected
by this connection.
REV. A
Custom programming tools are available for the AD1954 from ADI.
These graphical tools allow the user to modify the default signal
processing flow by individually placing each block (e.g., biquad
filter, Phat Stereo, dynamics processor) and connecting them in
any desired fashion.The program then creates a file that is loaded
into the AD1954’s program RAM.All of the contents of the parame-
ter RAM can also be set using these tools. For more information
on these programming tools, contact SigmaDSP@analog.com.
REV. A
3. Compute coefficients:
Cookbook Formulae for Audio EQ Biquad Coefficients
(Adapted from Robert Bristow-Johnson’s Internet Posting)
b0 = ( 1 + A )/( 1 + (/A))
cs/( 1 + (/A))
b2 = (1 – ( A))/(1 + (/A))
cs/(1 + (/A)) = –b1
a2 = –( 1 – (/A))/( 1 + (/A))
For designing a parametric EQ, follow the steps below.
Frequency
Q
4. The transfer function implemented by the AD1954 is given by:
H(Z) = (b0 + b1 Z – 2)/
(1 – a1 Z – 2)
dB_Gain
Sample_Rate
Note the inversion in sign of a1 and a2 relative to the more
the AD1954 implements the difference equation using the
2. Compute intermediate variables:
(dB_Gain/40)
Frequency/Sample_Rate
sn = sin()
cs = cos()
= sn/(2 Q)
Y(n) = a1 y(n – 1) + a2 y(n – 2) + b0 x(n)
x(n – 1) + b2 x(n – 2)
REV. A
44-Lead Metric Quad Flat Package [MQFP]
(S-44)
13.45
13.20 SQ
12.95
1.03
0.88
0.73
2.45
MAX
33
23
8
0.8
34
22
SEATING
PLANE
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
7 VIEW A
0
2.20
2.00
1.80
PIN 1
44
12
0.25 MAX
0.10 MIN
1
11
COPLANARITY
0.10
0.45
0.29
0.80
BSC
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MO-112-AB
48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
0.75
0.60
0.45
9.00 BSC
SQ
1.60
MAX
37
48
36
1
PIN 1
SEATING
PLANE
10
6
2
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
VIEW A
7
3.5
0
25
12
0.15
0.05
13
24
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
REV. A
Revision History
Page
8/03—Data Sheet changed from REV. 0 to REV. A.
Changes to ABSOLUTE MAXIMUM RATINGS
Changes to ORDERING GUIDE
Change toT
Change to Main Compressor/Limiter section
Change to Interpolation Filters section
Replaced Control Register 1 section
Changes to Control Register 2 section
Changes to Parameter RAM Contents section
Change toTableVI
Change toTa
Change toTa
Change to DATA CAPTURE REGISTERS section
Change toTable XX
Reversed Figures 22 and 23
Added Figure 24
Updated OUTLINE DIMENSIONS
REV. A
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