AD1857JRSZ [ADI]
Stereo, Single Supply 16-, 18- and 20-Bit Sigma-Delta DACs; 立体声，单电源16-， 18-和20位Σ-Δ型DAC的
| 型号： | AD1857JRSZ |
| 厂家： | 
ADI |
| 描述： | Stereo, Single Supply 16-, 18- and 20-Bit Sigma-Delta DACs |
| 文件： | 总16页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Stereo, Single Supply
16-, 18- and 20-Bit Sigma-Delta DACs
a
AD1857/AD1858
P RO D UCT O VERVIEW
FEATURES
T he AD1857/AD1858 are complete single-chip stereo digital
audio playback components. T hey each comprise an advanced
digital interpolation filter, a revolutionary “linearity-compensated”
multibit sigma-delta (∑∆) modulator with dither, a jitter-tolerant
DAC, switched capacitor and continuous time analog filters and
analog output drive circuitry. Other features include digital
de-emphasis processing and mute. T he AD1857/AD1858
support continuously variable sample rates with essentially
linear phase response, and support 50/15 µs digital de-emphasis
intended for “Redbook” 44.1 kHz sample frequency playback
from Compact Discs. T he user must provide a master clock that
is synchronous with the left/right clock at 256 or 384 times the
Low Cost, High Perform ance Stereo DACs
128 Tim es Oversam pling Interpolation Filter
Multibit ⌺⌬ Modulator w ith Triangular PDF Dither
Discrete Tim e and Continuous Tim e Analog
Reconstruction Filters
Extrem ely Low Out-of-Band Energy
Buffered Outputs w ith 2 k⍀ Output Load Drive
94 dB Dynam ic Range, –90 dB THD+N Perform ance
Digital De-em phasis and Mute
؎0.1؇C Maxim um Phase Linearity Deviation
Continuously Variable Sam ple Rate Support
Pow er-Dow n Mode
16-, 18- and 20-Bit I2S-J ustified, Left-J ustified Modes
Offered on AD1857
intended sample frequency.
T he AD1857/AD1858 have a simple but very flexible serial data
input port that allows for glueless interconnection to a variety of
ADCs, DSP chips, AES/EBU receivers and sample rate con-
verters. T he AD1857 serial data input port can be configured
in either 16-bit, 18-bit or 20-bit left-justified or I2S-justified
modes. T he AD1858 serial data input port can be configured in
either 16-bit right-justified or DSP serial port compatible modes.
T he AD1857/AD1858 accept serial audio data in MSB first,
twos-complement format. A power-down mode is offered to
minimize power consumption when the device is inactive. T he
AD1857/AD1858 operate from a single +5 V power supply.
T hey are fabricated on a single monolithic integrated circuit and
housed in 20-pin SSOP packages for operation over the
temperature range 0°C to +70°C.
Accepts 24-Bit Word
16-Bit Right-J ustified and DSP Serial Port Modes
Offered on AD1858
Single +5 V Supply
20-Pin SSOP Package
APPLICATIONS
Digital Cable TV and Direct Broadcast Satellite Set-Top
Decoder Boxes
Video Laser Disk, Video CD and CD-I Players
High Definition Televisions, Digital Audio Broadcast
Receivers
CD, CD-R, DAT, DCC and MD Players
Digital Audio Workstations, Com puter Multim edia
Products
FUNCTIO NAL BLO CK D IAGRAM
CLOCK
IN
CLOCK
MODE
DIGITAL
SUPPLY
COMMON
MODE
2
16-/18-/20-BIT
3
DIGITAL
SERIAL DATA
INTERFACE
VOLTAGE
REFERENCE
CLOCK
CIRCUIT
DATA INPUT
AD1857/AD1858
128x
INTERPOLATION
FILTER
MULTIBIT
Σ∆ MODULATOR
OUTPUT
BUFFER
ANALOG
FILTER
DAC
MUTE
SERIAL
MODE
ANALOG
OUTPUTS
128x
INTERPOLATION
FILTER
ANALOG
FILTER
MULTIBIT
Σ∆ MODULATOR
OUTPUT
BUFFER
DAC
MUTE
4
DE-EMPHASIS
MUTE
ANALOG
SUPPLY
POWER-DOWN/RESET
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
AD1857/AD1858–SPECIFICATIONS
TEST CO ND ITIO NS UNLESS O TH ERWISE NO TED
Supply Voltages (AVDD, DVDD
Ambient T emperature
)
+5.0 V
25°C
Input Clock (FMCLK
Input Signal
)
11.2896 MHz (256 × FS Mode)
1.0013 kHz
–0.5 dB Full Scale
44.1 kHz
20 Hz to 20 kHz
18 Bits
Input Sample Rate
Measurement Bandwidth
AD1857 Input Data Wordwidth
AD1858 Input Data Wordwidth
Load Capacitance
16 Bits
100 pF
Load Impedance
47 kΩ
Input Voltage HI (VIH
)
2.4 V
Input Voltage LO (VIL)
0.8 V
I2S-Justified Mode (Ref. Figure 7) for AD1857, Right-Justified Mode (Ref. Figure 8) for AD1858.
Performance of the right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Values in bold typeface are tested, all others are guaranteed, not tested.
ANALO G P ERFO RMANCE
Min
Typ
Max
Units
AD1857 Resolution
AD1858 Resolution
18
16
Bits
Bits
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No A-Weight Filter
With A-Weight Filter
91
94
–90
0.003
dB
dB
dB
%
T otal Harmonic Distortion + Noise
–85
0.006
Analog Outputs
Single-Ended Output Range (± Full Scale)
Output Impedance at Each Output Pin
Output Capacitance at Each Output Pin
Out-of-Band Energy (0.5 × FS to 100 kHz)
CMOUT
2.8
3.0
<200
3.2
V p-p
Ω
pF
dB
V
20
–72.5
2.4
2.1
2.25
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
Interchannel Crosstalk (EIAJ method)
Interchannel Phase Deviation
Mute Attenuation
±3.0
0.01
150
–120
±0.1
–100
؎7.5
؎0.2
300
%
dB
ppm/°C
dB
Degrees
dB
–100
–90
De-emphasis Gain Error
±0.1
dB
D IGITAL I/O
Min
Max
Units
Input Voltage HI (VIH
)
2.4
V
Input Voltage LO (VIL)
0.8
10
10
20
V
Input Leakage (IIH @ VIH = 2.4 V)
Input Leakage (IIL @ VIL = 0.8 V)
Input Capacitance
µA
µA
pF
REV. 0
–2–
AD1857/AD1858
D IGITAL TIMING (Guar anteed over 0°C to +70°C, AVD D = D VD D = +5.0 V ± 5%)
Min
Max
Units
tDML
tDMH
tDMP
tDML
tDMH
tDMP
tDBH
tDBL
tDBP
MCLK LO Pulse Width (256 × FS Mode)
MCLK HI Pulse Width (256 × FS Mode)
MCLK Period (256 × FS Mode)
MCLK LO Pulse Width (384 × FS Mode)
MCLK HI Pulse Width (384 × FS Mode)
MCLK Period (384 × FS Mode)
BCLK HI Pulse Width
BCLK LO Pulse Width
BCLK Period
LRCLK Setup
LRCLK Hold
35
40
88.577
25
25
59.0514
20
20
354.308
20
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDLS
tDLH
tDDS
tDDH
tPDRP
SDAT A Setup
SDAT A Hold
PD/RST LO Pulse Width
10
4 MCLK Periods
(355 ns @ 11.2896 MHz)
P O WER
Min
Typ
Max
Units
Supplies
Voltage, Analog and Digital
Analog Current
Analog Current – Power-Down
Digital Current
Digital Current – Power-Down
Dissipation
4.75
5
5.25
40
60
25
11
V
35
30
20
5
mA
µA
mA
mA
Operation – Both Supplies
Operation – Analog Supply
Operation – Digital Supply
Power-Down – Both Supplies
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
275
175
100
25
325
200
125
56
mW
mW
mW
mW
–60
–50
dB
dB
TEMP ERATURE RANGE
Min
Typ
Max
Units
Specifications Guaranteed
Functionality Guaranteed
Storage
25
°C
°C
°C
0
–55
70
125
ABSO LUTE MAXIMUM RATINGS*
Min
Typ
Max
Units
DVDD to DGND
AVDD to AGND
Digital Inputs
Analog Outputs
AGND to DGND
Reference Voltage
Soldering
–0.3
–0.3
DGND – 0.3
AGND – 0.3
–0.3
6
6
V
V
V
V
V
DVDD + 0.3
AVDD + 0.3
0.3
Indefinite Short Circuit to Ground
+300
10
°C
sec
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
REV. 0
–3–
AD1857/AD1858
P ACKAGE CH ARACTERISTICS
Min
Typ
Max
Units
θJA (T hermal Resistance [Junction-to-Ambient])
θJC (T hermal Resistance [Junction-to-Case])
195
13
°C/W
°C/W
D IGITAL FILTER CH ARACTERISTICS
Min
Max
Units
Passband Ripple
Stopband1 Attenuation
48 kHz FS
±0.045
dB
dB
62
Passband
Stopband
0
21.312
6117
kHz
kHz
26.688
44.1 kHz FS
Passband
Stopband
0
19.580
5620
kHz
kHz
24.520
32 kHz FS
Passband
Stopband
0
14.208
4078
kHz
kHz
17.792
Other FS
Passband
Stopband
Group Delay
Group Delay Variation
0
0.444
127.444
40/FS
0
FS
FS
sec
µs
0.556
ANALO G FILTER CH ARACTERISTICS
Min
Typ
Max
Units
Passband Ripple
Stopband Attenuation (at 64 × FS)
–0.075
dB
dB
58
NOT ES
1Stopband nominally repeats itself at multiples of 128 × FS, where FS is the input word rate. T hus the digital filter will attenuate to 62 dB across the frequency
spectrum, except for a range ±0.55 × FS wide at multiples of 128 × FS.
Specifications subject to change without notice.
O RD ERING GUID E
P ackage
P IN CO NFIGURATIO N
P ackage
O ption*
1
2
20
19
18
17
16
15
SDATA
BCLK
MCLK
PD/RST
MODE
NC
Model
Tem perature
D escription
3
LRCLK
AD1857JRS
0°C to +70°C
AD1857JRSRL 0°C to +70°C
20-Lead SSOP
20-Lead SSOP
RS-20
4
DV
DD
RS-20 on
13" Reels
RS-20
RS-20 on
13" Reels
AD1857
AD1858
TOP VIEW
5
DGND
MUTE
DEEMP
384/256
6
AD1858JRS 0°C to +70°C
AD1858JRSRL 0°C to +70°C
20-Lead SSOP
20-Lead SSOP
(Not to Scale)
AV
DD
14 AV
DD
7
8
13
12
OUTR
OUTL
AGND
9
AGND
*RS = Shrink Small Outline
10
11 FILT
CMOUT
NC = NO CONNECT
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1857/AD1858 feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. T herefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD1857/AD1858
P IN LIST
D igital Audio Ser ial Input Inter faces
P in Nam e
Num ber
I/O
D escription
SDAT A
20
I
Serial input, MSB first, containing two channels of 16, 18 or 20 bits (AD1857) or
16 bits (AD1858) of twos complement data per channel.
BCLK
19
I
Bit clock input for input data. Need not run continuously; may be gated or used in a
burst fashion.
LRCLK
18
3
I
I
Left/right clock input for input data. Must run continuously.
MODE
Input serial data port mode control. Selects between I2S-justified (HI) and left-justified
(LO) on the AD1857. Selects between DSP serial port style mode (HI) and right-
justified (LO) on the AD1858. The state of the mode pin should be changed only when
the AD1857/AD1858 is held in reset (PD/RST LO). Otherwise, the AD1857/
AD1858 serial port may lose synchronism.
Contr ol and Clock Signals
P in Nam e
Num ber
I/O
D escription
PD/RST
2
I
Power-Down/Reset. T he AD1857/AD1858 are placed in a low power consumption
“sleep” mode when this pin is held LO. T he AD1857/AD1858 are reset on the
rising edge of this signal. Connect HI for normal operation.
DEEMP
5
I
De-emphasis. Digital de-emphasis is enabled when this input signal is HI. T his is
used to impose a 50/15 µs response characteristic on the output audio spectrum at
an assumed 44.1 kHz sample rate.
MUT E
MCLK
15
1
I
I
Mute. Assert H I to mute both stereo analog outputs of the AD1857/AD1858.
Deassert LO for normal operation.
Master Clock Input. Connect to an external clock source at either 256 or 384 times
the intended sample frequency as determined by the 384/256 pin. Must be synchro-
nous with LRCLK, but may have any phase with respect to LRCLK.
384/256
6
I
Selects the master clock mode as either 384 times the intended sample frequency
(H I) or 256 times the intended sample frequency (LO). T he state of this input
should be hardwired to logic LO or logic HI or may be changed while the AD1857/
AD1858 is in power-down/reset. It must not be changed while the AD1857/AD1858
is operational.
Analog Signals
P in Nam e
Num ber
I/O
D escription
FILT
11
O
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage
reference with parallel 10 µF and 0.1 µF capacitors to the AGND pin.
CMOUT
10
O
Voltage Reference Common Mode Output. Should be decoupled with 10 µF
capacitor to the AGND pin or plane. T his output is available externally for dc
coupling and level-shifting. CMOUT should not have any signal dependent load,
or used where it will sink or source current.
OUT L
OUT R
8
O
O
Left channel line level analog output.
Right channel line level analog output.
13
P ower Supply Connections and Miscellaneous
P in Nam e
Num ber
I/O
D escription
AVDD
AGND
DVDD
DGND
N/C
7, 14
9, 12
17
I
I
I
I
Analog Power Supply. Connect to analog +5 V supply.
Analog Ground.
Digital Power Supply. Connect to digital +5 V supply.
Digital Ground.
16
4
No Connect. Reserved. Do not connect.
REV. 0
–5–
AD1857/AD1858
D EFINITIO NS
Inter channel Gain Mism atch
D ynam ic Range
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
T he ratio of a full-scale output signal to the integrated output
noise in the passband (0 kHz to 20 kHz), expressed in decibels
(dB). Dynamic range is measured with a –60 dB input signal
and is equal to (S/[T HD+N]) + 60 dB. Note that spurious
harmonics are below the noise with a –60 dB input, so the noise
level establishes the dynamic range. T his measurement tech-
nique is consistent with the recommendations of the Audio
Engineering Society (AES17-1991) and the Electronic Industries
Association of Japan (EIAJ CP-307).
Gain D r ift
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Cr osstalk (EIAJ Method)
Ratio of response on one channel with a zero input, to a full-
scale 1 kHz sine-wave input on the other channel, expressed in
decibels.
Inter channel P hase D eviation
Total H ar m onic D istor tion + Noise (TH D +N)
T he ratio of the root-mean-square (rms) value of a full-scale
fundamental input signal to the rms sum of all other spectral
components in the passband, expressed in decibels (dB) and
as a percentage.
Difference in output sampling times between stereo channels,
expressed as a phase difference in degrees between 1 kHz
inputs.
P ower Supply Rejection
With zero input, signal present at the output when a 300 mV
p-p signal is applied to power supply pins, expressed in decibels
of full scale.
P assband
T he region of the frequency spectrum unaffected by the
attenuation of the digital interpolation filter.
Gr oup D elay
P assband Ripple
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in seconds(s). More
precisely, the derivative of radian phase with respect to radian
frequency at a given frequency.
T he peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the passband,
expressed in decibels.
Stopband
Gr oup D elay Var iation
T he region of the frequency spectrum attenuated by the digital
interpolation filter to the degree specified by “stopband
attenuation.”
T he difference in group delays at different input frequencies.
Specified as the difference between the largest and the smallest
group delays in passband, expressed in microseconds (µs).
Gain Er r or
D e-Em phasis Gain Er r or
With a near full-scale input, the ratio of actual output to
expected output, expressed as a percentage.
A measure, expressed in decibels, of the difference between the
ideal 50/15 µs de-emphasis filter response, and the actual 50/15 µs
de-emphasis filter response.
–6–
REV. 0
AD1857/AD1858
Typical Performance Characteristics
Figures 1 through 4 illustrate the typical performance of the
AD1857/AD1858 as measured by an Audio Precision System
T wo. Signal-to-Noise (dynamic range) T HD+N performance is
shown under a range of conditions. Figure 5 shows the power
supply rejection performance of the AD1857/AD1858. T he
channel separation performance of the AD1857/AD1858 is
shown in Figure 6. T he digital filter transfer function is shown
in Figure 7.
0
–10
–20
–30
–40
–50
0
–10
–20
–30
–40
–50
–60
–60
–70
–80
–70
–80
–90
–90
–100
–110
–100
–110
–120
–130
–140
–150
–120
–130
–140
0
2.5
5.0
7.5
10.0
kHz
12.5
15.0
17.5
20.0
0
2.5
5.0
7.5
10.0
kHz
12.5
15.0
17.5
20.0
Figure 1. 1 kHz Tone at –0.5 dBFS
Figure 3. THD+N vs. Frequency at –0.5 dBFS
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–100
–110
–120
–130
–140
–100
0
2.5
5.0
7.5
10.0
kHz
12.5
15.0
17.5
20.0
–80
–60
–40
–20
0
dBFS
Figure 2. 1 kHz Tone at –10 dBFS
Figure 4. THD+N vs. Am plitude at 1 kHz
REV. 0
–7–
AD1857/AD1858
Typical Performance Characteristics (continued)
–40
–44
0
–10
–20
–30
–40
–50
–60
–40
–45
–50
–48
–52
–55
LEFT CHANNEL
RIGHT CHANNEL
–56
–60
–65
–60
–64
–68
–72
–76
–80
–70
–80
–90
–100
–110
–120
–130
–140
–70
–75
–80
0
2.5
5.0
7.5
10.0
kHz
12.5
15.0
17.5
20.0
0
2.5
5.0
7.5
10.0
kHz
12.5
15.0
17.5
20.0
Figure 5. Power Supply Rejection to 300 m V p-p on AVDD
Figure 6. Channel Separation vs. Frequency at –0.5 dBFS
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
F
S
Figure 7. Digital Filter Signal Transfer Function to 3.5 ϫ FS
–8–
REV. 0
AD1857/AD1858
TH EO RY O F O P ERATIO N
T he conventional problem limiting the performance of multibit
sigma-delta converters is the nonlinearity of the passive circuit
elements used to sum the quantization levels. Analog Devices has
developed (and received patents on) a revolutionary architecture
that overcomes the circuit element linearity problem that otherwise
limits the performance of multibit sigma-delta audio converters.
T his new architecture provides the AD1857/AD1858 with the
same excellent differential nonlinearity and linearity drift (over
temperature and time) specifications as single bit sigma-delta
DACs.
T he AD1857/AD1858 offer the advantages of sigma-delta con-
version architectures (no component trims, low cost CMOS
process technology, superb low-level linearity performance) with
the advantages of conventional multibit R-2R resistive ladder
audio DACs (continuously variable sample rate support, jitter
tolerance, very low output noise, etc.).
T he use of a multibit sigma-delta modulator means that the
AD1857/AD1858 generate dramatically lower amounts of out-
of-band noise energy, which greatly reduces the requirement on
post DAC filtering. T he required post-filtering is integrated on
the AD1857/AD1858. T he AD1857/AD1858’s multibit sigma-
delta modulator is also highly immune to digital substrate noise.
T he AD1857/AD1858’s multibit modulator has another
important advantage; it has a high immunity to substrate digital
noise. Substrate noise can be a significant problem in mixed-
signal designs, where it can produce intermodulation products
that fold down into the audio band. T he AD1857/AD1858 are
approximately eight times less sensitive to digital substrate noise
(voltage reference noise injection) than equivalent single-bit
sigma-delta modulator based DACs.
Ser ial Audio D ata Inter face
T he serial audio data interface uses the bit clock (BCLK) simply
to clock the data into the AD1857/AD1858. T he bit clock may
therefore be asynchronous to the L/R clock. T he left/right clock
(LRCLK) is both a framing signal and the sample frequency
input to the interpolation filter. T he left/right clock must be
synchronous with MCLK, but may have any phase relationship
with respect to MCLK; LRCLK is generally synchronously divided
down from MCLK. T he SDAT A input carries the serial stereo
digital audio in MSB first, twos-complement format.
D ither Gener ator
T he AD1857/AD1858 include an on-chip dither generator that
is intended to further “whiten” the quantization noise introduced
by the multibit DAC. T he dither has a triangular Probability
Distribution Function (PDF) characteristic, which is generally
considered to create the most favorable noise shaping of the
residual quantization noise. The AD1857/AD1858 are among the
first low cost IC audio DACs to include dithering.
D igital Inter polation Filter
T he purpose of the interpolator is to “oversample” the input
data, i.e., to increase the sample rate so the first signal image is
moved out to the oversample frequency, which relaxes the
attenuation requirements on the analog reconstruction filter.
T he AD1857/AD1858 interpolator increases the input data
sample rate by 128. T he interpolation is performed using a
multistage FIR digital filter structure. T he first stage is a droop
equalizer; the second and third stages are halfband filters; and
the fourth stage is a second-order comb filter. T he FIR filter
implementation is multiplier-free, i.e., the multiplies are performed
using shift-and-add operations. T he FIR filter coefficients have
been recoded in a canonical sign digit format to enable the use
of a compact arithmetic logic unit without a multiplier.
Analog Filter ing
The AD1857/AD1858 include a second-order switched
capacitor discrete time low-pass filter followed by a first-order
analog continuous time low-pass filter. T hese filters eliminate
the need for any additional off-chip external reconstruction
filtering. T his on-chip switched capacitor analog filtering is
essential to reduce the deleterious effects of master clock jitter.
D igital D e-Em phasis P r ocessing
The AD1857/AD1858 include digital circuitry for implementing
the 50/15 µs de-emphasis frequency response characteristic. A
control pin DEEMP (Pin 5) enables de-emphasis when it is
asserted HI. T he digital de-emphasis response assumes a sample
frequency of 44.1 kHz. T he transfer function magnitude error
of this digital filter is less than ±0.1 dB (from 0 kHz to 20 kHz)
compared to a 50/15 µs continuous time filter. If the sample
frequency is not 44.1 kHz, the de-emphasis frequency response
will scale directly with frequency. T he 44.1 kHz FS digital de-
emphasis frequency response is shown in Figure 8.
Multibit Sigm a-D elta Modulator
T he AD1857/AD1858 employ a 4-bit second-order sigma-delta
modulator. Whereas a traditional single-bit sigma-delta
modulator has two levels of quantization, the AD1857/AD1858’s
has 17 levels of quantization. T raditional single-bit sigma-delta
modulators sample the input signal at 64 times the input sample
rate; the AD1857/AD1858 sample the input signal at 128 times
the input sample rate. T he additional quantization levels
combined with the high oversampling ratio means that the
AD1857/AD1858 DAC output spectrum contains dramatically
lower levels of out-of-band noise energy, which is a major
stumbling block with more traditional single-bit sigma-delta
architectures. This means that the post-DAC analog reconstruction
filter has reduced transition band steepness and attenuation
requirements, which directly equates to lower phase distortion.
Since the analog filtering generally establishes the noise and
distortion characteristic of the DAC, the reduced requirements
translate into better audio performance.
T1 = 50µs
0
T2 = 15µs
–10
F2
F1
10.61
3.183
FREQUENCY – kHz
Multibit sigma-delta modulators bring an additional benefit:
they are essentially free of stability (and therefore potential loop
oscillation) problems. T hey are able to scale the output signal
to a wider range of the voltage reference, which can increase the
overall dynamic range of the converter.
Figure 8. Digital De-Em phasis Frequency Response
REV. 0
–9–
AD1857/AD1858
O P ERATING FEATURES
Ser ial Input P or t Modes
Ser ial D ata Input P or t
T he AD1857/AD1858 use an input pin to control the mode
configuration of the input data port. MODE (Pin 3) programs
the input data port mode as follows:
T he AD1857/AD1858 use the frequency of the left/right and
master input clocks to determine the input sample rate. Gen-
erally, the master clock (MCLK) is divided down to synthesize
the left/right clock (LRCLK). LRCLK must run continuously
and transition twice per stereo sample period (except in the left-
justified DSP serial port style mode, when it transitions four
times per stereo sample period). T he bit clock (BCLK) is edge-
sensitive and may be used in a gated or burst mode, i.e., a
stream of pulses during data transmission followed by periods of
inactivity. T he bit clock is only used to write the audio data
into the serial input port. It is important that the left/right clock
is “clean,” with monotonic rising and falling edge transitions
and no excessive overshoot or undershoot that could cause false
clock triggering of the AD1857/AD1858.
Figure 9 shows the AD1857 left-justified mode. LRCLK is HI
for the left channel, and LO for the right channel. Data is valid
on the rising edge of BCLK. T he MSB is left-justified to an
LRCLK transition, with no MSB delay. T he left-justified mode
can be used in the 16-, 18- or 20-bit input mode.
MODE (P in 3)
AD 1857 Serial Input P ort Mode
LO
HI
Left-Justified (See Figure 9)
I2S-Justified (See Figure 10)
T he AD1857/AD1858’s flexible serial data input port accepts
data in twos-complement, MSB first format. T he left channel
data field always precedes the right channel data field. T he
input data consists of 16, 18 or 20 bits (16 bits only to the
AD1858). All digital inputs are specified to T T L logic levels.
T he input data port is configured by a control pin, MODE,
Pin 3. T he AD1857 and the AD1858 are identical except for
the serial data input port modes offered. T he AD1857 offers
I2S-justified and left-justified modes, for 16-, 18- or 20-bit data
words. T he AD1858 offers right-justified and DSP serial port
style mode for 16-bit data words.
MODE (P in 3)
AD 1858 Serial Input P ort Mode
LO
HI
Right-Justified (See Figure 11)
Left-Justified DSP Serial Port Style
(See Figure 12)
Figure 10 shows the AD1857 I2S-justified mode. LRCLK is
LO for the left channel, and HI for the right channel. Data is
valid on the rising edge of BCLK. T he MSB is left-justified to
an LRCLK transition, but with a single BCLK period delay.
T he I2S-justified mode can be used in the 16-, 18- or 20-bit
input mode.
Note: During the first 30,000 MCLK cycles after coming out of
reset, the AD1857/AD1858 synchronizes its internal sequencer
counter to the incoming LRCLK. After this period of time, it is
assumed that the LRCLK and the internal AD1857/AD1858
output channels could be switched (L to R and R to L). Therefore,
if the incoming LRCLK is stopped and then restarted with a
different phase, the AD1857/AD1858 should be reset again to
synchronize with this new clock.
Figure 11 shows the AD1858 the right-justified mode. LRCLK
is HI for the left channel, and LO for the right channel. Data is
valid on the rising edge of BCLK. T he MSB is delayed 16-bit
clock periods from an LRCLK transition so that when there are
64 BCLK periods per LRCLK period, the LSB of the data will
be right-justified to the next LRCLK transition.
LRCLK
RIGHT CHANNEL
LEFT CHANNEL
INPUT
BCLK
INPUT
SDATA
MSB
MSB-1 MSB-2
MSB MSB-1 MSB-2
LSB+2 LSB+1
LSB
MSB
MSB-1
LSB+2 LSB+1
LSB
INPUT
Figure 9. AD1857 Left-J ustified Mode
LRCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB
MSB MSB-1 MSB-2
MSB MSB-1 MSB-2
LSB+2 LSB+1
LSB
LSB+2 LSB+1
LSB
Figure 10. AD1857 I2S-J ustified Mode
LRCLK
INPUT
RIGHT CHANNEL
LEFT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB MSB-1 MSB-2
MSB MSB-1 MSB-2
LSB
LSB+2 LSB+1 LSB
LSB+2 LSB+1 LSB
Figure 11. AD1858 Right-J ustified Mode
–10–
REV. 0
AD1857/AD1858
LRCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB
MSB
MSB-1
LSB+2 LSB+1
LSB
MSB
MSB-1
LSB+2 LSB+1 LSB
MSB-1
Figure 12. AD1858 Left-J ustified DSP Serial Port Style
LRCLK
INPUT
RIGHT CHANNEL
LEFT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB
MSB-1 MSB-2
LSB+2
LSB+1
LSB
MSB
LSB+2
LSB
MSB-1 MSB-2
LSB+1
LSB
MSB
MSB-1
Figure 13. AD1857/AD1858 32
؋
FS Packed Mode Figure 12 shows the AD1858 left-justified DSP serial port style
mode. LRCLK must pulse HI for at least one bit clock period
before the MSB of the left channel is valid, and LRCLK must
pulse HI again for at least one bit clock period before the MSB
of the right channel is valid. Data is valid on the falling edge of
BCLK. Note that in this mode, it is the responsibility of the DSP
to ensure that the left data is transmitted with the first LRCLK
pulse, the right data is transmitted with the second LRCLK pulse,
and synchronism is maintained from that point forward.
found within 1024 input sample periods (approximately 23
milliseconds at 44.1 kHz), the output is muted regardless.
O utput D r ive, Buffer ing and Loading
The AD1857/AD1858 analog output stage is able to drive a 2 kΩ
load. If lower impedance loads must be driven, an external
buffer stage such as the Analog Devices SSM2142 should be
used. T he analog output is generally ac coupled with a 10 µF
capacitor as shown in Figure 21. It is possible to dc couple the
AD1857/AD1858 output into an op amp stage using the
CMOUT signal as a bias point.
Note that in 16-bit input mode, the AD1857/AD1858 are
capable of a 32 × FS BCLK frequency “packed mode” where
the MSB is left-justified to an LRCLK transition, and the LSB
is right-justified to an LRCLK transition. LRCLK is HI for the
left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. Packed mode can be used when the
AD1857 is programmed in left-justified mode, or when the
AD1858 is programmed in right-justified mode. Packed mode
is shown in Figure 13.
O n-Chip Voltage Refer ence
T he AD1857/AD1858 include an on-chip voltage reference that
establishes the output voltage range. T he nominal value of this
reference is +2.25 V, which corresponds to a line output voltage
swing of 3 V p-p. T he line output signal is centered around a
voltage established by the CMOUT (common-mode output)
(Pin 10). T he reference must be bypassed both on the FILT
input (Pin 11) with 10 µF and 0.1 µF capacitors, and on the
CMOUT output (Pin 10) with 10 µF and 0.1 µF capacitors, as
shown in Figure 21. Both the FILT pin and the CMOUT pin
use the AGND ground. T he on-chip voltage reference may be
overdriven with an external reference source by applying this
voltage to the FILT pin. CMOUT and FILT must still be
bypassed as shown in Figure 21. An external reference can be
useful to calibrate multiple AD1857/AD1858 DACs to the same
gain. Reference bypass capacitors larger than those suggested
can be used to improve the signal-to-noise performance of the
AD1857/AD1858.
Master Clock
T he synchronous master clock of the AD1857/AD1858 is
supplied by an external clock source applied to MCLK. Figure
14 shows example connections. Do not change the state of the
384/256 pin while the AD1857/AD1858 is operational; this pin
should be hardwired LO or HI. Alternatively, its state may be
changed while the PD/RST pin is asserted LO.
MCLK FREQUENCY
SAMPLE RATE
12.288MHz
11.2896MHz
8.192MHz
18.432MHz
16.9344MHz
12.288MHz
48kHz
44.1kHz
32kHz
P ower -D own and Reset
The PD/RST input (Pin 2) is used to control the power consumed
by the AD1857/AD1858. When PD/RST is held LO, the
AD1857/AD1858 are placed in a low dissipation power-down
state. When PD/RST is brought H I, the AD1857/AD1858
become ready for normal operation. T he master clock (MCLK,
Pin 1) must be running for a successful reset or power-down
operation to occur. T he PD/RST signal must be LO for a
minimum of four master clock periods (326 ns with a 12.288 MHz
MCLK frequency).
256 MODE
384 MODE
384/256 = HI
384/256 = LO
1
6
MCLK
384/256
Figure 14. AD1857/AD1858 Clock Connections
D igital Mute
T he AD1857/AD1858 offer a control pin that mutes the analog
output. By asserting the MUT E (Pin 15) signal HI, both the
left channel and the right channel are muted. T he AD1857/
AD1858 have been designed to minimize pops and clicks when
muting and unmuting the device. T he AD1857/AD1858
include a zero crossing detector which attempts to implement
mute on waveform zero crossings only. If a zero crossing is not
When the PD/RST input (Pin 2) is brought HI, the AD1857/
AD1858 are reset. All registers in the AD1857/AD1858 digital
engine (serial data port, interpolation filter and modulator) are
zeroed, and the amplifiers in the analog section are shorted
during the reset operation. T he AD1857/AD1858 have been
designed to minimize pops and clicks when entering and exiting
the power-down state.
REV. 0
–11–
AD1857/AD1858
Contr ol Signals
Figure 18 shows the suggested interface to the Philips SAA2500*
MPEG audio decoder IC. T he SAA2500 supports 18 bits of
data using an I2S-compatible output format.
The MODE and DEEMP control inputs are normally connected
HI or LO to establish the operating state of the AD1857/AD1858.
They can be changed dynamically (and asynchronously to the
LRCLK and the master clock) as long as they are stable before
the first serial data input bit (i.e., the MSB) is presented to the
AD1857/AD1858.
BCLK
19
18
SCK
WS
SD
LRCLK
SAA2500
20 SDATA
AD1857
AP P LICATIO N ISSUES
Inter face to MP EG Audio D ecoder s
FSCLKIN
HI
HI
MODE
3
6
1
384/256
Figure 15 shows the suggested interface to the Analog Devices
ADSP-21xx family of DSP chips, for which several MPEG
audio decode algorithms are available. T he ADSP-21xx
supports 16 bits of data using a left-justified DSP serial port
style format.
MCLK
256 x F
s
Figure 18. Interface to SAA2500
Figure 19 shows the suggested interface to the Zoran ZR38000*
DSP chip, which can act as an MPEG audio or AC-3 audio
decoder. T he ZR38000 supports 16 bits of data using a left-
justified output format.
19 BCLK
SCLK
RFS
18 LRCLK
NC
NC
SDATA
MODE
20
3
TFS
ADSP-21xx
AD1858
BCLK
SCKB
WSB
19
18
20
3
HI
HI
DT
DR
LRCLK
6
384/256
ZR38000
SDATA
SDB
1
MCLK
NC = NO CONNECT
AD1857
MODE
SCKIN
LO
HI
6
384/256
Figure 15. Interface to ADSP-21xx
1
MCLK
Figure 16 shows the suggested interface to the T exas Instruments
TMS320AV110* MPEG audio decoder IC. The TMS320AV110
supports 18 bits of data using a right-justified output format.
256 x F
s
Figure 19. Interface to ZR38000
Figure 20 shows the suggested interface to the C-Cube
Microsystems CL480* MPEG system decoder IC. T he CL480
supports 16 bits of data using a right-justified output format.
SCLK
LRCLK
BCLK
19
18
20
3
LRCLK
TMS320AV110
PCMDATA
SDATA AD1858
PCMCLK
HI
HI
MODE
BCLK
DA-BCK
DA-LRCK
DA-DATA
19
18
6
384/256
LRCLK
MCLK
1
CL480
20
SDATA
256 x F
s
AD1858
3
6
1
MODE
HI
HI
DA-XCK
Figure 16. Interface to TMS320AV110
384/256
Figure 17 shows the suggested interface to the LSI Logic
L64111* MPEG audio decoder IC. T he L64111 supports 16
bits of data using a left-justified output format.
MCLK
256 x F
s
Figure 20. Interface to CL480
19 BCLK
SCLKO
LRCLKO
SERO
18
20
LRCLK
L64111
SDATA
AD1857
MODE
384/256
MCLK
LO
LO
3
6
1
SYSCLK
384 x F
s
Figure 17. Interface to L64111
*All trademarks are properties of their respective holders.
–12–
REV. 0
AD1857/AD1858
Layout and D ecoupling Consider ations
T he recommended decoupling, bypass and output circuits for
the AD1857/AD1858 are shown in Figure 21.
MCLK
1
2
3
4
5
6
7
8
9
20 SDATA
PD/RST
BCLK
19
18
17
16
DIGITAL
GROUND
PLANE
LRCLK
MODE
P CB and Gr ound P lane Recom m endations
T he AD1857/AD1858 ideally should be located above a split
ground plane, with the digital pins over the digital ground plane
and the analog pins over the analog ground plane. T he split
should occur between Pins 6 and 7, and between Pins 14 and
15 as shown in Figure 22. T he ground planes should be linked
with a ferrite bead. T his ground plane strategy maximizes the
AD1857/AD1858’s analog audio performance.
DV
DD
NC
DGND
DEEMP
15 MUTE
384/256
FERRITE
BEAD
AV
14
AV
DD
DD
OUTL
AGND
13 OUTR
12 AGND
ANALOG
GROUND
PLANE
CMOUT 10
FILT
11
NC = NO CONNECT
Figure 22. Recom m ended Ground Plane
SAMPLE RATE
MCLK FREQUENCY
12.288MHz
11.2896MHz
8.192MHz
18.432MHz
16.9344MHz
12.288MHz
48kHz
44.1kHz
32kHz
+5V
ANALOG
+5V
ANALOG
4.7µF
4.7µF
256 MODE
384 MODE
384/256 = HI
384/256 = LO
0.1µF
0.1µF
14
AV
1
9
6
7
AV
MCLK
AGND
384/256
DD
DD
11
12
FILT
4.7µF
0.1µF
AGND
20
19
18
SDATA
BLCK
BIAS VOLTAGE
FOR EXTERNAL
USE
10
8
CMOUT
OUTL
AD1857/AD1858
DSP OR
AUDIO
DECODER
LRCLK
2.2µF
2.2µF
LEFT LINE
OUTPUT
*
*
3
MODE
DV
RIGHT LINE
OUTPUT
OUTR 13
MUTE DEEMP
DGND
16
NC
4
PD/RST
DD
17
2
5
15
0.01µF
*OPTIONAL OUTPUT FILTER
2.2µF
1kΩ
+
4.7µF
µCONTROLLER
LEFT LINE
OUTPUT
OUTL
OUTR
8
100k
100k
820pF
1kΩ
+5V
DIGITAL
NC = NO CONNECT
2.2µF
+
RIGHT LINE
OUTPUT
13
820pF
Figure 21. Recom m ended Circuit Connection
REV. 0
–13–
AD1857/AD1858
Tim ing D iagr am s
minimum setup time is tDDS and the minimum serial data hold
time is tDDH
T he serial data port timing is shown in Figures 23 and 24. T he
minimum bit clock HI pulse width is tDBH and the minimum bit
clock LO pulse width is tDBL. T he minimum bit clock period is
.
T he power-down/reset timing is shown in Figure 25. T he
minimum reset LO pulse width is tPDRP (four MCLK periods)
to accomplish a successful AD1857/AD1858 reset operation.
t
DBP. T he left/right clock minimum setup time is tDLS and the
left/right clock minimum hold time is tDLH. T he serial data
tDBH
tDBP
BCLK
tDBL
tDLS
LRCLK
tDDS
SDATA
LEFT-JUSTIFIED
MODE
MSB
tDDH
MSB-1
AD1857
tDDS
SDATA
2
I S-JUSTIFIED
MSB
tDDH
MODE
AD1857
tDDS
tDDS
MSB
SDATA
RIGHT-JUSTIFIED
MODE
LSB
AD1858
tDDH
tDDH
Figure 23. Serial Data Port Tim ing
tDBH
tDBP
BCLK
tDBL
tDLS
tDLH
LRCLK
tDDS
MSB
tDDH
SDATA
LEFT-JUSTIFIED
DSP SERIAL
MSB-1
PORT STYLE MODE
AD1858
Figure 24. Serial Data Port Tim ing–DSP Serial Port Style Mode (AD1858 Only)
MCLK
PD/RST
tPDRP
Figure 25. Power-Down/Reset Tim ing
–14–
REV. 0
AD1857/AD1858
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
20-Lead SSO P
(RS-20)
0.295 (7.50)
0.271 (6.90)
20
11
0.212 (5.38)
0.205 (5.207)
0.311 (7.9)
0.301 (7.64)
10
1
0.07 (1.78)
0.078 (1.98)
PIN 1
0.066 (1.67)
0.068 (1.73)
0.037 (0.94)
8°
0°
0.0256
(0.65)
BSC
0.022 (0.559)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
1. LEAD NO. 1 IDENTIFIED BY A DOT.
2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
REV. 0
–15–
–16–
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