AD1859 [ADI]
Stereo, Single-Supply 18-Bit Integrated DAC; 立体声，单电源， 18位，集成DAC
| 型号： | AD1859 |
| 厂家： | 
ADI |
| 描述： | Stereo, Single-Supply 18-Bit Integrated DAC |
| 文件： | 总16页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Stereo, Single-Supply
18-Bit Integrated ⌺⌬ DAC
a
AD1859
P RO D UCT O VERVIEW
FEATURES
T he AD1859 is a complete 16-/18-bit single-chip stereo digital
audio playback subsystem. It comprises a variable rate digital
interpolation filter, a revolutionary multibit sigma-delta (∑∆)
modulator with dither, a jitter-tolerant DAC, switched capacitor
and continuous time analog filters, and analog output drive cir-
cuitry. Other features include an on-chip stereo attenuator and
mute, programmed through an SPI-compatible serial control
port.
Com plete, Low Cost Stereo DAC System in a Single Die
Package
Variable Rate Oversam pling Interpolation Filter
Multibit ⌺⌬ Modulator w ith Triangular PDF Dither
Discrete and Continuous Tim e Analog Reconstruction
Filters
Extrem ely Low Out-of-Band Energy
64 Step (1 dB/ Step) Analog Attenuator w ith Mute
Buffered Outputs w ith 2 k⍀ Output Load Drive
Rejects Sam ple Clock J itter
94 dB Dynam ic Range, –88 dB THD+N Perform ance
Option for Analog De-em phasis Processing w ith
External Passive Com ponents
؎0.1؇ Maxim um Phase Linearity Deviation
Continuously Variable Sam ple Rate Support
Digital Phase Locked Loop Based Asynchronous Master
Clock
On-Chip Master Clock Oscillator, Only External Crystal
Is Required
T he key differentiating feature of the AD1859 is its asynchro-
nous master clock capability. Previous ∑∆ audio DACs re-
quired a high frequency master clock at 256 or 384 times the
intended audio sample rate. T he generation and management
of this high frequency synchronous clock is burdensome to the
board level designer. T he analog performance of conventional
single bit ∑∆ DACs is also dependent on the spectral purity of
the sample and master clocks. T he AD1859 has a digital Phase
Locked Loop (PLL) which allows the master clock to be asyn-
chronous, and which also strongly rejects jitter on the sample
clock (left/right clock). T he digital PLL allows the AD1859 to
be clocked with a single frequency (27 MHz for example) while
the sample frequency (as determined from the left/right clock)
can vary over a wide range. T he digital PLL will lock to the
new sample rate in approximately 100 ms. Jitter components
15 Hz above and below the sample frequency are rejected by
6 dB per octave. T his level of jitter rejection is unprecedented
in audio DACs.
Pow er-Dow n Mode
Flexible Serial Data Port (I2S-J ustified, Left-J ustified,
Right-J ustified and DSP Serial Port Modes)
SPI* Com patible Serial Control Port
Single +5 V Supply
28-Pin SOIC and SSOP Packages
APPLICATIONS
Digital Cable TV and Direct Broadcast Satellite Set-Top
Decoder Boxes
Digital Video Disc, Video CD and CD-I Players
High Definition Televisions, Digital Audio Broadcast
Receivers
CD, CD-R, DAT, DCC, ATAPI CD-ROM and MD Players
Digital Audio Workstations, Com puter Multim edia
Products
T he AD1859 supports continuously variable sample rates with
essentially linear phase response, and with an option for external
analog de-emphasis processing. T he clock circuit includes an
on-chip oscillator, so that the user need only provide an external
crystal. T he oscillator may be overdriven, if desired, with an ex-
ternal clock source.
(continued on page 7)
FUNCTIO NAL BLO CK D IAGRAM
CONTROL
DATA
REFERENCE
FILTER AND
GROUND
DIGITAL
SUPPLY
ASYNCHRONOUS
CLOCK/CRYSTAL
INPUT
2
3
2
DPLL/CLOCK
MANAGER
DE-EMPHASIS
SWITCH LEFT
SERIAL
CONTROL
INTERFACE
VOLTAGE
REFERENCE
AD1859
COMMON MODE
MULTIBIT
ANALOG
FILTER
VARIABLE RATE
INTERPOLATION
ATTEN/
OUTPUT
BUFFER
DAC
DAC
∑∆ MODULATOR
MUTE
SERIAL
DATA
INTERFACE
16- OR 18-BIT
DIGITAL DATA
INPUT
6
ANALOG
OUTPUTS
MULTIBIT
∑∆ MODULATOR
ANALOG
FILTER
VARIABLE RATE
INTERPOLATION
ATTEN/
MUTE
OUTPUT
BUFFER
DE-EMPHASIS
SWITCH RIGHT
2
DE-EMPHASIS
MUTE
ANALOG
SUPPLY
POWER
DOWN/RESET
*SPI is a registered trademark of Motorola, Inc.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
AD1859–SPECIFICATIONS
TEST CO ND ITIO NS UNLESS O TH ERWISE NO TED
Supply Voltages (AVDD, DVDD
Ambient T emperature
)
+5.0
25
V
°C
Input Clock (FMCLK
Input Signal
)
27.1656
1001.2938 Hz
MHz
–0.5
44.1
dB Full Scale
kHz
Input Sample Rate
Measurement Bandwidth
Input Data Word Width
Load Capacitance
10 Hz to 20 kHz
18
Bits
pF
V
100
2.4
0.8
Input Voltage HI (VIH
)
Input Voltage LO (VIL)
V
NOT ES
I2S-Justified Mode (Ref. Figure 3).
Device Under T est (DUT ) is bypassed, decoupled and dc-coupled as shown in Figure 17 (no de-emphasis circuit).
Performance of the right and left channels are identical (exclusive of “Interchannel Gain Mismatch” and “Interchannel Phase Deviation” specifications).
Attenuation setting is 0 dB.
Values in bold typeface are tested; all others are guaranteed, not tested.
ANALO G P ERFO RMANCE
Min
Typ
Max
Units
Resolution
18
Bits
Dynamic Range (20 to 20 kHz, –60 dB Input)
(No A-Weight Filter)
(With A-Weight Filter)
85.7
88
91
94
–88
0.004
dB
dB
dB
%
T otal Harmonic Distortion + Noise
–84
0.0063
Analog Outputs
Single-Ended Output Range (±Full Scale)
Output Impedance at Each Output Pin
Output Capacitance at Each Output Pin
External Load Impedance (T HD +N ≤ –84 dB)
Out-of-Band Energy (0.5 × FS to 100 kHz)
CMOUT
2.8
3.0
17
3.2
24
20
V p-p
Ω
pF
Ω
dB
V
750
2K
–72.5
2.45
2.05
2.25
DC Accuracy
Gain Error
±1
؎5
%
Interchannel Gain Mismatch
Gain Drift
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
Attenuator Step Size
Attenuator Range Span
Mute Attenuation
De-Emphasis Switch (EMPL, EMPR) DC Resistance
0.01
140
0.225
270
dB
ppm/°C
dB
Degrees
dB
dB
101
±0.1
1.0
–62.5
–74.2
10
0.6
–61.5
–70
3
1.4
–63.5
dB
Ω
50
D IGITAL INP UTS
Min
Typ
Max
Units
Input Voltage HI (VIH
)
2.4
V
Input Voltage LO (VIL)
0.8
6
6
V
Input Leakage (IIH @ VIH = 2.4 V)
Input Leakage (IIL @ VIL = 0.8 V)
Input Capacitance
1
1
µA
µA
pF
20
REV. A
–2–
AD1859
D IGITAL TIMING (Guaranteed over –40°C to +105°C, AVDD = DVDD = +5.0 V ± 10%)
Min
Typ
Max
Units
tDBH
tDBL
tDBP
tDLS
tDLH
tDDS
tDDH
tCCH
tCCL
tCCP
tCSU
tCHD
tCLD
tCLL
tCLH
tPDRP
BCLK HI Pulse Width
BCLK LO Pulse Width
BCLK Period
LRCLK Setup
LRCLK Hold (DSP Serial Port Style Mode Only)
SDAT A Setup
25
25
50
5
0
0
5
15
15
30
0
5
15
5
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SDAT A Hold
CCLK HI Pulse Width
CCLK LO Pulse Width
CCLK Period
CDAT A Setup
CDAT A Hold
CLAT CH Delay
CLAT CH LO Pulse Width
CLAT CH HI Pulse Width
PD/RST LO Pulse Width
4 MCLK P er iods
(≈150 ns @ 27 MH z)
tMCP
FMC
tMCH
tMCL
MCLK Period
30
17
15
15
37
27
60
33
ns
MHz
ns
MCLK Frequency (1/tMCP
MCLK HI Pulse Width
MCLK LO Pulse Width
)
ns
P O WER
Min
Typ
Max
Units
Supplies
Voltage, Analog and Digital
Analog Current
Analog Current—Power Down
Digital Current
Digital Current—Power Down
Dissipation
4.5
29.5
5
5.5
mA
15
mA
9.5
V
36
0.5
30
6
µA
mA
23.5
Operation—Both Supplies
Operation—Analog Supply
Operation—Digital Supply
Power Down—Both Supplies
Power Supply Rejection Ratio
265
330
180
150
48
mW
mW
mW
mW
147.5
117.5
30
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
55
52
dB
dB
TEMP ERATURE RANGE
Min
Typ
Max
Units
Specifications Guaranteed
Functionality Guaranteed
Storage
25
°C
°C
°C
–40
–55
+105
+125
P ACKAGE CH ARACTERISTICS
Typ
Units
SOIC θJA (T hermal Resistance [Junction-to-Ambient])
SOIC θJC (T hermal Resistance [Junction-to-Case])
SSOP θJA (T hermal Resistance [Junction-to-Ambient])
SSOP θJC (T hermal Resistance [Junction-to-Case])
120.67
13.29
190.87
15.52
°C/W
°C/W
°C/W
°C/W
REV. A
–3–
AD1859
ABSO LUTE MAXIMUM RATINGS*
Min
Typ
Max
Units
DVDD to DGND
AVDD to AGND
Digital Inputs
Analog Inputs
AGND to DGND
Reference Voltage
Soldering
–0.3
–0.3
DGND – 0.3
AGND – 0.3
–0.3
6
6
V
V
V
V
V
DVDD + 0.3
AVDD + 0.3
0.3
Indefinite Short Circuit to Ground
+300
10
°C
sec
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. T his is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
D IGITAL FILTER CH ARACTERISTICS
Min
Typ
Max
Units
Passband Ripple
Stopband1 Attenuation
48 kHz FS
Passband
Stopband
±0.045
dB
dB
62
0
21.312
6117
kHz
kHz
26.688
44.1 kHz FS
Passband
Stopband
0
19.580
5620
kHz
kHz
24.520
32 kHz FS
Passband
Stopband
0
14.208
4078
kHz
kHz
17.792
Other FS
Passband
Stopband
Group Delay
Group Delay Variation
0
0.444
127.444
40/FS
0
FS
FS
sec
µs
0.556
ANALO G FILTER CH ARACTERISTICS
Min
Typ
Max
Units
Passband Ripple
Stopband Attenuation (at 64 × FS)
–0.075
dB
dB
58
NOT E
1Stopband nominally repeats itself at multiples of 128 × FS, where FS is the input word rate. T hus the digital filter will attenuate to 62 dB across the frequency
spectrum except for a range ±0.55 × FS wide at multiples of 128 × FS.
P IN CO NNECTIO NS
1
2
3
4
28
27
26
FILT
CMOUT
DEEMP
O RD ERING GUID E
FGND
EMPR
EMPL
OUTL
Tem perature
Range
P ackage
D escription
P ackage
O ption
25 OUTR
Model
NC
24
23
22
21
20
5
6
7
8
9
NC
AV
NC
AGND
MUTE
18/16
DD
AD1859
TOP VIEW
AD1859JR
AD1859JRS
–40°C to +105°C 28-Lead SOIC
–40°C to +105°C 28-Lead SSOP
R-28
RS-28
CLATCH
CDATA
(Not to Scale)
IDPM0
IDPM1
10
19
18
17
16
15
CCLK
DGND
PD/RST 11
12
DV
DD
SDATA
LRCLK
13
XTALI/MCLK
XTALO
14
BCLK
NC = NO CONNECT
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1859 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
AD1859
D EFINITIO NS
Gain Er r or
D ynam ic Range
With a near full-scale input, the ratio of actual output to ex-
pected output, expressed as a percentage.
T he ratio of a full-scale output signal to the integrated output
noise in the passband (0 to 20 kHz), expressed in decibels (dB).
Dynamic range is measured with a –60 dB input signal and is
equal to (S/[T HD+N]) + 60 dB. Note that spurious harmonics
are below the noise with a –60 dB input, so the noise level es-
tablishes the dynamic range. T his measurement technique is
consistent with the recommendations of the Audio Engineering
Society (AES17-1991) and the Electronics Industries Association
of Japan (EIAJ CP-307).
Inter channel Gain Mism atch
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
Gain D r ift
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Cr osstalk (EIAJ m ethod)
Ratio of response on one channel with a zero input to a full-scale
1 kHz sine-wave input on the other channel, expressed in decibels.
Total H ar m onic D istor tion + Noise (TH D +N)
T he ratio of the root-mean-square (rms) value of a full-scale
fundamental input signal to the rms sum of all other spectral
components in the passband, expressed in decibels (dB) and
percentage.
Inter channel P hase D eviation
Difference in output sampling times between stereo channels,
expressed as a phase difference in degrees between 1 kHz inputs.
P assband
P ower Supply Rejection
T he region of the frequency spectrum unaffected by the attenu-
ation of the digital interpolation filter.
With zero input, signal present at the output when a 300 mV
p-p signal is applied to power supply pins, expressed in decibels
of full scale.
P assband Ripple
T he peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the passband, ex-
pressed in decibels.
Gr oup D elay
Intuitively, the time interval required for an input pulse to ap-
pear at the converter’s output, expressed in seconds (s). More
precisely, the derivative of radian phase with respect to radian
frequency at a given frequency.
Stopband
T he region of the frequency spectrum attenuated by the digi-
tal interpolation filter to the degree specified by “stopband
attenuation.”
Gr oup D elay Var iation
T he difference in group delays at different input frequencies.
Specified as the difference between the largest and the smallest
group delays in the passband, expressed in microseconds (µs).
P IN D ESCRIP TIO NS
D igital Audio Ser ial Input Inter face
P in Nam e Num ber I/O D escription
Ser ial Contr ol P or t Inter face
P in Nam e Num ber I/O D escription
SDAT A
12
I
Serial input, MSB first, contain-
ing two channels of 16 or 18 bits
of twos complement data per
channel.
CDAT A
CCLK
20
I
I
I
Serial control input, MSB first,
containing 8 bits of unsigned
data per channel. Used for
specifying channel specific
attenuation and mute.
BCLK
14
I
Bit clock input for input data.
Need not run continuously; may
be gated or used in a burst
fashion.
19
Control clock input for control
data. Control input data must
be valid on the rising edge of
CCLK. CCLK may be continu-
ous or gated.
LRCLK
13
9
I
I
Left/right clock input for input
data. Must run continuously.
IDPM0
Input serial data port mode
control zero. With IDPM1,
defines one of four serial input
modes.
CLAT CH 21
Latch input for control data. This
input is rising edge sensitive.
IDPM1
10
8
I
I
Input serial data port mode con-
trol one. With IDPM0, defines
one of four serial input modes.
18/16
18-bit or 16-bit input data mode
control. Connect this signal HI
for 18-bit input mode, LO for
16-bit input mode.
REV. A
–5–
AD1859
P IN D ESCRIP TIO NS
Analog Signals
Contr ol and Clock Signals
P in Nam e Num ber I/O D escription
P in Nam e Num ber
I/O D escription
PD/RST
11
I
Power down/reset. T he AD1859 is
FILT
28
O
Voltage reference filter capacitor
placed in a low power consumption
“sleep” mode when this pin is held
LO. T he AD1859 is reset on the
rising edge of this signal. T he serial
control port registers are reset to
their default values. Connect HI
for normal operation.
connection. Bypass and decouple
the voltage reference with paral-
lel 10 µF and 0.1 µF capacitors
to the FGND pin.
FGND
27
1
I
Voltage reference filter ground.
Use exclusively for bypassing and
decoupling of the FILT pin
(voltage reference).
DEEMP
2
I
De-emphasis. An external analog de-
emphasis circuit network is enabled
when this input signal is HI. T his
circuit is typically used to impose a
50/15 µs (or perhaps the CCIT T
J.17) response characteristic on the
output audio spectrum.
CMOUT
O
Voltage reference common-mode
output. Should be decoupled
with 10 µF capacitor to the AGND
pin or plane. This output is available
externally for dc-coupling and level-
shifting. CMOUT should not have
any signal dependent load, or where
it will sink or source current.
MUT E
7
I
I
Mute. Assert HI to mute both
stereo analog outputs of the AD1859.
Deassert LO for normal operation.
OUT L
OUT R
EMPL
4
O
O
O
Left channel line level analog output.
Right channel line level analog output.
XT ALI/
MCLK
25
3
16
Crystal input or master clock input.
Connect to one side of a quartz
crystal to this input, or connect to
an external clock source to over-
drive the on-chip oscillator.
De-emphasis switch connection
for the left channel. Can be left
unconnected if de-emphasis is not
required in the target application.
XT ALO
15
O
Crystal output. Connect to other
side of a quartz crystal. Do not con-
nect if using the XTALI/MCLK
pin with an external clock source.
EMPR
26
O
De-emphasis switch connection
for the right channel. Can be left
unconnected if de-emphasis is not
required in the target application.
P ower Supply Connections and Miscellaneous
P in Nam e Num ber I/O D escription
AVDD
23
I
Analog Power Supply. Connect
to analog +5 V supply.
AGND
DVDD
6
I
I
Analog Ground.
17
Digital Power Supply. Connect
to digital +5 V supply.
DGND
NC
18
I
Digital Ground.
5, 22, 24
No Connect. Reserved. Do not
connect.
–6–
REV. A
AD1859
(continued from page 1)
the fourth stage is a second-order comb filter. T he FIR filter
implementation is multiplier-free, i.e., the multiplies are per-
formed using shift-and-add operations.
T he AD1859 has a simple but very flexible serial data input port
that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers and sample rate converters.
T he serial data input port can be configured in left-justified,
I2S-justified, right-justified and DSP serial port compatible
modes. T he AD1859 accepts 16- or 18-bit serial audio data in
MSB-first, twos-complement format. A power-down mode is
offered to minimize power consumption when the device is inac-
tive. T he AD1859 operates from a single +5 V power supply. It
is fabricated on a single monolithic integrated circuit using a
0.6 µM CMOS double polysilicon, double metal process, and is
housed in 28-pin SOIC and SSOP packages for operation over
the temperature range –40°C to +105°C.
Multibit Sigm a-D elta Modulator
The AD1859 employs a four-bit sigma-delta modulator. Whereas a
traditional single bit sigma-delta modulator has two levels of quan-
tization, the AD1859’s has 17 levels of quantization. T raditional
single bit sigma-delta modulators sample the input signal at 64
times the input sample rate; the AD1859 samples the input sig-
nal at nominally 128 times the input sample rate. T he addi-
tional quantization levels combined with the higher oversampling
ratio means that the AD1859 DAC output spectrum contains
dramatically lower levels of out-of-band noise energy, which is a
major stumbling block with more traditional single bit sigma-
delta architectures. T his means that the post-DAC analog re-
construction filter has reduced transition band steepness and
attenuation requirements, which equates directly to lower phase
distortion. Since the analog filtering generally establishes the
noise and distortion characteristic of the DAC, the reduced
requirements translate into better audio performance.
TH EO RY O F O P ERATIO N
T he AD1859 offers the advantages of sigma-delta conversion
architectures (no component trims, low cost CMOS process
technology, superb low level linearity performance) with the
advantages of conventional multibit R-2R resistive ladder audio
DACs (no requirement for any high frequency synchronous master
clocks [e.g., 256 or 384 × FS] continuously variable sample rate
support, jitter tolerance, low output noise, etc.).
Multibit sigma-delta modulators bring an additional benefit:
they are essentially free of stability (and therefore potential loop
oscillation) problems. T hey are able to use a wider range of the
voltage reference, which can increase the overall dynamic range
of the converter.
T he use of a multibit sigma-delta modulator means that the
AD1859 generates dramatically lower amounts of out-of-band
noise energy, which greatly reduces the requirement on post
DAC filtering. T he required post-filtering is integrated on the
AD1859. T he AD1859’s multibit sigma-delta modulator is also
highly immune to digital substrate noise.
T he conventional problem which limits the performance of
multibit sigma delta converters is the nonlinearity of the passive
circuit elements used to sum the quantization levels. Analog
Devices has developed (and been granted patents on) a revolu-
tionary architecture which overcomes the component linearity
problem that otherwise limits the performance of multibit sigma
delta audio converters. T his new architecture provides the
AD1859 with the same excellent differential nonlinearity and
linearity drift (over temperature and time) specifications as
single bit sigma-delta DACs.
T he digital phase locked loop feature gives the AD1859 an un-
precedented jitter rejection feature. T he bandwidth of the first
order loop filter is 15 Hz; jitter components on the input
left/right clock are attenuated by 6 dB per octave above and be-
low 15 Hz. Jitter on the crystal time base or MCLK input is re-
jected as well (by virtue of the on-chip switched capacitor filter),
but this clock should be low jitter because it is used by the DAC
to convert the audio from the discrete time (sampled) domain to
the continuous time (analog) domain. T he AD1859 includes an
on-chip oscillator, so that the user need only provide an inexpen-
sive quartz crystal or ceramic resonator as an external time base.
T he AD1859’s multibit modulator has another important ad-
vantage; it has a high immunity to substrate digital noise. Sub-
strate noise can be a significant problem in mixed-signal
designs, where it can produce intermodulation products that
fold down into the audio band. T he AD1859 is approximately
eight times less sensitive to digital substrate noise (voltage refer-
ence noise injection) than equivalent single bit sigma-delta
modulator based DACs.
Ser ial Audio D ata Inter face
T he serial audio data interface uses the bit clock (BCLK) simply
to clock the data into the AD1859. T he bit clock may, there-
fore, be asynchronous to the L/R clock. T he left/right clock
(LRCLK) is both a framing signal, and the sample frequency input
to the digital phase locked loop. The left/right clock (LRCLK) is
the signal that the AD1859 actually uses to determine the input
sample rate, and it is the jitter on LRCLK that is rejected by the
digital phase locked loop. T he SDAT A input carries the serial
stereo digital audio in MSB first, twos-complement format.
D ither Gener ator
T he AD1859 includes an on-chip dither generator, which is in-
tended to further reduce the quantization noise introduced by
the multibit DAC. T he dither has a triangular Probability Dis-
tribution Function (PDF) characteristic, which is generally con-
sidered to create the most favorable noise shaping of the residual
quantization noise. T he AD1859 is among the first low cost, IC
audio DACs to include dithering.
D igital Inter polation Filter
T he purpose of the interpolator is to “oversample” the input
data, i.e., to increase the sample rate so that the attenuation re-
quirements on the analog reconstruction filter are relaxed. T he
AD1859 interpolator increases the input data sample rate by a
variable factor depending on the sample frequency of the incom-
ing digital audio. T he interpolation is performed using a multi-
stage FIR digital filter structure. T he first stage is a droop
equalizer; the second and third stages are half-band filters; and
Analog Filter ing
T he AD1859 includes a second-order switched capacitor dis-
crete time low-pass filter followed by a first-order analog con-
tinuous time low-pass filter. T hese filters eliminate the need for
any additional off-chip external reconstruction filtering. T his
on-chip switched capacitor analog filtering is essential to reduce
the deleterious effects of any remaining master clock jitter.
REV. A
–7–
AD1859
O ption for Analog D e-em phasis P r ocessing
T he phase detector automatically switches the loop filter into
“slow” mode as phase lock is gradually obtained. T he loop
bandwidth is 15 Hz in slow mode. Since the loop filter is first
order, the digital PLL will reject jitter on the left/right clock
above 15 Hz, with an attenuation of 6 dB per octave. T he jitter
rejection frequency response is shown in Figure 1.
T he AD1859 includes three pins for implementing an external
analog 50/15 µs (or possibly the CCIT T J. 17) de-emphasis fre-
quency response characteristic. A control pin DEEMP (Pin 2)
enables de-emphasis when it is asserted HI. T wo analog out-
puts, EMPL (Pin 3) and EMPR (Pin 26) are used to switch the
required analog components into the output stage of the AD1859.
An analog implementation of de-emphasis is superior to a digital
implementation in several ways. It is generally lower noise, since
digital de-emphasis is usually created using recursive IIR filters,
which inject limit cycle noise. Also the digital de-emphasis is be-
ing applied in front of the primary analog noise generation source,
the DAC modulator, and its high frequency noise contributions
are not attenuated. An analog de-emphasis circuit is down-
stream from the relatively “noisy” DAC modulator and thus pro-
vides a more effective noise reduction role (which was the original
intent of the emphasis/de-emphasis scheme). A final key advan-
tage of analog de-emphasis is that it is sample rate invariant, so
that users can fully exploit the sample rate range of the AD1859
and simultaneously use de-emphasis. Digital implementations gen-
erally only support fixed, standard sample rates.
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
0
15 30 60 120 240 480 960 1920 3840 7680 15360
Hz ABOVE OR BELOW THE SAMPLE FREQUENCY
D igital P hase Locked Loop
T he digital PLL is adaptive, and locks to the applied sample rate
(on the LRCLK Pin 13) in 100 ms to 200 ms. T he digital PLL
is initially in “fast” mode, with a wide lock capture bandwidth.
Figure 1. Digital PLL J itter Rejection
O P ERATING FEATURES
Ser ial D ata Input P or t
Ser ial Input P or t Modes
T he AD1859 uses the frequency of the left/right input clock to
determine the input sample rate. LRCLK must run continu-
ously and transition twice per stereo sample period (except in
the left-justified DSP serial port style mode, when it transitions
four times per stereo sample period). T he bit clock (BCLK) is
edge sensitive and may be used in a gated or burst mode (i.e., a
stream of pulses during data transmission followed by periods of
inactivity). T he bit clock is only used to write the audio data
into the serial input port. It is important that the left/right clock
is “clean” with monotonic rising and falling edge transitions and
no excessive overshoot or undershoot which could cause false
clock triggering of the AD1859.
T he AD1859 uses two multiplexed input pins to control the
mode configuration of the input data port. IDPM0 and IDPM1
program the input data port mode as follows:
ID P M1
ID P M0
Serial Input P ort Mode
LO
LO
HI
HI
LO
HI
LO
HI
Right-Justified (See Figure 2)
I2S-Justified (See Figure 3)
Left-Justified (See Figure 4)
Left-Justified DSP Serial Port Style
(See Figure 5)
Figure 2 shows the right-justified mode. LRCLK is HI for the
left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. T he MSB is delayed 14-bit clock periods
(in 18-bit input mode) or 16-bit clock periods (in 16-bit input
mode) from an LRCLK transition, so that when there are 64
BCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.
T he AD1859’s flexible serial data input port accepts data in
twos-complement, MSB-first format. T he left channel data
field always precedes the right channel data field. T he input
data consists of either 16 or 18 bits, as established by the 18/16
input control (Pin 8). All digital inputs are specified to T T L
logic levels. T he input data port is configured by control pins.
LRCLK
RIGHT CHANNEL
LEFT CHANNEL
INPUT
BCLK
INPUT
SDATA
INPUT
LSB+2 LSB+1
LSB
MSB
LSB+2 LSB+1
MSB-1 MSB-2
LSB
MSB
MSB-2
LSB
MSB-1
Figure 2. Right-J ustified Mode
–8–
REV. A
AD1859
Figure 3 shows the I2S-justified mode. LRCLK is LO for the left
channel, and HI for the right channel. Data is valid on the rising
edge of BCLK. The MSB is left-justified to an LRCLK transition
but with a single BCLK period delay. T he I2S-justified mode
can be used in either the 16-bit or the 18-bit input mode.
Note that in 16-bit input mode, the AD1859 is capable of a 32
× FS BCLK frequency “packed mode” where the MSB is left-
justified to an LRCLK transition, and the LSB is right-justified
to an LRCLK transition. LRCLK is HI for the left channel,
and LO for the right channel. Data is valid on the rising edge of
BCLK. Packed mode can be used when the AD1859 is pro-
grammed in either right-justified or left-justified mode. Packed
mode is shown in Figure 6.
Figure 4 shows the left-justified mode. LRCLK is HI for the
left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. T he MSB is left-justified to an LRCLK
transition, with no MSB delay. T he left-justified mode can be
used in either the 16-bit or the 18-bit input mode.
Ser ial Contr ol P or t
T he AD1859 serial control port is SPI compatible. SPI
(Serial Peripheral Interface) is a serial port protocol popularized
by Motorola’s family of microcomputer and microcontroller
products. T he write-only serial control port gives the user ac-
cess to channel specific mute and attenuation. T he AD1859
serial control port consists of three signals, control clock CCLK
(Pin 19), control data CDAT A (Pin 20), and control latch
CLAT CH (Pin 21). T he control data input (CDAT A) must be
valid on the control clock (CCLK) rising edge, and the control
clock (CCLK) must only make a LO to HI transition when
there is valid data. T he control latch (CLAT CH) must make a
LO to HI transition after the LSB has been clocked into the
AD1859, while the control clock (CCLK) is inactive. T he tim-
ing relation between these signals is shown in Figure 7.
Figure 5 shows the left-justified DSP serial port style mode.
LRCLK must pulse HI for at least one bit clock period before
the MSB of the left channel is valid, and LRCLK must pulse HI
again for at least one bit clock period before the MSB of the
right channel is valid. Data is valid on the falling edge of
BCLK. T he left-justified DSP serial port style mode can be
used in either the 16-bit or the 18-bit input mode. Note that in
this mode, it is the responsibility of the DSP to ensure that the
left data is transmitted with the first LRCLK pulse, and that the
right data is transmitted with the second LRCLK pulse, and
that synchronism is maintained from that point forward.
LRCLK
LEFT CHANNEL
INPUT
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB
MSB-1 MSB-2
LSB+2 LSB+1
LSB
LSB+2 LSB+1
MSB
MSB-1 MSB-2
LSB
MSB
Figure 3. I2S-J ustified Mode
LRCLK
INPUT
RIGHT CHANNEL
LEFT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB
MSB-1 MSB-2
LSB+2 LSB+1
LSB
MSB
MSB-1 MSB-2
LSB+2 LSB+1
LSB
MSB
MSB-1
Figure 4. Left-J ustified Mode
LRCLK
INPUT
RIGHT CHANNEL
LEFT CHANNEL
BCLK
INPUT
SDATA
INPUT
LSB+2 LSB+1
LSB
MSB
MSB-1
MSB
MSB-1
LSB+2 LSB+1
LSB
MSB
MSB-1
Figure 5. Left-J ustified DSP Serial Port Style Mode
LRCLK
INPUT
RIGHT CHANNEL
LEFT CHANNEL
BCLK
INPUT
SDATA
INPUT
LSB+2 LSB+1
LSB
MSB
MSB-1 MSB-2
LSB+2 LSB+1
LSB
MSB
MSB-1
LSB
MSB
MSB-1 MSB-2
Figure 6. 32 × FS Packed Mode
REV. A
–9–
AD1859
CCLK
CDATA
D5
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
MSB
LSB
MSB
CLATCH
Figure 7. Serial Control Port Tim ing
MSB
LSB
DATA7
DATA6
Mute
DATA5
Atten5
DATA4
Atten4
DATA3
Atten3
DATA2
Atten2
DATA1
Atten1
DATA0
Atten0
LEFT/RIGHT
Right Channel = HI Mute = HI
Left Channel = LO Normal = LO
00 0000 = 0.0dB
00 0001 = –1.0dB
00 0010 = –2.0dB
00 0011 = –3.0dB
00 0100 = –4.0dB
00 0101 = –5.0dB
00 0110 = –6.0dB
00 0111 = –7.0dB
00 1000 = –8.0dB
*
*
*
11 1101 = –61.0dB
11 1110 = –62.0dB
11 1111 = –63.0dB
Figure 8. Serial Control Bit Definitions
T he serial control port is byte oriented. T he data is MSB first,
and is unsigned. T here is a control register for the left channel
and a control register for the right channel, as distinguished by
the MSB (DAT A7). T he bits are assigned as shown in Figure 8.
Highest Sample Rate = Master Clock Frequency ÷ 512
T he lowest sample rate supported can be computed as follows:
Lowest Sample Rate = Master Clock Frequency ÷ 1024
The left channel control register and the right channel control reg-
ister have identical power up and reset default settings. DATA6,
the Mute control bit, reset default state is LO, which is the nor-
mal (nonmuted) setting. DATA5:0, the Atten5 through Atten0
control bits, have a reset default value of 00 0000, which is an
attenuation of 0.0 dB (i.e., full scale, no attenuation). The intent
with these reset defaults is to enable AD1859 applications with-
out requiring the use of the serial control port. For those users
that do not use the serial control port, it is still possible to mute
the AD1859 output by using the external MUT E (Pin 7) signal.
It is recommended that the output be muted for approximately
1000 input sample periods during power-up or following any
radical sample rate change (>5%) to allow the digital phase
locked loop to settle.
AD1859
AD1859
XTALI/MCLK
XTALO
XTALI/MCLK
XTALO
NC
20-64pF
27MHz CRYSTAL CONNECTION
20-64pF
27MHz
27MHz
27MHz OSCILLATOR CONNECTION
Figure 9. Crystal and Oscillator Connections
Figure 10 illustrates these relations. As can be seen in Figure 10,
a 27 MHz MCLK or crystal frequency supports audio sample
rates from approximately 28 kHz to 52 kHz.
76
Note that the serial control port timing is asynchronous to the
serial data input port timing. Changes made to the attenuator
level will be updated on the next edge of the LRCLK after the
CLAT CH write pulse. T he AD1859 has been designed to re-
solve the potential for metastability between the LRCLK edge
and the CLAT CH write pulse rising edge. T he attenuator set-
ting is guaranteed to be valid even if the LRCLK edge and the
CLAT CH rising edge occur essentially simultaneously.
HIGHEST
L/R SAMPLE RATE
68
(MCLK/512)
60
52
LOWEST
L/R SAMPLE RATE
(MCLK/1024)
44
36
28
20
O n-Chip O scillator and Master Clock
T he asynchronous master clock of the AD1859 can be supplied
by either an external clock source applied to XT ALI/MCLK or
by connecting a crystal across the XT ALI/MCLK and XT ALO
pins, and using the on-chip oscillator. If a crystal is used, it
should be fundamental-mode and parallel-tuned. Figure 9
shows example connections.
18
20
22
24
26
28
30
32
34
36
XTAL/MCLK FREQUENCY – MHz
Figure 10. MCLK Frequency vs. L/R Clock Frequency
Mute and Attenuation
T he range of audio sample rates (as determined from the
LRCLK input) supported by the AD1859 is a function of the
master clock rate (i.e., the crystal frequency or external clock
source frequency) applied. T he highest sample rate supported
can be computed as follows:
T he AD1859 offers two methods of muting the analog output.
By asserting the MUT E (Pin 7) signal HI, both the left channel
and the right channel are muted. As an alternative, the user can
assert the mute bit in the serial control registers HI for indi-
vidual mute of either the left channel or the right channel. T he
–10–
REV. A
AD1859
AD1859 has been designed to minimize pops and clicks when
muting and unmuting the device. T he AD1859 includes a zero
crossing detector which attempts to implement attenuation
changes on waveform zero crossings only. If a zero crossing is
not found within 1024 input sample periods (approximately
23 ms at 44.1 kHz), the attenuation change is made regardless.
AP P LICATIO NS ISSUES
Inter face to MP EG Audio D ecoder s
Figure 11 shows the suggested interface to the Analog Devices
ADSP-21xx family of DSP chips, for which several MPEG
audio decode algorithms are available. The ADSP-21xx supports
16 bits of data using a left-justified DSP serial port style format.
O utput D r ive, Buffer ing and Loading
T he AD1859 analog output stage is able to drive a 2 kΩ load. If
lower impedance loads must be driven, an external buffer stage
such as the Analog Devices SSM2142 should be used. T he
analog output is generally ac coupled with a 10 µF capacitor,
even if the optional de-emphasis circuit is not used, as shown in
Figure 17. It is possible to dc couple the AD1859 output into an
op amp stage using the CMOUT signal as a bias point.
SCLK
RFS
TFS
DT
14 BCLK
13
NC
NC
LRCLK
ADSP-21xx
AD1859
SDATA
IDPM0
IDPM1
12
9
HI
10
8
HI
DR
18/16
LO
O n-Chip Voltage Refer ence
Figure 11. Interface to ADSP-21xx
T he AD1859 includes an on-chip voltage reference that estab-
lishes the output voltage range. T he nominal value of this refer-
ence is +2.25 V which corresponds to a line output voltage
swing of 3 V p-p. T he line output signal is centered around a
voltage established by the CMOUT (common mode) output
(Pin 1). T he reference must be bypassed both on the FILT in-
put (Pin 28) with 10 µF and 0.1 µF capacitors, and on the
CMOUT output (Pin 1) with a 10 µF and 0.1 µF capacitors, as
shown in Figures 17 and 18. T he FILT pin must use the
FGND ground, and the CMOUT pin must use the AGND
ground. T he on-chip voltage reference may be overdriven with
an external reference source by applying this voltage to the
FILT pin. CMOUT and FILT must still be bypassed as shown
in Figures 17 and 18. An external reference can be useful to
calibrate multiple AD1859 DACs to the same gain. Reference
bypass capacitors larger than those suggested can be used to im-
prove the signal-to-noise performance of the AD1859.
Figure 12 shows the suggested interface to the T exas Instru-
ments T MS320AV110 MPEG audio decoder IC. T he
T MS320AV110 supports 18 bits of data using a right-justified
output format.
SCLK
LRCLK
14 BCLK
TEXAS
INSTRUMENTS
13
LRCLK
AD1859
TMS320AV110
SDATA
IDPM0
IDPM1
12
9
PCMDATA
PCMCLK
LO
LO
HI
10
8
48 x F
TO
1536 x F
S
18/16
S
Figure 12. Interface to TMS320AV110
Figure 13 shows the suggested interface to the LSI Logic L64111
MPEG audio decoder IC. T he L64111 supports 16 bits of data
using a left-justified output format.
P ower D own and Reset
T he PD/RST input (Pin 11) is used to control the power con-
sumed by the AD1859. When PD/RST is held LO, the AD1859
is placed in a low dissipation power-down state. When PD/RST
is brought HI, the AD1859 becomes ready for normal operation.
T he master clock (XT ALI/MCLK, Pin 16) must be running for
a successful reset or power-down operation to occur. The PD/RST
signal must be LO for a minimum of four master clock periods
(approximately 150 ns with a 27 MH z XT ALI/MCLK
frequency).
SCLKO
LRCLKO
SERO
14 BCLK
LSI LOGIC
L64111
13
LRCLK
AD1859
SDATA
IDPM0
IDPM1
12
9
LO
HI
SYSCLK
10
8
384 x F
OR
S
18/16
LO
512 x F
S
Figure 13. Interface to L64111
When the PD/RST input (Pin 11) is asserted brought HI, the
AD1859 is reset. All registers in the AD1859 digital engine (se-
rial data port, interpolation filter and modulator) are zeroed, and
the amplifiers in the analog section are shorted during the reset
operation. T he two registers in the serial control port are initial-
ized to their default values. T he user should wait 100 ms after
bringing PD/RST HI before using the serial data input port and
the serial control input port in order for the digital phase locked
loop to re-acquire lock. T he AD1859 has been designed to
minimize pops and clicks when entering and exiting the power-
down state.
Figure 14 shows the suggested interface to the Philips SAA2500
MPEG audio decoder IC. T he SAA2500 supports 18 bits of
data using an I2S compatible output format.
14 BCLK
SCK
WS
PHILIPS
13
12
9
LRCLK
AD1859
SAA2500
SDATA
SD
IDPM0
IDPM1
HI
LO
HI
FSCLKIN
10
8
256 x F
OR
S
18/16
384 x F
S
Contr ol Signals
T he IDPM0, IDPM1, 18/16, and DEEMP control inputs are
normally connected HI or LO to establish the operating state of
the AD1859. T hey can be changed dynamically (and asynchro-
nously to the LRCLK and the master clock) as long as they are
stable before the first serial data input bit (i.e., the MSB) is pre-
sented to the AD1859.
Figure 14. Interface to SAA2500
REV. A
–11–
AD1859
Figure 15 shows the suggested interface to the Zoran ZR38000
DSP chip, which can act as an MPEG audio or AC-3 audio
decoder. T he ZR38000 supports 16 bits of data using a left-
justified output format.
14 BCLK
DA-BCK
DA-LRCK
DA-DATA
DA-XCK
C-CUBE
CL480
13
LRCLK
AD1859
SDATA
IDPM0
IDPM1
12
9
LO
LO
LO
10
8
256 x F
OR
S
18/16
14 BCLK
SCKB
WSB
384 x F
S
ZORAN
13
LRCLK
AD1859
ZR38000
SDATA
IDPM0
IDPM1
12
9
SDB
LO
HI
SCKIN
Figure 16. Interface to CL480
Layout and D ecoupling Consider ations
10
8
256 x F
S
18/16
LO
T he recommended decoupling, bypass circuits for the AD1859
are shown in Figure 17. Figure 17 illustrates a connection dia-
gram for systems which do not require de-emphasis support.
T he recommended circuit connection for system including de-
emphasis is shown in Figure 18.
Figure 15. Interface to ZR38000
Figure 16 shows the suggested interface to the C-Cube
Microsystems CL480 MPEG system decoder IC. T he CL480
supports 16 bits of data using a right-justified output format.
+5V ANALOG
20-64pF
20-64pF
1µF
µCONTROLLER
0.1µF
27MHz
10µF
0.1µF
10µF
23
AV
21
6
20
19
16
15
28
27
1
FILT
FGND
CCLK CLATCH XTALI/MCLK XTALO
AGND CDATA
DD
12 SDATA
14 BLCK
BIAS VOLTAGE
FOR EXTERNAL USE
CMOUT
0.1µF
10µF
5
DSP OR
AUDIO
NC
13
9
LRCLK
IDPM0
IDPM1
18/16
24
4
AD1859
NC
DECODER
LEFT LINE
OUTPUT
OUTL
10
8
1kΩ
1kΩ
2.2nF
2.2nF
3
EMPL
OUTR
EMPR
10µF
RIGHT LINE
OUTPUT
25
26
DV
NC
22
DEEMP
2
MUTE
7
DGND
18
PD/RST
DD
17
11
30Ω
0.01µF
1µF
(CHIP RESISTOR
PREFERRED)
µCONTROLLER
+5V DIGITAL
Figure 17. Recom m ended Circuit Connection (Without De-em phasis)
+5V ANALOG
1µF
20-64pF
20-64pF
µCONTROLLER
0.1µF
27MHz
10µF
0.1µF
20
23
AV
21
6
19
16
15
28
27
1
FILT
FGND
CCLK CLATCH XTALI/MCLK XTALO
AGND CDATA
DD
12 SDATA
14 BLCK
BIAS VOLTAGE
CMOUT
FOR EXTERNAL USE
10µF
0.1µF
5
DSP OR
AUDIO
DECODER
NC
13
9
LRCLK
IDPM0
IDPM1
18/16
24
4
AD1859
NC
1µF
LEFT LINE
OUTPUT
OUTL
10
8
2.2nF
1kΩ
1kΩ
470Ω
3
10MΩ
EMPL
OUTR
EMPR
33nF
NPO
25
26
1µF
RIGHT LINE
OUTPUT
DV
DEEMP
2
MUTE
7
DGND
18
NC
22
PD/RST
DD
2.2nF
470Ω
17
11
10MΩ
33nF
NPO
30Ω
0.01µF
1µF
(CHIP RESISTOR
PREFERRED)
µCONTROLLER
OPTIONAL DE-EMPHASIS
CIRCUIT SHOWN
+5V DIGITAL
Figure 18. Recom m ended Circuit Connection (With De-em phasis)
–12–
REV. A
AD1859
tDBH
tDBP
P CB and Gr ound P lane Recom m endations
BCLK
T he AD1859 ideally should be located above a split ground
plane, with the digital pins over the digital ground plane, and
the analog pins over the analog ground plane. T he split should
occur between Pins 6 and 7 and between Pins 22 and 23 as
shown in Figure 19. T he ground planes should be tied together
at one spot underneath the center of the package with an ap-
proximately 3 mm trace. T his ground plane strategy minimizes
RF transmission and reception as well as maximizes the AD1859’s
analog audio performance.
tDLS
tDBL
LRCLK
tDLH
tDDS
SDATA
LEFT-JUSTIFIED
DSP SERIAL
PORT STYLE
MODE
MSB
tDDH
MSB-1
Figure 21. Serial Data Input Port Tim ing DSP Serial
Port Style
T he serial control port timing is shown in Figure 22. T he mini-
mum control clock HI pulse width is tCCH, and the minimum
control clock LO pulse width is tCCL. T he minimum control
clock period is tCCP. T he control data minimum setup time is
1
2
CMOUT
DEEMP
EMPL
28 FILT
27 FGND
ANALOG
GROUND PLANE
3
26
25
24
23
22
EMPR
OUTR
OUTL
4
t
CSU, and the minimum control data hold time is tCHD. T he
5
NC
AGND
MUTE
18/16
NC
minimum control latch delay is tCLD, the minimum control latch
LO pulse width is tCLL, and the minimum control latch HI pulse
AV
DD
6
7
NC
width is tCLH
CCLK
.
8
21 CLATCH
CDATA
9
20
19 CCLK
IDPM0
IDPM1
tCCP
tCCL
10
11
DIGITAL
GROUND PLANE
18
17
16
PD/RST
DGND
SDATA 12
13
DV
DD
tCCH
tCSU
XTALI/MCLK
LRCLK
BCLK 14
15 XTALO
CDATA
LSB
tCLH
tCHD
tCLD
Figure 19. Recom m ended Ground Plane
TIMING D IAGRAMS
CLATCH
tCLL
T he serial data port timing is shown in Figures 20 and 21. T he
minimum bit clock HI pulse width is tDBH , and the minimum bit
clock LO pulse width is tDBL. T he minimum bit clock period is
Figure 22. Serial Control Port Tim ing
T he master clock (or crystal input) and power down/reset tim-
ing is shown in Figure 23. T he minimum MCLK period is tMCP
which determines the maximum MCLK frequency at FMC. T he
minimum MCLK HI and LO pulse widths are tMCH and tMCL
respectively. T he minimum reset LO pulse width is tPDRP (four
t
DBP. T he left/right clock minimum setup time is tDLS, and the
,
left/right clock minimum hold time is tDLH. T he serial data mini-
mum setup time is tDDS, and the minimum serial data hold time
,
is tDDH
.
XT ALI/MCLK periods) to accomplish a successful AD1859 re-
set operation.
tDBH
tDBP
BCLK
tDBL
tDLS
t
t
MCH
MCP
LRCLK
XTALI/MCLK
SDATA
LEFT-
JUSTIFIED
MODE
tDDS
tDDH
t
MCL
MSB
MSB-1
PD/RST
t
SDATA
2
PDRP
tDDS
I
S-
MSB
JUSTIFIED
MODE
tDDS
tDDS
tDDH
Figure 23. MCLK and Power Down/Reset Tim ing
SDATA
RIGHT-
MSB
LSB
JUSTIFIED
MODE
tDDH
tDDH
Figure 20. Serial Data Port Tim ing
REV. A
–13–
AD1859
TYP ICAL P ERFO RMANCE
20 Hz to 24 kHz bandwidth, while the analog performance is
specified over a 20 Hz to 20 kHz bandwidth (i.e., the AD1859
performs slightly better than the plots indicate). Figure 28
shows the power supply rejection performance of the AD1859.
T he channel separation performance of the AD1859 is shown in
Figure 29. T he AD1859’s low level linearity is shown in Figure
30. T he digital filter transfer function is shown in Figure 31.
Figures 24 through 27 illustrate the typical analog performance
of the AD1859 as measured by an Audio Precision System One.
Signal-to-Noise (dynamic range) and T HD+N performance is
shown under a range of conditions. Note that there is a small
variance between the AD1859 analog performance specifica-
tions and some of the performance plots. T his is because the
Audio Precision System One measures T HD and noise over a
0
0
–10
–20
–30
–40
–50
–60
–70
F
= 44.1kHz
FS = 44.1kHz
–10
S
THD+N vs dBFS @ 1kHz
–20
FFT @ –0.5dBFS
–30
–40
–50
–60
–80
–90
–70
–100
–110
–120
–130
–140
–80
–90
–100
–110
0
2k
4k
6k
8k
10k 12k 14k 16k 18k 20k
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
AMPLITUDE – dBFS
0
FREQUENCY – Hz
Figure 24. 1 kHz Tone at –0.5 dBFS (16K-Point FFT)
Figure 27. THD+N vs. Am plitude at 1 kHz
0
–40
–10
–20
–30
–40
–50
–60
–70
F
= 44.1kHz
S
–45
–50
FFT @ –10dBFS
LEFT CHANNEL
RIGHT CHANNEL
–55
–60
–80
–90
–65
–70
–75
–80
–100
–110
–120
–130
–140
0
2k
4k
6k
8k
0
2k
4k
6k
8k
10k 12k 14k 16k 18k 20k
10k 12k 14k 16k 18k 20k
FREQUENCY – Hz
FREQUENCY – Hz
Figure 28. Power Supply Rejection to 300 m V p-p on AVDD
Figure 25. 1 kHz Tone at –10 dBFS (16K-Point FFT)
0
0
F
= 44.1kHz
–10
S
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
F
= 44.1kHz
S
THD+N vs FREQ @ –0.5dBFS
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
2k
4k
6k
8k
10k 12k 14k 16k 18k 20k
0
2k
4k
6k
8k
FREQUENCY – Hz
10k 12k 14k 16k 18k 20k
FREQUENCY – Hz
Figure 29. Channel Separation vs. Frequency at –0.5 dBFS
–14–
REV. A
Figure 26. THD+N vs. Frequency at –0.5 dBFS
AD1859
0
0
–10
–20
–30
–40
–50
–60
–70
–10
–20
–30
–40
100
90
–50
–60
–70
–80
10
–90
–80
–90
0%
–100
–110
–100
–110
–120
–130
–140
–120
–130
–140
–150
–160
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
2k
4k
6k
8k 10k 12k 14k 16k 18k 20k 22k
FREQUENCY – Hz
F
S
Figure 31. Digital Filter Signal Transfer Function to
3.5 × FS
Figure 30. 1 kHz Tone at –90 dBFS (16K-Point FFT) Includ-
ing Tim e Dom ain Plot Bandlim ited to 22 kHz
Application Cir cuits
perfectly acceptable. MPEG audio decoders are insensitive to
this clock jitter (using these signals to clock audio data from their
output serial port, and perhaps to decrement their audio/video
synchronization timer), while the AD1859 will reject the left/right
clock jitter by virtue of its on-chip digital phase locked loop.
Contact Analog Devices Computer Products Division Customer
Support at (617) 461-3881 or cpd_support@analog.com for more
information on this NCO circuit.
Figure 32 illustrates a 600 ohm line driver using the Analog
Devices SSM2017 and SSM2142 components. Figure 33
illustrates a “Numerically Controlled Oscillator” (NCO) that
can be implemented in programmable logic or a system ASIC to
provide the synchronous bit and left/right clocks from 27 MHz
for MPEG audio decoders. Note that the bit clock and left/right
clock outputs are highly jittered, but this jitter should be
C5
+15V
100n
C11
100n
C12
100n
+5VDD
+5VCC
C6
100n
+15V
7
6
17
23
+V
5Vrms
4
3
8
7
VIN
DVDD
AVDD
+OUT
+SENSE
1Vrms
1Vrms
3
1
4
3
+IN
14
13
OUTL
EMPL
V+
BCLK
RG1
6
U4
SSM2142P
LRCLK
SDATA
IDPM1
IDPM0
R1, 2k49
OUT
5
12
10
9
8
2
REF
V–
RG2
–IN
2
1
U2
SSM2017P
–SENSE
–OUT
4
GND
8
AD1859-JR
–V
18/16
25
26
C8
100n
OUTR
EMPR
R3
600Ω
21
20
19
–15V
+15V
5
J1 P1
P2 J2
CLATCH
CDATA
CCLK
C7
100n
C4
100n
1
1
2
3
4
5
1
2
3
4
5
1
–15V
+15V
2
3
4
5
2
3
4
5
7
11
2
7
PD/RST
DEEMP
MUTE
3
1
+IN
VREF
2.25V
V+
1
RG1
R4
CMOUT
6
C3
100n
R2, 2k49
600Ω
OUT
5
8
2
REF
V–
28
27
16
15
RG2
–IN
U3
SSM2017P
FILT
XTALI/MCLK
XTALO
4
6
FGND
+
–
MAX OUTPUT EACH
CHANNEL
C9
100n
C10
+V
4
3
C1
8
7
DGND
18
AGND
5Vrms
VIN
+OUT
–15V
4µ7
100n
6
10Vrms (166.7mV V = +22dBm)
INTO 600Ω
+SENSE
U5
SSM2142P
–SENSE
2
1
–OUT
GND
–V
5
C2
100n
–15V
Figure 32. 600 Ohm Balanced Line Driver
REV. A
–15–
AD1859
BCLK
Q
T
13
N [12..0]
+
27 MHz
MSB
13-BIT
ADDER
SELECT K BUS WHEN K < N (MSB = 0)
SELECT R BUS WHEN K > N (MSB = 1)
13
_
13
RI BUS
1
R BUS
13
13
13
13-BIT
LATCH
2 TO 1
SELECTOR
M [12..0]
+
13-BIT
ADDER
K BUS
L BUS
13
0
+
27MHz
Figure 33. Num erically Controlled Oscillator Circuit
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
28-Lead Wide-Body SO
(R-28)
28-Lead Shrink Sm all O utline P ackage (SSO P )
(RS-28)
0.7125 (18.10)
0.6969 (17.70)
0.41 (10.50)
0.39 (9.90)
28
15
28
15
14
1
14
1
0.1043 (2.65)
0.0926 (2.35)
0.029 (0.74)
0.010 (0.25)
PIN 1
x 45°
0.073 (1.85)
0.065 (1.65)
PIN 1
0.079 (2.0)
MAX
0.050 (1.27)
0.016 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.020 (0.49)
0.013 (0.35)
0.0118 (0.30)
0.0040 (0.10)
0.037 (0.95)
0.022 (0.55)
8°
0°
SEATING
PLANE
0.0125 (0.32)
0.026
(0.65)
BSC
0.015 (0.38)
0.009 (0.22)
0.002 (0.05)
MIN
SEATING
PLANE
0.01 (0.25)
0.0091 (0.23)
0.004 (0.09)
–16–
REV. A
相关型号：
AD1859JRS-REEL
IC SERIAL INPUT LOADING, 18-BIT DAC, PDSO28, SSOP-28, Digital to Analog Converter
ADI
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