AD1839A [ADI]
2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec; 2 ADC ， DAC， 6 ， 96千赫，24位Σ-Δ编解码器
| 型号： | AD1839A |
| 厂家： | 
ADI |
| 描述： | 2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec |
| 文件： | 总24页 (文件大小：998K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 ADC, 6 DAC,
96 kHz, 24-Bit Sigma-Delta Codec
AD1839A
FEATURES
GENERAL DESCRIPTION
5 V stereo audio system with 3.3 V tolerant digital interface
Supports up to 96 kHz sample rates
192 kHz sample rate available on 1 DAC
Supports 16-/20-/24-bit word lengths
The AD1839A is a high performance single-chip codec that
features three stereo DACs and one stereo ADC. Each DAC
comprises a high performance digital interpolation filter, a
multibit Σ-∆ modulator featuring Analog Devices’ patented
technology, and a continuous-time voltage-out analog section.
Each DAC has independent volume control and clickless mute
functions. The ADC comprises two 24-bit conversion channels
with multibit Σ-∆ modulators and decimation filters.
Multibit Σ-∆ modulators with perfect differential linearity
restoration for reduced idle tones and noise floor
Data-directed scrambling DACs—least sensitive to jitter
Single-ended output
ADCs: −95 dB THD + N, 105 dB SNR and dynamic range
DACs: −92 dB THD + N, 108 dB SNR and dynamic range
The AD1839A also contains an on-chip reference with a
nominal value of 2.25 V.
On-chip volume controls per channel with 1024-step linear
scale
The AD1839A contains a flexible serial interface that allows
glueless connection to a variety of DSP chips, AES/EBU
receivers, and sample rate converters. The AD1839A can be
configured in left-justified, right-justified, I2S, or DSP compati-
ble serial modes. Control of the AD1839A is achieved by means
of an SPI® compatible serial port. While the AD1839A can be
operated from a single 5 V supply, it also features a separate
supply pin for its digital interface that allows the device to be
interfaced to other devices using 3.3 V power supplies. The
AD1839A is available in a 52-lead MQFP package and is
specified for the −40°C to +85°C industrial temperature range.
DAC and ADC software controllable clickless mutes
Digital de-emphasis processing
Supports 256 × fS, 512 × fS, and 768 × fS master mode clocks
Power-down mode and soft power-down mode
Flexible serial data port with right-justified, left-justified,
I2S compatible, and DSP serial modes
TDM interface mode supports 8-in/8-out operation using a
single SHARC® SPORT
52-lead MQFP plastic package
APPLICATIONS
DVD video and audio players
Home theater systems
Automotive audio systems
Audio/visual receivers
Digital audio effects process
FUNCTIONAL BLOCK DIAGRAM
DVDD DVDD ODVDD ALRCLK ABCLK ASDATA CCLK CLATCH CIN COUT
MCLK PD/RST M/S AVDD AVDD
AAUXDATA3
DLRCLK
CONTROL PORT
VOLUME
CLOCK
OUTL1
OUTR1
OUTL2
OUTR2
OUTL3
DIGITAL
FILTER
Σ-∆
DBCLK
DAC
DSDATA1
DSDATA2
DSDATA3
DAUXDATA
VOLUME
SERIAL DATA
I/O PORT
VOLUME
DIGITAL
FILTER
Σ-∆
DAC
VOLUME
VOLUME
ADCLP
ADCLN
Σ-∆
ADC
DIGITAL
FILTER
DIGITAL
FILTER
Σ-∆
DAC
OUTR3
FILTD
FILTR
VOLUME
ADCRP
ADCRN
Σ-∆
ADC
DIGITAL
FILTER
V
AD1839A
REF
DGND DGND AGND AGND AGND AGND
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD1839A
TABLE OF CONTENTS
Specifications..................................................................................... 3
DAC and ADC Coding.............................................................. 12
AD1839A Clocking Scheme ..................................................... 12
RESET and Power-Down .......................................................... 13
Power Supply and Voltage Reference....................................... 13
Serial Control Port ..................................................................... 13
Serial Data Ports—Data Format............................................... 14
Packed Modes ............................................................................. 14
Auxiliary Time Division Multiplexing (TDM) Mode ........... 14
Control/Status Registers............................................................ 19
Cascade Mode............................................................................. 22
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Test Conditions............................................................................. 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
Temperature Range ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 11
Functional Overview...................................................................... 12
ADCs............................................................................................ 12
DACs ............................................................................................ 12
REVISION HISTORY
5/04—Data Sheet Changed from Rev. A to Rev. B
Updated FormatUniversal
Changes to Data Sheet Title1
2/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Ordering Guide ............................................................. 6
Deleted Clock Signals Section ....................................................... 11
Added AD1835A Clocking Scheme Section................................ 11
Added Table II and Table III and renumbered following tables 11
Changes to Auxiliary (TDM Mode) Section................................ 13
Changes to Figure 5......................................................................... 14
Changes to Figure 6......................................................................... 14
Added Figures 7a and 8a................................................................. 15
Renamed Figure 7 and Figure 8 to Figure 7b and Figure 8b ..... 15
Changes to Figure 9......................................................................... 15
Changes to Table VIII ..................................................................... 21
Updated Outline Dimensions........................................................ 24
Rev. B | Page 2 of 24
AD1839A
SPECIFICATIONS
TEST CONDITIONS
Supply Voltages
Ambient Temperature
Input Clock
DAC Input Signal
ADC Input Signal
Input Sample Rate (fS)
Measurement Bandwidth
Word Width
5.0 V (AVDD, DVDD)
25°C
12.288 MHz (256 × fS mode)
1.0078125 kHz, 0 dBFS
1.0078125 kHz, −1 dBFS
48 kHz
0 Hz to 20 kHz
24 bits
Load Capacitance
Load Impedance
100 pF
47 kΩ
Performance of all channels is identical (except for the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Table 1.
Parameter
Min
Typ
Max
Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
24
Bits
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter
A-Weighted (48 kHz and 96 kHz)
Total Harmonic Distortion + Noise (THD + N)
48 kHz
96 kHz
Interchannel Isolation
Interchannel Gain Mismatch
Analog Inputs
103
105
dB
dB
100
–95
–95
100
0.025
–88.5
–87.5
dB
dB
dB
dB
Differential Input Range ( Full Scale)
Common-Mode Input Voltage
Input Impedance
Input Capacitance
VREF
–2.828
+2.828
V
V
kΩ
pF
V
2.25
4
15
2.25
DC Accuracy
Gain Error
5
%
Gain Drift
35
ppm/°C
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
24
Bits
Dynamic Range (20 Hz to 20 kHz, –60 dBFS Input)
No Filter
A-Weighted Filter (48 kHz and 96 kHz)
Total Harmonic Distortion + Noise (48 kHz and 96 kHz)
Interchannel Isolation
103
105
105
108
–92
110
dB
dB
dB
dB
–90
DC Accuracy
Gain Error
4
%
Interchannel Gain Mismatch
Gain Drift
0.025
200
dB
ppm/°C
Interchannel Phase Deviation
Volume Control Step Size (1023 Linear Steps)
Volume Control Range (Maximum Attenuation)
Mute Attenuation
De-emphasis Gain Error
Full-Scale Output Voltage at Each Pin (Single-Ended)
Output Resistance at Each Pin
Common-Mode Output Voltage
0.1
0.098
60
–100
0.1
1.0 (2.8)
180
Degrees
%
dB
dB
dB
V rms (V p-p)
Ω
V
2.25
Rev. B | Page 3 of 24
AD1839A
Parameter
ADC DECIMATION FILTER, 48 kHz1
Min
Typ
Max
Unit
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
21.77
0.01
26.23
120
kHz
dB
kHz
dB
910
µs
1
ADC DECIMATION FILTER, 96 kHz
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
43.54
0.01
52.46
120
kHz
dB
kHz
dB
460
µs
1
DAC INTERPOLATION FILTER, 48 kHz
Pass Band
21.77
43.54
81.2
kHz
dB
kHz
dB
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
0.01
340
28
55
µs
1
DAC INTERPOLATION FILTER, 96 kHz
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
kHz
dB
kHz
dB
0.01
160
52
55
µs
1
DAC INTERPOLATION FILTER, 192 kHz
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
kHz
dB
kHz
dB
0.06
110
97
80
µs
DIGITAL I/O
Input Voltage High
Input Voltage Low
Output Voltage High
Output Voltage Low
Leakage Current
2.4
V
V
V
V
0.8
ODVDD – 0.4
0.4
10
µA
POWER SUPPLIES
Supply Voltage (AVDD and DVDD)
Supply Voltage (ODVDD)
Supply Current IANALOG
Supply Current IANALOG, Power-Down
Supply Current IDIGITAL
4.5
3.0
5.0
5.5
DVDD
95
67
74
V
V
mA
mA
mA
mA
84
55
64
1
Supply Current IDIGITAL, Power-Down
Dissipation
4.5
Operation, Both Supplies
Operation, Analog Supply
Operation, Digital Supply
Power-Down, Both Supplies
Power Supply Rejection Ratio
1 kHz, 300 mV p-p Signal at Analog Supply Pins
20 kHz, 300 mV p-p Signal at Analog Supply Pins
740
420
320
280
mW
mW
mW
mW
–70
–75
dB
dB
1 Guaranteed by design.
Rev. B | Page 4 of 24
AD1839A
TIMING SPECIFICATIONS
Table 2.
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
tMH
tML
tPDR
MCLK High
MCLK Low
PD/RST Low
15
15
20
ns
ns
ns
SPI PORT
tCCH
tCCL
tCCP
tCDS
tCDH
tCLS
tCLH
tCOE
CCLK High
CCLK Low
40
40
80
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Three-State
To CCLK rising edge
From CCLK rising edge
To CCLK rising edge
From CCLK rising edge
From CLATCH falling edge
From CCLK falling edge
From CLATCH rising edge
15
20
25
tCOD
tCOTS
DAC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Slave)
tDBH
tDBL
DBCLK High
DBCLK Low
60
60
ns
ns
fDB
tDLS
tDLH
tDDS
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
64 × fS
10
10
10
10
ns
ns
ns
ns
To DBCLK rising edge
From DBCLK rising edge
To DBCLK rising edge
From DBCLK rising edge
tDDH
Packed 128/256 Modes (Slave)
tDBH
tDBL
DBCLK High
DBCLK Low
15
15
ns
ns
fDB
tDLS
tDLH
tDDS
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
256 × fS
10
10
10
10
ns
ns
ns
ns
To DBCLK rising edge
From DBCLK rising edge
To DBCLK rising edge
From DBCLK rising edge
tDDH
ADC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Master)
tABD
tALD
tABDD
ABCLK Delay
ALRCLK Delay
ASDATA Delay
25
5
10
ns
ns
ns
From MCLK rising edge
From ABCLK falling edge
From ABCLK falling edge
Normal Mode (Slave)
tABH
tABL
ABCLK High
ABCLK Low
60
60
ns
ns
fAB
tALS
tALH
tABDD
ABCLK Frequency
ALRCLK Setup
ALRCLK Hold
ASDATA Delay
64 × fS
5
15
ns
ns
ns
To ABCLK rising edge
From ABCLK rising edge
From ABCLK falling edge
15
Packed 128/256 Mode (Master)
tPABD
tPALD
tPABDD
ABCLK Delay
LRCLK Delay
ASDATA Delay
40
5
10
ns
ns
ns
From MCLK rising edge
From ABCLK falling edge
From ABCLK falling edge
Rev. B | Page 5 of 24
AD1839A
Parameter
Min
Max
Unit
Comments
TDM256 MODE (Master, 48 kHz and 96 kHz)
tTBD
tFSD
tTABDD
tTDDS
BCLK Delay
FSTDM Delay
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
40
5
10
ns
ns
ns
ns
ns
From MCLK rising edge
From BCLK rising edge
From BCLK rising edge
To BCLK falling edge
From BCLK falling edge
15
15
tTDDH
TDM256 MODE (Slave, 48 kHz and 96 kHz)
fAB
tTBCH
BCLK Frequency
BCLK High
256 × fS
17
ns
ns
ns
ns
ns
ns
ns
tTBCL
tTFS
tTFH
tTBDD
tTDDS
tTDDH
BCLK Low
17
10
10
FSTDM Setup
FSTDM Hold
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
To BCLK falling edge
From BCLK falling edge
From BCLK rising edge
To BCLK falling edge
From BCLK falling edge
15
15
15
TDM512 MODE (Master, 48 kHz)
tTBD
tFSD
tTABDD
tTDDS
BCLK Delay
40
5
10
ns
ns
ns
ns
ns
From MCLK rising edge
From BCLK rising edge
From BCLK rising edge
To BCLK falling edge
From BCLK falling edge
FSTDM Delay
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
15
15
tTDDH
TDM512 MODE (Slave, 48 kHz)
fAB
tTBCH
BCLK Frequency
BCLK High
512 × fS
17
ns
ns
ns
ns
ns
ns
tTBCL
tTFS
tTFH
tTBDD
tTDDS
tTDDH
BCLK Low
17
10
10
15
15
15
FSTDM Setup
FSTDM Hold
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
To BCLK falling edge
From BCLK falling edge
From BCLK rising edge
To BCLK falling edge
From BCLK falling edge
AUXILIARY INTERFACE (48 kHz and 96 kHz)
tAXDS
tAXDH
tDXD
AAUXDATA Setup
AAUXDATA Hold
DAUXDATA Delay
AUXBCLK Frequency
10
10
10
64 × fS
ns
ns
ns
ns
To AUXBCLK rising edge
From AUXBCLK rising edge
From AUXBCLK falling edge
fABP
Slave Mode
tAXBH
tAXBL
tAXLS
tAXLH
AUXBCLK High
AUXBCLK Low
AUXLRCLK Setup
AUXLRCLK Hold
15
15
10
10
ns
ns
ns
ns
To AUXBCLK rising edge
From AUXBCLK rising edge
Master Mode
tAUXBCLK
tAUXLRCLK
AUXBCLK Delay
AUXLRCLK Delay
20
15
ns
ns
From MCLK rising edge
From AUXBCLK falling edge
tMCLK
tMH
MCLK
tML
PD/RST
tPDR
PD RST
/ Timing
Figure 2. MCLK and
Rev. B | Page 6 of 24
AD1839A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
AVDD, DVDD, ODVDD to AGND,
DGND
−0.3 V to +6.0 V
AGND to DGND
−0.3 V to +0.3 V
Digital I/O Voltage to DGND
Analog I/O Voltage to AGND
Operating Temperature Range
Industrial (A Version)
−0.3 V to ODVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−40°C to +85°C
TEMPERATURE RANGE
Table 4.
Parameter
Min
Typ
Max
Unit
°C
°C
Specifications Guaranteed
Functionality Guaranteed
Storage
+25
−40
−65
+85
+150
°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 7 of 24
AD1839A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
38
37
36
35
34
33
32
31
30
29
28
27
DVDD
DVDD
DBCLK
DLRCLK
DAUXDATA
M/S
2
CLATCH
3
4
CIN
PD/RST
AGND
NC
5
AD1839A
TOP VIEW
(Not to Scale)
6
AGND
NC
7
OUTL1
NC
8
NC
9
OUTR1
AGND
AVDD
NC
NC
10
11
12
13
AGND
AVDD
OUTR3
NC
OUTL2
14 15 16 17 18 19 20 21 22 23 24 25 26
NC = NO CONNECT
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Input/Output
Description
1, 39
2
3
4
DVDD
CLATCH
CIN
PD/RST
AGND
Digital Power Supply. Connect to digital 5 V supply.
Latch Input for Control Data.
Serial Control Input.
I
I
I
Power-Down/Reset.
5, 10, 16, 24, 30, 34
Analog Ground.
6, 8, 12, 14, 25, 27, 31–33
NC
Not connected.
7, 13, 26
9, 15, 28
11, 19, 29
17
18
20
21
22
23
35
OUTLx
OUTRx
AVDD
FILTD
FILTR
ADCLN
ADCLP
ADCRN
ADCRP
M/S
O
O
DACx Right Channel Negative Output.
DACx Right Channel Positive Output.
Analog Power Supply. Connect to analog 5 V supply.
Filter Capacitor Connection. Recommended 10 µF/100 nF.
Reference Filter Capacitor Connection. Recommended 10 µF/100 nF.
ADC Left Channel Negative Input.
ADC Left Channel Positive Input.
ADC Right Channel Negative Input.
ADC Right Channel Positive Input.
ADC Master/Slave Select.
I
I
I
I
I
36
37
38
40, 52
41–43
44
45
46
DAUXDATA
DLRCLK
DBCLK
DGND
DSDATAx
AAUXDATA3
ABCLK
ALRCLK
MCLK
O
I/O
I/O
Auxiliary DAC Output Data.
DAC LR Clock.
DAC Bit Clock.
Digital Ground.
DACx Input Data (left and right channels).
Auxiliary ADC3 Digital Input.
ADC Bit Clock.
ADC LR Clock.
Master Clock Input.
I
I
I/O
I/O
I
47
48
49
50
51
ODVDD
ASDATA
COUT
Digital Output Driver Power Supply.
ADC Serial Data Output.
Output for Control Data.
O
O
I
CCLK
Control Clock Input for Control Data.
Rev. B | Page 8 of 24
AD1839A
TYPICAL PERFORMANCE CHARACTERISTICS
0
5
0
–50
–100
–150
–5
–10
–15
–20
–25
–30
0
5
10
15
0
5
10
15
20
FREQUENCY (Normalized to fS
)
FREQUENCY (Hz)
Figure 4. ADC Composite Filter Response
Figure 7. ADC High-Pass Filter Response, fS = 96 kHz
5
0
0
–5
–50
–10
–15
–20
–25
–30
–100
–150
50
100
150
0
200
0
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (Hz)
Figure 5. ADC High-Pass Filter Response, fS = 48 kHz
Figure 8. DAC Composite Filter Response, fS = 48 kHz
0
0
–50
–50
–100
–150
–100
–150
0
0.5
1.0
1.5
2.0
0
50
100
150
200
FREQUENCY (Normalized to fS
)
FREQUENCY (kHz)
Figure 6. ADC Composite Filter Response (Pass-Band Section)
Figure 9. DAC Composite Filter Response, fS = 96 kHz
Rev. B | Page 9 of 24
AD1839A
0.2
0.1
0
0
–50
–100
–0.1
–0.2
–150
0
50
100
150
200
10
20
30
40
0
50
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 10. DAC Composite Filter Response, fS = 192 kHz
Figure 12. DAC Composite Filter Response, fS = 96 kHz (Pass-Band Section)
0.10
0.05
0
0.10
0.05
0
–0.05
–0.10
–0.05
–0.10
20
40
60
80
0
5
10
15
20
0
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 11. DAC Composite Filter Response, fS = 48 kHz (Pass-Band Section)
Figure 13. DAC Composite Filter Response, fS = 192 kHz (Pass-Band Section)
Rev. B | Page 10 of 24
AD1839A
TERMINOLOGY
Dynamic Range
Gain Drift
The ratio of a full-scale input signal to the integrated input
noise in the pass band (20 Hz to 20 kHz), expressed in decibels.
Dynamic range is measured with a −60 dB input signal and is
equal to (S/[THD + N]) + 60 dB. Note that spurious harmonics
are below the noise with a −60 dB input, so the noise level
establishes the dynamic range. The dynamic range is specified
with and without an A-weight filter applied.
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine wave input on the other channel, expressed
in decibels.
Power Supply Rejection
Signal-to-(Total Harmonic Distortion + Noise)
[S/(THD + N)]
With no analog input, signal present at the output when a
300 mV p-p signal is applied to the power supply pins,
expressed in decibels of full scale.
The ratio of the root-mean-square (rms) value of the
fundamental input signal to the rms sum of all other spectral
components in the pass band, expressed in decibels.
Group Delay
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in microseconds.
More precisely, the derivative of radian phase with respect to
the radian frequency at a given frequency.
Pass Band
The region of the frequency spectrum unaffected by the
attenuation of the digital decimator’s filter.
Pass-Band Ripple
Group Delay Variation
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the pass band,
expressed in decibels.
The difference in group delays at different input frequencies.
Specified as the difference between the largest and the smallest
group delays in the pass band, expressed in microseconds.
Stop Band
Acronyms
The region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by stop-band
attenuation.
ADC—Analog-to-digital converter.
DAC—Digital-to-analog converter.
DSP—Digital signal processor.
Gain Error
With identical near full-scale inputs, the ratio of actual output
to expected output, expressed as a percentage.
IMCLK—Internal master clock signal used to clock the ADC
and DAC engines.
Interchannel Gain Mismatch
MCLK—External master clock signal applied to the AD1839A.
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
Rev. B | Page 11 of 24
AD1839A
FUNCTIONAL OVERVIEW
ADCS
DAC AND ADC CODING
The DAC and ADC output data stream is in a twos complement
encoded format. A 16-bit, 20-bit, or 24-bit word width can be
selected. The coding scheme is detailed in Table 6.
There are two ADC channels in the AD1839A, configured as a
stereo pair. Each ADC has fully differential inputs. The ADC
section can operate at a sample rate of up to 96 kHz. The ADCs
include on-board digital decimation filters with 120 dB stop-
band attenuation and linear phase response, operating at an
oversampling ratio of 128 (for 48 kHz operation) or 64 (for
96 kHz operation).
Table 6. Coding Scheme
Code
Level
+FS
0 (Ref level)
−FS
01111......1111
00000......0000
10000......0000
The peak level information for each ADC may be read from the
ADC Peak 0 and ADC Peak 1 registers. The data is supplied as a
6-bit word with a maximum range of 0 dB to −63 dB and a
resolution of 1 dB. The registers hold peak information until
read; after reading, the registers are reset so that new peak
information can be acquired. (Refer to the register description
in Table 10 for details of the format.) The two ADC channels
have a common serial bit clock and a left-right framing clock.
The clock signals are all synchronous with the sample rate.
AD1839A CLOCKING SCHEME
By default, the AD1839A requires an MCLK signal that is
256 times the required sample frequency up to a maximum of
12.288 MHz. The AD1839A uses a clock scaler to double the
clock frequency for use internally. The default setting of the
clock scaler is Multiply by 2. The clock scaler can also be set to
Multiply by 1 (bypass) or Multiply by 2/3. The clock scaler is
controlled by programming the bits in the ADC Control 3
register. The internal MCLK signal, IMCLK, should not exceed
24.576 MHz to ensure correct operation.
The ADC digital pins, ABCLK and ALRCLK, can be set to
operate as inputs or outputs by connecting the /S pin to
M
ODVDD or DGND, respectively. When the pins are set as
outputs, the AD1839A generates the timing signals. When the
pins are set as inputs, the timing must be generated by the
external audio controller.
The MCLK of the AD1839A should remain constant during
normal operation of the DAC and ADC. If it is required to
change the MCLK rate, the AD1838A should be reset. Also, if
MCLK scaler needs to be modified so that the IMCLK does not
exceed 24.576 MHz, this should be done during the internal
reset phase of the AD1839A by programming the bits in the
first 3,072 MCLK periods following the reset.
DACS
The AD1839A has six DAC channels arranged as three
independent stereo pairs, with six single-ended analog outputs.
Each channel has its own independently programmable
attenuator, adjustable in 1,024 linear steps. Digital inputs are
supplied through three serial data input pins (one for each
stereo pair) and a common frame (DLRCLK) and bit clock
(DBCLK). Alternatively, one of the packed data modes can be
used to access all six channels on a single TDM data pin. A
stereo replicate feature is included where the DAC data sent to
the first DAC pair is also sent to the other DACs in the part.
The AD1839A can accept DAC data at a sample rate of 192 kHz
on DAC 1 only. The stereo replicate feature can then be used to
copy the audio data to the other DACs.
Selecting the DAC Sampling Rate
The AD1839A DAC engine has a programmable interpolator
that allows the user to select different interpolation rates based
on the required sample rate and MCLK value available. Table 7
shows the settings required for sample rates based on a fixed
MCLK of 12.288 MHz.
Table 7. DAC Sample Rate Settings
Sample Rate
Interpolator Rate
DAC Control 1 Register
000000xxxxxxxx00
000000xxxxxxxx01
000000xxxxxxxx10
48 kHz
96 kHz
192 kHz
8×
4×
2×
Each of the output pins sits at a dc level of VREF and swings
1.4 V for a 0 dB digital input signal. A single op amp, third-
order, external low-pass filter is recommended to remove high
frequency noise present on the output pins. Note that the use of
op amps with low slew rate or low bandwidth may cause high
frequency noise and tones to fold down into the audio band;
care should be exercised in selecting these components.
Selecting an ADC Sample Rate
The AD1839A ADC engine has a programmable decimator that
allows the user to select the sample rate based on the MCLK
value. By default, the output sample rate is IMCLK/512. To
achieve a sample rate of IMCLK/256, the sample rate bit in the
ADC Control 1 register should be set as shown in Table 8.
The FILTD pin should be connected to an external grounded
capacitor. This pin reduces the noise of the internal DAC bias
circuitry, thus reducing the DAC output noise. At times, this
capacitor may be eliminated with little effect on performance.
Table 8. ADC Sample Rate Settings
Sample Rate
IMCLK/512
IMCLK/256
ADC Control 1 Register
1100000xx0xxxxxx (48 kHz)
1100000xx1xxxxxx (96 kHz)
Rev. B | Page 12 of 24
AD1839A
To maintain the highest performance possible, the clock
jitter of the master clock signal should be limited to less than
300 ps rms, measured using the edge-to-edge technique. Even at
these levels, extra noise or tones may appear in the DAC outputs
if the jitter spectrum contains large spectral peaks. It is highly
recommended that the master clock be generated by an inde-
pendent crystal oscillator. In addition, it is especially important
that the clock signal not be passed through an FPGA or other
large digital chip before being applied to the AD1839A. In most
cases, this induces clock jitter because the clock signal is sharing
common power and ground connections with unrelated digital
output signals.
pickup. A bulk aluminum electrolytic capacitor of at least 22 µF
should also be provided on the same PC board as the codec. For
critical applications, improved performance is obtained with
separate supplies for the analog and digital sections. If this is
not possible, it is recommended that the analog and digital
supplies be isolated by two ferrite beads in series with the
bypass capacitor of each supply. It is important that the analog
supply be as clean as possible.
The internal voltage reference is brought out on the FILTR pin
and should be bypassed as close as possible to the chip, with a
parallel combination of 10 µF and 100 nF. The reference voltage
may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the VREF pin should be limited to less than 50 µA.
RESET AND POWER-DOWN
/
powers down the chip and sets the control registers
PD RST
to their default settings. After
/
is deasserted, an initial-
PD RST
SERIAL CONTROL PORT
ization routine runs inside the device to clear all memories to
zero. The initialization lasts approximately 20 LRCLK intervals.
During this time, it is recommended that no SPI writes occur.
The AD1839A has an SPI compatible control port to permit
programming the internal control registers for the ADCs and
DACs, and for reading the ADC signal levels from the internal
peak detectors. The SPI port is a 4-wire serial control port. The
format is similar to the Motorola SPI format except the input
data-word is 16 bits wide. The maximum serial bit clock
frequency is 12.5 MHz and may be completely asynchronous to
the sample rate of the ADCs and DACs. Figure 15 shows the
format of the SPI signal.
POWER SUPPLY AND VOLTAGE REFERENCE
The AD1839A is designed for 5 V supplies. Separate power
supply pins are provided for the analog and digital sections.
These pins should be bypassed with 100 nF ceramic chip
capacitors, as close to the pins as possible, to minimize noise
DAC ENGINE
48kHz/96kHz/192kHz
ANALOG
OUTPUT
INTERPOLATION
FILTER
Σ-∆
DAC INPUT
DAC
MODULATOR
CLOCK SCALING
×1
×2
IMCLK = 24.576MHz
MCLK
12.288MHz
×2/3
ADC ENGINE
48kHz/96kHz
OPTIONAL
HPF
DECIMATOR/
FILTER
Σ-∆
MODULATOR
ANALOG
INPUT
ADC OUTPUT
Figure 14. Modular Clocking Scheme
tCCH tCCL
tCLS
tCLH
tCCP
CLATCH
CCLK
tCOTS
tCDS tCDH
D8
CIN
D15
D14
D9
D0
D0
tCOE
COUT
D9
D8
tCOD
Figure 15. Format of SPI Timing
Rev. B | Page 13 of 24
AD1839A
SERIAL DATA PORTS—DATA FORMAT
AUXILIARY TIME DIVISION MULTIPLEXING
(TDM) MODE
The ADC serial data output mode defaults to the popular I2S
format, where the data is delayed by 1 BCLK interval from the
edge of the LRCLK. By changing Bits 6 to 8 in ADC Control
Register 2, the serial mode can be changed to right-justified
(RJ), left-justified DSP (DSP), or left-justified (LJ). In the RJ
mode, it is necessary to set Bits 4 and 5 to define the width of
the data-word. The DAC serial data input mode defaults to I2S.
By changing Bits 5, 6, and 7 in DAC Control Register 1, the
mode can be changed to RJ, DSP, LJ, or Packed Mode 256. The
word width defaults to 24 bits but can be changed by
A special auxiliary mode is provided to allow three external
stereo ADCs and one external stereo DAC to be interfaced to
the AD1839A to provide 8-in/8-out operation. In addition, this
mode supports a glueless interface to a single SHARC DSP
serial port, allowing a SHARC DSP to access all eight channels
of analog I/O. In this special mode, many pins are redefined; see
Table 9 for a list of redefined pins.
The auxiliary and TDM interfaces are independently
configurable to operate as masters or slaves. When the auxiliary
interface is set as a master, by programming the auxiliary mode
bit in ADC Control Register 2, AUXLRCLK and AUXBCLK are
generated by the AD1839A. When the auxiliary interface is set
as a slave, AUXLRCLK and AUXBCLK need to be generated by
an external ADC, as shown in Figure 27.
reprogramming Bits 3 and 4 in DAC Control Register 1.
PACKED MODES
The AD1839A has a packed mode that allows a DSP or other
controller to write to all DACs and read all ADCs using one
input data pin and one output data pin. Packed Mode 256 refers
to the number of BCLKs in each frame. The LRCLK is low
while data from a left-channel DAC or ADC is on the data pin;
LRCLK is high while data from a right-channel DAC or ADC is
on the data pin. DAC data is applied on the DSDATA1 pin, and
ADC data is available on the ASDATA pin. Figure 19 to
Figure 24 show the timing for the packed mode. Packed mode is
available for 48 kHz and 96 kHz.
The TDM interface can be set to operate as a master or slave by
connecting the /S pin to DGND or ODVDD, respectively. In
M
master mode, the FSTDM and BCLK signals are outputs and are
generated by the AD1839A. In slave mode, the FSTDM and
BCLK are inputs and should be generated by the SHARC. Both
48 kHz and 96 kHz operations are available (based on a
12.288 MHz or 24.576 MHz MCLK) in this mode.
Table 9. Pin Function Changes in Auxiliary Mode
Pin Name
I2S Mode
Auxiliary Mode
ASDATA (O)
DSDATA1 (I)
DSDATA2 (I)/AAUXDATA1 (I)
DSDATA3 (I)/AAUXDATA2 (I)
AAUXDATA3 (I)
I2S Data Out, Internal ADC
I2S Data In, Internal DAC1
I2S Data In, Internal DAC2
I2S Data In, Internal DAC3
Not Connected
TDM Data Out to SHARC.
TDM Data In from SHARC.
AUX-I2S Data In 1 (from external ADC).
AUX-I2S Data In 2 (from external ADC).
AUX-I2S Data In 3 (from external ADC).
TDM Frame Sync Out to SHARC (FSTDM).
TDM BCLK Out to SHARC.
ALRCLK (O)
ABCLK (O)
LRCLK for ADC
BCLK for ADC
DLRCLK (I)/AUXLRCLK (I/O)
LRCLK In/Out Internal DACs
AUX LRCLK In/Out. Driven by external LRCLK from ADC in slave mode.
In master mode, driven by MCLK/512.
DBCLK (I)/AUXBCLK (I/O)
DAUXDATA (O)
BCLK In/Out Internal DACs
Not Connected
AUX BCLK In/Out. Driven by external BCLK from ADC in slave mode.
In master mode, driven by MCLK/8.
AUX-I2S Data Out (to external DAC).
Rev. B | Page 14 of 24
AD1839A
LRCLK
BCLK
LEFT CHANNEL
RIGHT CHANNEL
SDATA
MSB
LSB
MSB
LSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
BCLK
RIGHT CHANNEL
MSB
LSB
MSB
LSB
SDATA
2
I S MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
MSB
LSB
MSB
LSB
SDATA
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2.
LRCLK NORMALLYOPERATES AT fS EXCEPT FOR DSP MODE, WHICH IS 2 × fS.
3. BCLK FREQUENCY IS NORMALLY 64× LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 16. Stereo Serial Modes
tABH
ABCLK
tABL
tALS
tABDD
ALRCLK
ASDATA
LEFT-JUSTIFIED
MODE
MSB
MSB – 1
MSB
ASDATA
I S COMPATIBLE
2
MODE
ASDATA
RIGHT-JUSTIFIED
MODE
LSB
MSB
Figure 17. ADC Serial Mode Timing
Rev. B | Page 15 of 24
AD1839A
tDBH
DBCLK
tDBL
tDLS
tDLH
DLRCLK
tDDS
DSDATA
LEFT-JUSTIFIED
MODE
MSB
tDDH
MSB – 1
DSDATA
I S COMPATIBLE
tDDS
2
MSB
tDDH
MODE
tDDS
tDDS
DSDATA
RIGHT-JUSTIFIED
MODE
LSB
MSB
tDDH
tDDH
Figure 18. DAC Serial Mode Timing
LRCLK
BCLK
128 BCLKs
16 BCLKs
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8
LEFT 1 LEFT 2 LEFT 3 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4
ADC DATA
MSB
MSB – 1 MSB – 2
Figure 19. ADC Packed Mode 128
LRCLK
BCLK
256 BCLKs
32 BCLKs
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8
LEFT 1 LEFT 2 LEFT 3 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4
ADC DATA
MSB
MSB – 1 MSB – 2
Figure 20. ADC Packed Mode 256
Rev. B | Page 16 of 24
AD1839A
LRCLK
BCLK
128 BCLKs
16 BCLKs
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8
LEFT 1 LEFT 2 LEFT 3 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4
DAC DATA
MSB
MSB – 1 MSB – 2
Figure 21. DAC Packed Mode 128
LRCLK
BCLK
256 BCLKs
32 BCLKs
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8
LEFT 1 LEFT 2 LEFT 3 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4
DAC DATA
MSB
MSB – 1 MSB – 2
Figure 22. DAC Packed Mode 256
tABH
ABCLK
tABL
tABH
ALRCLK
ASDATA
tALH
tABDD
MSB
MSB – 1
Figure 23. ADC Packed Mode Timing
tDBH
DBCLK
tDBL
tDLS
DLRCLK
DSDATA
tDLH
tDDS
MSB
tDDH
MSB – 1
Figure 24. DAC Packed Mode Timing
Rev. B | Page 17 of 24
AD1839A
FSTDM
BCLK
TDM
MSB TDM
MSB TDM
1ST
CH
8TH
CH
ASDATA1
TDM (OUT)
INTERNAL
ADC L1
AUX_ADC
L2
AUX_ADC
L3
AUX_ADC
L4
INTERNAL
ADC R1
AUX_ADC
R2
AUX_ADC
R3
AUX_ADC
R4
ASDATA
32
MSB TDM
MSB TDM
1ST
CH
8TH
CH
DSDATA1
TDM (IN)
INTERNAL
DAC L1
INTERNAL
DAC L2
INTERNAL
DAC L3
INTERNAL
DAC L4
INTERNAL
DAC R1
INTERNAL
DAC R2
INTERNAL
DAC R3
INTERNAL
DAC R4
DSDATA1
32
AUX
2
RIGHT
LRCLK I S
LEFT
(FROM AUX ADC NO. 1)
AUX
2
BCLK I S
(FROM AUX ADC NO. 1)
AAUXDATA1 (IN)
(FROM AUX ADC NO. 1)
2
2
I S - MSB LEFT
I S - MSB RIGHT
AAUXDATA2 (IN)
(FROM AUX ADC NO. 2)
2
2
I S - MSB LEFT
I S - MSB RIGHT
AAUXDATA3 (IN)
(FROM AUX ADC NO. 3)
2
2
I S - MSB LEFT
I S - MSB RIGHT
FRAME RATE.
Figure 25. Auxiliary Mode Timing
30MHz
SHARC IS ALWAYS
RUNNING IN SLAVE MODE
(INTERRUPT DRIVEN).
SHARC
12.288MHz
LRCLK
BCLK
DATA
MCLK
ADC NO. 1
SLAVE
LRCLK
BCLK
DATA
MCLK
ADC NO. 2
SLAVE
ASDATA FSTDM BCLK DSDATA1
DBCLK/AUXBCLK
LRCLK
BCLK
DLRCLK/AUXLRCLK
DSDATA2/AAUXDATA1
DSDATA3/AAUXDATA2
AAUXDATA3
DAC NO. 1
SLAVE
LRCLK
BCLK
DATA
MCLK
DAUXDATA
DATA
MCLK
ADC NO. 3
SLAVE
AD1839A
MCLK
MASTER
Figure 26. Auxiliary Mode Connection (Master Mode) to SHARC
Rev. B | Page 18 of 24
AD1839A
30MHz
SHARC IS ALWAYS
RUNNING IN SLAVE MODE
(INTERRUPT DRIVEN).
SHARC
12.288MHz
LRCLK
BCLK
DATA
MCLK
ADC NO. 1
SLAVE
LRCLK
BCLK
DATA
MCLK
ADC NO. 2
SLAVE
ASDATA FSTDM BCLK DSDATA1
DBCLK/AUXBCLK
LRCLK
BCLK
DLRCLK/AUXLRCLK
DSDATA2/AAUXDATA1
DSDATA3/AAUXDATA2
AAUXDATA3
DAC NO. 1
SLAVE
LRCLK
BCLK
DATA
MCLK
DAUXDATA
DATA
MCLK
ADC NO. 3
SLAVE
AD1839A
MCLK
SLAVE
Figure 27. Auxiliary Mode Connection (Slave Mode) to SHARC
CONTROL/STATUS REGISTERS
The AD1839A has 13 control registers, 11 of which are used to
set the operating mode of the part. The other two registers,
ADC Peak 0 and ADC Peak 1, are read-only and should not be
programmed. Each of the registers is 10 bits wide with the
exception of the ADC peak reading registers, which are 6 bits
wide. Writing to a control register requires a 16-bit data frame
to be transmitted. Bits 15 to 12 are the address bits of the
required register. Bit 11 is a read/write bit. Bit 10 is reserved and
should always be programmed to 0. Bits 9 to 0 contain the
10-bit value that is to be written to the register, or, in the case of
a read operation, the 10-bit register contents. Figure 15 shows
the format of the SPI read and write operation.
DAC Data-Word Width
These two bits set the word width of the DAC data. Compact
disk (CD) compatibility may require 16 bits, but many modern
digital audio formats require 24-bit sample resolution.
DAC Data Format
The AD1839A serial data interface can be configured to be
compatible with a choice of popular interface formats, including
I2S, LJ, RJ, or DSP modes. Details on these interface modes are
provided in the Serial Data Ports—Data Format section.
De-emphasis
The AD1839A provides built-in de-emphasis filtering for the
three standard sample rates of 32.0 kHz, 44.1 kHz, and 48 kHz.
DAC Control Registers
Mute DAC
Each of the six DACs in the AD1839A has its own independent
mute control. Setting the appropriate bit mutes the DAC output.
The AD1839A uses a clickless mute function that attenuates the
output to approximately −100 dB over a number of cycles.
The AD1839A register map has eight registers that are used to
control the functionality of the DAC section of the part. The
function of the bits in these registers is discussed next.
Sample Rate
Stereo Replicate
These bits control the sample rate of the DACs. Based on a
24.576 MHz IMCLK, sample rates of 48 kHz, 96 kHz, and
192 kHz are available. The MCLK scaling bits in ADC Control 3
should be programmed appropriately, based on the master clock
frequency.
Setting this bit copies the digital data sent to the stereo pair
DAC1 to the three other stereo DACs in the system. This allows
all three stereo DACs to be driven by one digital data stream.
Note that in this mode, DAC data sent to the other DACs is
ignored.
Power-Down/Reset
DAC Volume Control
This bit controls the power-down status of the DAC section. By
default, normal mode is selected; by setting this bit, the digital
section of the DAC stage can be put into a low power mode,
thus reducing the digital current. The analog output section of
the DAC stage is not powered down.
Each DAC in the AD1839A has its own independent volume
control. The volume of each DAC can be adjusted in 1,024
linear steps by programming the appropriate register. The
default value for this register is 1023, which provides no
attenuation, that is, full volume.
Rev. B | Page 19 of 24
AD1839A
ADC Control Registers
High-Pass Filter
The ADC signal path has a digital high-pass filter. Enabling this
filter removes the effect of any dc offset in the analog input
signal from the digital output codes.
The AD1839A register map has five registers that are used to
control the functionality and read the status of the ADCs. The
function of the bits in each of these registers is discussed below.
ADC Data-Word Width
These two bits set the word width of the ADC data.
ADC Peak Level
These two registers store the peak ADC result from each
channel when the ADC peak readback function is enabled. The
peak result is stored as a 6-bit number from 0 dB to −63 dB in
1 dB steps. The value contained in the register is reset once it
has been read, allowing for continuous level adjustment as
required. Note that the ADC peak level registers use the six
most significant bits in the register to store the results.
ADC Data Format
The AD1839A serial data interface can be configured to be
compatible with a choice of popular interface formats, including
I2S, LJ, RJ, or DSP modes.
Master/Slave Auxiliary Mode
When the AD1839A is operating in the auxiliary mode, the
auxiliary ADC control pins, AUXBCLK and AUXLRCLK, which
connect to the external ADCs, can be set to operate as a master
or slave. If the pins are set in slave mode, one of the external
ADCs should provide the LRCLK and BCLK signals.
Sample Rate
This bit controls the sample rate of the ADCs. Based on a
24.576 MHz IMCLK, sample rates of 48 kHz and 96 kHz are
available. The MCLK scaling bits in ADC Control 3 should be
programmed appropriately, based on the master clock
frequency.
ADC Peak Readback
Setting this bit enables ADC peak reading. See the ADCs
section for more information.
ADC Power-Down
This bit controls the power-down status of the ADC section and
operates in a manner similar to the DAC power-down.
Table 10. Control Register Map
Register Address
Register Name
DACCTRL1
DACCTRL2
DACVOL1
DACVOL2
DACVOL3
DACVOL4
DACVOL5
DACVOL6
DACVOL7
DACVOL8
ADCPeak0
ADCPeak1
ADCCTRL1
ADCCTRL2
ADCCTRL3
Reserved
Description
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Width
10
10
10
10
10
10
10
10
10
10
6
Reset Setting (Hex)
0000
DAC Control 1
000
000
3FF
0001
DAC Control 2
0010
DAC Volume—Left 1
DAC Volume—Right 1
DAC Volume—Left 2
DAC Volume—Right 2
DAC Volume—Left 3
DAC Volume—Right 3
DAC Volume—Left 4
DAC Volume—Right 4
ADC Left Peak
0011
3FF
0100
3FF
0101
3FF
0110
3FF
0111
3FF
1000
3FF
1001
3FF
1010
1011
1100
000
000
000
000
000
Reserved
ADC Right Peak
ADC Control 1
R
6
R/W
R/W
R/W
R/W
10
10
10
10
1101
ADC Control 2
1110
ADC Control 3
1111
Reserved
Rev. B | Page 20 of 24
AD1839A
Table 11. DAC Control 1
Function
Address
15, 14, 13, 12 11
0000
R/W RES De-emphasis DAC Data Format DAC Data-Word Width
Power-Down Reset Sample Rate
10
0
9, 8
7, 6, 5
000 = I2S
4, 3
2
1, 0
0
00 = None
01 = 44.1 kHz
10 = 32.0 kHz
11 = 48.0 kHz
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
0 = Normal
1 = Power-Down
00 = 8 × (48 kHz)
01 = 4 × (96 kHz)
10 = 2 × (192 kHz)
11 = 8 × (48 kHz)
001 = RJ
010 = DSP
011 = LJ
100 = Packed 256
101 = Packed128
110 = Reserved
111 = Reserved
Table 12. DAC Control 2
Function
MUTE DAC
Stereo
Replicate
W
R/
Address
RES Reserved
Reserved
Reserved
OUTR3
OUTL3
OUTR2
OUTL2
OUTR1
OUTL1
15, 14,
13, 12
11
10
9
8
7
6
5
4
3
2
1
0
0001
0
0
0
0 = Off
0 = On
0 = On
0 = On
0 = On
0 = On
0 = On
0 = On
0 = On
1 = Replicate
1 = Mute
1 = Mute
1 = Mute
1 = Mute
1 = Mute
1 = Mute
1 = Mute
1 = Mute
Table 13. DAC Volume Control
Function
R/W
11
0
Address
RES
DAC Volume
15, 14, 13, 12
0010 = DACL1
0011 = DACR1
0100 = DACL2
0101 = DACR2
0110 = DACL3
0111 = DACR3
10
0
9, 8, 7, 6, 5, 4, 3, 2, 1, 0
0000000000 = Mute
0000000001 = 1/1023
0000000010 = 2/1023
1111111110 = 1022/1023
1111111111 = 1023/1023
Table 14. ADC Peak
Function
R/W
Address
RES
10
0
Six Data Bits
Four Fixed Bits
15, 14, 13, 12
1010 = Left ADC
1011 = Right ADC
11
1
9, 8, 7, 6, 5, 4
3, 2, 1, 0
0000
000000 = 0.0 dBFS
000001 = –1.0 dBFS
000010 = –2.0 dBFS
These four bits are always 0.
111111 = –63.0 dBFS
Table 15. ADC Control 1
Function
ADC Power-
Down
R/W
11
0
Address
15, 14, 13, 12
1100
RES
10
0
Reserved
Filter
Sample Rate
6
Reserved
9
0
8
7
5, 4, 3, 2, 1, 0
0, 0, 0, 0, 0, 0
0, 0, 0, 0, 0, 0
0 = All Pass
1 = High-Pass
0 = Normal
1 = Power-Down
0 = 48 kHz
1 = 96 kHz
Rev. B | Page 21 of 24
AD1839A
Table 16. ADC Control 2
Function
ADC Data-
ADC MUTE
Word Width
R/W
11
0
Address
15, 14, 13, 12
1101
RES Master/Slave Aux Mode
ADC Data Format
8, 7, 6
000 = I2S
001 = RJ
010 = DSP
AUXDATA
3
RES Right
Left
10
0
9
5, 4
2
0
1
0
0 = Slave
1 = Master
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
0 = Off
1 = On
0 = On
0 = On
1 = Mute
1 = Mute
011 = LJ
100 = Packed 256
101 = Packed 128
110 = Auxiliary 256
111 = Auxiliary 512
Table 17. ADC Control 3
Function
R/W RES
Address
RES Reserved IMCLK Clocking Scaling ADC Peak Readback
DAC Test Mode
ADC Test Mode
1, 0
15, 14,
13, 12
11
10
9, 8
7, 6
5
4, 3, 2
1110
0
0
0, 0
00 = MCLK × 2
01 = MCLK
0 = Disabled Peak Readback 000 = Normal Mode 00 = Normal Mode
1 = Enabled Peak Readback All Others Reserved All Others Reserved
10 = MCLK × 2/3
11 = MCLK × 2
CASCADE MODE
Dual AD1839A Cascade
Device 1 set as a master, it generates the frame-sync and bit
clock signals. These signals are sent to the SHARC and Device 2,
ensuring that both know when to send and receive data.
The AD1839A can be cascaded to an additional AD1839A that,
in addition to six external stereo ADCs and two external stereo
DACs, can be used to create a 32-channel audio system with
16 inputs and 16 outputs. The cascade is designed to connect
to a SHARC DSP and operates in a time division multiplexing
(TDM) format. Figure 28 shows the connection diagram for
cascade operation. The digital interface for both parts must be
set to operate in Auxiliary 512 mode by programming ADC
Control Register 2. AD1839A Device 1 is set as the master
The cascade can be thought of as two 256-bit shift registers, one
for each device. At the beginning of a sample interval, the shift
registers contain the ADC results from the previous sample
interval. The first shift register (Device 1) clocks data into the
SHARC and clocks in data from the second shift register
(Device 2). While this is happening, the SHARC is sending DAC
data to the second shift register. By the end of the sample
interval, all 512 bits of ADC data in the shift registers have been
clocked into the SHARC and replaced by DAC data, which is
subsequently written to the DACs. Figure 29 shows the timing
diagram for the cascade operation.
device by connecting the /S pin to DGND; AD1839A
M
Device 2 is set as a slave device by connecting the /S to
M
ODVDD. Both devices should be run from the same MCLK
and
/
signals to ensure that they are synchronized. With
PD RST
Rev. B | Page 22 of 24
AD1839A
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
ASDATA
ASDATA
DRx
RFSx
RCLKx
DSDATA
DSDATA
ALRCLK
ABCLK
ALRCLK
ABCLK
AD1839A NO. 1
AD1839A NO. 2
(MASTER)
(SLAVE)
SHARC
(SLAVE)
TFSx
TCLKx
DTx
Figure 28. Dual AD1839A Cascade
256 ABCLKs
256 ABCLKs
TFSx/
RFSx
AD1839A NO. 1 DACs
L3 L4 R1 R2
AD1839A NO. 2 DACs
L3 L4 R1 R2
DTx
L1
L1
L2
L2
R3
R3
R4
R4
L1
L1
L2
L2
R3
R3
R4
R4
AD1839A NO. 1 ADCs
L3 L4 R1 R2
AD1839A NO. 2 ADCs
L3 L4 R1 R2
DRx
BCLK
LSB
LSB
MSB MSB – 1
MSB MSB – 1
DON’T CARE
DTx
DRx
32 ABCLKs
Figure 29. Dual AD1839A Cascade Timing
47µF
600Z
5.76kΩ
5.76kΩ
AUDIO
INPUT
+
68pF
NPO
11kΩ
3.01kΩ
120pF NPO
V
100pF
NPO
BIAS
(2.25V)
11kΩ
270pF
NPO
237Ω
ADCxN
OP275
AUDIO
OUTPUT
2.2nF
NPO
V
OP275
REF
604Ω
1nF
NPO
560pF
NPO
OUTx
100pF
NPO
5.62kΩ
5.76kΩ
750kΩ
5.76kΩ
1.5kΩ
5.62kΩ
150pF
NPO
1nF
NPO
237Ω
OP275
ADCxP
V
REF
Figure 31. Typical DAC Output Filter Circuit
Figure 30. Typical ADC Input Filter Circuit
Rev. B | Page 23 of 24
AD1839A
OUTLINE DIMENSIONS
13.45
1.03
0.88
0.73
13.20 SQ
12.95
2.45
MAX
39
27
40
26
SEATING
PLANE
10.20
10.00 SQ
9.80
7.80
REF
10°
6°
2°
TOP VIEW
(PINS DOWN)
2.20
2.00
1.80
0.23
0.11
VIEW A
7°
0°
PIN 1
0.25
MAX
52
14
0.13 MIN
1
13
COPLANARITY
VIEW A
ROTATED 90° CCW
0.65 BSC
0.40
0.22
COMPLIANT TO JEDEC STANDARDS MS-022-AC.
Figure 32. 52-Lead Metric Quad Flat Package [MQFP]
(S-52-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD1839AAS
AD1839AAS-REEL
AD1839AASZ1
AD1839AASZ-REEL1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
52-Lead MQFP
52-Lead MQFP
52-Lead MQFP
52-Lead MQFP
52-Lead MQFP
Package Option
S-52-1
S-52-1
S-52-1
S-52-1
S-52-1
EVAL-AD1839AEB
1 Z = Pb-free part.
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03627–0–6/04(B)
Rev. B | Page 24 of 24
相关型号：
AD1839AASZ
IC SPECIALTY CONSUMER CIRCUIT, PQFP52, LEAD FREE, PLASTIC, MS-022-AC, MQFP-52, Consumer IC:Other
ADI
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