AD1839AS-REEL [ADI]
2 ADC, 6 DAC, 96 kHz, 24-Bit sigma-delta Codec; 2 ADC ， DAC， 6 ， 96千赫，24位Σ-Δ编解码器
| 型号： | AD1839AS-REEL |
| 厂家： | 
ADI |
| 描述： | 2 ADC, 6 DAC, 96 kHz, 24-Bit sigma-delta Codec |
| 文件： | 总24页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 ADC, 6 DAC,
96 kHz, 24-Bit ꢀ-ꢁ Codec
AD1839
APPLICATIONS
FEATURES
DVD Video and Audio Players
Home Theater Systems
5 V Stereo Audio System with 3.3 V Tolerant
Digital Interface
Automotive Audio Systems
Audio/Visual Receivers
Digital Audio Effects Processors
Supports up to 96 kHz Sample Rates
192 kHz Sample Rate Available on One DAC
Supports 16-/20-/24-Bit Word Lengths
Multibit ꢀ-ꢁ Modulators with
Perfect Differential Linearity Restoration for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least
Sensitive to Jitter
Single-Ended Output
ADCs: –95 dB THD + N, 105 dB SNR and
Dynamic Range
DACs: –92 dB THD + N, 108 dB SNR and
Dynamic Range
PRODUCT OVERVIEW
The AD1839 is a high performance single-chip codec featuring
three stereo DACs and one stereo ADC. Each DAC comprises
a high performance digital interpolation filter, a multibit ⌺-⌬
modulator featuring Analog Devices’ patented technology, and
a continuous-time voltage out analog section. Each DAC has
independent volume control and clickless mute functions. The
ADC comprises two 24-bit conversion channels with multibit
⌺-⌬ modulators and decimation filters.
On-Chip Volume Controls per Channel with
1024 Step Linear Scale
The AD1839 also contains an on-chip reference with a nominal
value of 2.25 V.
DAC and ADC Software Controllable Clickless Mutes
Digital De-emphasis Processing
Supports 256 ꢂ fS, 512 ꢂ fS, and 768 ꢂ fS Master
Mode Clocks
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S Compatible, and DSP Serial Port Modes
TDM Interface Mode Supports 8 In/8 Out Using a
Single SHARC ® SPORT
The AD1839 contains a flexible serial interface that allows
for glueless connection to a variety of DSP chips, AES/EBU
receivers, and sample rate converters. The AD1839 can be
configured in left-justified, right-justified, I2S, or DSP com-
patible serial modes. Control of the AD1839 is achieved by
means of an SPI® compatible serial port. While the AD1839
can be operated from a single 5 V supply, it also features a
separate supply pin for its digital interface that allows the device
to be interfaced to other devices using 3.3 V power supplies.
52-Lead MQFP Plastic Package
The AD1839 is available in a 52-lead MQFP package and is
specified for the industrial temperature range of –40ºC to +85ºC.
FUNCTIONAL BLOCK DIAGRAM
DVDD DVDD ODVDD ALRCLK ABCLK ASDATA CCLK CLATCH CIN COUT
MCLK
AVDD
PD/RST M/S
AVDD
AAUXDATA3
DLRCLK
CLOCK
CONTROL PORT
OUTL1
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
SERIAL DATA
I/O PORT
DBCLK
ꢀ-ꢁ
DAC
DIGITAL
FILTER
DSDATA1
DSDATA2
DSDATA3
DAUXDATA
OUTR1
OUTL2
ꢀ-ꢁ
DAC
DIGITAL
FILTER
OUTR2
OUTL3
ꢀ-ꢁ
DAC
DIGITAL
FILTER
ADCLP
ADCLN
ꢀ-ꢁ
ADC
DIGITAL
FILTER
OUTR3
FILTD
FILTR
ADCRP
ADCRN
ꢀ-ꢁ
ADC
DIGITAL
FILTER
V
AD1839
REF
DGND DGND AGND AGND AGND AGND
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD1839–SPECIFICATIONS
TEST CONDITIONS
Supply Voltages (AVDD, DVDD) 5.0 V
Ambient Temperature
Input Clock
DAC Input Signal
ADC Input Signal
Input Sample Rate (fS)
Measurement Bandwidth
Word Width
25∞C
12.288 MHz, (256 ϫ fS Mode)
1.0078125 kHz, 1.0 dBFS
1.0078125 kHz, 0 dBFS
48 kHz
20 Hz to 20 kHz
24 Bits
Load Capacitance
Load Impedance
100 pF
47 kW
Performance of all channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Parameter
Min
Typ
Max
Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
24
Bits
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter
A-Weighted
Total Harmonic Distortion + Noise (THD+N)
Interchannel Isolation
Interchannel Gain Mismatch
Analog Inputs
103
105
–95
100
0.025
dB
dB
dB
dB
dB
100
–88.5
Differential Input Range (± Full Scale)
Common-Mode Input Voltage
Input Impedance
Input Capacitance
VREF
–2.828
+2.828
V
V
kW
pF
V
2.25
4
15
2.25
DC Accuracy
Gain Error
Gain Drift
±5
35
%
ppm/ºC
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
Dynamic Range (20 Hz to 20 kHz, –60 dBFS Input)
No Filter
With A-Weighted Filter
Total Harmonic Distortion + Noise
Interchannel Isolation
103
105
105
108
–92
110
dB
dB
dB
dB
–90
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
±4
0.025
200
%
dB
ppm/∞C
Interchannel Phase Deviation
Volume Control Step Size (1023 Linear Steps)
Volume Control Range (Max Attenuation)
Mute Attenuation
±0.1
0.098
60
–100
±0.1
1.0 (2.8)
180
Degrees
%
dB
dB
De-emphasis Gain Error
dB
Full-Scale Output Voltage at Each Pin
Output Resistance at Each Pin
Common-Mode Output Voltage
V rms (V p-p)
W
V
2.25
ADC DECIMATION FILTER, 48 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
21.77
±0.01
26.23
120
kHz
dB
kHz
dB
910
ms
–2–
REV. B
AD1839
Parameter
Min
Typ
Max
Unit
ADC DECIMATION FILTER, 96 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
43.54
±0.01
52.46
120
kHz
dB
kHz
dB
460
ms
DAC INTERPOLATION FILTER, 48 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
21.77
43.54
81.2
kHz
dB
kHz
dB
±0.06
28
55
340
ms
DAC INTERPOLATION FILTER, 96 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
kHz
dB
kHz
dB
±0.06
52
55
160
ms
DAC INTERPOLATION FILTER, 192 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
kHz
dB
kHz
dB
±0.06
97
80
110
ms
DIGITAL I/O
Input Voltage High
Input Voltage Low
Output Voltage High
Output Voltage Low
Leakage Current
2.4
V
V
V
V
0.8
ODVDD – 0.4
0.4
±10
mA
POWER SUPPLIES
Supply Voltage (AVDD and DVDD
Supply Voltage (ODVDD
Supply Current IANALOG
Supply Current IANALOG, Power-Down
Supply Current IDIGITAL
)
4.5
3.0
5.0
5.5
DVDD
95
67
74
V
V
mA
mA
mA
mA
)
84
55
64
1
Supply Current IDIGITAL, Power-Down
Dissipation
4.5
Operation, Both Supplies
Operation, Analog Supply
Operation, Digital Supply
Power-Down, Both Supplies
740
420
320
280
mW
mW
mW
mW
Power Supply Rejection Ratio
1 kHz, 300 mV p-p Signal at Analog Supply Pins
20 kHz, 300 mV p-p Signal at Analog Supply Pins
–70
–75
dB
dB
*Guaranteed by design.
Specifications subject to change without notice.
REV. B
–3–
AD1839
TIMING SPECIFICATIONS
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
tMH
tML
MCLK High
MCLK Low
PD/RST Low
15
15
20
ns
ns
ns
tPDR
SPI PORT
tCCH
tCCL
tCCP
tCDS
tCDH
tCLS
tCLH
tCOE
tCOD
CCLK High
CCLK Low
40
40
80
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Three-State
To CCLK Rising
From CCLK Rising
To CCLK Rising
From CCLK Rising
From CLATCH Falling
From CCLK Falling
From CLATCH Rising
15
20
25
tCOTS
DAC SERIAL PORT
Normal Mode (Slave)
tDBH
tDBL
fDB
tDLS
tDLH
tDDS
tDDH
DBCLK High
DBCLK Low
60
60
64 ϫ fS
10
10
10
10
ns
ns
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
ns
ns
ns
ns
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
Packed 256 Modes (Slave)
tDBH
tDBL
fDB
tDLS
tDLH
tDDS
tDDH
DBCLK High
DBCLK Low
15
15
256 ϫ fS
10
5
ns
ns
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
ns
ns
ns
ns
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
10
10
ADC SERIAL PORT
Normal Mode (Master)
tABD
ABCLK Delay
25
5
10
ns
ns
ns
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
tALD
tABDD
ALRCLK Delay Low
ASDATA Delay
Normal Mode (Slave)
tABH
tABL
fAB
tALS
tALH
ABCLK High
ABCLK Low
ABCLK Frequency
ALRCLK Setup
ALRCLK Hold
60
60
64 ϫ fS
5
ns
ns
ns
ns
To ABCLK Rising
15
From ABCLK Rising
Packed 256 Mode (Master)
tPABD
tPALD
tPABDD
ABCLK Delay
LRCLK Delay
ASDATA Delay
20
5
10
ns
ns
ns
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
–4–
REV. B
AD1839
Parameter
Min
Max
Unit
Comments
TDM256 MODE (Master)
tTBD
BCLK Delay
20
5
10
ns
ns
ns
ns
ns
From MCLK Rising
From BCLK Rising
From BCLK Rising
To BCLK Falling
tFSD
FSTDM Delay
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
tTABD
tTDDS
tTDDH
15
15
From BCLK Falling
TDM256 MODE (Slave)
fAB
BCLK Frequency
256 ϫ fS
tTBCH
tTBCL
tTFS
BCLK High
BCLK Low
FSTDM Setup
FSTDM Hold
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
15
15
10
10
ns
ns
ns
ns
ns
ns
ns
To BCLK Falling
From BCLK Falling
From BCLK Rising
To BCLK Falling
From BCLK Falling
tTFH
tTBDD
tTDDS
tTDDH
10
15
15
AUXILIARY INTERFACE
tAXDS
AAUXDATA Setup
10
10
15
64 ϫ fS
ns
ns
ns
To AUXBCLK Rising
From AUXBCLK Rising
From AUXBCLK Falling
tAXDH
tDXD
fABP
AAUXDATA Hold
DAUXDATA Delay
AUXBCLK Frequency
Slave Mode
tAXBH
tAXBL
tAXLS
tAXLH
AUXBCLK High
AUXBCLK Low
AUXLRCLK Setup
AUXLRCLK Hold
15
15
10
10
ns
ns
ns
ns
To AUXBCLK Rising
From AUXBCLK Rising
Master Mode
tAUXLRCLK
tAUXBCLK
AUXLRCLK Delay
AUXBCLK Delay
5
15
ns
ns
From AUXBCLK Falling
From MCLK Rising
Specifications subject to change without notice.
tMCLK
tMH
MCLK
tML
PD/RST
tPDR
Figure 1. MCLK and PD/RST Timing
REV. B
–5–
AD1839
TEMPERATURE RANGE
Parameter
Min
Typ
Max
Unit
Specifications Guaranteed
Functionality Guaranteed
Storage
25
∞C
∞C
∞C
–40
–65
+85
+150
ABSOLUTE MAXIMUM RATINGS*
(TA = 25∞C, unless otherwise noted.)
AVDD, DVDD, ODVDD to AGND, DGND . . –0.3 V to +6.0 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to ODVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40∞C to +85∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD1839AS
–40oC to +85oC
52-Lead MQFP
52-Lead MQFP
Evaluation Board
S-52
S-52
AD1839AS-REEL –40oC to +85oC
EVAL-AD1839EB
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD1839 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–6–
REV. B
AD1839
PIN CONFIGURATION
48
50 49
47 46 45 44 43 42 41 40
51
52
39 DVDD
1
2
DVDD
CLATCH
CIN
38
37
36
DBCLK
DLRCLK
DAUXDATA
M/S
3
4
PD/RST
AGND
NC
5
35
34
AGND
NC
6
AD1839
TOP VIEW
33
32
31
OUTL1
NC
7
(Not to Scale
)
8
NC
OUTR1
AGND
AVDD
9
NC
10
11
12
13
30 AGND
29 AVDD
28 OUTR3
27 NC
NC
OUTL2
14 15 16 17 18 19 20 21 22 23 24 25 26
PIN FUNCTION DESCRIPTIONS
Input/
Pin No.
Mnemonic
Output
Description
1, 39
2
3
4
DVDD
CLATCH
CIN
PD/RST
AGND
NC
Digital Power Supply. Connect to digital 5 V supply.
Latch Input for Control Data.
Serial Control Input.
Power-Down/Reset.
Analog Ground.
I
I
I
5, 10, 16, 24, 30, 34
6, 8, 12, 14, 25,
Not Connected.
27, 31–33
7, 13, 26
9, 15, 28
11, 19, 29
17
18
20
21
22
NC
Not Connected.
OUTLx
OUTRx
AVDD
FILTD
FILTR
ADCLN
ADCLP
ADCRN
ADCRP
M/S
O
O
DACx Left Channel Output.
DACx Right Channel Output.
Analog Power Supply. Connect to analog 5 V supply.
Filter Capacitor Connection. Recommended 10 mF/100 nF.
Reference Filter Capacitor Connection. Recommended 10 mF/100 nF.
ADC Left Channel Negative Input.
ADC Left Channel Positive Input.
ADC Right Channel Negative Input.
ADC Right Channel Positive Input.
ADC Master/Slave Select.
I
I
I
I
23
35
I
36
37
38
DAUXDATA
DLRCLK
DBCLK
I
I/O
I/O
Auxiliary DAC Input Data.
DAC LR Clock.
DAC Bit Clock.
40, 52
41–43
44
45
46
DGND
Digital Ground.
DSDATAx
AAUXDATA3
ABCLK
ALRCLK
MCLK
I
I
I/O
I/O
I
DACx Input Data (Left and Right Channels).
Auxiliary ADC3 Digital Input.
ADC Bit Clock.
ADC LR Clock.
Master Clock Input.
47
48
49
50
51
ODVDD
ASDATA
COUT
Digital Output Driver Power Supply.
ADC Serial Data Output.
Output for Control Data.
O
O
I
CCLK
Control Clock Input for Control Data.
REV. B
–7–
AD1839–Typical Performance Characteristics
5
0
0
–5
–50
–10
–15
–20
–25
–30
–100
–150
0
5
10
15
20
0
5
10
15
FREQUENCY (Hz)
FREQUENCY (Normalized to fS)
TPC 1. ADC Composite Filter Response
TPC 4. ADC High-Pass Filter Response, fS = 96 kHz
0
5
0
–5
–50
–100
–150
–10
–15
–20
–25
–30
0
50
100
150
200
0
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (Hz)
TPC 2. ADC High-Pass Filter Response, fS = 48 kHz
TPC 5. DAC Composite Filter Response, fS = 48 kHz
0
0
–50
–100
–150
–50
–100
–150
0
0.5
1.0
1.5
2.0
0
50
100
150
200
FREQUENCY (Normalized to fS)
FREQUENCY (kHz)
TPC 3. ADC Composite Filter Response
(Pass-Band Section)
TPC 6. DAC Composite Filter Response, fS = 96 kHz
–8–
REV. B
AD1839
0.2
0.1
0
–50
0
–0.1
–0.2
–100
–150
0
50
100
150
200
0
10
20
30
40
50
FREQUENCY (kHz)
FREQUENCY (kHz)
TPC 7. DAC Composite Filter Response, fS = 192 kHz
TPC 9. DAC Composite Filter Response, fS = 96 kHz
(Pass-Band Section)
0.10
0.05
0
0.10
0.05
0
–0.05
–0.10
–0.05
–0.10
0
5
10
15
20
0
20
40
60
80
100
FREQUENCY (kHz)
FREQUENCY (kHz)
TPC 8. DAC Composite Filter Response, fS = 48 kHz
(Pass-Band Section)
TPC 10. DAC Composite Filter Response, fS = 192 kHz
(Pass-Band Section)
REV. B
–9–
AD1839
TERMINOLOGY
Gain Drift
Dynamic Range
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per ∞C.
The ratio of a full-scale input signal to the integrated input noise
in the pass band (20 Hz to 20 kHz), expressed in decibels (dB).
Dynamic range is measured with a –60 dB input signal and is
equal to (S/[THD + N]) + 60 dB. Note that spurious harmon-
ics are below the noise with a –60 dB input, so the noise level
establishes the dynamic range. The dynamic range is specified
with and without an A-Weight filter applied.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine wave input on the other channel, expressed
in decibels.
Power Supply Rejection
With no analog input, signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.
Signal-to-(Total Harmonic Distortion + Noise)
[S/(THD + N)]
The ratio of the root-mean-square (rms) value of the fundamental
input signal to the rms sum of all other spectral components in
the pass band, expressed in decibels (dB).
Group Delay
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in milliseconds (ms).
More precisely, the derivative of radian phase with respect to
radian frequency at a given frequency.
Pass Band
The region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Group Delay Variation
Pass-Band Ripple
The difference in group delays at different input frequencies.
Specified as the difference between the largest and the smallest
group delays in the pass band, expressed in microseconds (ms)
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the pass band, expressed
in decibels.
Stop Band
ACRONYMS
The region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by stop-band attenuation.
ADC—Analog-to-Digital Converter
DAC—Digital-to-Analog Converter
DSP—Digital Signal Processor
Gain Error
With identical near full-scale inputs, the ratio of actual output to
expected output, expressed as a percentage.
IMCLK—Internal Master Clock Signal used to clock the ADC
and DAC engines
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
MCLK—External Master Clock Signal applied to the AD1838
–10–
REV. B
AD1839
FUNCTIONAL OVERVIEW
ADCs
order external low-pass filter is recommended to remove high
frequency noise present on the output pins. Note that the use of
op amps with low slew rate or low bandwidth may cause high
frequency noise and tones to fold down into the audio band;
care should be exercised in selecting these components.
There are two ADC channels in the AD1839, configured as a
stereo pair. Each ADC has fully differential inputs. The ADC
section can operate at a sample rate of up to 96 kHz. The ADCs
include on-board digital decimation filters with 120 dB stop-band
attenuation and linear phase response, operating at an over-
sampling ratio of 128 (for 48 kHz operation) or 64 (for 96 kHz
operation).
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases, this capacitor may be eliminated with little effect
on performance.
ADC peak level information for each ADC may be read from
the ADC Peak 0 and ADC Peak 1 registers. The data is supplied
as a 6-bit word with a maximum range of 0 dB to –63 dB and a
resolution of 1 dB. The registers will hold peak information until
read; after reading, the registers are reset so that new peak
information can be acquired. Refer to the register description
for details of the format. The two ADC channels have a common
serial bit clock and a left-right framing clock. The clock signals
are all synchronous with the sample rate.
DAC and ADC Coding
The DAC and ADC output data stream is in a twos complement
encoded format. The word width can be selected from 16-bit,
20-bit, or 24-bit. The coding scheme is detailed in Table I.
Table I. Coding Scheme
Code
Level
The ADC digital pins, ABCLK and ALRCLK, can be set to
operate as inputs or outputs by connecting the M/S pin to
ODVDD or DGND, respectively. When the pins are set as
outputs, the AD1839 will generate the timing signals. When
the pins are set as inputs, the timing must be generated by the
external audio controller.
01111......1111
00000......0000
10000......0000
+FS
0 (Ref Level)
–FS
Clock Signals
The DAC and ADC engines in the AD1839 are designed to oper-
ate from a 24.576 MHz internal master clock (IMCLK). This
clock is used to generate 48 kHz and 96 kHz sampling on the
ADC and 48 kHz, 96 kHz, and 192 kHz on the DAC, although
the 192 kHz option is available only on one DAC pair. The
stereo replicate feature can be used to copy this DAC data to
the other DACs if required.
DACs
The AD1839 has six DAC channels arranged as three independent
stereo pairs, with six single-ended analog outputs. Each channel
has its own independently programmable attenuator, adjustable
in 1024 linear steps. Digital inputs are supplied through three
serial data input pins (one for each stereo pair) and a common
frame (DLRCLK) and bit (DBCLK) clock. Alternatively, one
of the packed data modes may be used to access all six channels
on a single TDM data pin. A stereo replicate feature is included
where the DAC data sent to the first DAC pair is also sent to the
other DACs in the part. The AD1839 can accept DAC data at a
sample rate of 192 kHz on DAC 1 only. The stereo replicate
feature can then be used to copy the audio data to the other DACs.
To facilitate the use of the different MCLK values, the AD1839
provides a clock scaling feature. The MCLK scaler can be pro-
grammed via the SPI port to scale the MCLK by a factor of 1
(pass through), 2 (doubling), or 2/3. The default setting of the
MCLK scaler is 2, which will generate 48 kHz sampling from a
12.288 MHz MCLK. Additional sample rates can be achieved
by changing the MCLK value. For example, the CD standard
sampling frequency of 44.1 kHz can be achieved using an
11.2896 kHz MCLK. Figure 2 shows the internal configura-
tion of the clock scaler and converter engines.
Each of the output pins sits at a dc level of VREF and swings
1.4 V for a 0 dB digital input signal. A single op amp third
DAC ENGINE
48kHz/96kHz/192kHz
ANALOG
OUTPUT
⌺-⌬
MODULATOR
INTERPOLATION
DAC INPUT
DAC
FILTER
CLOCK SCALING
؋
1 ؋
2 MCLK
IMCLK = 24.576MHz
12.288MHz
؋
2/3 ADC ENGINE
48kHz/96kHz
⌺-⌬
MODULATOR
ANALOG
INPUT
OPTIONAL
HPF
DECIMATOR/
FILTER
ADC OUTPUT
Figure 2. Modulator Clocking Scheme
–11–
REV. B
AD1839
To maintain the highest performance possible, it is recommended
that the clock jitter of the master clock signal be limited to less
than 300 ps rms, measured using the edge-to-edge technique.
Even at these levels, extra noise or tones may appear in the
DAC outputs if the jitter spectrum contains large spectral peaks.
It is highly recommended that the master clock be generated by
an independent crystal oscillator. In addition, it is especially
important that the clock signal should not be passed through an
FPGA or other large digital chip before being applied to the
AD1839. In most cases, this will induce clock jitter due to the
fact that the clock signal is sharing common power and ground
connections with other unrelated digital output signals.
Serial Data Ports—Data Format
The ADC serial data output mode defaults to the popular I2S
format, where the data is delayed by 1 BCLK interval from the
edge of the LRCLK. By changing Bits 6 to 8 in ADC Control
Register 2, the serial mode can be changed to right-justified
(RJ), left-justified DSP (DSP), or left-justified (LJ). In the RJ
mode, it is necessary to set Bits 4 and 5 to define the width of
the data-word.
The DAC serial data input mode defaults to I2S. By changing
Bits 5, 6, and 7 in DAC Control Register 1, the mode can be
changed to RJ, DSP, LJ, or Packed Mode 256. The word width
defaults to 24 bits but can be changed by reprogramming Bits 3
and 4 in DAC Control Register 1.
RESET and Power-Down
PD/RST will power down the chip and set the control registers
to their default settings. After PD/RST is deasserted, an initial-
ization routine will run inside the AD1839 to clear all memories
to zero. This initialization lasts for approximately 20 LRCLK
intervals. During this time, it is recommended that no SPI
writes occur.
Packed Modes
The AD1839 has a packed mode that allows a DSP or other
controller to write to all DACs and read all ADCs using one
input data pin and one output data pin. Packed Mode 256
refers to the number of BCLKs in each frame. The LRCLK is
low while data from a left channel DAC or ADC is on the data
pin, and high while data from a right channel DAC or ADC is
on the data pin. DAC data is applied on the DSDATA1 pin,
and ADC data is available on the ASDATA pin. Figures 7 to 10
show the timing for the packed mode. Packed mode is available
only for 48 kHz (based on MCLK = 12.288 MHz), and when
the M/S is low.
Power Supply and Voltage Reference
The AD1839 is designed for 5 V supplies. Separate power supply
pins are provided for the analog and digital sections. These pins
should be bypassed with 100 nF ceramic chip capacitors, as
close to the pins as possible, to minimize noise pickup. A bulk
aluminum electrolytic capacitor of at least 22 mF should also
be provided on the same PC board as the codec. For critical
applications, improved performance will be obtained with
separate supplies for the analog and digital sections. If this is
not possible, it is recommended that the analog and digital
supplies be isolated by means of two ferrite beads in series with
the bypass capacitor of each supply. It is important that the
analog supply be as clean as possible.
Auxiliary (TDM) Mode
A special auxiliary mode is provided to allow three external
stereo ADCs and one external stereo DAC to be interfaced to
the AD1839 to provide 8-in/8-out operation. In addition, this
mode supports glueless interface to a single SHARC DSP serial
port, allowing a SHARC DSP to access all eight channels of
analog I/O. In this special mode, many pins are redefined; see
Table II for a list of redefined pins. The auxiliary and the TDM
interfaces are independently configurable to operate as masters
or slaves. When the auxiliary interface is set as a master, by
programming the Aux Mode bit in ADC Control Register 2, the
AUXLRCLK and AUXBCLK are generated by the AD1839.
When the auxiliary interface is set as a slave, the AUXLRCLK and
AUXBCLK need to be generated by an external ADC as shown
in Figure 13.
The internal voltage reference is brought out on the FILTR pin
and should be bypassed as close as possible to the chip, with a
parallel combination of 10 mF and 100 nF. The reference voltage
may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the FILTR pin should be limited to less than 50 mA.
Serial Control Port
The AD1839 has an SPI compatible control port to permit
programming the internal control registers for the ADCs and
DACs, and to read the ADC signal levels from the internal
peak detectors. The SPI control port is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 16 bits wide. The maximum serial bit
clock frequency is 12.5 MHz and may be completely asynchro-
nous to the sample rate of the ADCs and DACs. Figure 3
shows the format of the SPI signal.
The TDM interface can be set to operate as a master or slave by
connecting the M/S pin to DGND or ODVDD, respectively. In
master mode, the FSTDM and BCLK signals are outputs and
are generated by the AD1839. In slave mode, the FSTDM and
BCLK are inputs and should be generated by the SHARC. Slave
mode operation is available for 48 kHz and 96 kHz operation
(based on a 12.288 MHz or 24.576 MHz MCLK), and master
mode operation is available for 48 kHz only.
–12–
REV. B
AD1839
tCLS
tCLH
tCCH tCCL
tCCP
CLATCH
CCLK
tCOTS
tCDS tCDH
CIN
D9
D9
D8
D15
D14
D0
tCOE
COUT
D8
D0
tCOD
Figure 3. Format of SPI Timing
LRCLK
BCLK
LEFT CHANNEL
RIGHT CHANNEL
SDATA
MSB
LSB
MSB
LSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
BCLK
RIGHT CHANNEL
MSB
LSB
MSB
LSB
SDATA
2
I S MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
MSB
LSB
MSB
LSB
SDATA
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 ꢂ fS
.
3. BCLK FREQUENCY IS NORMALLY 64 ꢂ LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 4. Stereo Serial Modes
REV. B
–13–
AD1839
tABH
tABP
ABCLK
tABL
tALS
tALH
ALRCLK
ASDATA
LEFT-JUSTIFIED
MODE
MSB
MSB –1
MSB
ASDATA
2
I S MODE
ASDATA
RIGHT-JUSTIFIED
MODE
LSB
MSB
Figure 5. ADC Serial Mode Timing
tDBP
tDBH
DBCLK
tDBL
tDLS
tDLH
DLRCLK
tDDS
DSDATA
LEFT-JUSTIFIED
MODE
MSB
tDDH
MSB – 1
tDDS
MSB
tDDH
DSDATA
2
I S MODE
tDDS
LSB
tDDH
tDDS
MSB
tDDH
DSDATA
RIGHT-JUSTIFIED
MODE
Figure 6. DAC Serial Mode Timing
–14–
REV. B
AD1839
LRCLK
BCLK
256 BCLKs
32 BCLKs
SLOT 1
LEFT
SLOT 5
RIGHT
ADC DATA
SLOT 2 SLOT 3 SLOT 4
SLOT 7 SLOT 8
SLOT 6
MSB
MSB – 1 MSB – 2
Figure 7. ADC Packed Mode 256
LRCLK
BCLK
256 BCLKs
32 BCLKs
SLOT 1 SLOT 2 SLOT 3
LEFT 1 LEFT 2 LEFT 3
SLOT 5 SLOT 6 SLOT 7
RIGHT 1 RIGHT 2 RIGHT 3
DAC DATA
SLOT 4
SLOT 8
MSB
MSB – 1 MSB – 2
Figure 8. DAC Packed Mode 256
ABCLK
DBCLK
ALRCLK
ASDATA
DLRCLK
DSDATA
MSB
MSB
MSB – 1
MSB – 1
Figure 9. ADC Packed Mode Timing
Figure 10. DAC Packed Mode Timing
REV. B
–15–
AD1839
Table II. Pin Function Changes in Auxiliary Mode
Pin Name
I2S Mode
Aux Mode
ASDATA (O)
DSDATA1 (I)
DSDATA2 (I)/AAUXDATA1 (I)
DSDATA3 (I)/AAUXDATA2 (I)
AAUXDATA3 (I)
ALRCLK (O)
ABCLK (O)
I2S Data Out, Internal ADC
I2S Data In, Internal DAC1
I2S Data In, Internal DAC2
I2S Data In, Internal DAC3
Not Connected
TDM Data Out to SHARC
TDM Data In from SHARC
AUX-I2S Data In 1 (from Ext. ADC)
AUX-I2S Data In 2 (from Ext. ADC)
AUX-I2S Data In 3 (from Ext. ADC)
TDM Frame Sync Out to SHARC (FSTDM)
TDM BCLK Out to SHARC
LRCLK for ADC
BCLK for ADC
DLRCLK (I)/AUXLRCLK(I/O)
LRCLK In/Out Internal DACs
AUX LRCLK In/Out. Driven by Ext. LRCLK
from ADC in slave mode. In master mode,
driven by MCLK/512.
DBCLK (I)/AUXBCLK(I/O)
DAUXDATA(O)
BCLK In/Out Internal DACs
Not Connected
AUX BCLK In/Out. Driven by Ext. BCLK from
ADC in slave mode. In master mode, driven by
MCLK/8.
AUX-I2S Data Out (to Ext. DAC)
FSTDM
BCLK
TDM
MSB TDM
MSB TDM
1ST
CH
8TH
CH
ASDATA1
TDM (OUT)
INTERNAL
ADC L1
INTERNAL
ADC R1
AUX_ADC R3
AUX_ADC R2
AUX_ADC R4
AUX_ADC L4
AUX_ADC L2
AUX_ADC L3
ASDATA
32
MSB TDM
MSB TDM
1ST
CH
8TH
CH
DSDATA1
TDM (IN)
INTERNAL
DAC L1
INTERNAL
DAC L2
INTERNAL
DAC L3
INTERNAL
DAC R1
INTERNAL
DAC R2
INTERNAL
DAC R3
AUX DAC L4
AUX DAC R4
DSDATA1
32
AUX
2
LRCLK I S
RIGHT
LEFT
(FROM AUX ADC 1)
AUX
2
BCLK I S
(FROM AUX ADC 1)
AAUXDATA1 (IN)
(FROM AUX ADC 1)
2
2
I S—MSB LEFT
I S—MSB RIGHT
AAUXDATA2 (IN)
(FROM AUX ADC 2)
2
2
I S—MSB LEFT
I S—MSB RIGHT
AAUXDATA3 (IN)
(FROM AUX ADC 3)
2
2
I S—MSB LEFT
I S—MSB RIGHT
AUX BCLK FREQUENCY IS 64 ꢂ FRAME RATE; TDM BCLK FREQUENCY IS 256 ꢂ FRAME RATE.
Figure 11. Aux Mode Timing
–16–
REV. B
AD1839
30MHz
SHARC IS ALWAYS
RUNNING IN SLAVE MODE
(INTERRUPT DRIVEN).
SHARC
12.288MHz
LRCLK
BCLK
DATA
MCLK
ADC 1
SLAVE
LRCLK
BCLK
DATA
MCLK
ADC 1
ASDATA FSTDM
BCLK DSDATA1
SLAVE
LRCLK
BCLK
DBCLK/AUXBCLK
DAC 1
SLAVE
DLRCLK/AUXLRCLK
DAUXDATA
DATA
MCLK
LRCLK
BCLK
DATA
MCLK
DSDATA2/AAUXDATA1
ADC 2
SLAVE
DSDATA3/AAUXDATA2
AAUXDATA3
MCLK
AD1839
MASTER
Figure 12. Aux Mode Connection to SHARC (Master Mode)
30MHz
SHARC IS ALWAYS
RUNNING IN SLAVE MODE
(INTERRUPT DRIVEN).
SHARC
12.288MHz
LRCLK
BCLK
DATA
MCLK
ADC 1
MASTER
LRCLK
BCLK
DATA
MCLK
ADC 1
ASDATA FSTDM
BCLK DSDATA1
SLAVE
LRCLK
BCLK
DBCLK/AUXBCLK
DAC 1
SLAVE
DLRCLK/AUXLRCLK
DAUXDATA
DATA
MCLK
LRCLK
BCLK
DATA
MCLK
DSDATA2/AAUXDATA1
ADC 2
SLAVE
DSDATA3/AAUXDATA2
AAUXDATA3
MCLK
AD1839
SLAVE
Figure 13. Aux Mode Connection to SHARC (Slave Mode)
REV. B
–17–
AD1839
CONTROL/STATUS REGISTERS
DAC Volume Control
The AD1839 has 13 control registers, 11 of which are used to set
the operating mode of the part. The other two registers, ADC
Peak 0 and ADC Peak 1, are read-only and should not be pro-
grammed. Each of the registers is 10 bits wide with the exception
of the ADC peak reading registers, which are six bits wide. Writing
to a control register requires a 16-bit data frame to be transmit-
ted. Bits 15 to 12 are the address bits of the required register.
Bit 11 is a read/write bit. Bit 10 is reserved and should always
be programmed to 0. Bits 9 to 0 contain the 10-bit value that is
to be written to the register or, in the case of a read operation,
the 10-bit register contents. Figure 3 shows the format of the
SPI read and write operation.
Each DAC in the AD1839 has its own independent volume
control. The volume of each DAC can be adjusted in 1024 linear
steps by programming the appropriate register. The default
value for this register is 1023, which provides no attenuation,
i.e., full volume.
ADC CONTROL REGISTERS
The AD1839 register map has five registers that are used to
control the functionality and read the status of the ADCs. The
function of the bits in each of these registers is discussed below.
ADC Peak Level
These two registers store the peak ADC result from each channel
when the ADC peak readback function is enabled. The peak
result is stored as a 6-bit number from 0 dB to –63 dB in 1 dB
steps. The value contained in the register is reset once it has
been read, allowing for continuous level adjustment as required.
Note that the ADC peak level registers use the six most signifi-
cant bits in the register to store the results.
DAC CONTROL REGISTERS
The AD1839 register map has eight registers that are used to
control the functionality of the DAC section of the part. The
function of the bits in these registers is discussed below.
Sample Rate
These bits control the sample rate of the DACs. Based on a
24.576 MHz IMCLK, sample rates of 48 kHz, 96 kHz, and
192 kHz are available. The MCLK scaling bits in ADC Control 3
should be programmed appropriately, based on the master clock
frequency.
Sample Rate
This bit controls the sample rate of the ADCs. Based on a
24.576 MHz IMCLK, sample rates of 48 kHz and 96 kHz are
available. The MCLK scaling bits in ADC Control III should be
programmed appropriately based on the master clock frequency.
Power-Down/Reset
ADC Power-Down
This bit controls the power-down status of the ADC section and
operates in a similar manner to the DAC power-down.
This bit controls the power-down status of the DAC section.
By default, normal mode is selected, but by setting this bit, the
digital section of the DAC stage can be put into a low power
mode, thus reducing the digital current. The analog output
section of the DAC stage is not powered down.
High-Pass Filter
The ADC signal path has a digital high-pass filter. Enabling this
filter will remove the effect of any dc offset in the analog input
signal from the digital output codes.
DAC Data-Word Width
These two bits set the word width of the DAC data. Compact
disc (CD) compatibility may require 16 bits, but many modern
digital audio formats require 24-bit sample resolution.
ADC Data-Word Width
These two bits set the word width of the ADC data.
ADC Data Format
DAC Data Format
The AD1839 serial data interface can be configured to be com-
patible with a choice of popular interface formats, including I2S,
LJ, RJ, or DSP modes.
The AD1839 serial data interface can be configured to be com-
patible with a choice of popular interface formats, including I2S,
LJ, RJ, or DSP modes. Details of these interface modes are given
in the Serial Data Ports section of this data sheet.
Master/Slave Auxiliary Mode
When the AD1839 is operating in the auxiliary mode, the
auxiliary ADC control pins, AUXBCLK and AUXLRCLK,
that connect to the external ADCs can be set to operate as a
master or slave. If the pins are set in slave mode, one of the
external ADCs should provide the LRCLK and BCLK signals.
De-emphasis
The AD1839 provides built-in de-emphasis filtering for the
three standard sample rates of 32.0 kHz, 44.1 kHz, and 48 kHz.
Mute DAC
Each of the six DACs in the AD1839 has its own independent
mute control. Setting the appropriate bit will mute the DAC
output. The AD1839 uses a clickless mute function that attenu-
ates the output to approximately –100 dB over a number of cycles.
ADC Peak Readback
Setting this bit enables ADC peak reading. See the ADC section
for more information.
Stereo Replicate
Setting this bit copies the digital data sent to the stereo pair
DAC 1 to the three other stereo DACs in the system. This
allows all three stereo DACs to be driven by one digital data
stream. Note that in this mode, DAC data sent to the other
DACs is ignored.
–18–
REV. B
AD1839
Table III. Control Register Map
Description
Register
Address
Register
Name
Reset
Setting (Hex)
Type
Width
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DACCTRL1
DACCTRL2
DACVOL1
DACVOL2
DACVOL3
DACVOL4
DACVOL5
DACVOL6
RES
DAC Control 1
DAC Control 2
DAC Volume–Left 1
DAC Volume–Right 1
DAC Volume–Left 2
DAC Volume–Right 2
DAC Volume–Left 3
DAC Volume–Right 3
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
10
10
10
10
10
10
10
10
10
10
6
000
000
3FF
3FF
3FF
3FF
3FF
3FF
Reserved
Reserved
000
000
000
000
000
Reserved
RES
Reserved
ADCPeak0
ADCPeak1
ADCCTRL1
ADCCTRL2
ADCCTRL3
Reserved
ADC Left Peak
ADC Right Peak
ADC Control 1
ADC Control 2
ADC Control 3
Reserved
R
6
R/W
R/W
R/W
R/W
10
10
10
10
Table IV. DAC Control 1
Function
Power-Down
Word Width
DAC Data
R/W RES De-emphasis
DAC Data-
Format
Address
Reset
Sample Rate
1, 0
15, 14, 13, 12 11
0000
10
0
9, 8
7, 6, 5
000 = I2S
001 = RJ
010 = DSP
4, 3
2
0
00 = None
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
0 = Normal
1 = Power-Down 01 = 96 kHz
10 = 192 kHz
00 = 48 kHz
01 = 44.1 kHz
10 = 32.0 kHz
11 = 48.0 kHz
011 = LJ
11 = 48 kHz
100 = Pack Mode 256
101 = Reserved
110 = Reserved
111 = Reserved
Table V. DAC Control 2
Function
Mute DAC
Reserved Reserved OUTR3 OUTL3 OUTR2 OUTL2 OUTR1 OUTL1
Stereo
Address R/W RES Reserved Replicate
15, 14,
13, 12
11
0
10
0
9
0
8
7
0
6
0
5
4
3
2
1
0
0001
0 = Off
0 = On
0 = On
0 = On
0 = On
0 = On
0 = On
1 = Replicate
1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute
REV. B
–19–
AD1839
Table VI. DAC Volume Control
Function
Table VII. ADC Peak
Function
Address
R/W
RES
DAC Volume
Four Fixed
Bits
Address
R/W RES Six Data Bits
15, 14, 13, 12
11
10
9, 8, 7, 6, 5, 4, 3, 2, 1, 0
15, 14, 13, 12
11 10 9, 8, 7, 6, 5, 4
3, 2, 1, 0
0010 = DACL1
0011 = DACR1
0100 = DACL2
0101 = DACR2
0110 = DACL3
0111 = DACR3
0
0
0000000000 = Mute
0000000001 = 1/1023
0000000010 = 2/1023
1111111110 = 1022/1023
1111111111 = 1023/1023
1010 = Left ADC 1
1011 = Right ADC
0
000000 = 0.0 dBFS 0000
000001 = –1.0 dBFS
000010 = –2.0 dBFS These four
bits are
always zero.
111111 = –63.0 dBFS
Table VIII. ADC Control 1
Function
ADC
Power-Down
Sample
Rate
Address
15, 14, 13, 12
1100
R/W
11
RES
RES
Filter
Reserved
10
0
9
0
8
7
6
5, 4, 3, 2, 1, 0
0
0 = All Pass
1 = High-Pass
0 = Normal
1 = Power-Down
0 = 48 kHz
1 = 96 kHz
0, 0, 0, 0, 0, 0
0, 0, 0, 0, 0, 0
Table IX. ADC Control 2
Function
ADC Data-
Word Width AUXDATA
R/W
Master/Slave ADC
ADC Mute
Address
RES RES Aux Mode
Data Format
Reserved Right
Left
15, 14, 13, 12 11
10
0
9
8, 7, 6
000 = I2S
001 = RJ
010 = DSP
5,4
3
2
0
1
0
1101
0
0 = Slave
1 = Master
00 = 24 Bits 0 = Disabled
01 = 20 Bits 1 = Enabled
10 = 16 Bits
0 = On
1 = Mute 1 = Mute
0 = On
011 = LJ
11 = Reserved
100 = Packed 256
101 = Reserved
110 = Auxiliary 256
111 = Reserved
Table X. ADC Control 3
Function
R/W
IMCLK
ADC
DAC
ADC
Address
RES RES Reserved Clocking Scaling Peak Readback
Test Mode
Test Mode
15, 14, 13, 12 11
1110
10
0
9, 8
0, 0
7, 6
5
4, 3, 2
1, 0
0
00 = MCLK ϫ 2
01 = MCLK
0 = Disabled Peak Readback 000 = Normal Mode 00 = Normal Mode
1 = Enabled Peak Readback All others reserved. All others reserved.
10 = MCLK ϫ 2/3
11 = MCLK ϫ 2
–20–
REV. B
AD1839
47ꢄF
600Z
5.76kꢃ
5.76kꢃ
+
AUDIO
INPUT
120pF NPO
100pF
NPO
68pF
NPO
11kꢃ
11kꢃ
3.01kꢃ
V
237ꢃ
BIAS
(2.25V)
ADCxN
OP275
5.76kꢃ
OP275
V
270pF
NPO
REF
1nF
NPO
604ꢃ
AUDIO
OP275
OUTPUT
100pF
NPO
2.2nF
NPO
560pF
NPO
5.76kꢃ
750kꢃ
5.62kꢃ
OUTx
1nF
1.5kꢃ
NPO
150pF
NPO
5.62kꢃ
237ꢃ
ADCxP
V
REF
Figure 14. Typical ADC Input Filter Circuit
Figure 15. Typical DAC Output Filter Circuit
REV. B
–21–
AD1839
OUTLINE DIMENSIONS
52-Lead Plastic Quad Flatpack [MQFP]
(S-52)
Dimensions shown in millimeters
13.45
1.03
0.88
0.73
13.20 SQ
12.95
2.45
MAX
39
27
40
26
SEATING
PLANE
10.20
10.00 SQ
9.80
7.80
REF
TOP VIEW
(PINS DOWN)
VIEW A
PIN 1
52
14
1
13
0.23
0.11
0.65 BSC
0.40
0.22
2.20
2.00
1.80
7ꢅ
0ꢅ
0.13 MIN
COPLANARITY
VIEW A
ROTATED 90ꢅ CCW
COMPLIANT TO JEDEC STANDARDS MS-022-AC
–22–
REV. B
AD1839
Revision History
Location
Page
8/03—Data Sheet changed from REV. A to REV. B.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Replaced Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Changes to Table IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Changes to Table IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Changes to Figure 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10/02—Data Sheet changed from REV. 0 to REV. A.
Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to FUNCTIONAL OVERVIEW section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Changes to Figure 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REV. B
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