AD1845JP-REEL [ADI]
Parallel-Port 16-Bit SoundPort Stereo Codec; 并口16位SoundPort立体声编解码器
| 型号： | AD1845JP-REEL |
| 厂家： | 
ADI |
| 描述： | Parallel-Port 16-Bit SoundPort Stereo Codec |
| 文件： | 总40页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Parallel-Port 16-Bit
SoundPort® Stereo Codec
a
AD1845
FEATURES
plete on-chip filtering, MPC Level-2 compliant analog mixing,
programmable gain, attenuation and mute, a variable sample
frequency generator, FIFOs, and supports advanced power-
down modes. It provides a direct, byte-wide interface to both
ISA (“AT ”) and EISA computer buses for simplified implemen-
tation on a computer motherboard or add-in card.
Single-Chip Integrated ∑∆ Digital Audio Stereo Codec
Microsoft® and Window s® Sound System Com patible
MPC Level-2+ Com pliant Mixing
16 m A Bus Drive Capability
Supports Tw o DMA Channels for Full Duplex Operation
On-Chip Capture and Playback FIFOs
Advanced Pow er-Dow n Modes
Program m able Gain and Attenuation
Sam ple Rates from 4.0 kHz to 50 kHz Derived from a
Single Clock or Crystal Input
68-Lead PLCC, 100-Lead TQFP Packages
Operation from +5 V Supplies
Byte-Wide Parallel Interface to ISA and EISA Buses
Pin Com patible w ith AD1848, AD1846, CS4248, CS4231
T he AD1845 SoundPort Stereo Codec supports a DMA re-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control
register accesses and for applications lacking DMA control.
T wo input control lines support mixed direct and indirect ad-
dressing of thirty-seven internal control registers over this asyn-
chronous interface. T he AD1845 includes dual DMA count
registers for full duplex operation enabling the AD1845 to cap-
ture data on one DMA channel and play back data on a separate
channel. T he FIFOs on the AD1845 reduce the risk of losing
data when making DMA transfers over the ISA/EISA bus. T he
FIFOs buffer data transfers and allow for relaxed timing in
acknowledging requests for capture and playback data.
P RO D UCT O VERVIEW
T he Parallel Port AD1845 SoundPort Stereo Codec integrates
key audio data conversion and control functions into a single
integrated circuit. T he AD1845 provides a complete, single chip
computer audio solution for business audio and multimedia
applications. T he codec includes stereo audio converters, com-
(Continued on Page 9)
FUNCTIO NAL BLO CK D IAGRAM
ANALOG
POWER DOWN
RESET
ANALOG SUPPLY
DIGITAL SUPPLY
CLOCK SOURCE
DIGITAL
L_MIC
R_MIC
0 dB/
20 dB
VARIABLE SAMPLE
FREQUENCY GENERATOR
AD1845
PLAYBACK REQ
PLAYBACK ACK
CAPTURE REQ
CAPTURE ACK
ADR1:0
L_LINE
R_LINE
L_AUX1
R_AUX1
L
⌺⌬ A/D
CONVERTER
M
U
X
GAIN
-LAW
A-LAW
FIFO
R
⌺⌬ A/D
CONVERTER
LINEAR
GAIN
P
A
R
A
L
L
E
L
DATA7:0
DIGITAL MIX
ATTENUATE
GAM = GAIN
ATTENTUATE
GAM
GAM
GAM
CS
MUTE
RD
L
⌺⌬ D/A
CONVERTER
ATTENUATE
MUTE
⌺
⌺
⌺
⌺
P
O
R
T
L_OUT
M_OUT
R_OUT
WR
-LAW
A-LAW
LINEAR
MUTE
⌺
FIFO
BUS DRIVER
CONTROL
R
⌺⌬ D/A
CONVERTER
ATTENUATE
MUTE
HOST DMA
INTERRUPT
⌺
⌺
⌺
⌺
EXTERNAL
CONTROL
GAM
GAM
M_IN
L_AUX2
R_AUX2
REFERENCE
CONTROL
REGISTERS
V
V
REF
REF_F
SoundPort is a registered trademark of Analog Devices, Inc.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
REV. C
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
AD1845–SPECIFICATIONS
STAND ARD TEST CO ND ITIO NS UNLESS O TH ERWISE NO TED
DAC Test Conditions
Calibrated
T emperature
25
°C
V
V
kHz
Hz
Digital Supply (VDD
Analog Supply (VCC
Word Rate (FS)
Input Signal
Analog Output Passband
ADC FFT Size
)
)
5.0
5.0
48
0 dB Relative to Full Scale
16-Bit Linear Mode
10 kΩ Output Load
Mute Off, OL = 0
ADC Test Conditions
Calibrated
1008
20 Hz to 20 kHz
2048
DAC FFT Size
8192
0 dB Gain
–1.0 dB Relative to Full Scale
Line Input
VIH
VIL
5
0
V
V
16-Bit Linear Mode
ANALO G INP UT
Min
Typ
Max
Units
Input Voltage (RMS Values Assume Sine Wave Input)
Line
1
V rms
V p-p
V rms
V p-p
V rms
V p-p
kΩ
2.55
2.83
0.1
0.283
1
2.83
17
3.35
0.335
3.35
MIC with +20 dB Gain (MGE = 1)
MIC with 0 dB Gain (MGE = 0)
0.255
2.55
10
Input Impedance*
Input Capacitance
15
pF
P RO GRAMMABLE GAIN AMP LIFIER–AD C
Min
Typ
Max
Units
Step Size (All Steps T ested)
(0 dB to 22.5 dB)
PGA Gain Range Span
0.7
21.5
1.5
22.5
1.9
23.5
dB
dB
AUXILIARY LINE, MO NO , AND MICRO P H O NE INP UT ANALO G GAIN/AMP LIFIERS/ATTENUATO RS
Min
Typ
Max
Units
Step Size : AUX1, AUX2, LINE, MIC (All Steps T ested)
(+12 dB to –30 dB)
(–31.5 dB to –34.5 dB)
1.25
1
1.5
1.5
1.75
2.0
dB
dB
Step Size: M_IN (All Steps T ested)
(0 dB to –39 dB)
(–42 dB to –45 dB)
Input Gain/Attenuation Range: AUX1, AUX2, LINE, MIC
Input Gain/Attenuation Range: M_IN
2.5
2.2
45.0
42
3.0
3.0
46.5
45
3.6
dB
dB
dB
dB
3.85
49.0
49
D IGITAL D ECIMATIO N AND INTERP O LATIO N FILTERS*
Min
Max
Units
Passband
0
0.4 × FS
±0.1
0.6 × FS
∞
Hz
dB
Hz
Hz
dB
Passband Ripple
T ransition Band
Stopband
Stopband Rejection
Group Delay
0.4 × FS
0.6 × FS
74
15/FS
0.0
Group Delay Variation Over Passband
µs
*Guaranteed, not tested.
–2–
REV. C
AD1845
ANALO G-TO -D IGITAL CO NVERTERS
Min
Typ
Max
Units
Resolution
16
81
Bits
dB
%
dB
dB
Dynamic Range (–60 dB Input, T HD+N Referenced to Full Scale, A-Weighted)
T HD+N (Referenced to Full Scale)
73
0.025
–72
–76
85
Signal-to-Intermodulation Distortion
ADC Crosstalk*
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
Line to MIC (Input LINE, Ground and Select MIC, Read ADC)
Line to AUX1
–90
–90
–90
–90
–80
–80
–80
–80
+10
±0.9
10
dB
dB
dB
dB
%
Line to AUX2
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error
–18.5
dB
mV
D IGITAL-TO -ANALO G CO NVERTERS
Min
Typ
Max
Units
Resolution
16
82
Bits
dB
%
dB
dB
%
dB
dB
dB
dB
Dynamic Range (–60 dB Input, T HD+N Referenced to Full Scale, A-Weighted)
T HD+N (Referenced to Full Scale)
74
0.032
–70
–78
90
Signal-to-Intermodulation Distortion
Gain Error (Full-Scale Span Relative to Nominal Output Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
DAC Crosstalk* (Input L, Zero R, Measure R_OUT ; Input R, Zero L, Measure L_OUT )
T otal Out-of-Band Energy (Measured from 0.6 × FS to 100 kHz)*
Audible Out-of-Band Energy (Measured from 0.6 × FS to 20 kHz)*
–14.5
+10
±0.6
–80
–50
–70
D AC ATTENUATO R
Min
Typ
Max
Units
Step Size (0 dB to –22.5 dB)
Step Size (–22.5 dB to –94.5 dB)*
Output Attenuation Range Span*
1.3
1.0
93.5
1.5
1.5
94.5
1.7
2.0
95.5
dB
dB
dB
ANALO G O UTP UT
Min
Typ
Max
Units
Full-Scale Output Voltage
OL = 0
OL = 1
Output Impedance*
1.7
2.4
2.0
2.83
2.2
3.11
600
V p-p
V p-p
Ω
External Load Impedance
Output Capacitance*
10
kΩ
pF
15
External Load Capacitance
VREF
VREF Current Drive
VREF Output Impedance
Mute Attenuation of 0 dB Fundamental* (L_OUT , R_OUT , M_OUT )
Mute Click (Muted Output Minus Unmuted Midscale DAC Output)*
100
2.60
pF
V
µA
kΩ
dB
2.05
2.25
100
4
–80
±5
mV
*Guaranteed, not tested.
REV. C
–3–
AD1845
SYSTEM SP ECIFICATIO NS
Min
Min
Typ
Max
Units
System Frequency Response Ripple (Line In to Line Out)*
Differential Nonlinearity*
Phase Linearity Deviation*
1.0
±1
5
dB
LSB
Degrees
STATIC D IGITAL SP ECIFICATIO NS
Max
Units
High Level Input Voltage (VIH
Digital Inputs
XT AL1I
)
2.4
2.4
V
V
Low Level Input Voltage (VIL)
0.8
V
High Level Output Voltage (VOH ) IOH = –2 mA
Low Level Output Voltage (VOL) IOL = 2 mA
Input Leakage Current
2.4
V
V
µA
µA
0.4
10
10
–10
–10
Output Leakage Current
TIMING P ARAMETERS (GUARANTEED O VER O P ERATING TEMP ERATURE RANGE, VD D = VCC = 5.0 V)
Min
Max
Units
WR/RD Strobe Width
(tST W
(tBWND
(tWDSU
)
100
80
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WR/RD Rising to WR/RD Falling
Write Data Setup to WR Rising
RD Falling to Valid Read Data
CS Setup to WR/RD Falling
CS Hold from WR/RD Rising
Adr Setup to WR/RD Falling
Adr Hold from WR/RD Rising
DAK Rising to WR/RD Falling
DAK Falling to WR/RD Rising
DAK Setup to WR/RD Falling
Data Hold from RD Rising
Data Hold from WR Rising
DRQ Hold from WR/RD Falling
DAK Hold from WR Rising
DAK Hold from RD Rising
)
)
)
(tRDDV
40
(tCSSU
(tCSHD
(tADSU
(tADHD
(tSUDK1
(tSUDK2
(tDKSU
(tDHD1
(tDHD2
(tDRHD
(tDKHDa
(tDKHDb
)
10
0
10
10
20
0
)
)
)
)
)
)
)
)
10
20
25
15
)
)
)
10
10
DBEN/ DBDIR Delay from WR/ RD Falling (tDBDL
PWRDWN and RESET Low Pulsewidth
)
30
300
*Guaranteed, not tested.
REV. C
–4–
AD1845
P O WER SUP P LY
Min
Typ
Max
Units
Power Supply Range–Digital and Analog
Power Supply Current
Analog Supply Current
4.75
5.25
130
45
V
mA
mA
mA
Digital Supply Current
85
Power Dissipation
(Current × Nominal Supplies)
Power-Down Supply Current
Reset Supply Current
T otal Power-Down Supply Current
Standby Supply Current
Mixer Power-Down Supply Current
Mixer Only Supply Current
ADC Power-Down Supply Current
DAC Power-Down Supply Current
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*
(At Both Analog and Digital Supply Pins, both ADCs and DACs)
650
2
mW
mA
mA
mA
mA
mA
mA
mA
mA
2
30
70
36
52
80
85
40
dB
CLO CK SP ECIFICATIO NS*
Min
Max
Units
Input Clock Frequency
Recommended Clock Duty Cycle
Power Up Initialization T ime
33
90
512
MHz
%
ms
10
*Guaranteed, not tested.
Specifications subject to change without notice.
O RD ERING GUID E
ABSO LUTE MAXIMUM RATINGS*
Min
Tem perature
Range
P ackage
D escription
P ackage
O ption1
Max
Units
Model
Power Supplies
AD1845JP
0°C to +70°C
0°C to +70°C
0°C to +70°C
68-Lead PLCC
68-Lead PLCC
100-Lead T QFP ST -100
P-68A
P-68A
Digital (VDD
Analog (VCC
Input Current
)
)
–0.3
–0.3
6.0
6.0
V
V
AD1845JP-REEL2
AD1845JST
(Except Supply Pins)
Analog Input Voltage (Signal Pins) –0.3
Digital Input Voltage (Signal Pins) –0.3
Ambient T emperature (Operating)
Storage T emperature
±10.0
mA
V
V
°C
°C
NOT ES
1P = Plastic Leaded Chip Carrier; ST = T hin Quad Flatpack.
213" Reel, multiples of 250 pcs.
VCC +0.3
VDD +0.3
+70
0
–65
ENVIRO NMENTAL CO ND ITIO NS
Ambient T emperature Rating:
+150
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. T his is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
T
AMB = T CASE – (PD × θCA)
T CASE = Case T emperature in °C
PD = Power Dissipation in W
θCA = T hermal Resistance (Case-to-Ambient)
θJA = T hermal Resistance (Junction-to-Ambient)
θJC = T hermal Resistance (Junction-to-Case)
P ackage
JA
JC
CA
PLCC
T QFP
38°C/W
44°C/W
8°C/W
8°C/W
30°C/W
93°C/W
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1845 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–5–
AD1845
P IN D ESIGNATIO NS
60 RD
ADR0
CDAK
CDRQ
PDAK
PDRQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59 CS
58 XCTL1
57 INT
56 XCTL0
55 NC
V
DD
68-Lead P LCC
54
53
52
51
50
49
48
47
46
45
44
V
DD
AD1845
TOP VIEW
(Not to Scale)
GNDD
XTAL1I
XTAL1O
GNDD
NC
NC
V
DD
NC
GNDD
XTAL2I
XTAL2O
PWRDWN
RESET
NC
NC
M_OUT
M_IN
V
DD
GNDD
GNDD
R_FILT
NC = NO CONNECT
RD
75
ADR0
NC
1
2
CS
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
XCTL1
INT
NC
3
NC
4
XCTL0
NC
NC
5
CDAK
CDRQ
PDAK
PDRQ
6
NC
7
V
DD
8
GNDD
NC
9
V
10
DD
NC
GNDD 11
XTAL1I 12
XTAL1O 13
AD1845
NC
100-Lead TQFP
NC
TOP VIEW
NC
(Not to Scale)
V
14
15
16
17
18
19
20
21
22
23
24
25
DD
NC
GNDD
XTAL2I
XTAL2O
PWRDWN
RESET
GNDD
NC
NC
NC
NC
M_OUT
M_IN
V
DD
GNDD
NC
NC
NC
NC
NC
NC
R_FILT
NC = NO CONNECT
REV. C
–6–
AD1845
P IN FUNCTIO N D ESCRIP TIO NS
P ar allel Inter face
P in Nam e
P LCC TQFP
I/O
D escription
CDRQ
12
7
O
Capture Data Request. T he assertion of this signal HI indicates that the codec has a cap-
tured audio sample from the ADC ready for transfer. T his signal will remain asserted
until the internal capture FIFO is empty.
CDAK
11
14
6
9
I
Capture Data Acknowledge. T he assertion of this active LO signal indicates that the RD
cycle occurring is a DMA read from the capture buffer.
PDRQ
O
Playback Data Request. T he assertion of this signal HI indicates that the codec is ready
for more DAC playback data. T he signal will remain asserted until the internal playback
FIFO is full.
PDAK
13
8
I
I
Playback Data Acknowledge. T he assertion of this active LO signal indicates that the WR
cycle occurring is a DMA write to the playback buffer.
ADR1:0
9 & 10 100 & 1
Codec Addresses. T hese address pins are asserted by the codec interface logic during a
control register/PIO access. T he state of these address lines determine which direct
register is accessed.
RD
WR
60
61
59
75
76
74
I
I
I
Read Command Strobe. T his active LO signal defines a read cycle from the codec. T he
cycle may be a read from the control/PIO registers, or the cycles could be a read from
the codec’s DMA sample registers.
Write Command Strobe. T his active LO signal indicates a write cycle to the codec. T he
cycle may be a write to the control/PIO registers, or the cycle could be a write to the
codec’s DMA sample registers.
CS
AD1845 Chip Select. T he codec will not respond to any control/PIO cycle accesses
unless this active LO signal is LO. T his signal is ignored during DMA transfers.
DAT A7:0
DBEN
3–6 & 84–87 & I/O
65–68 90–93
Data Bus. T hese pins transfer data and control information between the codec and
the host.
63
78
O
Data Bus Enable. T his pin enables the external bus drivers. T his signal is normally HI.
For control register/PIO cycles,
DBEN = (WR or RD) and CS
For DMA cycles,
DBEN = (WR or RD) and (PDAK or CDAK).
DBDIR
62
77
O
Data Bus Direction. T his pin controls the direction of the data bus transceiver. HI
enables writes from the host bus to the AD1845; LO enables reads from the AD1845 to
the host bus. T his signal is normally HI.
For control register/PIO cycles,
DBDIR = RD and CS
For DMA cycles,
DBDIR = RD and (PDAK or CDAK).
REV. C
–7–
AD1845
Analog Signals
P in Nam e
P LCC TQFP
I/O
D escription
L_LINE
R_LINE
L_MIC
30
27
29
31
28
30
I
I
I
Left Line Input.
Right Line Input.
Left Microphone Input. T his signal can be either line level or –20 dB from line level
(using the on-chip 20 dB gain block).
R_MIC
28
29
I
Right Microphone Input. T his signal can be either line level or –20 dB from line level
(using the on-chip 20 dB gain block).
L_AUX1
R_AUX1
L_AUX2
R_AUX2
L_OUT
R_OUT
M_IN
39
42
38
43
40
41
46
47
45
48
44
49
46
47
56
57
I
Left Auxiliary # 1 Line Input.
Right Auxiliary # 1 Line Input.
Left Auxiliary # 2 Line Input.
Right Auxiliary # 2 Line Input.
Left Line Output.
I
I
I
O
O
I
Right Line Output.
Mono Input.
M_OUT
O
Mono Output.
Miscellaneous
P in Nam e
P LCC TQFP
I/O
I
D escription
XT AL1I
17
18
21
22
23
12
13
16
17
18
24.576 MHz Crystal # 1 Input.
24.576 MHz Crystal # 1 Output.
Not used on the AD1845.
Not used on the AD1845.
XT AL1O
XT AL2I
O
XT AL2O
PWRDWN
I
Power Down Signal. Active LO places the AD1845 in its lowest power consumption
mode. All sections of the AD1845, including the digital interface, are shut down and
consume minimal power.
INT
57
72
O
O
I
Host Interrupt Pin. A host interrupt is generated to notify the host that a specified
event has occurred.
XCT L1:0
RESET
58 & 56 73 & 71
External Control. T hese signals reflect the current status of register bits inside the
AD1845. T hey can be used for signaling or to control external logic.
24
32
19
35
Reset. Active LO resets all digital registers and filters, and resets all analog filters. Active
LO places the AD1845 in the lowest power consumption mode. XT AL1 is required to be
running during the minimum low pulsewidth of the reset signal.
VREF
O
Voltage Reference. Nominal 2.25 volt reference available for dc-coupling and level-
shifting. VREF should not be used to sink or source current.
VREF_F
33
31
38
33
I
I
Voltage Reference Filter. Voltage reference filter point for external bypassing only.
L_FILT
Left Channel Filter. T his pin requires a 1.0 µF capacitor to analog ground for proper
operation.
R_FILT
NC
26
25
I
Right Channel Filter. T his pin requires a 1.0 µF capacitor to analog ground for proper
operation.
48–52, 2–5, 21–24
No Connect.
55
26, 27, 32, 34,
36, 37, 39,
50–53, 58–66,
69, 70, 80–83,
94–97
REV. C
–8–
AD1845
P ower Supplies
P in Nam e
P LCC
TQFP
I/O
D escription
VCC
35 & 36
34 & 37
41 & 42
40 & 43
I
I
I
Analog Supply Voltage (+5 V).
Analog Ground.
GNDA
VDD
1, 7, 15,
19, 45,
54
10, 14,
55, 68,
88, 98
Digital Supply Voltage (+5 V).
GNDD
2, 8, 16,
20, 25,
44, 53,
64
11, 15, 20,
54, 67,
79, 89,
99
I
Digital Ground.
(Continued from page 1)
unsigned magnitude PCM linear data, and 8-bit µ-law or A-law
companded digital data.
AEN
AD1845
ADDRESS
DECODE
18
SA19:2
SA1
CS
A1
T he ∑∆ DACs are preceded by a digital interpolation filter. An
attenuator provides independent user volume control over each
DAC channel. Nyquist images and shaped quantized noise are
removed from the DACs’ analog stereo output by on-chip
switched-capacitor and continuous-time filters.
SA0
A0
IOWC
IORC
WR
RD
I
S
A
8
8
74_245
DATA7:0
DATA7:0
B
U
S
DIR
DBDIR
DBEN
T he AD1845 supports multiple low power and power-down
modes to support notebook and portable computing multimedia
applications. T he ADC, DAC, and mixer paths can be sus-
pended independently allowing the AD1845 to be used for
capture-only or playback-only, lessening power consumption
and extending battery life.
G
B
A
DRQ <X>
DRQ <Y>
DAK <X>
DAK <Y>
IRQ <Z>
PDRQ
CDRQ
PDAK
CDAK
INT
T he AD1845 includes a variable sample frequency generator,
that allows the codec to instantaneously change sample rates
with a resolution of 1 Hz without “clicks” and “pops.” Addi-
tionally, ∑∆ quantization noise is kept out of the 20 kHz audio
band regardless of the chosen sample rate. T he codec uses the
variable sample frequency generator to derive all internal clocks
from a single external crystal or clock source.
Figure 1. Interface to ISA Bus
External circuit requirements are limited to a minimal number
of low cost support components. Anti-imaging DAC output
filters are incorporated on-chip. Dynamic range exceeds 80 dB
over the 20 kHz audio band. Sample rates from 4 kHz to 50 kHz
are supported from a single external crystal or clock source.
Expanded Mode (MO D E2)
MODE1 is the initial state of the AD1845. In this state the
AD1845 appears as an AD1848 compatible device. T o access
the expanded modes of operation on the AD1845, the MODE2
bit should be set in the Miscellaneous Information Control
Register. When this bit is set to one, 16 additional indirect
registers can be addressed allowing the user to access the
AD1845’s expanded features. T he AD1845 can return to
MODE1 operation by clearing the MODE2 bit. In both
MODE1 and MODE2, the capture and playback FIFOs are
active to prevent data loss.
T he AD1845 has built-in 8/16 mA (user selectable) bus drivers.
If 24 mA drive capability is required, the AD1845 generates
enable and direction controls for IC bus buffers such as the
74 245.
T he codec includes a stereo pair of ∑∆ analog-to-digital con-
verters and a stereo pair of ∑∆ digital-to-analog converters. T he
AD1845 mixer surpasses MPC Level-2 recommendations.
Inputs to the ADC can be selected from four stereo pairs of
analog signals: line (LINE), microphone (MIC), auxiliary line
# 1 (AUX1), and post-mixed DAC output. A software-con-
trolled programmable gain stage allows independent gain for
each channel going into the ADC. In addition, the analog mixer
allows the mono input (M_IN), MIC, AUX1, LINE and auxil-
iary line # 2 (AUX2) signals to be mixed with the DACs’ output.
T he ADCs’ output can be digitally mixed with the DACs’ input.
T he additional MODE2 functions are:
1. Full-Duplex DMA support.
2. MIC input mixer, mute and volume control.
3. Mono output with mute control.
4. Mono input with mixer volume control.
5. Software controlled advanced power-down modes.
T he pair of 16-bit outputs from the ADCs is available over a
byte-wide bidirectional interface that also supports 16-bit digital
input to the DACs and control information. T he AD1845 can
accept and generate 16-bit twos complement PCM linear digital
data in both little endian or big endian byte ordering, 8-bit
6. Programmable sample rates from 4 kHz to 50 kHz in 1 Hz
increments.
REV. C
–9–
AD1845
D igital Mixing
FUNCTIO NAL D ESCRIP TIO N
Stereo digital output from the ADCs can be digitally mixed with
the input to the DACs. Digital output from the ADCs going out
of the data port is unaffected by the digital mix. Along the
digital mix datapath, the 16-bit linear output from the ADCs
is attenuated by an amount specified with control bits. Both
channels of the digital mix datapath are attenuated by the same
amount. (Note that internally the AD1845 always works with
16-bit PCM linear data, digital mixing included; format conver-
sions take place at the input and output.)
T his section overviews the functionality of the AD1845 and is
intended as a general introduction to the capabilities of the
device. As much as possible, detailed reference information has
been placed in “Control Registers” and other sections. T he
user is not expected to refer repeatedly to this section.
Analog Inputs
T he AD1845 SoundPort Stereo Codec accepts stereo line-level
and microphone-level inputs. T he LINE, MIC, AUX1, and
post-mixed DAC output are available to the ADC multiplexer.
T he DAC output can be mixed with LINE, MIC, AUX1,
AUX2 and M_IN. Each channel of the MIC inputs can be
amplified by +20 dB to compensate for the difference between
line levels and typical condenser microphone levels.
Sixty-four steps of –1.5 dB attenuation are supported to –94.5 dB.
T he digital mix datapath can also be completely muted. Note
that the level of the mixed signal is also a function of the input
PGA settings, since they affect the ADCs’ output.
T he attenuated digital mix data is digitally summed with the
DAC input data prior to the DACs’ datapath attenuators. T he
digital sum of digital mix data and DAC input data is clipped at
plus or minus full scale and does not wrap around. Because both
stereo signals are mixed before the output attenuators, mix data is
attenuated a second time by the DACs’ datapath attenuators.
Analog Mixing
T he M_IN mono input signal, MIC, LINE, AUX1 and AUX2
analog stereo signals can be mixed in the analog domain with
the DAC output. Each channel of each AUX, LINE and MIC
analog input can be independently gained/attenuated from
+12 dB to –34.5 dB in 1.5 dB steps or completely muted.
M_IN can be attenuated from 0 dB to –45 dB in 3 dB steps or
muted. T he post-mixed DAC outputs are available on L_OUT
and R_OUT and also to the ADC input multiplexer.
In case the AD1845 is capturing data, but ADC output data is
not removed in time (“ADC overrun”), the last sample captured
before overrun will be used for the digital mix. In case the
AD1845 is playing back data, but input digital DAC data fails
to arrive in time (“DAC underrun”), a midscale zero will be
added to the digital mix data when the DACZ control bit is set
to 0; otherwise, the DAC will output the previous valid sample
in an underrun condition.
Even if the AD1845 is not playing back data from its DACs, the
analog mix function can still be active.
Analog-to-D igital D atapath
T he PGA following the input multiplexer allows independent
selectable gains for each channel from 0 dB to 22.5 dB in
+1.5 dB steps. T he codec can operate either in a global stereo
mode or in a global mono mode with left-channel inputs
appearing at both channel outputs.
Analog O utputs
Stereo and mono line-level outputs are available at external
pins. Each channel of this output can be independently muted.
When muted, the outputs will settle to a dc value near VREF, the
midscale reference voltage. T he output is selectable for 2.0 V
peak-to-peak or 2.8 V peak-to-peak. When selecting the LINE
output as an input to the ADC, the ADC automatically com-
pensates for the output level selection.
T he AD1845 ∑∆ ADCs incorporate a fourth-order modulator.
A single pole of passive filtering is all that is required for anti-
aliasing the analog input because of the ADC’s high over sam-
pling ratio. T he ADCs include linear-phase digital decimation
filters that low-pass filter the input to 0.4 × FS. (“FS” is the
word rate or “sampling frequency.”) ADC input over range
conditions are reported on status bits in the T est and Initializa-
tion Register.
D igital D ata Types
The AD1845 supports five global data types: 16-bit twos comple-
ment linear PCM (little endian and big endian byte ordering),
8-bit unsigned linear PCM, companded µ-law, and 8-bit com-
panded A-law, as specified by control register bits. Data in all
formats is always transferred MSB first. All data formats that are
less than 16 bits are MSB-aligned to ensure the use of full
system resolution.
D igital-to-Analog D atapath
T he ∑∆ DACs are preceded by a programmable attenuator and
a low-pass digital interpolation filter. T he anti-imaging interpo-
lation filter over samples and digitally filters the higher fre-
quency images. T he attenuator allows independent control of
each DAC channel from 0 dB to –94.5 dB in –1.5 dB steps plus
full mute. T he DACs’ ∑∆ noise shapers also over sample and
convert the signal to a single-bit stream. T he DAC outputs are
then filtered in the analog domain by a combination of switched-
capacitor and continuous-time filters. T hey remove the very
high frequency components of the DAC bit stream output. No
external components are required.
T he 16-bit PCM data format is capable of representing 96 dB
of dynamic range. Eight-bit PCM can represent 48 dB of dy-
namic range. Companded µ-law and A-law data formats use
nonlinear coding with less precision for large amplitude signals.
T he loss of precision is compensated for by an increase in dy-
namic range to 64 dB and 72 dB, respectively.
On input, 8-bit companded data is expanded to an internal
linear representation, according to whether µ-law or A-law was
specified in the codec’s internal registers. Note that when µ-law
compressed data is expanded to a linear format, it requires
14 bits. A-law data expanded requires 13 bits.
Changes in DAC output attenuation take effect only on zero
crossings, eliminating “zipper” noise on playback. Each chan-
nel has its own independent zero-crossing detector and attenua-
tor change control circuitry. A timer guarantees that requested
volume changes will occur even in the absence of a zero cross-
ing. T he time-out period is 8 milliseconds at a 48 kHz sampling
rate and 48 milliseconds at an 8 kHz sampling rate. (T imeout
[ms] ≈ 384 ÷ FS [kHz].)
REV. C
–10–
AD1845
0
0
0
15
8 7
P ower Supplies and Voltage Refer ence
COMPRESSED
INPUT DATA
MSB
LSB
T he AD1845 operates from a +5 V power supply. Independent
analog and digital supplies are recommended for optimal perfor-
mance though excellent results can be obtained in single-supply
systems. A voltage reference is included on the codec and its
2.25 V buffered output is available on an external pin (VREF).
T he reference output can be used for biasing op amps used in
dc coupling. T he internal reference is externally bypassed to
analog ground at the VREF_F pin.
15
MSB
3/2
2/1
LSB
EXPANSION
DAC INPUT
15
MSB
3/2 2/1
LSB
000/00
Figure 2. µ-Law or A-Law Expansion
Clocks and Sam ple Rates
T he AD1845 operates from a single external crystal or clock
source. From a single input, a wide range of sample rates can be
generated. T he AD1845 default frequency source is a
24.576 MHz input. T he AD1845 can also be driven from a
14.31818 MHz (OSC), 24 MHz, 25 MHz or 33 MHz input
frequency source. In MODE1, the input drives the internal
variable sample frequency generator to derive the following
AD1848 compatible sample rates: 5.5125, 6.615, 8, 9.6,
11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1,
48 kHz. In MODE2, the AD1845 can be programmed to gen-
erate any sample frequency between 4 kHz and 50 kHz with
1 Hz resolution. Note that it is no longer required to enter
Mode Change Enable (MCE) to change the sample rate. T his
feature allows the user to change the AD1845’s sample rate “on
the fly.”
When 8-bit companding is specified, the ADCs’ linear output is
compressed to the format specified.
0
15
MSB
LSB
ADC OUTPUT
TRUNCATION
15
MSB
0
0
3/2 2/1
LSB
15
MSB
8 7
LSB
COMPRESSION
00000000
Figure 3. µ-Law or A-Law Com pression
Note that all format conversions take place at input or output.
Internally, the AD1845 always uses 16-bit linear PCM represen-
tations to maintain maximum precision.
CO NTRO L REGISTERS
Contr ol Register Ar chitectur e
Tim er Register s
T he AD1845 SoundPort Stereo Codec accepts both data and
control information through its byte-wide parallel port. Indirect
addressing minimizes the number of external pins required to
access all 37 of its byte-wide internal registers. Only two exter-
nal address pins, ADR1:0, are required to accomplish all data
and control transfers. T hese pins select one of five direct regis-
ters. (ADR1:0 = 3 addresses two registers, depending on
whether the transfer is for a playback or capture.)
T he timer registers are provided for system level synchroniza-
tion, and for periodic interrupt generation. T he 16-bit timer
time base is determined by the frequency of the connected input
clock source.
T he timer is enabled by setting the T imer Enable bit, T E, in the
Alternate Feature Enable register. T o set the timer, load the
Upper and Lower T imer Bits Registers. T he timer value will
then be loaded into an internal count register with a value of
approximately 10 µs (the exact timer value is listed in the regis-
ter descriptions). T he internal count register will decrement
until it reaches zero, then the T imer Interrupt bit, T I, is set and
an interrupt will be sent to the host. T he next timer clock will
load the internal count register with the value of the T imer
Register, and the timer will be reinitialized. T o clear the inter-
rupt, write to the Status Register or write a “0” to T I.
AD R1:0
Register Nam e
0
1
2
3
Index Address Register
Indexed Data Register
Status Register
PIO Data Register
Figure 4. Direct Register Map
Inter r upts
T he AD1845 supports interrupt conditions generated by DMA
playback count expiration, DMA capture count expiration, or
timer expiration. T he INT bit will remain set, HI, until a write
has been completed to the Status Register or by clearing the T I,
CI, or PI bit (depending on the existing condition) in the Cap-
ture Playback T imer Register. T he IEN bit of the Pin Control
Register determines whether the interrupt pin responds to an
interrupt condition and reflects the interrupt state on the
INT status bit.
REV. C
–11–
AD1845
A write to or a read from the Indexed Data Register will access the Indirect Register which is indexed by the value most recently
written to the Index Address Register. T he Status Register and the PIO Data Register are always accessible directly, without
indexing. T he 32 Indirect Register indexes are shown in Figure 5:
Index
Register Nam e
Reset/D efault State
0
1
Left Input Control
Right Input Control
000x
000x
0000
0000
2
3
Left Aux # 1 Input Control
Right Aux # 1 Input Control
1xx0
1xx0
1000
1000
4
5
Left Aux # 2 Input Control
Right Aux # 2 Input Control
1xx0
1xx0
1000
1000
6
7
Left Output Control
Right Output Control
1x00
1x00
0000
0000
8
9
Clock and Data Format
Interface Configuration
0000
00xx
0000
1000
10
11
Pin Control
T est and Initialization
00xx
0000
xx00
0000
12
13
Miscellaneous Information
Digital Mix/Attenuation
10x0
0000
1010
00x0
14
15
Upper Base Count
Lower Base Count
0000
0000
0000
0000
16
17
Alternate Feature Enable/Left MIC Input Control
MIC Mix Enable/Right MIC Input Control
0001
0001
0001
000x
18
19
Left Line Gain, Attenuate, Mute, Mix
Right Line Gain, Attenuate, Mute, Mix
1xx0
1xx0
1000
1000
20
21
Lower T imer
Upper T imer
0000
0000
0000
0000
22
23
Upper Frequency Select
Lower Frequency Select
0001
0100
1111
0000
24
25
Capture Playback T imer
Revision ID
x000
100x
0000
x000
26
27
Mono Control
Power-Down Control
00xx
000x
0011
0xxx
28
29
Capture Data Format Control
Crystal Clock Select/T otal Power-Down
0000
000x
xxxx
xxx0
30
31
Capture Upper Base Count
Capture Lower Base Count
0000
0000
0000
0000
“x” indicates reserved bit, always write “0s” to these bits.
Figure 5. Indirect Register Map and Reset/Default States
A detailed map of all direct and indirect register contents is summarized for reference as follows:
REV. C
–12–
AD1845
Direct Registers
AD Rl:0
D ata 7
INIT
IXD7
CU/L
CD7
D ata 6
MCE
IXD6
CL/R
CD6
D ata 5
TRD
D ata 4
IXA4
IXD4
SOUR
CD4
D ata 3
IXA3
IXD3
PU/L
CD3
D ata 2
IXA2
IXD2
PL/R
CD2
D ata 1
D ata 0
IXA0
IXD0
INT
0
1
2
3
3
IXA1
IXD1
PRDY
CD1
IXD5
CRDY
CD5
CD0
PD0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
Indirect Registers
IXA3:0
D ata 7
LSS1
D ata 6
LSS0
RSS0
res
D ata 5
LMGE
RMGE
res
D ata 4
res
D ata 3
LIG3
D ata 2
LIG2
RIG2
LX1A2
RX1A2
LX2A2
RX2A2
LDA2
RDA2
CFS1
SDC
D ata 1
LIG1
RIG1
LX1A1
RX1A1
LX1A1
RX2A1
LDA1
RDA1
CFS0
CEN
D ata 0
LIG0
RIG0
LX1A0
RX1A0
LX2A0
RX2A0
LDA0
RDA0
CSS
0
1
RSS1
res
RIG3
LX1A3
RX1A3
LX2A3
RX2A3
LDA3
RDA3
CFS2
ACAL
res
2
LMX1
RMX1
LMX2
RMX2
LDM
LX1A4
RX1A4
LX2A4
RX2A4
LDA4
RDA4
S/M
3
res
res
4
res
res
5
res
res
6
res
LDA5
RDA5
C/L
7
RDM
FMT1
CPIO
XCTL1
COR
res
8
FMT0
PPIO
XCTL0
PUR
MODE2
DMA4
UB6
LB6
9
res
res
PEN
10
11
12
13
14
15
res
res
res
IEN
INITD
ORL0
ID0
ACI
DRS
res
ORR1
ID3
ORR0
ID2
ORL1
ID1
MID
BUF8
DMA3
UB5
LB5
DMA5
UB7
DMA2
UB4
DMA1
UB3
DMA0
UB2
res
DME
UB0
UB1
LB7
LB4
LB3
LB2
LB1
LB0
Expanded Mode (Requires MO D E2=1)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
OL
LMME
LLM
TE
RMME
res
LMG4
RMG4
res
LMG3
RMG3
LLG4
RLG4
TL4
TU4
FU4
FL4
LMG2
RMG2
LLG3
RLG3
TL3
LMG1
RMG1
LLG2
RLG2
TL2
LMG0
RMG0
LLG1
RLG1
TL1
DACZ
res
LLG0
RLG0
TL0
RLM
TL7
res
res
TL6
TL5
TU7
TU6
TU5
FU5
TU3
FU3
TU2
FU2
TU1
FU1
TU0
FU7
FU6
FU0
FL7
FL6
FL5
FL3
FL2
FL1
FL0
res
TI
CI
PI
CU
CO
PO
PU
V2
V1
V0
res
res
CID2
MIA2
res
CID1
MIA1
res
CID0
MIA0
res
MIM
ADCPWD
CFMT1
XFS2
CUB7
CLB7
MOM
DACPWD
CFMT0
XFS1
CUB6
CLB6
res
res
MIA3
FREN
res
MIXPWD
CC/L
XFS0
CUB5
CLB5
res
CS/M
res
res
res
res
res
res
res
TOTPWD
CUB0
CLB0
CUB4
CLB4
CUB3
CLB3
CUB2
CLB2
CUB1
CLB1
Figure 6. Register Sum m ary
Note that the only sticky bit in any of the AD1845 control registers is the interrupt (INT ) bit. All other bits can change with every
sample period.
REV. C
–13–
AD1845
D IRECT CO NTRO L REGISTER D EFINITIO NS
Index Address Register (ADR1:0 = 0)
AD R1:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
0
INIT
MCE
TRD
IXA4
IXA3
IXA2
IXA1
IXA0
IXA4:0
T RD
Index Address. T hese bits define the address of the AD1845 register accessed by the Indexed Data Register.
T hese bits are read/write. IXA4 is not active in MODE1. Always write 0 to this bit when using the AD1845 in
MODE1.
T ransfer Request Disable. T his bit, when set, causes PIO and DMA transfers to cease when the Interrupt Status
(INT ) bit of the Status Register is set.
0
T ransfers Enabled During Interrupt. PDRQ and CDRQ pin outputs are generated uninhibited by interrupts.
DMA Current Counter Register decrements with every sample transferred when either PEN or CEN are enabled.
T ransfers Disabled By Interrupt. PDRQ and CDRQ pin outputs are generated only if INT bit is 0 (when
either PEN or CEN, respectively are enabled). Any pending playback or capture requests are allowed to
complete at the time when INT is set. After pending requests complete, the data in the FIFO will be con-
sumed at the sample rate. Subsequently, the midscale inputs will be internally generated for the DACs if
the DACZ bit is set, otherwise, the previous valid sample will be repeated, and the ADC output buffer will
contain the last valid output. Clearing the sticky INT bit (or the TRD bit) will cause the resumption of
playback and/or capture requests (presuming PEN and/or CEN are enabled). T he DMA Current Counter
Register will not decrement while both the T RD bit is set and the INT bit is a one. No over run or under
run error will be reported when transfers are disabled by INT .
1
MCE
Mode Change Enable. T his bit must be set whenever the current functional mode of the AD1845 is changed
where noted in the Indirect Control Registers 8, 9, 28 and 29. MCE must be cleared at the completion of the
desired register changes.
T he DAC outputs are automatically muted when the MCE bit is set. After MCE is cleared, the DAC outputs will
be restored to the state specified by the LDM and RDM mute bits.
Both ADCs and DACs are automatically muted for 32 sample cycles after exiting the MCE state to allow the refer-
ence and all filters to settle. T he ADCs will produce midscale values; the DACs’ analog output will be muted. All
converters are internally operating during these 32 sample cycles, and the AD1845 will expect playback data and
will generate (midscale) capture data. Note that the autocalibrate-in-progress (ACI) bit will be set on exiting from
the MCE state only when ACAL is set. If ACAL bit is set, ACI will remain HI for these 384 sample cycles, allow-
ing system software to poll this bit rather than count cycles.
Special sequences must be followed if autocalibrate (ACAL) is set during mode change enable. See the
“Autocalibration” section.
INIT
AD1845 Initialization. T his bit is set when the AD1845 cannot respond to parallel bus cycles. T his bit is
read-only.
Immediately after reset and once the AD1845 has left the INIT state, the initial value of this register will be “0100 0000 (40h).”
During AD1845 initialization, this register cannot be written and always reads “1000 0000 (80h).”
Indexed Data Register (ADR1:0 = 1)
AD R1:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
1
IXD7
IXD6
IXD5
IXD4
IXD3
IXD2
IXD1
IXD0
IXD7:0
Indexed Register Data. T hese bits contain the contents of the AD1845 register referenced by the Indexed Data
Register.
During AD1845 initialization, this register cannot be written and always reads as “1000 0000 (80h).”
REV. C
–14–
AD1845
Status Register (ADR1:0 = 2)
AD R1:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
2
CU/L
CL/R
CRDY
SOUR
PU/L
PL/R
PRDY
INT
INT
Interrupt Status. T his sticky bit (the only one) indicates the status of the interrupt logic of the AD1845. T his bit
is cleared by any host write of any value to this register. T he IEN bit of the Pin Control Register determines
whether the state of this bit is reflected on the INT pin of the AD1845. T he only interrupt conditions supported
by the AD1845 are generated by the underflow of the DMA Current Count Register or the T imer Registers. T he
T imer Register operates at a 10 µs resolution. Clearing INT requires a 10 µs wait. If an immediate clearing of a T I
condition is desired, clear the T E bit to remove the timer interrupt.
0
1
Interrupt pin inactive
Interrupt pin active
PRDY
Playback Data Register Ready. The PIO or DMA Playback Data Register is ready for more data. T his bit is intended
to be used when direct programmed I/O data transfers are desired; however, it is also valid for DMA transfers.
T his bit is read-only.
0
1
DAC data is still valid. Do not overwrite.
DAC data is stale. Ready for next host data write value.
PL/R
PU/L
Playback Left/Right Sample. T his bit indicates whether the PIO or DMA playback data needed is for the right
channel DAC or left channel DAC. T his bit is read-only.
0
1
Right channel needed
Left channel or mono
Playback Upper/Lower Byte. T his bit indicates whether the PIO or DMA playback data needed is for the upper or
lower byte of the channel. T his bit is read-only.
0
1
Lower byte needed
Upper byte needed or any 8-bit mode
SOUR
CRDY
Sample Over/Underrun. T his bit indicates that the most recent sample was not serviced in time and therefore
either a capture overrun (COR) or playback underrun (PUR) has occurred. T he bit indicates an overrun for ADC
capture and an underrun for DAC playback. If both capture and playback are enabled, the source that set this bit
can be determined by reading COR and PUR. This bit changes on a sample by sample basis. This bit is read-only.
Capture Data Ready. T he PIO Capture Data Register contains data ready for reading by the host. T his bit
should only be used when direct programmed I/O data transfers are desired. T his bit is read-only.
0
1
ADC data is stale. Do not reread the information.
ADC data is fresh. Ready for next host data read.
CL/R
CU/L
Capture Left/Right Sample. T his bit indicates whether the PIO capture data waiting is for the right channel ADC
or left channel ADC. T his bit is read-only.
0
1
Right channel
Left channel or mono
Capture Upper/Lower Byte. T his bit indicates whether the PIO capture data ready is for the upper or lower byte
of the channel. T his bit is read-only.
0
1
Lower byte ready
Upper byte ready or any 8-bit mode
T he PRDY, CRDY, and INT bits of this status register can change asynchronously to host accesses. T he host may access this regis-
ter while the bits are transitioning. T he host read may return a zero value just as these bits are changing, for example. A one value
would not be read until the next host access.
While the FIFOs have multiple samples available for transfer, the CRDY and PRDY status bits for consecutive samples are approxi-
mately 320 ns–600 ns apart.
T his register’s initial state after reset is “1100 1100.”
REV. C
–15–
AD1845
PIO Data Registers (ADR1:0 = 3)
AD R1:0
D ata 7
CD7
D ata 6
CD6
D ata 5
CD5
D ata 4
CD4
D ata 3
CD3
D ata 2
CD2
D ata 1
CD1
D ata 0
CD0
3
3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
T he PIO Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register
(PD7:0). Reads will receive data from the PIO Capture Data Register (CD7:0).
During AD1845 initialization, the PIO Playback Data Register cannot be written to and the Capture Data Register is always read
as “1000 0000 (80h).”
CD7:0
PIO Capture Data Register. T his is the control register where capture data is read during programmed I/O data
transfers.
T he reading of this register will increment the capture byte state machine so that the following read will be from
the next appropriate byte in the sample. T he exact byte which is next to be read can be determined by reading the
Status Register. Once all relevant bytes have been read, the state machine will stay pointed to the last byte of the
sample until a new sample is received from the ADCs. Once this has occurred, the state machine and Status
Register will point to the first byte of the sample.
PD7:0
PIO Playback Data Register. T his is the control register where playback data is written during programmed I/O
data transfers.
Writing data to this register will increment the playback byte tracking state machine so that the following write will
be to the correct byte of the sample. Once all bytes of a sample have been written, subsequent byte writes to this
port are ignored. T he state machine is reset when the current sample is sent to the DACs.
IND IRECT CO NTRO L REGISTER D EFINITIO NS
T he following control registers are accessed by writing index values to IXA3:0 in the Index Address Register (ADR1:0 = 0) followed
by a read/write to the Indexed Data Register (ADR1:0 = 1).
Left Input Control (IXA3:0 = 0)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
0
LSS1
LSS0
LMGE
res
LIG3
LIG2
LIG1
LIG0
LIG3:0
res
Left input gain select. T he least significant bit of this gain select represents +1.5 dB. Maximum gain is +22.5 dB.
Reserved for future expansion. Always write a zero to this bit.
LMGE
LSS1:0
Left Input Microphone Gain Enable. T his bit will enable the +20 dB gain of the left MIC input signal.
Left Input Source Select. T hese bits select the input source for the left gain stage preceding the left ADC.
LSS1
LSS0
Left Input Sour ce
0
0
1
1
0
1
0
1
Left Line Source Selected
Left Auxiliary 1 Source Selected
Left Microphone Source Selected
Left Line Post-Mixed DAC Output Source Selected
T his register’s initial state after reset is “000x 0000.”
Right Input Control (IXA3:0 = 1)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
1
RSS1
RSS0
RMGE
res
RIG3
RIG2
RIG1
RIG0
RIG3:0
res
Right Input Gain Select. The least significant bit of this gain select represents +1.5 dB. Maximum gain is +22.5 dB.
Reserved for future expansion. Always write a zero to this bit.
RMGE
RSS1:0
Right Input Microphone Gain Enable. T his bit will enable the +20 dB gain of the right MIC input signal.
Right Input Source Select. T hese bits select the input source for the right channel gain stage preceding the right
ADC.
REV. C
–16–
AD1845
RSS1 RSS0 Right Input Sour ce
0
0
1
1
0
1
0
1
Right Line Source Selected
Right Auxiliary 1 Source Selected
Right Microphone Source Selected
Right Post-Mixed DAC Output Source Selected
T his register’s initial state after reset is “000x 0000.”
Left Auxiliary # 1 Input Control (IXA3:0 = 2)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
2
LMX1
res
res
LX1A4
LX1A3
LX1A2
LX1A1
LX1A0
LX1A4:0
Left Auxiliary Input # 1 Attenuate Select. T he least significant bit of this gain/attenuate select represents 1.5 dB.
LX1A4:0 = 0 produces a +12 dB gain. LX1A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenua-
tion is –34.5 dB. See Figure 10.
res
Reserved for future expansion. Always write zeros to these bits.
LMX1
Left Auxiliary # 1 Mute. T his bit, when set, will mute the left channel of the Auxiliary # 1 input source. T his bit
powers up set.
T his register’s initial state after reset is “1xx0 1000.”
Right Auxiliary # 1 Input Control (IXA3:0 = 3)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
3
RMX1
res
res
RX1A4
RX1A3
RX1A2
RX1A1
RX1A0
RX1A4:0
Right Auxiliary Input # 1 Attenuate Select. T he least significant bit of this gain/attenuate select represents
1.5 dB. RX1A4:0 = 0 produces a +12 dB gain. RX1A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum
attenuation is –34.5 dB. See Figure 10.
res
Reserved for future expansion. Always write zeros to these bits.
RMX1
Right Auxiliary # 1 Mute. T his bit, when set, will mute the right channel of the Auxiliary # 1 input source. T his
bit powers up set.
T his register’s initial state after reset is “1xx0 1000.”
Left Auxiliary # 2 Input Control (IXA3:0 = 4)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
4
LMX2
res
res
LX2A4
LX2A3
LX2A2
LX2A1
LX2A0
LX2A4:0
Left Auxiliary Input # 2 Attenuate Select. T he least significant bit of this gain/attenuate select represents 1.5 dB.
LX2A4:0 = 0 produces a +12 dB gain. LX2A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenua-
tion is –34.5 dB. See Figure 10.
res
Reserved for future expansion. Always write zeros to these bits.
LMX2
Left Auxiliary # 2 Mute. T his bit, when set to 1, will mute the left channel of the Auxiliary # 2 input source. T his
bit powers up set.
T his register’s initial state after reset is “1xx0 1000.”
Right Auxiliary # 2 Input Control (IXA3:0 = 5)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
5
RMX2
res
res
RX2A4
RX2A3
RX2A2
RX2A1
RX2A0
REV. C
–17–
AD1845
RX2A4:0
Right Auxiliary Input # 2 Attenuate Select. T he least significant bit of this gain/attenuate select represents
1.5 dB. RX2A4:0 = 0 produces a +12 dB gain. RX2A4:0 = “01000” (8 decimal) produces 0 dB gain.
Maximum attenuation is –34.5 dB. See Figure 10.
res
Reserved for future expansion. Always write zeros to these bits.
RMX2
Right Auxiliary # 2 Mute. T his bit, when set, will mute the right channel of the Auxiliary # 2 input source. T his bit
powers up set.
T his register’s initial state after reset is “1xx0 1000.”
Left DAC Control (IXA3:0 = 6)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
6
LDM
res
LDA5
LDA4
LDA3
LDA2
LDA1
LDA0
LDA5:0
Left DAC Attenuate Select. T he least significant bit of this gain/attenuate select represents 1.5 dB. Maximum
attenuation is –94.5 dB. See Figure 7.
res
Reserved for future expansion. Always write a zero to this bit.
LDM
Left DAC Mute. T his bit, when set to 1, will mute the left DAC output. T his bit powers up active.
T his register’s initial state after reset is “1x00 0000.”
Right DAC Control (IXA3:0 = 7)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
7
RDM
res
RDA5
RDA4
RDA3
RDA2
RDA1
RDA0
RDA5:0
Right DAC Attenuate Select. T he least significant bit of this gain/attenuate select represents 1.5 dB. Maximum
attenuation is –94.5 dB. See Figure 7.
res
Reserved for future expansion. Always write a zero to this bit.
RDM
Right DAC Mute. T his bit, when set to 1, will mute the right DAC output. T his bit powers up active.
T his register’s initial state after reset is “1x00 0000.”
A5
A4
A3
A2
A1
A0
Mix Gain
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1–1.0 dB
1–1.5 dB
1–3.0 dB
1–4.5 dB
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1–6.0 dB
1–7.5 dB
1–9.0 dB
–10.5 dB
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
–12.0 dB
–13.5 dB
–15.0 dB
–16.5 dB
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
–78.0 dB
–79.5 dB
–81.0 dB
–82.5 dB
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
–84.0 dB
–85.5 dB
–87.0 dB
–88.5 dB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
–90.0 dB
–91.5 dB
–93.0 dB
–94.5 dB
Figure 7. Mix Gain Level Setting: DAC
–18–
REV. C
AD1845
Clock and Data Form at Register (IXA3:0 = 8)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
8
FMT1
FMT0
C/L
S/M
CFS2
CFS1
CFS0
CSS
NOT E: Placing the AD1845 in the Mode Change Enable (MCE) state is not required when changing the sample rate. However,
changes to FMT [1:0], C/L, and S/M require MCE or setting PEN = 0.
CSS
Clock Source Select. T his bit in conjunction with CFS2:0 selects the audio sample rate frequency. See Figure 8
below. Note: MODE2 allows a wider range of sample rate frequencies to be selected by using the Frequency
Select Register (refer to Registers 22 and 23).
CFS2:0
Clock Frequency Divide Select. T hese bits in conjunction with CSS select the audio sample frequency.
CFS2
CFS1
CFS0
CSS
Sam ple Rate
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
8.0
5.5125
16.0
11.025
kHz
kHz
kHz
kHz
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
27.42857 kHz
18.9
32.0
22.05
kHz
kHz
kHz
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
Reserved
37.8
Reserved
44.1
kHz
kHz
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
48.0
33.075
9.6
kHz
kHz
kHz
kHz
6.615
Figure 8. MODE1 Audio Sam ple Frequency Select
S/M
C/L
Stereo/Mono Select. T his bit determines how the audio data streams are formatted. Selecting stereo will result
with alternating samples representing left and right audio channels. Mono playback plays the same audio sample
on both channels. Mono capture only captures data from the left audio channel.
0
1
Mono
Stereo
Companded/Linear Select. T his bit selects between a linear digital representation of the audio signal or a nonlinear,
companded format for all input and output data. T he type of linear PCM or the type of companded format is
defined by the FMT bits.
0
1
Linear PCM
Companded
FMT [1:0]
res
Format Select. T he bits define the format for all digital audio input and outputs based on the state of the C/L bit.
See Figure 9 for FMT and C/L bit settings that determine the audio data type format.
Reserved for future expansion. Always write a zero to this bit.
T his register’s initial state after reset is “0000 0000.”
FMT1
FMT0
C/L
Audio D ata Type
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Linear, 8-Bit Unsigned PCM
µ-Law, 8-Bit Companded
Linear, 16-Bit T wos-Complement PCM Little Endian
A-Law, 8-Bit Companded
Reserved
Reserved
Linear, 16-Bit T wos Complement Big Endian
Reserved
Figure 9. Digital Audio Data Type
–19–
REV. C
AD1845
Interface Configuration Register (IXA3:0 = 9)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
9
CPIO
PPIO
res
res
ACAL
SDC
CEN
PEN
NOT E: Placing the AD1845 in the Mode Change Enable (MCE) state is not required when changing the CEN and PEN bits in this
register.
PEN
CEN
SDC
Playback Enable. T his bit will enable the playback of data in the format selected. T he AD1845 will generate
PDRQ and respond to PDAK signals when this bit is enabled and PPIO = 0. If PPIO = 1, this bit enables Pro-
grammed I/O (PIO) playback mode.
0
1
Playback disabled (PDRQ and PIO Playback Data Register inactive)
Playback enabled
Capture Enable. T his bit will enable the capture of data in the format selected. T he AD1845 will generate
CDRQ and respond to CDAK signals when this bit is enabled and CPIO = 0. If CPIO = 1, this bit enables PIO
capture mode.
0
1
Capture disable (CDRQ and PIO Capture Data Register inactive)
Capture enable
Single DMA Channel. T his bit will force both capture and playback DMA requests to occur on the Playback
DMA channel. T he Capture DMA CDRQ pin will be LO. T his bit will allow the AD1845 to be used with only
one DMA channel. Simultaneous capture and playback cannot occur in this mode. Should both capture and
playback be enabled (CEN=PEN=1) in the mode, only playback will occur. See “Data and Control T ransfers” for
further explanation.
0
1
Dual DMA channel mode
Single DMA channel mode
ACAL
Autocalibrate Enable. T his bit determines whether the AD1845 performs an autocalibration whenever the Mode
Change Enable (MCE) bit changes from HI to LO. See “Autocalibration” for a description of a complete
autocalibration sequence. Note that an autocalibration is forced whenever the RESET or PWRDWN pin is
asserted LO then transitions HI regardless of the state of the ACAL bit.
0
1
No autocalibration
Autocalibration after mode change
res
Reserved for future expansion. Always write zeros to these bits.
PPIO
Playback PIO Enable. T his bit determines whether the playback data is transferred via DMA or PIO.
0
1
DMA transfers only
PIO transfers only
CPIO
Capture PIO Enable. T his bit determines whether the capture data is transferred via DMA or PIO.
0
1
DMA transfers only
PIO transfers only
T his register’s initial state after reset is “00xx 1000.”
Pin Control Register (IXA3:0 = 10)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
10
XCTL1
XCTL0
res
res
res
res
IEN
INITD
INIT D
IEN
Disable setting the INIT bit after changing the sample rate in MODE1. Otherwise the INIT bit is set HI for
approximately 200 µs after changing the sample rate.
0
1
INIT bit is enabled
INIT bit is disabled
Interrupt Enable. T his bit enables the interrupt pin. T he Interrupt Pin will go active HI when the number of
samples programmed in the Base Count Register is reached.
0
1
Interrupt disabled
Interrupt enabled
res
Reserved for future expansion. Always write zeros to these bits.
REV. C
–20–
AD1845
XCT L1:0
External Control. T he state of these bits is reflected on the XCT L1:0 pins of the AD1845.
0
1
Logic LO on XCT L1:0 pins
Logic HI on XCT L1:0 pins
T his register’s initial state after reset is “00xx xx00.”
Test and Initialization Register (IXA3:0 = 11)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
11
COR
PUR
ACI
DRS
ORR1
ORR0
ORL1
ORL0
ORL1:0
ORR1:0
Overrange Left Detect. T hese bits indicate the overrange on the left capture channel. T hese bits change on
a sample-by-sample basis, and are read-only.
ORL1 ORL0
0
0
1
1
0
1
0
1
Less than –1 dB underrange
Between –1 dB and 0 dB underrange
Between 0 dB and +1 dB overrange
Greater than +1 dB overrange
Overrange Right Detect. T hese bits indicate the overrange on the right capture channel. T hese bits change
on a sample-by-sample basis, and are read-only.
ORR1 ORR0
0
0
1
1
0
1
0
1
Less than –1 dB underrange
Between –1 dB and 0 dB underrange
Between 0 dB and +1 dB overrange
Greater than +1 dB overrange
DRS
ACI
Data Request Status. T his bit indicates the current status of the PDRQ and CDRQ pins of the AD1845.
0
1
CDRQ and PDRQ are presently inactive (LO)
CDRQ or PDRQ are presently active (HI)
Autocalibrate-In-Progress. T his bit indicates the state of autocalibration or a recent exit from Mode Change
Enable (MCE). T his bit is read-only.
0
1
Autocalibration is not in progress
Autocalibration is in progress or MCE was exited within the last 128 sample periods
PUR
COR
Playback Underrun. T his bit is set when the playback FIFO is empty and after the next valid sample has been
played back. If this condition exists, DACZ determines the DAC playback value. In MODE1, DACZ is always set
and returns a midscale value.
Capture Overrun. T his bit is set when the capture FIFO is full and an additional sample has been captured. T he
sample being read will not be overwritten by the new sample. T he new sample will be ignored. T his bit changes on
a sample by sample basis.
T he occurrence of a PUR and/or COR is designated in the Status Register’s Sample Overrun/Underrun (SOUR) bit. T he SOUR bit
is the logical OR of the COR and PUR bits. T his enables a polling host CPU to detect an overrun/underrun condition while check-
ing other status bits.
T his register’s initial state after reset is “0000 0000.”
Miscellaneous Control Register (IXA3:0 = 12)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
12
MID
MODE2
res
BUF8
ID3
ID2
ID1
ID0
ID3:0
BUF8
AD1845 Revision ID. T hese four bits define the revision level of the AD1845. T he AD1845 will have ID =
“1010.” T hese bits are read-only.
Parallel Interface Bus T ransceiver Current Buffer Drive. T he AD1845 can be programmed to provide a current
drive of 16 mA or 8 mA.
0
1
16 mA current drive.
8 mA current drive.
res
Reserved for future expansion. Always write 0s to these bits.
REV. C
–21–
AD1845
MODE2
When the AD1845 is initialized, the MODE2 bit is set to 0, LO, and the AD1845 is register set compatible with
the AD1848 and the AD1846. Setting the MODE2 bit to 1, HI, enables access to the indirect registers 16
through 31 which controls the AD1845 Expanded Mode of operation.
0
1
MODE1: AD1848, AD1846, and CS4248 mode
MODE2: AD1845 enhanced feature mode
MID
Manufacturer ID Bit. T his bit is set to 1.
T his register’s initial state after reset is “10x0 1010.”
Digital Mix/Attenuation Control Register (IXA3:0 = 13)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
13
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
res
DME
DME
Digital Mix Enable. T his bit will enable the digital mix of the ADC’s output with the DAC’s input. When en-
abled, the data from the ADCs are digitally mixed with other data being delivered to the DACs regardless of
whether or not playback is enabled (PEN = 1). If capture is enabled (CEN = 1) and there is a capture overrun
(COR), then the last sample captured before overrun will be used for the digital mix. If playback is enabled
(PEN = 1) and there is a playback underrun (PUR), then a midscale zero will be added to the digital mix data if
DACZ = 1, otherwise, the last valid sample will be repeated.
0
1
Digital mix disabled (muted)
Digital mix enabled
res
Reserved for future expansion. Always write a zero to this bit.
DMA5:0
Digital Mix Attenuation. T hese bits determine the attenuation of the ADC data that is mixed with the DAC in-
put. Each attenuate step is –1.5 dB ranging from 0 dB to –94.5 dB.
T his register’s initial state after reset is “0000 00x0.”
DMA Pla yba ck Ba se Count Register s (IXA3:0 = 14 & 15)
T he DMA Base Count Registers in the AD1845 simplify integration of the AD1845 in ISA systems. T he ISA DMA controller re-
quires an external count mechanism to notify the host CPU via interrupt of a full DMA buffer. T he programmable DMA Base
Count Registers will allow such interrupts to occur.
T he Base Count Registers contain the number of samples to be transferred before an interrupt is generated on the interrupt (INT)
pin. T o load, first write a value to the Lower Base Count Register. Writing a value to the Upper Base Register will cause both Base
Count Registers to load into the Current Count Register. Once AD1845 transfers are enabled, each sample transferred causes the
Current Count Register to decrement until zero count is reached. T he next sample after zero will generate the interrupt and reload
the Current Count Register with the values in the Base Count Registers. T he interrupt is cleared by a write to the Status Register.
T he Host Interrupt Pin (INT ) will go HI during the sample period in which the Current Count Register underflows.
When using the AD1845 in MODE1 (AD1848 compatible), the Current Count Register is decremented every sample period when
either the PEN or CEN bit is enabled. T he Current Count Register is decremented in both PIO and DMA data transfer modes.
Interrupt conditions are generated by Current Count Register underflows in both PIO and DMA transfers.
Program maximum value to the Upper Base Count Register to avoid receiving DMA count interrupts while operating in PIO mode.
By enabling MODE2, the AD1845 Expanded Mode, the playback counter is only decremented when a playback sample transfer occurs.
Upper Base Count Register (IXA3:0 = 14)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
14
UB7
UB6
UB5
UB4
UB3
UB2
UB1
UB0
UB7:0
Upper Base Count. T his byte is the upper byte of the base count register containing the eight most significant bits
of the 16-bit base register. Reads from this register return the same value which was written. T he current count
contained in the counters can not be read.
T his register’s initial state after reset is “ 0000 0000.”
REV. C
–22–
AD1845
Lower Base Count Register (IXA3:0 = 15)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
15
LB7
LB6
LB5
LB4
LB3
LB2
LB1
LB0
LB7:0
Lower Base Count. T his byte is the lower byte of the base count register containing the eight least significant bits
of the 16-bit base register. Reads from this register return the same value which was written. T he current count
contained in the counters cannot be read.
T his register’s initial state after reset is “0000 0000.”
Expanded Modes (MO D E2 = 1)
T he following registers are enabled when the AD1845 is operating in MODE2 only.
Alternate Feature Enable/Left MIC Input Control Register (IXA3:0 = 16)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
16
OL
TE
LMG4
LMG3
LMG2
LMG1
LMG0
DACZ
DACZ
DAC Zero. When an underrun error occurs, this bit will force the DAC output to midscale.
0
1
Output previous valid sample
Output to midscale value
LMG4:0
T E
Left MIC Gain. T he least significant bit of this gain/attenuate select represents 1.5 dB. LMG4:0 = 0 produces
a +12 dB gain. LMG4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 dB.
See Figure 10.
T imer Enable. Setting this bit enables the 16-bit programmable timer (see Registers 20 and 21). When the timer
is enabled, the timer count is reloaded, and interrupts are generated at specified periods on the INT pin. When the
timer is disabled, the timer stops counting and the INT pin and T I bit are cleared immediately.
OL
Output Level. T his bit sets the analog output level. T he line output level may be attenuated by 3 dB.
0
1
Full scale of 2.0 V p-p (–3 dB)
Full scale of 2.8 V p-p (0 dB)
T his register’s initial state after reset is “0001 0001.”
MIC Mix Enable/Right MIC Input Control Register (IXA3:0 = 17)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
17
LMME
RMME
RMG4
RMG3
RMG2
RMG1
RMG0
res
res
Reserved for future expansion. Always write zero to this bit.
RMG4:0
Right MIC Gain. T he least significant bit of this gain/attenuate select represents 1.5 dB. RMG4:0 = 0 produces a
+12 dB gain. RMG4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 dB.
See Figure 10.
RMME
LMME
Right MIC Mix Enable. Setting this bit enables the right microphone input to be mixed with the DAC output on
R_OUT .
Left MIC Mix Enable. Setting this bit enables the left microphone input to be mixed with the DAC output on
L_OUT .
T his register’s initial state after reset is “0001 000x.”
Left Line Gain, Attenuate, Mute Mix Register (IXA3:0 = 18)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
18
LLM
res
res
LLG4
LLG3
LLG2
LLG1
LLG0
LLG4:0
res
Left Line Mix Gain. Allows setting the left line mix gain in thirty-two 1.5 dB steps. See Figure 10 for mix gain
level setting.
Reserved for future expansion. Always write zeros to these bits.
REV. C
–23–
AD1845
LLM
Left Line Mute. Setting this bit to 1 mutes the left line input into the output mixer.
T his register’s initial state after reset is “1xx0 1000.”
Right Line Gain, Attenuate, Mute, Mix Register (IXA3:0 = 19)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
19
RLM
res
res
RLG4
RLG3
RLG2
RLG1
RLG0
RLG4:0
Right Line Mix Gain. Allows setting the right line mix gain in thirty-two 1.5 dB steps. See Figure 10 for mix
gain level setting.
res
Reserved for future expansion. Always write zeros to these bits.
RLM
Right Line Mute. Setting this bit to 1 mutes the right line input into the output mixer.
T his register’s initial state after reset is “1xx0 1000.”
A4/G4
A3/G3
A2/G2
A1/G1
A0/G0
Mix Gain
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
+12.0 dB
+10.5 dB
+9.0 dB
+7.5 dB
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
+6.0 dB
+4.5 dB
+3.0 dB
+1.5 dB
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
+0.0 dB
–1.5 dB
–3.0 dB
–4.5 dB
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
–6.0 dB
–7.5 dB
–9.0 dB
–10.5 dB
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
–12.0 dB
–13.5 dB
–15.0 dB
–16.5 dB
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
–18.0 dB
–19.5 dB
–21.0 dB
–22.5 dB
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
–24.0 dB
–25.5 dB
–27.0 dB
–28.5 dB
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
–30.0 dB
–31.5 dB
–33.0 dB
–34.5 dB
Figure 10. Mix Gain Level Setting: AUX1, AUX2, MIC and LINE
Lower Tim er Bits Register (IXA3:0 = 20)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
20
TL7
TL6
TL5
TL4
TL3
TL2
TL1
TL0
T L7:0
Lower T imer Bits. T his byte is the lower byte of the timer register containing the eight least significant bits of the
16-bit register. Reads from this register return the same value which was written. T he current timer value con-
tained in the counters cannot be read.
T his register’s initial state after reset is “0000 0000.”
REV. C
–24–
AD1845
Upper Tim er Bits Register (IXA3:0 = 21)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
21
TU7
TU6
TU5
TU4
TU3
TU2
TU1
TU0
T U7:0
Upper T imer Bits. T his byte is the upper byte of the timer register containing the eight most significant bits of the
16-bit register. Reads from this register return the same value which was written. T he current timer value con-
tained in the counters cannot be read. T he timer counter is determined by the clock source selected (see below).
Input Frequency
Divider
T imer Counter
24.576 MHz
14.31818 MHz
24.000 MHz
25.000 MHz
33.000 MHz
247
144
242
252
333
10.050 µs
10.057 µs
10.083 µs
10.080 µs
10.091 µs
T his register’s initial state after reset is “0000 0000.”
Upper Frequency Select Bits Register (IXA3:0 = 22)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
FU3
D ata 2
D ata 1
D ata 0
22
FU7
FU6
FU5
FU4
FU2
FU1
FU0
FU7:0
Upper Frequency Select Bits. T his register is accessible when FREN is 1. Writing to this register allows the user
to program the sampling frequency from 4 kHz to 50 kHz in 1 Hz increments. Writing to the Lower and Upper
Frequency Select Register allows the AD1845 to process audio data using approximately 50,000 different audio
sample rates. One LSB represents exactly one hertz. Selecting frequencies below 4 kHz or above 50 kHz will
result in degraded audio performance. Some common sample rates are listed below:
Quality
Sampling Frequency
FU7:0 (hex)
FL7:0 (hex)
Voice
Radio
T ape
CD
8.0 kHz
0001 1111
0010 1011
0101 0110
1010 1100
1011 1011
0100 0000
0001 0001
0010 0010
0100 0100
1000 0000
default
11.025 kHz
22.05 kHz
44.1 kHz
48.0 kHz
DAT
T his register’s initial state after reset is “0001 1111.”
Lower Frequency Select Bits Register (IXA3:0 = 23)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
FL3
D ata 2
FL2
D ata 1
D ata 0
23
FL7
FL6
FL5
FL4
FL1
FL0
FL7:0
Lower Frequency Select Bits. Writing to the Lower Frequency Select register updates the entire 16-bit frequency register.
T his register’s initial state after reset is “0100 0000.”
Capture Playback Tim er Register (IXA3:0 = 24)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
24
res
TI
CI
PI
CU
CO
PO
PU
PU
PO
Playback Underrun. T his bit is set when the DAC runs out of data and a sample has been missed.
Playback Overrun. T his bit is set when the host tries to write data into the FIFO and the write was ignored be-
cause the FIFO was full.
CO
CU
Capture Overrun. T his bit is set when the ADC has a sample to load into the FIFO, and the data was ignored
because the capture FIFO was full.
Capture Underrun. T his bit is set when the host attempts to read from the capture FIFO when it is empty. Under
these circumstances, the last valid byte is sent to the host.
PI
Playback Interrupt. T his bit indicates that there is an interrupt pending from the playback DMA count registers.
Capture Interrupt. T his bit indicates that there is an interrupt pending from the capture DMA count registers.
CI
REV. C
–25–
AD1845
T I
T imer Interrupt. T his bit indicates that there is an interrupt pending from the timer count registers.
Reserved for future expansion. Always write zero to this bit.
res
Playback, Capture and timer interrupts may be cleared simultaneously by writing to the Status Register. T hese interrupts may be
cleared individually by writing a “0” to the corresponding bit. Note that the timer interrupt requires a minimum wait period of 10 µs
after the interrupt is set and before T I is recognized. Use T E to clear the timer interrupt immediately.
T his register’s initial state after reset is “100x x000.”
Revision ID Register (IXA3:0 = 25)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
25
V2
V1
V0
res
res
CID2
CID1
CID0
V2:0
res
Version Number. Indicates the version of the AD1845.
Reserved for future expansion. Always write zeros to these bits.
Chip ID Number.
CID2:0
T his register’s initial state after reset is “x000 0000.”
Mono Control Registers (IXA3:0 = 26)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
26
MIM
MOM
res
res
MIA3
MIA2
MIA1
MIA0
MIA3:0
Mono Input Attenuation. T he least significant bit represents 3.0 dB attenuation. See Figure 11 to determine
the attenuation.
res
Reserved for future expansion. Always write zeros to these bits.
Mono Output Mute. M_OUT is muted by setting MOM to 1.
MOM
0
1
Mono output not muted
Mono output muted
MIM
Mono Input Mute. M_IN is muted by setting MIM to 1.
0
1
Mono input not muted
Mono input muted
T his register’s initial state after reset is “00xx 0011.”
MIA3
MIA2
MIA1
MIA0
MO NO Attenuation
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0.0 dB
–3.0 dB
–6.0 dB
–9.0 dB
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
–12.0 dB
–15.0 dB
–18.0 dB
–21.0 dB
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
–24.0 dB
–27.0 dB
–30.0 dB
–33.0 dB
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
–36.0 dB
–39.0 dB
–42.0 dB
–45.0 dB
Figure 11. Mono Attenuation
REV. C
–26–
AD1845
Power-Down Control Register (IXA3:0 = 27)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
27
ADCPWD
DACPWD
MIXPWD
res
FREN
res
res
res
res
Reserved for future expansion. Always write zeros to these bits.
FREN
Frequency Select Register Enable. In MODE2, selecting this bit will turn on the Frequency Select Registers (see
indirect registers 22 and 23) and disable CFS2:0.
0
1
CFS Active.
Frequency Select Registers Active, CFS disabled.
MIXPWD
DACPWD
ADCPWD
Mixer Power Down. T he DAC and the output mixer are powered down, and the DAC sample clock is turned off.
DAC Power Down. T he DAC is powered down and the DAC sample clock is turned off.
ADC Power Down. T he ADC is powered down and the ADC sample clock is turned off.
T his register’s initial state after reset is “000x 0xxx.”
Capture Data Form at Control Register (IXA3:0 = 28)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
28
CFMT1
CFMT0
CC/L
CS/M
res
res
res
res
NOT E: Changing CFMT [1:0], CC/L, CS/M, requires the Mode Change Enable (MCE) state or setting CEN = 0.
res
Reserved for future expansion. Always write zeros to these bits.
CS/M
Capture Stereo/Mono Select. Setting this bit determines how the captured audio data will be formatted. In the
Mono mode, valid information is captured on the “left” channel, and the “right” channel data is not valid.
0
1
Mono Format
Stereo Format
CC/L
Capture Companding/Linear Select. T his bit is set to determine linear, µ-Law or A-Law companding. See Figure
12 for CFMT [1:0] and CC/L bit settings that determine the audio data type capture format.
CFMT [1:0]
Capture Data Format. T his bit is set to format the data being captured in MODE 2. See Figure 12 for CFMT
and CC/L bit settings that determine the capture audio data type format.
T his register’s initial state after reset is “0000 xxxx.”
CFMT1
CFMT0
CC/L
Audio D ata Type
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Linear, 8-Bit Unsigned PCM
µ-Law, 8-Bit Companded
Linear, 16-Bit T wos Complement PCM Little Endian
A-Law, 8-Bit Companded
Reserved
Reserved
Linear, 16-Bit T wos-Complement Big Endian
Reserved
Figure 12. Capture Audio Data Type
Crystal, Clock Select/Total Power-Down Register (IXA3:0 = 29)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
29
XFS2
XFS1
XFS0
res
res
res
res
TOTPWD
T OT PWD
T otal Power Down. When T OT PWD = HI, the ADC, DAC, mixer, and voltage reference are powered down, and
the ADC and DAC sample clocks are turned off. Only the digital interface remains active to allow the host to exit
the AD1845 from the total power-down state.
res
Reserved for future expansion. Always write zeros to these bits.
REV. C
–27–
AD1845
XFS2:0
Crystal/Clock Input Frequency Select. On power up or reset, the AD1845 expects a 24.576 MHz input clock. If
the clock source connected to the AD1845 is different from the default condition, then the clock input must be
selected using this register. For a detailed explanation see the Power Up and Reset section of the data sheet. Figure
13 summarizes the valid input clock frequencies. Clock sources with excessive jitter may not yield optimal analog
performance.
T his register’s initial state after reset is “000x xxx0.”
XFS2
XFS1
XFS0
Input Fr equency
24.576 MHz
14.31818 MHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
24.000
25.000
33.000
MHz
MHz
MHz
Reserved
Reserved
Reserved
Figure 13. Input Frequency Selection
Capture Upper Base Count Register (IXA3:0 = 30)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
30
CUB7
CUB6
CUB5
CUB4
CUB3
CUB2
CUB1
CUB0
CUB7:0
Capture Upper Base Count. T his byte is the upper byte of the base count register containing the eight most sig-
nificant bits of the second 16-bit base register. Reads from this register return the same value that was written.
T he current count contained in the counters cannot be read.
T his register’s initial state after reset is “0000 0000.”
Capture Lower Base Count Register (IXA3:0 = 31)
IXA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
31
CLB7
CLB6
CLB5
CLB4
CLB3
CLB2
CLB1
CLB0
CLB7:0
Capture Lower Base Count. T his byte is the lower byte of the base count register containing the eight least signifi-
cant bits of the second 16-bit base register. Reads from this register return the same value that was written. T he
current count contained in the counters cannot be read.
T his register’s initial state after reset is “0000 0000.”
REV. C
–28–
AD1845
TIME
D ATA AND CO NTRO L TRANSFERS
T he AD1845 SoundPort Stereo Codec supports a DMA re-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control
register accesses and for applications lacking DMA control.
PIO transfers can be made on one channel while the other is
performing DMA. T ransfers to and from the AD1845
SoundPort Codec are asynchronous relative to the internal data
conversion clock. T ransfers are buffered by FIFOs located in
the capture and playback paths.
SAMPLE 3
SAMPLE 3
SAMPLE 2
SAMPLE 2
SAMPLE 1
SAMPLE 1
RIGHT MS
RIGHT LS
LEFT MS
LEFT LS
BYTES 3 AND 4
BYTES 1 AND 2
Figure 17. 16-Bit Stereo Data Stream Sequencing, Little
Endian
TIME
SAMPLE 6 SAMPLE 5 SAMPLE 4 SAMPLE 4 SAMPLE 3 SAMPLE 2 SAMPLE 1
D ata O r der ing
T he number of byte-wide transfers required depends on the
data format selected. T he AD1845 is designed for “little and
big endian” formats. In little endian format, the least significant
byte (i.e., occupying the lowest memory address) gets trans-
ferred first. T herefore, 16-bit data transfers require first trans-
ferring the least significant bits [7:0] and then transferring the
most significant bits [15:8], where Bit 15 is the most significant
bit in the word. In big endian format, byte ordering for the most
significant (MS) byte and least significant (LS) byte are swapped.
LS
MS
LS
MS
BYTES 3 AND 4
BYTES 1 AND 2
Figure 18. 16-Bit Mono Data Stream Sequencing, Big
Endian
TIME
SAMPLE 1
SAMPLE 3
SAMPLE 3
SAMPLE 2
SAMPLE 2
SAMPLE 1
In addition, left channel data is always transferred before right
channel data with the AD1845. T he following figures should
make these requirements clear.
RIGHT LS
RIGHT MS
LEFT LS
LEFT MS
TIME
BYTES 3 AND 4
BYTES 1 AND 2
SAMPLE 6
SAMPLE 5
SAMPLE 4
SAMPLE 3
SAMPLE 2
SAMPLE 1
Figure 19. 16-Bit Stereo Data Stream Sequencing, Big
Endian
MONO
BYTE 4
MONO
MONO
BYTE 2
MONO
BYTE 1
FIFO
BYTE 3
T he AD1845 includes two 16-sample deep FIFOs. T he FIFOs
are built into the capture and playback paths and are completely
transparent to the user and require no programming. T he
FIFOs are active in MODE1 and MODE2.
Figure 14. 8-Bit Mono Data Stream Sequencing
TIME
T he AD1845 maintains a continuous playback stream by re-
questing data from the host until the FIFO located in the play-
back path is full. As the FIFO empties, new samples are
requested to keep the playback FIFO full. In the event that the
FIFO runs out of data and DACZ is reset to “0,” the last valid
sample will be continuously played back. If DACZ is “1,” the
AD1845 will output a midscale value.
SAMPLE 3
SAMPLE 3
SAMPLE 2
SAMPLE 2
SAMPLE 1
SAMPLE 1
RIGHT
BYTE 4
LEFT
RIGHT
BYTE 2
LEFT
BYTE 3
BYTE 1
Figure 15. 8-Bit Stereo Data Stream Sequencing
T he FIFO located in the capture data path attempts to stay
empty by making requests of the host every sample period that it
contains valid data. When the host system cannot respond
during the same sample period, the capture FIFO starts filling,
and avoids a loss of data in the audio data stream.
TIME
SAMPLE 1
SAMPLE 6
SAMPLE 5
SAMPLE 4
SAMPLE 3
SAMPLE 2
LS
MS
LS
MS
D ata Bus D r iver s
T he AD1845 has built-in 8 or 16 mA bus drivers for interfacing
to the ISA bus. T he drivers reduce the need for the off-chip
74_245 bus transceiver buffers in many applications. If higher
drive capability is required, 24 mA for example, the AD1845
generates the appropriate direction and enable signals. See
Figure 1 and refer to the Applications Circuits section of the
data sheet.
BYTES 3 AND 4
BYTES 1 AND 2
Figure 16. 16-Bit Mono Data Stream Sequencing, Little
Endian
Contr ol and P r ogr am m ed I/O (P IO ) Tr ansfer s
T his simpler mode of transfers is used both for control register
accesses and programmed I/O. T he 37 control and PIO data
registers cannot be accessed via DMA transfers. Playback PIO
REV. C
–29–
AD1845
CDRQ/PDRQ
OUTPUTS
is activated when both Playback Enable (PEN) is set and Play-
back PIO (PPIO) is set. Capture PIO is activated when both
Capture Enable (CEN) is set and Capture PIO (CPIO) is set.
See Figures 20 and 21 for the detailed timing of the control
register/PIO transfers. T he RD and WR signals are used to
define the actual read and write cycles, respectively. T he host
holds CS LO during these transfers. T he DMA Capture Data
Acknowledge (CDAK) and Playback Data Acknowledge
(PDAK) must be held inactive, i.e., HI.
tSUDK1
tCSSU
tSUDK2
tCSHD
PDAK INPUT
CS INPUT
tDBDL
DBEN OUTPUT
HI
DBDIR OUTPUT
tSTW
WR INPUT
tDHD2
For read/capture cycles, the AD1845 will place data on the
DAT A7:0 lines while the host is asserting the read strobe, RD,
by holding it LO. For write/playback, the host must place data
on the DAT A7:0 pins while strobing the WR signal LO. T he
AD1845 latches the write/playback data on the rising edge of
the WR strobe.
tWDSU
DATA7:0
INPUTS
tADHD
tADSU
DATA1:0
INPUTS
Figure 21. Control Register/PIO Write Cycle
When using PIO data transfers, the Status Register must be
polled to determine when data should be transferred. Note that
the ADC capture data will be ready (CRDY HI) from the previ-
ous sample period shortly before the DAC playback data is
ready (PRDY HI) for the next sample period. T he user should
not wait for both ADCs and DACs to become ready before
initiating data transfers. Instead, as soon as capture data is
ready, it should be read; as soon as the DACs are ready, play-
back data should be written.
Acknowledge signals cause the AD1845 to perform DMA trans-
fers. T he input address lines, ADR1:0, are ignored. Data is
transferred between the proper internal sample registers.
T he read strobe (RD) and write strobe (WR) delimit valid data
for DMA transfers. Chip select (CS) is a “don’t care”; its state
is ignored by the AD1845.
T he AD1845 may assert the Data Request signals, CDRQ and
PDRQ, at any time. Once asserted, these signals will remain
active HI until the corresponding DMA cycle occurs with the
host’s Data Acknowledge signals. T he Data Request signals will
be deasserted after the falling edge of the final RD or WR strobe
in the transfer of a sample, which typically consists of multiple
bytes. See “Data Ordering” above for a definition of “sample.”
Values written to the XCT L1:0 bits in the Pin Control Register
(IXA3:0 = 10) will be reflected in the state of the XCT L1:0
external output pins. T his feature allows a simple method for
signaling or software control of external logic. Changes in state
of the external XCT L pins will occur within one sample period.
Because their change is referenced to the internal sample clock,
no useful timing diagram can be constructed.
DMA transfers may be independently aborted by resetting the
Capture Enable (CEN) and/or Playback Enable (PEN) bits in
the Interface Configuration Register. T he current capture
sample transfer will be completed if a capture DMA is termi-
nated. T he current playback sample transfer must be completed
if a playback DMA is terminated. If CDRQ and/or PDRQ are
asserted HI while the host is resetting CEN and/or PEN, the
request must be acknowledged. T he host must assert CDAK
and/or PDAK LO and complete a final sample transfer.
D IRECT MEMO RY ACCESS (D MA) TRANSFERS
T he second type of bus cycle supported by the AD1845 are
DMA transfers. Both dual channel and single channel DMA
operations are supported. T o enable Playback DMA transfers,
playback enable (PEN) must be set and PPIO cleared. T o
enable Capture DMA transfers, capture enable (CEN) must be
set and CPIO cleared. During DMA transfers, the AD1845
asserts HI the Capture Data Request (CDRQ) or the Playback
Data Request (PDRQ) followed by the host’s asserting LO
the DMA Capture Data Acknowledge (CDAK) or Playback
Data Acknowledge (PDAK), respectively. The host’s asserted
Single-Channel D MA
Single-Channel DMA mode allows the AD1845 to be used in
systems with only a single DMA channel. It is enabled by set-
ting the SDC bit in the Interface Configuration Register. All
captures and playbacks take place on the playback channel.
Obviously, the AD1845 cannot perform a simultaneous capture
and playback in Single-Channel DMA mode.
CDRQ/PDRQ
OUTPUTS
tSUDK1
tCSSU
tSUDK2
tCSHD
CDAK INPUT
CS INPUT
Playback will occur in Single-Channel DMA mode exactly as it
does in T wo-Channel mode. Capture, however, is diverted to
the playback channel which means that the capture data request
occurs on the PDRQ pin and the capture data acknowledge
must be received on the PDAK pin. T he CDRQ pin will re-
main inactive LO. Any inputs to CDAK will be ignored.
tDBDL
tSTW
DBEN & DBDIR
OUTPUTS
RD INPUT
tRDDV
tDHD1
tADHD
Playback and capture are distinguished in Single-Channel DMA
mode by the state of the playback enable (PEN) or capture
enable (CEN) control bits. If both PEN and CEN are set in
Single-Channel DMA mode, playback will be presumed.
DATA7:0
OUTPUTS
tADSU
DATA1:0
INPUTS
T o avoid confusion of the origin of a request when switching
between playback and capture in Single-Channel DMA mode,
both CEN and PEN should be disabled and all pending re-
quests serviced before enabling the alternative enable bit.
Figure 20. Control Register/PIO Read Cycle
REV. C
–30–
AD1845
ISA BUS BCLK
Switching between playback and capture in Single-Channel
DMA mode does not require changing the PPIO and CPIO bits
or passing through the Mode Change Enable state except for
initial setup. For setup, assign zeros to both PPIO and CPIO.
T his configures both playback and capture for DMA. Following
setup, switching between playback and capture can be effected
entirely by setting and clearing the PEN and CEN control bits,
a technique which avoids having to enter Mode Change Enable.
CDRQ /PDRQ
OUTPUTS
CDAK/PDAK
INPUTS
tBWDN
RD OR WR
INPUTS
RIGHT/
HIGH BYTE
LEFT/
LOW BYTE
D ual-Channel D MA
DATA7:0
T he AD1845 is designed to support full duplex DMA operation
by allowing simultaneous capture and playback. T he Dual-
Channel DMA feature enables playback and capture DMA
requests and acknowledges to occur on separate DMA channels.
Capture and playback are enabled and set for DMA transfers.
In addition, Dual-Channel DMA must be set (SDC = 0). It is
not necessary to enter MCE (Mode Change Enable) to change
PEN and CEN (Playback and Capture Enable).
Figure 24. 8-Bit Stereo or 16-Bit Mono DMA Cycle
ISA BUS BCLK
CDRQ /PDRQ
OUTPUTS
CDAK/PDAK
INPUTS
tBWDN
D MA Tim ing
RD OR WR
Below, timing parameters are shown for 8-Bit Mono Sample
Read/Capture and Write/Playback DMA transfers in Figures 22
and 23. T he same timing parameters apply to multi-byte trans-
fers. T he relationship between timing signals is shown in Fig-
ures 24 and 25.
INPUTS
LOW
BYTE
LOW
BYTE
HIGH
BYTE
HIGH
BYTE
DATA7:0
LEFT
SAMPLE
RIGHT
SAMPLE
T he Host Interrupt Pin (INT ) will go HI after a sample transfer
in which the Current Count Register underflows.
Figure 25. 16-Bit Stereo DMA Interrupt
D MA Inter r upt
Writing to the internal 16-bit Base Count Register sets up the
count value for the number of samples to be transferred. Note
that the number of bytes transferred for a given count will be a
function of the selected global data format. T he internal Cur-
rent Count Register is updated with the current contents of the
Upper and Lower Base Count Registers when a write occurs to
the Upper Base Count Register.
ISA BUS BCLK
CDRQ OUTPUT
tDRHD
tDKSU
CDAK INPUT
tDKHDb
tDBDL
DBEN & DBDIR
OUTPUTS
T he Current Count Register cannot be read by the host. Read-
ing the Base Count Registers will only read back the initializa-
tion values written to them.
tSTW
RD INPUT
tDHD1
tRDDV
DATA7:0
T he Current Count Register decrements by one after every
sample transferred. An interrupt event is generated after the
Current Count Register is zero and an additional playback
sample is transferred. T he INT bit in the Status Register always
reflects the current internal interrupt state defined above. T he
external INT pin will only go active HI if the Interrupt Enable
(wIEN) bit in the Interface Configuration Register is set. If the
IEN bit is zero, the external INT pin will always stay LO, even
though the Status Register’s INT bit may be set.
OUTPUTS
Figure 22. 8-Bit Mono DMA Read/Capture Cycle
ISA BUS BCLK
PDRQ OUTPUT
tDRHD
tDKSU
PDAK INPUT
tDKHDa
tDSDL
DBEN OUTPUT
HI
DBDIR OUTPUT
tSTW
WR INPUT
tDHD2
tWDSU
DATA7:0
OUTPUTS
Figure 23. 8-Bit Mono DMA Write/Playback Cycle
REV. C
–31–
AD1845
P O WER-UP AND RESET
H ar dwar e Contr olled States
The PWRDWN and RESET pin should be held in the active LO
state when power is first applied to the AD1845. The AD1845’s
initialization commences when PWRDWN and RESET have both
been deasserted (HI). While initializing, the AD1845 ignores all
writes and all reads will yield “1000 0000 (80h).” At the conclu-
sion of initialization, all registers will be set to their default values as
listed in Figure 5. When CDAK and PDAK are inactive during
power-up or reset, the conclusion of the initialization period,
after approximately 512 ms, can be detected by polling the
index register for some value other than “1000 0000 (80h).”
T he hardware power-down states are accessed by bringing the
PWRDWN or RESET pin LO. Either of these signals place the
AD1845 into the maximum power conservation mode. Bringing
the PWRDWN or RESET pin HI will power-up the codec in
approximately 512 ms (see the Power-Up and Reset section of
this data sheet).
•
Power-Down: PWRDWN immediately puts the AD1845 into
its lowest power-down state. T he AD1845’s parallel inter-
face will not function and all bidirectional signal lines will be
in a high-impedance state.
Upon power-up the AD1845 enters the Mode Change Enable
(MCE) state. In the default condition, the AD1845 expects to
receive a 24.576 MHz input clock source. T o change the selec-
tion of the current or default input clock source, follow the steps
listed below:
•
Reset: RESET powers down the AD1845 gradually to its
lowest power-down state. T he AD1845 performs a se-
quenced power-down that eliminates audible effects from the
DAC’s output. T he XT AL1 input must be clocked for the
minimum duration of the RESET pulsewidth. T he
AD1845’s parallel interface will not function and all bidirec-
tional signal lines will be in a high-impedance state. Note:
the clock must operate during the software or hardware
power-down process.
•
•
•
Wait for the AD1845 to initialize.
Set the MODE2 bit to 1.
Enter the MCE state, write to the Crystal/Clock Input Fre-
quency Select bits (XFS2:0) to select the desired frequency.
Softwar e Contr olled States
•
•
T he AD1845 will now resynchronize its internal states to the
new clock. Writes to the AD1845 will be ignored. Poll the
index register for some value other than “1000 0000 (80h).”
T o enter the T otal Power-Down mode requires entering the
Mode Change Enable (MCE) state. After entering MCE, the
T otal Power-Down mode can be accessed by writing a “1” to
the T OT PWD bit in the T otal Power-Down Register. Exiting
the T otal Power-Down mode (writing a “0” to the T OT PWD
bit in the T otal Power-Down Register) will initialize the
AD1845 in approximately 512 ms (see the Power-Up and Reset
section of this data sheet).
Clear the MCE bit.
AD VANCED P O WER-D O WN MO D ES
T he AD1845 has eight Advanced Power-Down Modes available
at any time. T he user can control these power-down modes
through hardware by asserting the PWRDWN and RESET pins
or through software by writing to the Power-Down and the
T otal Power-Down Control Registers. Figure 26 summarizes
the power-down delay, power-up delay, and power dissipation
for each power-down mode. A priority listing and description of
the power-down modes follows. Note that the hardware con-
trolled Power-Down and Reset modes take precedence over the
software controlled power-down states.
•
Total Power-Down: In the T otal Power-Down mode the
ADC, DAC, Mixer, and voltage reference are turned off,
but the digital interface remains active awaiting power-up.
All ADC and DAC data is flushed including data in the
capture and playback FIFOs.
T o enter the software controlled power-down states in the
Power-Down Control Register, write a “1” to the control bits.
Advanced
P ower-D own
PWRDWN RESET TO TP WD AD CP WD D ACP WD MIXP WD P ower-D own P ower-Up
P ower
Mode
P in
P in
Bit
Bit
Bit
Bit
D elay*
D elay*
D issipation
Operating
HI
HI
0
0
0
0
x
x
600 mW
1. Power-Down
2. Reset
3. T otal Power-Down HI
4. Standby HI
5. Mixer Power-Down HI
6. Mixer Only HI
LO
HI
x
x
x
1
0
0
0
0
0
x
x
x
1
0
1
1
0
x
x
x
x
x
1
0
1
x
x
x
1
1
0
0
0
0 s
512 ms
512 ms
512 ms
1/FS
1/FS
1/FS
10 mW
10 mW
LO
HI
HI
HI
HI
HI
HI
3 ms
3 ms
1/FS
1/FS
1/FS
1/FS
1/FS
150 mW
180 mW
350 mW
260 mW
400 mW
425 mW
7. ADC Power-Down HI
8. DAC Power-Down HI
1/FS
1/FS
“x” = Don’t Care
*Values shown are derived using a 24.576 MHz input clock source.
All values are proportional to the input clock source.
Figure 26. Advanced Power-Down Mode Sum m ary
REV. C
–32–
AD1845
T he AD1845 performs a sequenced power-down that eliminates
audible effects from the DAC’s output, and saves the codec’s
internal operating state. Clearing the bits (writing a “0” to the
control bits) returns the AD1845 from the power-down state
and begins the initialization sequence. T he AD1845 exits the
power-down mode within 1 sample period. However, an
additional 128 sample periods are required to unmute the out-
puts and restore the internal settings to the pre-Power-Down
operating state.
• Clear the Mode Change Enable (MCE) bit.
• T he Autocalibrate-In-Progress (ACI) bit will remain HI for
384 sample periods. Poll the ACI bit until it transitions from
HI to LO.
• Set desired gain/attenuation/mute and digital mix values.
During the autocalibration sequence, data output from the
ADCs is meaningless. Inputs to the DACs are ignored. Even if
the user specified the muting of all analog outputs, near the end
of the autocalibration sequence, dc analog outputs very close to
VREF will be produced at the line output.
•
Standby: Entering the Standby mode places the ADC, DAC
and the Mixer into a low power state, and forces all outputs
to be muted. Standby turns off all internal digital and analog
circuitry with the exception of the digital interface and the
voltage reference. All ADC and DAC data is flushed includ-
ing data in the capture and playback FIFOs.
CH ANGING SAMP LE RATES
In MODE1 the AD1845 can change sample rates by entering
the Mode Change Enable state or writing directly to the Clock
and Data Format Register. In MODE2, the AD1845 changes
sample rates by writing directly to the Upper and Lower Fre-
quency Select Register. Please refer to the following examples
for changing the sample rate.
•
•
Mixer Power-Down: Entering the Mixer Power-Down mode,
causes both the mixer and the DAC circuitry to be turned
off. All DAC data is flushed including data in the playback
FIFO. In this mode the mixer is off and the AD1845 is
muted, but the ADC remains functional.
T o change the selection of the current sample rate by entering
the Mode Change Enable state requires the sequence which is
summarized as follows (this is the same sequence used by the
AD1848, AD1846, CS4248, and CS4231):
Mixer Only: T he Mixer Only mode is initiated by powering
down both the ADC and DAC, leaving the analog mixer and
the digital interface active. MIC, LINE, AUX1, AUX2, and
M_IN can be mixed in the analog domain on the AD1845
outputs. All ADC and DAC data is flushed including data in
the capture and playback FIFOs.
• Set the Mode Change Enable (MCE) bit.
• In a single write cycle, change the Clock Frequency Divide
Select (CFS2:0) and/or the Clock Source Select (CSS).
•
•
ADC Power-Down: Entering the ADC Power-Down mode,
causes the ADC digital and analog engines to be turned off.
All ADC data is flushed including data in the capture FIFO
and the AD1845 is rendered deaf. T he input programmable
gain amplifier (PGA) is also shut down. T he DAC and
mixer remain active allowing the AD1845 to continue to
playback and mix samples.
• T he AD1845 now needs to resynchronize its internal states to
the new clock. Writes to the AD1845 will be ignored. Reads
will produce “1000 0000 (80h)” until the resynchronization is
complete. Poll the Index Register until something other than
this value is returned.
• Clear the Mode Change Enable (MCE) bit.
• If ACAL is set, follow the procedure described in
“Autocalibration” above.
DAC Power-Down: Entering the DAC Power-Down mode
suspends the DAC digital and analog engines, and all DAC
data is flushed including data in the playback FIFO. How-
ever, the mixer and ADC are functional allowing the
AD1845 to continue to capture and mix samples.
• Wait 128 sample cycles or poll the ACI bit until it transitions
LO.
• Set to desired gain/attenuation values, and unmute DAC
outputs (if muted).
AUTO CALIBRATIO N
Alternatively, the AD1845 can be programmed to change the
sample rate selection “on the fly” without entering the Mode
Change Enable Sequence. T he following sequence applies to
the AD1845 operating in MODE1 or MODE2.
T he AD1845 calibrates the ADCs and DACs for greater accu-
racy by minimizing dc offsets. Upon power-up or after RESET,
the AD1845 automatically performs an autocalibration after the
first return from the Mode Change Enable state, regardless of
the state of the ACAL bit. Autocalibration can be forced when
the AD1845 returns from the Mode Change Enable state and
the ACAL bit in the Interface Configuration register has been
set. If the ACAL bit is not set, the RAM normally containing
ADC and DAC offset compensations will be saved, retaining
the offsets of the most recent autocalibration.
• In a single write cycle, change the Clock Frequency Divide
Select (CFS2:0) and/or the Clock Source Select (CSS). For
compatibility reasons, the AD1845 will send out “1000 0000
(80h)” for approximately 200 µs. Even this short wait can be
disabled by setting the INIT D bit. When the INIT D bit is set,
the AD1845 is ready immediately after changing the sample
rate using CFS and CSS.
T he completion of autocalibration can be determined by polling
the Autocalibrate-In-Progress (ACI) bit in the T est and Initial-
ization Register, which will be set during autocalibration. T rans-
fers enabled during autocalibration do not begin until the
completion of autocalibration.
• T he AD1845 now needs to resynchronize its internal states to
the new clock. Writes to the AD1845 will be ignored. Reads
will produce “1000 0000 (80h)” until the resynchronization is
complete. Poll the Index Register until something other than
this value is returned.
T he following summarizes the procedure for autocalibration:
• Set the Mode Change Enable (MCE) bit.
• Set the Autocalibration (ACAL) bit.
• Set to desired gain/attenuation values, and unmute DAC
outputs (if muted).
REV. C
–33–
AD1845
1F
3.3k⍀
In the Expanded Mode, MODE2, the AD1845 can be pro-
grammed to change the sample rate selection in 1 Hz incre-
ments “on the fly” and without entering the Mode Change
Enable Sequence. T he following sequence applies to the
AD1845 in MODE2 only:
L_LINE
R_LINE
560pF
NPO
4.3k⍀
1F
3.3k⍀
• Enable the Frequency Select Register by setting FREN to 1.
560pF
NPO
4.3k⍀
• Change the Lower and Upper Frequency Select Register,
FU7:0 and FL7:0.
AP P LICATIO NS CIRCUITS
Figure 27. 2 V rm s Line-Level Input Circuit for LINE Inputs
T he AD1845 Stereo Codec has been designed to require a
minimum of external circuitry. T he recommended circuits are
shown in Figures 27 through 35.
1F
3.3k⍀
L_AUX1
L_AUX2
M_IN
1000pF
NPO
4.3k⍀
See Figure 1 for an illustration of the connection between the
AD1845 SoundPort Codec and the Industry Standard Archi-
tecture (ISA) computer bus, also known as the “PC-AT bus.”
Note that the 74_245 transceiver receives its enable and direc-
tion signals directly from the Codec. Analog Devices recom-
mends using the “slowest” 74_245 adequately fast to meet all
AD1845 and computer bus timing and drive requirements. So
doing will minimize switching transients of the 74_245. T his in
turn will minimize the digital feed through effects of the trans-
ceiver when driving the AD1845, which can cause the audio
noise floor to rise. In most applications, the 74_245 can be
omitted and the AD1845 connected directly ISA bus taking
advantage of the AD1845’s built-in 16 mA drivers.
1F
3.3k⍀
R_AUX1
R_AUX2
1000pF
NPO
4.3k⍀
Figure 28. 2 V rm s Line-Level Input Circuit for M_IN and
AUX Inputs
T he AD1845 codec contains an optional +20 dB gain block to
accommodate condenser microphones. Particular system re-
quirements will depend upon the characteristics of the intended
microphone. Figure 29 illustrates one example of how an elec-
tret condenser mike requiring phantom power could be con-
nected to the AD1845. VREF is shown buffered by an op amp; a
transistor like a 2N4124 will also work fine for this purpose.
Note that if a battery-powered microphone is used, the buffer
and R2s are not needed. T he values of R1, R2, and C should be
chosen in light of the mic characteristics and intended gain.
T ypical values for these might be R1 = 20 kΩ, R2 = 2 kΩ, and
C = 220 pF.
Industry-standard compact disc “line-levels” are 2 V rms cen-
tered around analog ground. (For other audio equipment, “line
level” is much more loosely defined.) T he AD1845 SoundPort
is a +5 V only powered device. Line level voltage swings for the
AD1845 are defined to be 1 V rms for a sine wave ADC input
and user selectable 0.707 V rms or 1 V rms for a sine wave
DAC output. T hus, 2 V rms input analog signals must be
attenuated and either centered around the reference voltage
intermediate between 0 V and +5 V or ac coupled. T he VREF
pin will be at this intermediate voltage, nominally 2.25 V. It has
limited drive but can be used as a voltage datum to an op amp
input. Note, however, that dc-coupled inputs are not recom-
mended, as they provide no performance benefits with the
AD1845 architecture. Furthermore, dc offset differences be-
tween multiple dc-coupled inputs create the potential for
“clicks” when changing the input mixer selection.
C
LEFT ELECTRET
R1
CONDENSER
MICROPHONE
INPUT
1F
5k⍀
0.33F
L_MIC
1/2 SSM2135
OR AD820
R2
R2
V
REF
1/2 SSM2135 OR AD820
C
A circuit for 2 V rms mono, line-level inputs and auxiliaries is
shown in Figure 27 and Figure 28. Note that this is a divide-
by-two resistive dividers considering the codec input imped-
ance. T he input resistor and 560 pF (1000 pF) capacitor
provides the single-pole of antialias filtering required for the
ADCs. If line-level inputs are already at the 1 V rms levels
expected by the AD1845, the resistors in parallel with the
560 pF (1000 pF) capacitors can be omitted. If the application
does not route the AUX2 inputs to the ADCs, then no antialias
filtering is required (only the 1 µF ac coupling capacitor).
R1
1F
5k⍀
0.33F
R_MIC
RIGHT ELECTRET
CONDENSER
MICROPHONE
INPUT
1/2 SSM2135
OR AD820
V
REF
Figure 29. “Phantom -Powered” Microphone Input
Circuit
REV. C
–34–
AD1845
XTAL1O
XTAL1I
Figure 30 shows ac-coupled line outputs. T he resistors are used
to center the output signals around analog ground. If dc-cou-
pling is desired, VREF could be used with op amps as mentioned
above, if desired.
20–64pF
20–64pF
24.576 MHz
Figure 34. Crystal Connections
1F
Note: XT AL2I and XT AL2O, are not used in the AD1845.
L_OUT
Analog Devices also recommends a pull-down resistor for
47k⍀
PWRDWN.
Good, standard engineering practices should be applied for
power-supply decoupling. Decoupling capacitors should be
placed as close as possible to package pins. If a separate analog
power supply is not available, we recommend the circuit shown
in Figure 35 for using a single +5 V supply. Ferrite beads suffice
for the inductors shown (typically 600 Ω at 100 MHz). T his
circuitry should be as close to the supply pins as is practical.
1F
R_OUT
47k⍀
Figure 30. Line Output Connections
A circuit for headphone drive is illustrated in Figure 31. Drive is
supplied by +5 V operational amps. T he circuit shown ac
couples the headphones to the line output.
FB
+5V
SUPPLY
+
–
0.1F
10F
0.1F
0.1F
0.1F
0.1F
8.66k⍀
10k⍀
L_OUT
V
V
HEADPHONE
LEFT
DD
DD
+
470F
10F
–
V_REF
R_OUT
SSM-2135
V
HEADPHONE
RIGHT
DD
10k⍀
FB
470F
+
10F
0.1F
–
0.1F
8.66k⍀
Figure 31. Headphone Drive Connections
V
V
CC
CC
Figure 32 illustrates reference bypassing. VREF_F should only be
connected to its bypass capacitors.
Figure 35. Recom m ended Power Supply Bypassing
V
V
GRO UND ING AND LAYO UT
REF_F
REF
1.0µF
10µF
10µF
Analog Devices recommends a split ground plane as shown in
Figure 36. T he analog plane and the digital plane are connected
directly under the AD1845. Splitting the ground plane directly
under the SoundPort Codec is optimal because analog pins will
be located above the analog ground plane and digital pins will
be located directly above the digital ground plane for the best
isolation.
Figure 32. Voltage Reference Bypassing
Figure 33 illustrates signal-path filtering capacitors, L_FILT
and R_FILT . T he AD1845 must use 1.0 µF capacitors; the
AD1845 will not perform properly with 1000 pF capacitors.
T he 1.0 µF capacitors required by the AD1845 can be of any
type.
Other schemes may also yield satisfactory results. If the split
ground plane recommended here is not possible, the AD1845
should be entirely over the analog ground plane with the op-
tional 74_245 transceiver over the digital plane.
L_FILT
R_FILT
Some manufacturers of compatible devices differentiate between
digital supply pins used to power internal logic and digital sup-
ply pins used to power the ISA bus driver. T heir recommended
layout suggests connecting the internal logic supply pins to the
analog supply. A potential problem can occur if the layout con-
nects digital supply pins to the analog supply. Connecting some
of the digital supply pins to one supply and some of the digital
supply pins to a different supply can create an internal short
between the two different +5 V supplies.
1.0µF
1.0µF
Figure 33. External Filter Capacitor Connections
T he crystal shown in the crystal connection circuitry of Fig-
ure 34 should be 24.576 MHz, fundamental-mode and parallel-
tuned. Note that using the exact data sheet frequencies is not
required and that external clock sources can be used to over-
drive the AD1845’s internal oscillators. (See the description of
the CFS2:0 control bits above.) If using an external clock source,
apply it to the crystal input pins while leaving the crystal output
pins unconnected. Attention should be paid to providing low
jitter external input clocks.
REV. C
–35–
AD1845
3. T he CS4231 does not require the power pins (VDD) 24,
45, and 54, or the ground pins (GNDD) 25, and 44. It is
suggested that the appropriate power/ground pin connec-
tions be made. T his will not affect the performance of the
CS4231.
Analog Devices recommends that all digital pins be driven from
the same supply. A common technique to achieve maximum
performance is to use a +5 V regulator to power the analog side
of the codec from the PCs +12 V supply line, while the standard
PC +5 V supply line powers the entire digital side of the codec.
T he separate supplies provide noise isolation for the analog side
of the codec, and maximize performance of the AD1845.
4. T he CS4231 does not provide software programmable
power-down modes.
5. T he CS4231 does not have the ability to mix the MIC
input with the DAC output.
DIGITAL
GROUND
PLANE
ANALOG
GROUND
PLANE
DIGITAL
GROUND
PLANE
ANALOG
GROUND
PLANE
NC NC
52 51
GNDD R_AUX2
44 43
6. T he CS4231 does not contain a Variable Sample Fre-
quency Generator and cannot change sample rates “on the
fly.” T he CS4231 and CS4248 require entering MCE to
change the sample rate. T he AD1845 can change the
sample rate without entering MCE. T he AD1845’s 50,000
selectable sample rates are not available on the CS4231.
T he Variable Sample Frequency Generator reduces clicks
and pops encountered in many game applications.
AD1845
PLCC
AD1845
TQFP
25 26
GNDD R_FILT
24 25
NC R_FILT
Figure 36. Recom m ended Ground Plane
CO MP ATIBILITY WITH CS4231
1. T he CS4231 requires a 1000 pF NPO type capacitor on
Pins 26 and 31. T he AD1845 requires a 1 µF capacitor on
filter Pins 26 and 31. T o achieve compatibility with the
AD1845, use pad spacing that will accommodate either
1000 pF NPO capacitors for the CS4231 and the CS4248
or the 1 µF capacitors for the AD1845.
7. T he CS4231 requires two crystal inputs, 24.575 MHz and
16.9344 MH z. T he AD1845 requires only one input of
24.576 MH z or can be driven from OSC or other exter-
nal clocks.
8. T he CS4231 does not contain the INIT D bit.
9. T he CS4231 minimum RIN = 20 kΩ. T he AD1845 mini-
mum input resistance is 10 kΩ.
2. T he AD1845 requires the input antialiasing filters for the
ADCs (refer to Figures 27 and 28). T he CS4231 can use
the same filters with no degradation in performance. For
compatibility it is suggested that the filters be added.
10. T he AD1845 does not include hardware for compressing
and decompressing ADPCM data. Analog Devices offers
Windows based software applets for using ADPCM for-
mats with the AD1845.
REV. C
–36–
AD1845
FREQ UENCY RESP O NSE P LO TS
10
0
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–10
–20
–30
–40
–50
dB
dB
–60
–70
–80
–90
–100
–110
–120
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
SAMPLE FREQUENCY – FS
SAMPLE FREQUENCY – F
S
Figure 39. Digital-to-Analog Frequency
Response to FS (Full-Scale Inputs, 0 dB)
Figure 37. Analog-to-Digital Frequency Response
to FS (Full-Scale Line-Level Inputs, 0 dB)
10
0
10
0
–10
–20
–30
–40
–10
–20
–30
–40
–50
–60
–50
dB
dB
–60
–70
–70
–80
–90
–80
–90
–100
–100
–110
–120
–110
–120
0.40
0.44
0.48
0.52
0.56
0.60
0.64
0.68 0.70
0.40
0.44
0.48
0.52
0.56
0.60
0.64
0.68 0.70
SAMPLE FREQUENCY – FS
SAMPLE FREQUENCY – FS
Figure 40. Digital-to-Analog Frequency Response
—Transition Band (Full-Scale Inputs, 0 dB)
Figure 38. Analog-to-Digital Frequency Response
—Transition Band (Full-Scale Line-Level Inputs, 0 dB)
REV. C
–37–
AD1845
AP P END IX
EXTEND ED TEMP ERATURE SP ECIFICATIO NS
Test Conditions
T he AD1845 has been tested over the industrial temperature range. T he typical values represent the limits that change with tempera-
ture. All other limits remain unchanged.
T emperature
Digital Supply (VDD
Analog Supply (VCC
Sample Rate (FS
Input Signal
Analog Output Passband
–40°C to +85°C
5.0 V
5.0 V
DAC T est Conditions
Calibrated
)
)
0 dB Attenuation
16-Bit Linear Mode
Mute Off, OL = 0
)
48 kHz
1008 Hz
20 Hz to 20 kHz
2.0 V
VIH
VIL
ADC Input Conditions
Calibrated
0.8 V
VOH
VOL
2.4 V
0.4 V
0 dB Gain
–1.0 dB Relative to Full Scale
Line Input
16-Bit Linear Mode
P RO GRAMMABLE GAIN AMP LIFIER—AD C
P aram eter
Min
Typ
Max
Max
Units
Step Size (All Steps T ested) (0 dB to 22.5 dB)
PGA Gain Range Span
1.75
22.83
dB
dB
AUXILIARY, LINE, MO NO , AND MICRO P H O NE INP UT
ANALO G GAIN/AMP LIFIERS/ATTENUATO RS
P aram eter
Min
Typ
Units
Step Size AUX1, AUX2, LINE, MIC (All Steps T ested):
(+12 dB to –34.5 dB, Referenced to DAC Full Scale)
Step Size: M_IN (All Steps T ested) (0 dB to –45 dB)
Input Gain/Attenuation Range: AUX1, AUX2, LINE, MIC
Input Gain/Attenuation Range: M_IN
1.5
3.0
46.2
43.5
dB
dB
dB
dB
ANALO G-TO -D IGITAL CO NVERTERS
P aram eter
Min
Min
Typ
Max
Max
Units
Dynamic Range (–60 dB Input T HD+N Referenced to
Full Scale, A-Weighted)
T HD+N (Referenced to Full Scale)
–81
–76
dB
dB
D IGITAL-TO -ANALO G CO NVERTERS
P aram eter
Typ
Units
Dynamic Range (–60 dB Input T HD+N Referenced to
Full Scale, A-Weighted)
T HD+N (Referenced to Full Scale)
–82
–78
dB
dB
D AC ATTENUATO R
P aram eter
Min
Min
Typ
Max
Max
Units
Step Size (0 dB to –22.5 dB)
–1.5
dB
ANALO G O UTP UT
P aram eter
Typ
Units
VREF
2.36
V
REV. C
–38–
AD1845
TABLE O F CO NTENTS
Control and Programmed I/O (PIO) T ransfers . . . . . . . . . . . 29
DIRECT MEMORY ACCESS (DMA) T RANSFERS . . . . . . . 30
Single-Channel DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Dual-Channel DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DMA T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DMA Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
POWER-UP AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ADVANCED POWER-DOWN MODES . . . . . . . . . . . . . . . . . 32
AUT OCALIBRAT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CHANGING SAMPLE RAT ES . . . . . . . . . . . . . . . . . . . . . . . . 33
APPLICAT IONS CIRCUIT S . . . . . . . . . . . . . . . . . . . . . . . . . 34
GROUNDING AND LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . 35
COMPAT IBILIT Y WIT H CS4231 . . . . . . . . . . . . . . . . . . . . . 36
FREQUENCY RESPONSE PLOT S . . . . . . . . . . . . . . . . . . . . 37
APPENDIX—EXT ENDED T EMPERAT URE
PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Expanded Mode (MODE2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN DESIGNAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN FUNCT ION DESCRIPT IONS . . . . . . . . . . . . . . . . . . . . . 7
FUNCT IONAL DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . 10
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Analog Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Analog-to-Digital Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Digital-to-Analog Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Digital Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Digital Data T ypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
T imer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Supplies and Voltage Reference . . . . . . . . . . . . . . . . . 11
Clocks and Sample Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CONT ROL REGIST ERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Control Register Architecture . . . . . . . . . . . . . . . . . . . . . . . . 11
Direct Control Register Definitions . . . . . . . . . . . . . . . . . . . . 14
Index Address Register (ADR1:0 = 0) . . . . . . . . . . . . . . . . 14
Indexed Data Register (ADR1:0 = 1) . . . . . . . . . . . . . . . . . 14
Status Register (ADR1:0 = 2) . . . . . . . . . . . . . . . . . . . . . . 15
PIO Data Registers (ADR1:0 = 3) . . . . . . . . . . . . . . . . . . . 16
Indirect Control Register Definitions . . . . . . . . . . . . . . . . . . . 16
Left Input Control (IXA3:0 = 0) . . . . . . . . . . . . . . . . . . . . 16
Right Input Control (IXA3:0 = 1) . . . . . . . . . . . . . . . . . . . 16
Left Aux # 1 Input Control (IXA3:0 = 2) . . . . . . . . . . . . . . 17
Right Aux # 1 Input Control (IXA3:0 = 3) . . . . . . . . . . . . . 17
Left Aux # 2 Input Control (IXA3:0 = 4) . . . . . . . . . . . . . . 17
Right Aux # 2 Input Control (IXA3:0 = 5) . . . . . . . . . . . . . 17
Left DAC Control (IXA3:0 = 6) . . . . . . . . . . . . . . . . . . . . 18
Right DAC Control (IXA3:0 = 7) . . . . . . . . . . . . . . . . . . . 18
Clock and Data Format (IXA3:0 = 8) . . . . . . . . . . . . . . . . 19
Interface Configuration (IXA3:0 = 9) . . . . . . . . . . . . . . . . . 20
Pin Control (IXA3:0 = 10) . . . . . . . . . . . . . . . . . . . . . . . . . 20
T est and Initialization (IXA3:0 = 11) . . . . . . . . . . . . . . . . . 21
Miscellaneous Control (IXA3:0 = 12) . . . . . . . . . . . . . . . . 21
Digital Mix/Attenuation Control (IXA3:0 = 13) . . . . . . . . 22
DMA Playback Base Count . . . . . . . . . . . . . . . . . . . . . . . . 22
Upper Base Count (IXA3:0 = 14) . . . . . . . . . . . . . . . . . 22
Lower Base Count (IXA3:0 = 15) . . . . . . . . . . . . . . . . . . 23
Alternate Feature Enable /Left MIC Input Control
(IXA3:0 =16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MIC Mix Enable/Right MIC Input Control (IXA3:0 = 17) . 23
Left Line Gain, Attenuate, Mute, Mix (IXA3:0 = 18) . . . . 23
Right Line Gain, Attenuate, Mute, Mix (IXA3:0 = 19) . . . 24
Lower T imer Bits (IXA3:0 = 20) . . . . . . . . . . . . . . . . . . . . 24
Upper T imer Bits (IXA3:0 = 21) . . . . . . . . . . . . . . . . . . . . 25
Upper Frequency Select (IXA3:0 = 22) . . . . . . . . . . . . . . . 25
Lower Frequency Select (IXA3:0 = 23) . . . . . . . . . . . . . . . 25
Capture Playback T imer (IXA3:0 = 24) . . . . . . . . . . . . . . . 25
Revision ID (IXA3:0 = 25) . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mono Control (IXA3:0 = 26) . . . . . . . . . . . . . . . . . . . . . . . 26
Power-Down Control (IXA3:0 = 27) . . . . . . . . . . . . . . . . . 27
Capture Data Format Control (IXA3:0 = 28) . . . . . . . . . . 27
Crystal, Clock Select/T otal Power-Down (IXA3:0 = 29) . . 27
Capture Upper Base Count (IXA3:0 = 30) . . . . . . . . . . . . 28
Capture Lower Base Count (IXA3:0 = 31) . . . . . . . . . . . . 28
DAT A AND CONT ROL T RANSFERS . . . . . . . . . . . . . . . . . 29
Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Data Bus Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PACKAGE OUT LINE DIMENSIONS . . . . . . . . . . . . . . . . . . 40
FIGURES TABLE O F CO NTENTS
1. Interface to ISA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2. µ-Law or A-Law Expansion . . . . . . . . . . . . . . . . . . . . . . . . 11
3. µ-Law or A-Law Compression . . . . . . . . . . . . . . . . . . . . . . 11
4. Direct Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. Indirect Register Map and Reset/Default States . . . . . . . . . 12
6. Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7. Mix Gain Level Setting: DAC . . . . . . . . . . . . . . . . . . . . . . . 18
8. MODE1 Audio Sample Frequency Select . . . . . . . . . . . . . . 19
9. Digital Audio Data T ype . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10. Mix Gain Level Setting: AUX1, AUX2, MIC, LINE . . . . . 24
11. Mono Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12. Capture Audio Data T ype . . . . . . . . . . . . . . . . . . . . . . . . . 27
13. Input Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . 28
14. 8-Bit Mono Data Stream Sequencing . . . . . . . . . . . . . . . . . 29
15. 8-Bit Stereo Data Stream Sequencing . . . . . . . . . . . . . . . . . 29
16. 16-Bit Mono Data Stream Sequencing, Little Endian . . . . 29
17. 16-Bit Stereo Data Stream Sequencing, Little Endian . . . . 29
18. 16-Bit Mono Data Stream Sequencing, Big Endian . . . . . . 29
19. 16-Bit Stereo Data Stream Sequencing, Big Endian . . . . . . 29
20. Control Register/PIO Read Cycle . . . . . . . . . . . . . . . . . . . . 30
21. Control Register/PIO Write Cycle . . . . . . . . . . . . . . . . . . . 30
22. 8-Bit Mono DMA Read/Capture Cycle . . . . . . . . . . . . . . . 31
23. 8-Bit Mono DMA Write/Playback Cycle . . . . . . . . . . . . . . 31
24. 8-Bit Stereo or 16-Bit Mono DMA Cycle . . . . . . . . . . . . . . 31
25. 16-Bit Stereo DMA Interrupt . . . . . . . . . . . . . . . . . . . . . . . 31
26. Advanced Power-Down Mode Summary . . . . . . . . . . . . . . 32
27. 2 V rms Line-Level Input Circuit for LINE Inputs . . . . . . . 34
28. 2 V rms Line-Level Input Circuit for M_IN and
AUX Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
29. “Phantom Powered” Microphone Input Circuit . . . . . . . . . 34
30. Line Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 35
31. Headphone Drive Connections . . . . . . . . . . . . . . . . . . . . . . 35
32. Voltage Reference Bypassing . . . . . . . . . . . . . . . . . . . . . . . . 35
33. External Filter Capacitor Connections . . . . . . . . . . . . . . . . 35
34. Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
35. Recommended Power Supply Bypassing . . . . . . . . . . . . . . . 35
36. Recommended Ground Plane . . . . . . . . . . . . . . . . . . . . . . . 36
37. Analog-to-Digital Frequency Response to FS (Full-Scale
Line-Level Inputs, 0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . 37
38. Analog-to-Digital Frequency Response—T ransition Band
(Full-Scale Line-Level Inputs, 0 dB) . . . . . . . . . . . . . . . . . 37
39. Digital-to-Analog Frequency Response to F S (Full-Scale
Inputs, 0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
40. Digital-to-Analog Frequency Response—T ransition Band
(Full-Scale Inputs, 0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . 37
REV. C
–39–
AD1845
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
68-Lead P lastic Leaded Chip Car r ier
(P -68A)
0.175 (4.45)
0.995 (25.27)
0.885 (22.48)
0.169 (4.29)
SQ
9
61
60
10
PIN 1
0.050
(1.27)
TYP
IDENTIFIER
0.925 (23.50)
0.895 (22.73)
TOP VIEW
(PINS DOWN)
0.019 (0.48)
0.017 (0.43)
0.029 (0.74)
0.027 (0.69)
26
44
43
27
0.954 (24.23)
0.950 (24.13)
SQ
0.104 (2.64) TYP
100-Lead Thin Q uad Flatpack
(ST-100)
0.640 (16.25)
SQ
SQ
0.620 (15.75)
0.553 (14.05)
0.549 (13.95)
0.057 (1.45)
0.053 (1.35)
0.030 (0.75)
0.020 (0.50)
100
1
76
75
12°
TYP
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.004
(0.102)
MAX LEAD
25
51
50
26
COPLANARITY
6° ± 4°
0° – 7°
0.006 (0.15)
0.002 (0.05)
0.020 (0.50)
BSC
0.011 (0.27)
0.007 (0.17)
REV. C
–40–
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