5962-8853901EA [ADI]
Precision Instrumentation Amplifier; 精密仪表放大器器
| 型号： | 5962-8853901EA |
| 厂家： | 
ADI |
| 描述： | Precision Instrumentation Amplifier |
| 文件： | 总16页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision
a
Instrumentation Amplifier
AD524
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Low Noise: 0.3 V p-p 0.1 Hz to 10 Hz
Low Nonlinearity: 0.003% (G = 1)
High CMRR: 120 dB (G = 1000)
PROTECTION
–INPUT
4.44k⍀
AD524
Low Offset Voltage: 50 V
G = 10
G = 100
404⍀
Low Offset Voltage Drift: 0.5 V/؇C
Gain Bandwidth Product: 25 MHz
Pin Programmable Gains of 1, 10, 100, 1000
Input Protection, Power On–Power Off
No External Components Required
Internally Compensated
V
b
20k⍀
40⍀
SENSE
G = 1000
20k⍀
20k⍀
20k⍀
20k⍀
RG
1
V
OUT
RG
2
20k⍀
REFERENCE
MIL-STD-883B and Chips Available
16-Lead Ceramic DIP and SOIC Packages and
20-Terminal Leadless Chip Carriers Available
Available in Tape and Reel in Accordance
with EIA-481A Standard
+INPUT
PROTECTION
Standard Military Drawing Also Available
PRODUCT HIGHLIGHTS
PRODUCT DESCRIPTION
1. The AD524 has guaranteed low offset voltage, offset voltage
drift and low noise for precision high gain applications.
The AD524 is a precision monolithic instrumentation amplifier
designed for data acquisition applications requiring high accu-
racy under worst-case operating conditions. An outstanding
combination of high linearity, high common mode rejection, low
offset voltage drift and low noise makes the AD524 suitable for
use in many data acquisition systems.
2. The AD524 is functionally complete with pin programmable
gains of 1, 10, 100 and 1000, and single resistor program-
mable for any gain.
3. Input and output offset nulling terminals are provided for
very high precision applications and to minimize offset volt-
age changes in gain ranging applications.
The AD524 has an output offset voltage drift of less than 25 µV/°C,
input offset voltage drift of less than 0.5 µV/°C, CMR above
90 dB at unity gain (120 dB at G = 1000) and maximum non-
linearity of 0.003% at G = 1. In addition to the outstanding dc
specifications, the AD524 also has a 25 kHz gain bandwidth
product (G = 1000). To make it suitable for high speed data
acquisition systems the AD524 has an output slew rate of 5 V/µs
and settles in 15 µs to 0.01% for gains of 1 to 100.
4. The AD524 is input protected for both power-on and power-
off fault conditions.
5. The AD524 offers superior dynamic performance with a gain
bandwidth product of 25 MHz, full power response of 75 kHz
and a settling time of 15 µs to 0.01% of a 20 V step (G = 100).
As a complete amplifier the AD524 does not require any exter-
nal components for fixed gains of 1, 10, 100 and 1000. For
other gain settings between 1 and 1000 only a single resistor is
required. The AD524 input is fully protected for both power-on
and power-off fault conditions.
The AD524 IC instrumentation amplifier is available in four
different versions of accuracy and operating temperature range.
The economical “A” grade, the low drift “B” grade and lower
drift, higher linearity “C” grade are specified from –25°C to
+85°C. The “S” grade guarantees performance to specification
over the extended temperature range –55°C to +125°C. Devices
are available in 16-lead ceramic DIP and SOIC packages and a
20-terminal leadless chip carrier.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(@ V = ؎15 V, R = 2 k⍀ and T = +25؇C unless otherwise noted)
AD524–SPECIFICATIONS
S
L
A
AD524A
Typ
AD524B
Typ
AD524C
Typ
AD524S
Typ
Model
Min
Max
Min
Max
Min
Max
Min
Max
Units
GAIN
Gain Equation
(External Resistor Gain
Programming)
40, 000
40, 000
40, 000
40, 000
+ 1 ± 20%
+ 1 ± 20%
+ 1 ± 20%
+ 1 ± 20%
R
R
R
R
G
G
G
G
Gain Range (Pin Programmable)
Gain Error1
G = 1
1 to 1000
1 to 1000
1 to 1000
1 to 1000
؎0.05
؎0.25
؎0.5
؎0.03
؎0.02
؎0.05
%
%
%
%
G = 10
؎0.15
؎0.35
؎1.0
؎0.1
؎0.25
؎0.5
؎0.25
؎0.5
؎2.0
G = 100
G = 1000
Nonlinearity
G = 1
G = 10,100
G = 1000
±2.0
±0.01
±0.01
±0.01
± 0.005
± 0.005
± 0.01
± 0.003
± 0.003
± 0.01
± 0.01
± 0.01
± 0.01
%
%
%
Gain vs. Temperature
G = 1
5
5
5
5
ppm/°C
ppm/°C
ppm/°C
ppm/°C
G = 10
15
35
100
10
25
50
10
25
50
10
25
50
G = 100
G = 1000
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage
vs. Temperature
Output Offset Voltage
vs. Temperature
Offset Referred to the
Input vs. Supply
G = 1
250
2
100
0.75
3
50
100
2.0
3.0
50
µV
0.5
2.0
25
µV/°C
mV
5
100
50
µV/°C
70
75
80
75
dB
dB
dB
dB
G = 10
85
95
100
110
115
95
G = 100
G = 1000
95
100
105
110
105
110
INPUT CURRENT
Input Bias Current
vs. Temperature
Input Offset Current
vs. Temperature
؎50
؎35
؎25
؎15
؎15
؎10
؎50
؎35
nA
±100
±100
±100
±100
± 100
± 100
± 100
± 100
pA/°C
nA
pA/°C
INPUT
Input Impedance
Differential Resistance
Differential Capacitance
Common-Mode Resistance
Common-Mode Capacitance
109
10
109
10
109
10
109
10
Ω
pF
Ω
109
10
109
10
109
10
109
10
pF
Input Voltage Range
Max Differ. Input Linear (VDL
2
)
±10
±10
± 10
± 10
V
V
G
2
G
2
G
2
G
2
Max Common-Mode Linear (VCM
)
12 V –
× VD
12 V –
× VD
12 V –
× VD
12 V –
× VD
Common-Mode Rejection dc to
60 Hz with 1 kΩ Source Imbalance
G = 1
70
90
100
110
75
95
105
115
80
70
90
100
110
dB
dB
dB
dB
G = 10
G = 100
G = 1000
100
110
120
OUTPUT RATING
VOUT, RL = 2 kΩ
±10
±10
± 10
± 10
V
DYNAMIC RESPONSE
Small Signal – 3 dB
G = 1
1
1
1
1
MHz
kHz
kHz
kHz
V/µs
G = 10
400
150
25
400
150
25
400
150
25
400
150
25
G = 100
G = 1000
Slew Rate
5.0
5.0
5.0
5.0
Settling Time to 0.01%, 20 V Step
G = 1 to 100
G = 1000
15
75
15
75
15
75
15
75
µs
µs
NOISE
Voltage Noise, 1 kHz
R.T.I.
R.T.O.
7
90
7
90
7
90
7
90
nV/√Hz
nV√Hz
R.T.I., 0.1 Hz to 10 Hz
G = 1
15
2
15
2
15
2
15
2
µV p-p
µV p-p
µV p-p
G = 10
G = 100, 1000
Current Noise
0.1 Hz to 10 Hz
0.3
0.3
0.3
0.3
60
60
60
60
pA p-p
REV. E
–2–
AD524
AD524A
Typ
AD524B
Typ
AD524C
Typ
AD524S
Typ
Model
Min
Max
Min
Max
Min
Max
Min
Max
Units
SENSE INPUT
RIN
20
15
20
15
20
15
20
15
kΩ ±20%
IIN
µA
V
%
Voltage Range
Gain to Output
±10
±10
±10
±10
l
l
1
l
REFERENCE INPUT
RIN
40
15
40
15
40
15
40
15
kΩ ±20%
IIN
µA
V
%
Voltage Range
Gain to Output
±10
±10
10
10
l
1
l
1
TEMPERATURE RANGE
Specified Performance
Storage
–25
–65
+85
+150
–25
–65
+85
+150
–25
–65
+85
+150
–55
–65
+125
+150
°C
°C
POWER SUPPLY
Power Supply Range
Quiescent Current
؎6
±15
3.5
؎18
5.0
؎6
±15
3.5
؎18
5.0
؎6
±15
3.5
؎18
5.0
؎6
±15
3.5
؎18
5.0
V
mA
NOTES
1Does not include effects of external resistor RG.
2VOL is the maximum differential input voltage at G = 1 for specified nonlinearity.
VDL at the maximum = 10 V/G.
VD = Actual differential input voltage.
Example: G = 10, VD = 0.50.
VCM = 12 V – (10/2 × 0.50 V) = 9.5 V.
Specification subject to change without notice.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to
calculate outgoing quality levels.
REV. E
–3–
AD524
ABSOLUTE MAXIMUM RATINGSl
CONNECTION DIAGRAMS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 450 mW
Input Voltage2
Ceramic (D) and
SOIC (R) Packages
(Either Input Simultaneously) |VIN| + |VS| . . . . . . . . <36 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range
(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
(D, E) . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD524A/B/C . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
AD524S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature (Soldering 60 secs) . . . . . . . . . . . . +300°C
16
15
14
13
12
11
1
2
3
4
5
6
7
8
RG
– INPUT
+ INPUT
1
OUTPUT NULL
OUTPUT NULL
G = 10
RG
2
AD524
TOP VIEW
(Not to Scale)
INPUT NULL
INPUT NULL
REFERENCE
SHORT TO
RG FOR
2
G = 100
DESIRED
GAIN
G = 1000
10 SENSE
–V
S
+V
S
9
OUTPUT
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
4
5
15
14
–V
S
+V
S
INPUT
OFFSET NULL
OUTPUT
OFFSET NULL
2Max input voltage specification refers to maximum voltage to which either input
terminal may be raised with or without device power applied. For example, with ±18
volt supplies max VIN is ±18 volts, with zero supply voltage max VIN is ±36 volts.
Leadless Chip Carrier
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
OUTPUT
NULL G = 10 G = 100 G = 1000
14
SENSE
10
3
1 20 19
2
11
13
12
OUTPUT
NULL
18
17
16
15
14
4
5
6
7
8
RG
OUTPUT NULL
G = 10
2
15
OUTPUT
9
8
INPUT NULL
NC
INPUT NULL
SHORT TO
AD524
TOP VIEW
RG FOR
2
NC
RG 16
1
+V
S
DESIRED
GAIN
G = 100
G = 1000
REFERENCE
0.103
(2.61)
9
10 11 12 13
–INPUT
1
2
NC = NO CONNECT
+INPUT
7 –V
S
RG
2
3
7
5
19
18
5
4
6
–V
S
+V
S
INPUT
NULL
INPUT
NULL
REFERENCE
INPUT
OFFSET NULL
OUTPUT
OFFSET NULL
0.170 (4.33)
PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE
D-16 AND R-16 16-PIN CERAMIC PACKAGES.
ORDERING GUIDE
Package Descriptions
16-Lead Ceramic DIP
Model
Temperature Ranges
Package Options
AD524AD
AD524AE
AD524AR-16
AD524AR-16-REEL
AD524AR-16-REEL7
AD524BD
AD524BE
AD524CD
AD524SD
AD524SD/883B
5962-8853901EA*
AD524SE/883B
AD524SCHIPS
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
D-16
E-20A
R-16
20-Terminal Leadless Chip Carrier
16-Lead Gull-Wing SOIC
Tape & Reel Packaging 13"
Tape & Reel Packaging 7"
16-Lead Ceramic DIP
20-Terminal Leadless Chip Carrier
16-Lead Ceramic DIP
16-Lead Ceramic DIP
16-Lead Ceramic DIP
16-Lead Ceramic DIP
20-Terminal Leadless Chip Carrier
Die
D-16
E-20A
D-16
D-16
D-16
D-16
E-20A
*Refer to official DESC drawing for tested specifications.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD524 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. E
AD524–Typical Characteristics
20
15
10
5
20
15
10
5
30
20
10
0
+25؇C
0
0
10
100
1k
10k
0
5
10
15
20
0
5
10
15
20
SUPPLY VOLTAGE – ؎V
SUPPLY VOLTAGE – ؎V
LOAD RESISTANCE – ⍀
Figure 2. Output Voltage Swing vs.
Supply Voltage
Figure 1. Input Voltage Range vs.
Supply Voltage, G = 1
Figure 3. Output Voltage Swing vs.
Load Resistance
16
14
12
10
8
8.0
6.0
4.0
2.0
0
40
30
20
10
0
6
–10
–20
–30
–40
4
2
0
0
5
10
15
20
0
5
10
15
20
–75
–25
25
75
125
SUPPLY VOLTAGE – ؎V
TEMPERATURE – ؇C
SUPPLY VOLTAGE – ؎V
Figure 5. Input Bias Current vs.
Supply Voltage
Figure 4. Quiescent Current vs.
Supply Voltage
Figure 6. Input Bias Current vs.
Temperature
16
14
12
10
8
0
1
2
3
4
5
6
1000
100
10
6
1
4
2
0
0
5
10
15
20
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
WARM-UP TIME – Minutes
0
10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz
INPUT VOLTAGE – ؎V
Figure 9. Gain vs. Frequency
Figure 7. Input Bias Current vs. Input
Voltage
Figure 8. Offset Voltage, RTI, Turn
On Drift
–5–
REV. E
AD524
30
20
10
0
–140
10.0
8.0
G = 1000
G = 100
–120
–100
–80
–60
–40
–20
0
G = 1, 10, 100
G = 10
G = 1
6.0
4.0
G = 1000
2.0
0
BANDWIDTH LIMITED
G100 G10
G1000
10k
1k
100k
FREQUENCY – Hz
1M
1
10
100
1000
0
10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz
GAIN – V/V
Figure 11. Large Signal Frequency
Response
Figure 12. Slew Rate vs. Gain
Figure 10. CMRR vs. Frequency RTI,
Zero to 1k Source Imbalance
1000
160
160
–V = –15V dc +
S
1V p-p SINEWAVE
+V = 15V dc +
S
140
120
100
80
140
1V p-p SINEWAVE
G = 1
100
120
100
80
G = 10
10
1
G = 100, 1000
60
60
G = 1000
40
40
20
0
20
0
0.1
1
10
100
1k
10k
100k
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
Figure 13. Positive PSRR vs.
Frequency
Figure 15. RTI Noise Spectral
Density vs. Gain
Figure 14. Negative PSRR vs.
Frequency
0.1 – 10Hz
0.1 – 10Hz
100k
10k
1000
100
VERTICAL SCALE; 1 DIVISION = 0.1V
VERTICAL SCALE; 1 DIVISION = 5V
0
1
10
100
1k
10k
FREQUENCY – Hz
Figure 16. Input Current Noise vs.
Frequency
Figure 17. Low Frequency Noise –
G = 1 (System Gain = 1000)
Figure 18. Low Frequency Noise –
G = 1000 (System Gain = 100,000)
–6–
REV. E
AD524
–12 TO +12
–8 TO +8
–4 TO +4
–12 TO +12
–8 TO +8
–4 TO +4
1%
0.1%
0.01%
0.1%
0.01%
1%
OUTPUT
STEP – V
OUTPUT
STEP – V
+4 TO –4
+8 TO –8
+4 TO –4
+8 TO –8
1%
0.1%
0.01%
1%
0.01%
15
0.1%
10
+12 TO –12
+12 TO –12
0
5
10
15
20
0
5
20
SETTLING TIME – s
SETTLING TIME – s
Figure 21. Settling Time Gain = 10
Figure 20. Large Signal Pulse
Response and Settling Time – G =1
Figure 19. Settling Time Gain = 1
–12 TO +12
0.1%
0.01%
1%
–8 TO +8
–4 TO +4
OUTPUT
STEP – V
+4 TO –4
+8 TO –8
1%
0.01%
15
0.1%
10
+12 TO –12
0
5
20
SETTLING TIME – s
Figure 24. Large Signal Pulse
Response and Settling Time
G = 100
Figure 22. Large Signal Pulse
Response and Settling Time
G = 10
Figure 23. Settling Time Gain = 100
–12 TO +12
–8 TO +8
–4 TO +4
1%
0.1% 0.01%
OUTPUT
STEP – V
+4 TO –4
+8 TO –8
1%
0.1% 0.01%
+12 TO –12
0
10 20 30 40 50 60 70 80
SETTLING TIME – s
Figure 25. Settling Time Gain = 1000
Figure 26. Large Signal Pulse Re-
sponse and Settling Time G = 1000
REV. E
–7–
AD524
As RG is reduced to increase the programmed gain, the trans-
conductance of the input preamp increases to the transconduct-
ance of the input transistors. This has three important advantages.
First, this approach allows the circuit to achieve a very high
open loop gain of 3 × 108 at a programmed gain of 1000, thus
reducing gain-related errors to a negligible 30 ppm. Second, the
gain bandwidth product, which is determined by C3 or C4 and
the input transconductance, reaches 25 MHz. Third, the input
voltage noise reduces to a value determined by the collector
current of the input transistors for an RTI noise of 7 nV/√Hz at
G = 1000.
10k⍀
0.01%
10k⍀
0.1%
1k⍀
10T
INPUT
20V p-p
V
OUT
100k⍀
0.1%
+V
S
RG
1
G = 10
G = 100
AD524
11k⍀
0.1%
100⍀
0.1%
1k⍀
0.1%
G = 1000
RG
2
–V
S
Figure 27. Settling Time Test Circuit
INPUT PROTECTION
As interface amplifiers for data acquisition systems, instrumen-
tation amplifiers are often subjected to input overloads, i.e.,
voltage levels in excess of the full scale for the selected gain
range. At low gains, 10 or less, the gain resistor acts as a current
limiting element in series with the inputs. At high gains the
lower value of RG will not adequately protect the inputs from
excessive currents. Standard practice would be to place series
limiting resistors in each input, but to limit input current to
below 5 mA with a full differential overload (36 V) would re-
quire over 7k of resistance which would add 10 nV√Hz of noise.
To provide both input protection and low noise a special series
protect FET was used.
+V
S
I
I
2
1
V
B
50A
50A
R52
A1
A2
C4
20k⍀
SENSE
R53
C3
20k⍀
A3
V
R57
20k⍀
O
CH ,
2
R56
20k⍀
R54
20k⍀
CH , CH
3
4
R55
20k⍀
Q1, Q3
Q2, Q4
–IN
4.44k⍀
REFERENCE
+IN
CH
1
CH , CH ,
2
CH
3
RG
RG
2
1
404⍀
40⍀
4
A unique FET design was used to provide a bidirectional cur-
rent limit, thereby, protecting against both positive and negative
overloads. Under nonoverload conditions, three channels CH2,
CH3, CH4, act as a resistance (≈1 kΩ) in series with the input as
before. During an overload in the positive direction, a fourth
channel, CH1, acts as a small resistance (≈3 kΩ) in series with
the gate, which draws only the leakage current, and the FET
limits IDSS. When the FET enhances under a negative overload,
the gate current must go through the small FET formed by CH1
and when this FET goes into saturation, the gate current is
limited and the main FET will go into controlled enhancement.
The bidirectional limiting holds the maximum input current to
3 mA over the 36 V range.
G100
G1000
I
3
I
4
50A
CH
50A
1
–V
S
Figure 28 Simplified Circuit of Amplifier; Gain Is Defined as
((R56 + R57)/(RG)) + 1. For a Gain of 1, RG Is an Open Circuit
Theory of Operation
The AD524 is a monolithic instrumentation amplifier based on
the classic 3 op amp circuit. The advantage of monolithic con-
struction is the closely matched components that enhance the
performance of the input preamp. The preamp section develops
the programmed gain by the use of feedback concepts. The
programmed gain is developed by varying the value of RG (smaller
values increase the gain) while the feedback forces the collector
currents Q1, Q2, Q3 and Q4 to be constant, which impresses
the input voltage across RG.
INPUT OFFSET AND OUTPUT OFFSET
Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may be
adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an autozero cycle, but there are many small-
signal high-gain applications that don’t have this capability.
+V
S
AD712
+V
s
10
16.2k⍀
100
AD524
1F
DUT
1000
1/2
RG
2
1/2
1F
9.09k⍀
1k⍀
1F
16.2k⍀
1.82k⍀
G1, 10, 100
G1000
–V
–V
S
S
100⍀
1.62M⍀
Figure 29. Noise Test Circuit
–8–
REV. E
AD524
Voltage offset and drift comprise two components each; input
and output offset and offset drift. Input offset is that component
of offset that is directly proportional to gain i.e., input offset as
measured at the output at G = 100 is 100 times greater than at
G = 1. Output offset is independent of gain. At low gains, out-
put offset drift is dominant, while at high gains input offset drift
dominates. Therefore, the output offset voltage drift is normally
specified as drift at G = 1 (where input effects are insignificant),
while input offset voltage drift is given by drift specification at a
high gain (where output offset effects are negligible). All input-
related numbers are referred to the input (RTI) which is to say
that the effect on the output is “G” times larger. Voltage offset
vs. power supply is also specified at one or more gain settings
and is also RTI.
For best results RG should be a precision resistor with a low
temperature coefficient. An external RG affects both gain accuracy
and gain drift due to the mismatch between it and the internal
thin-film resistors. Gain accuracy is determined by the tolerance
of the external RG and the absolute accuracy of the internal resis-
tors (±20%). Gain drift is determined by the mismatch of the
temperature coefficient of RG and the temperature coefficient of
the internal resistors (– 50 ppm/°C typ).
+V
S
–INPUT
RG
1
1.5k⍀
2.105k⍀
AD524
V
OUT
1k⍀
By separating these errors, one can evaluate the total error inde-
pendent of the gain setting used. In a given gain configuration
both errors can be combined to give a total error referred to the
input (R.T.I.) or output (R.T.O.) by the following formula:
RG
REFERENCE
+1 = 20 ؎20%
2
+INPUT
40,000
2.105
G =
–V
S
Figure 31. Operating Connections for G = 20
Total Error R.T.I. = input error + (output error/gain)
The second technique uses the internal resistors in parallel with
an external resistor (Figure 32). This technique minimizes the
gain adjustment range and reduces the effects of temperature
coefficient sensitivity.
Total Error R.T.O. = (Gain × input error) + output error
As an illustration, a typical AD524 might have a +250 µV out-
put offset and a –50 µV input offset. In a unity gain configura-
tion, the total output offset would be 200 µV or the sum of the
two. At a gain of 100, the output offset would be –4.75 mV or:
+250 µV + 100(–50 µV) = –4.75 mV.
+V
S
–INPUT
RG
1
The AD524 provides for both input and output offset adjust-
ment. This simplifies very high precision applications and mini-
mize offset voltage changes in switched gain applications. In
such applications the input offset is adjusted first at the highest
programmed gain, then the output offset is adjusted at G = 1.
G = 10
4k⍀
V
AD524
OUT
RG
REFERENCE
2
+INPUT
40,000
4000||4444.44
G =
+1 = 20 ؎17%
*R|
*R|
*R|
= 4444.44⍀
= 404.04⍀
–V
S
G = 10
GAIN
G = 100
= 40.04⍀
G = 1000
The AD524 has internal high accuracy pretrimmed resistors for
pin programmable gain of 1, 10, 100 and 1000. One of the
preset gains can be selected by pin strapping the appropriate
gain terminal and RG2 together (for G = 1 RG2 is not connected).
*NOMINAL (؎20%)
Figure 32. Operating Connections for G = 20, Low Gain
T.C. Technique
The AD524 may also be configured to provide gain in the out-
put stage. Figure 33 shows an H pad attenuator connected to
the reference and sense lines of the AD524. R1, R2 and R3
should be made as low as possible to minimize the gain variation
and reduction of CMRR. Varying R2 will precisely set the gain
without affecting CMRR. CMRR is determined by the match of
R1 and R3.
INPUT
OFFSET
NULL
+V
S
10k⍀
–INPUT
RG
1
G = 10
G = 100
V
AD524
OUT
G = 1000
RG
2
OUTPUT
SIGNAL
+V
S
+INPUT
R1
2.26k⍀
COMMON
–INPUT
–V
S
RG
1
R2
5k⍀
G = 10
Figure 30. Operating Connections for G = 100
G = 100
V
AD524
OUT
The AD524 can be configured for gains other than those that
are internally preset; there are two methods to do this. The first
method uses just an external resistor connected between pins 3
and 16, which programs the gain according to the formula
G = 1000
RG
R
L
2
R3
2.26k⍀
+INPUT
(R2||40k⍀) + R1 + R3
(R2||40k⍀)
–V
S
G =
(R1 + R2 + R3)||R Ն 2k⍀
L
40k
RG =
Figure 33. Gain of 2000
G = –1
(see Figure 31).
REV. E
–9–
AD524
Although instrumentation amplifiers have differential inputs,
there must be a return path for the bias currents. If this is not
provided, those currents will charge stray capacitances, causing
the output to drift uncontrollably or to saturate. Therefore,
when amplifying “floating” input sources such as transformers
and thermocouples, as well as ac-coupled sources, there must
still be a dc path from each input to ground.
Table I. Output Gain Resistor Values
Nominal
Output
Gain
R2
R1, R3
Gain
2
5
10
5 kΩ
1.05 kΩ
1 kΩ
2.26 kΩ
2.05 kΩ
4.42 kΩ
2.02
5.01
10.1
COMMON-MODE REJECTION
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance. “Common-Mode
Rejection Ratio” (CMRR) is a ratio expression while “Common-
Mode Rejection” (CMR) is the logarithm of that ratio. For
example, a CMRR of 10,000 corresponds to a CMR of 80 dB.
INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the input
transistors of a dc amplifier. Bias currents are an additional
source of input error and must be considered in a total error
budget. The bias currents, when multiplied by the source resis-
tance, appear as an offset voltage. What is of concern in calculat-
ing bias current errors is the change in bias current with respect to
signal voltage and temperature. Input offset current is the differ-
ence between the two input bias currents. The effect of offset
current is an input offset voltage whose magnitude is the offset
current times the source impedance imbalance.
In an instrumentation amplifier, ac common-mode rejection is
only as good as the differential phase shift. Degradation of ac
common-mode rejection is caused by unequal drops across
differing track resistances and a differential phase shift due to
varied stray capacitances or cable capacitances. In many appli-
cations shielded cables are used to minimize noise. This tech-
nique can create common mode rejection errors unless the
shield is properly driven. Figures 35 and 36 shows active data
guards that are configured to improve ac common mode rejec-
tion by “bootstrapping” the capacitances of the input cabling,
thus minimizing differential phase shift.
+V
S
AD524
LOAD
–V
S
TO POWER
SUPPLY
GROUND
+V
S
–INPUT
G = 100
a. Transformer Coupled
100⍀
AD524
V
RG
OUT
2
+V
S
AD711
+INPUT
REFERENCE
–V
S
AD524
Figure 35. Shield Driver, G ≥ 100
LOAD
–V
S
+V
S
TO POWER
SUPPLY
GROUND
–INPUT
RG
AD712
1
100⍀
100⍀
b. Thermocouple
V
AD524
OUT
+V
S
–V
S
REFERENCE
RG
2
+INPUT
–V
S
AD524
Figure 36. Differential Shield Driver
GROUNDING
LOAD
–V
S
Many data acquisition components have two or more ground
pins that are not connected together within the device. These
grounds must be tied together at one point, usually at the sys-
tem power-supply ground. Ideally, a single solid ground would
be desirable. However, since current flows through the ground
wires and etch stripes of the circuit cards, and since these paths
have resistance and inductance, hundreds of millivolts can be
generated between the system ground point and the data
TO POWER
SUPPLY
GROUND
c. AC Coupled
Figure 34. Indirect Ground Returns for Bias Currents
–10–
REV. E
AD524
acquisition components. Separate ground returns should be
provided to minimize the current flow in the path from the sensi-
tive points to the system ground point. In this way supply currents
and logic-gate return currents are not summed into the same
return path as analog signals where they would cause measure-
ment errors.
REFERENCE TERMINAL
The reference terminal may be used to offset the output by up
to ±10 V. This is useful when the load is “floating” or does not
share a ground with the rest of the system. It also provides a
direct means of injecting a precise offset. It must be remem-
bered that the total output swing is ±10 volts to be shared be-
tween signal and reference offset.
Since the output voltage is developed with respect to the poten-
tial on the reference terminal, an instrumentation amplifier can
solve many grounding problems.
When the IA is of the three-amplifier configuration it is neces-
sary that nearly zero impedance be presented to the reference
terminal.
Any significant resistance from the reference terminal to ground
increases the gain of the noninverting signal path, thereby upset-
ting the common-mode rejection of the IA.
DIGITAL P.S.
ANALOG P.S.
+15V –15V
+5V
C
C
In the AD524 a reference source resistance will unbalance the
CMR trim by the ratio of 20 kΩ/RREF. For example, if the refer-
ence source impedance is 1 Ω, CMR will be reduced to 86 dB
(20 kΩ/1 Ω = 86 dB). An operational amplifier may be used to
provide that low impedance reference point as shown in Figure
39. The input offset voltage characteristics of that amplifier will
add directly to the output offset voltage performance of the
instrumentation amplifier.
0.1 0.1
0.1 0.1
1F 1F
1F
F F
F F
DIG
COM
AD583
SAMPLE
AND HOLD
DIGITAL
DATA
OUTPUT
AD524
AD574A
6
*ANALOG
GROUND
OUTPUT
REFERENCE
SIGNAL
GROUND
+V
S
SENSE
*IF INDEPENDENT; OTHERWISE RETURN AMPLIFIER REFERENCE
TO MECCA AT ANALOG P.S. COMMON
V
+
IN
Figure 37. Basic Grounding Practice
AD524
LOAD
REF
V
–
SENSE TERMINAL
IN
The sense terminal is the feedback point for the instrument
amplifier’s output amplifier. Normally it is connected to the
instrument amplifier output. If heavy load currents are to be
drawn through long leads, voltage drops due to current flowing
through lead resistance can cause errors. The sense terminal can
be wired to the instrument amplifier at the load, thus putting
the IxR drops “inside the loop” and virtually eliminating this
error source.
–V
S
V
OFFSET
AD711
Figure 39. Use of Reference Terminal to Provide Output
Offset
An instrumentation amplifier can be turned into a voltage-to-
current converter by taking advantage of the sense and reference
terminals as shown in Figure 40.
V+
(SENSE)
OUTPUT
CURRENT
SENSE
+INPUT
V
+
IN
BOOSTER
R1
X1
AD524
AD524
I
L
V
X
R
L
(REF)
V
–
IN
–INPUT
REF
A2
V–
AD711
LOAD
Figure 38. AD524 Instrumentation Amplifier with Output
Current Booster
V
V
IN
40,000
X
I
=
=
=
(1 +
)
R
G
L
R1
R1
Typically, IC instrumentation amplifiers are rated for a full ±10
volt output swing into 2 kΩ. In some applications, however, the
need exists to drive more current into heavier loads. Figure 38
shows how a high-current booster may be connected “inside the
loop” of an instrumentation amplifier to provide the required
current boost without significantly degrading overall perfor-
mance. Nonlinearities, offset and gain inaccuracies of the buffer
are minimized by the loop gain of the IA output amplifier. Off-
set drift of the buffer is similarly reduced.
Figure 40. Voltage-to-Current Converter
By establishing a reference at the “low” side of a current setting
resistor, an output current may be defined as a function of input
voltage, gain and the value of that resistor. Since only a small
current is demanded at the input of the buffer amplifier A2, the
forced current IL will largely flow through the load. Offset and
drift specifications of A2 must be added to the output offset and
drift specifications of the IA.
REV. E
–11–
AD524
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–IN
+IN
PROTECTION
PROTECTION
OUTPUT
OFFSET
TRIM
G = 100
K2
G = 1000
K3
G = 10
K1
NC
R2
+V
S
10k⍀
INPUT
OFFSET
TRIM
4.44k⍀
404⍀
40⍀
R1
10k⍀
RELAY
SHIELDS
20k⍀
20k⍀
20k⍀
20k⍀
20k⍀
+5V
20k⍀
–V
S
D1
K3
D3
A1
AD524
K1
D2
K2
OUT
+V
S
1F
35V
C2
C1
INPUTS
GAIN
RANGE
A
B
K1 – K3 =
THERMOSEN DM2C
4.5V COIL
ANALOG
COMMON
Y0
Y1
Y2
7407N
D1 – D3 = IN4148
74LS138
DECODER
BUFFER
DRIVER
GAIN TABLE
10F
A
B
GAIN
0
0
1
1
0
1
0
1
10
+5V
1000
100
1
LOGIC
COMMON
NC = NO CONNECT
Figure 41. Three Decade Gain Programmable Amplifier
PROGRAMMABLE GAIN
(+INPUT)
Figure 41 shows the AD524 being used as a software program-
mable gain amplifier. Gain switching can be accomplished with
mechanical switches such as DIP switches or reed relays. It
should be noted that the “on” resistance of the switch in series
with the internal gain resistor becomes part of the gain equation
and will have an effect on gain accuracy.
1
2
3
16
15
14
–IN
+IN
PROTECTION
PROTECTION
OUTPUT
OFFSET
NULL
(–INPUT)
TO –V
+V
S
R2
10k⍀
INPUT
OFFSET
NULL
4.44k⍀
4
10k⍀
5
13
12
11
10
9
20k⍀
20k⍀
20k⍀
404⍀
40⍀
The AD524 can also be connected for gain in the output stage.
Figure 42 shows an AD711 used as an active attenuator in the
output amplifier’s feedback loop. The active attenuation pre-
sents a very low impedance to the feedback resistors, therefore
minimizing the common-mode rejection ratio degradation.
20k⍀
20k⍀
6
7
8
20k⍀
–V
S
AD524
+V
S
V
OUT
1F
35V
20k⍀
10pF
V
V
GND
SS
DD
+V
S
39.2k⍀
28.7k⍀
316k⍀
1k⍀
AD711
1k⍀
1k⍀
–V
S
AD7590
V
A4 WR
A2 A3
DD
Figure 42. Programmable Output Gain
–12–
REV. E
AD524
+V
S
+INPUT
(–INPUT)
PROTECTION
4.44k⍀
+INPUT
1
RG
1
AD524
G = 10 13
G = 100 12
G = 1000 11
G = 10
404⍀
V
G = 100
AD524
b
20k⍀
40⍀
10
G = 1000
RG
20k⍀
20k⍀
20k⍀
2
RG 16
1
V
9
6
–INPUT
OUT
3
RG
2
20k⍀
–V
S
39k⍀
V
REF
–V
S
R3
20k⍀
20k⍀
AD589
+V
S
R5
20k⍀
–INPUT
(+INPUT)
2
PROTECTION
C1
+V
S
MSB
LSB
+V
S
1/2
AD712
1/2
AD712
DATA
INPUTS
R4
10k⍀
OUT1
OUT2
17
3
AD7524
2
1
4
14
7
DAC A
CS
1/2
DATA
INPUTS
DB0
DB7
WR
R6
5k⍀
AD712
256:1
–V
S
CS
15
16
6
AD7528
GND
WR
19
20
DAC A/DAC B
Figure 44. Software Controllable Offset
18
DAC B
5
1/2
AD712
In many applications complex software algorithms for autozero
applications are not available. For those applications Figure 45
provides a hardware solution.
Figure 43. Programmable Output Gain Using a DAC
+V
S
Another method for developing the switching scheme is to use a
DAC. The AD7528 dual DAC, which acts essentially as a pair
of switched resistive attenuators having high analog linearity and
symmetrical bipolar transmission, is ideal in this application.
The multiplying DAC’s advantage is that it can handle inputs of
either polarity or zero without affecting the programmed gain.
The circuit shown uses an AD7528 to set the gain (DAC A) and
to perform a fine adjustment (DAC B).
15 16
RG
1
V
OUT
14
13
AD524
9
10
0.1F LOW
RG
CH
2
LEAKAGE
1k⍀
–V
S
11
12
AD711
AUTOZERO CIRCUITS
In many applications it is necessary to provide very accurate
data in high gain configurations. At room temperature the offset
effects can be nulled by the use of offset trimpots. Over the
operating temperature range, however, offset nulling becomes a
problem. The circuit of Figure 44 show a CMOS DAC operat-
ing in the bipolar mode and connected to the reference terminal
to provide software controllable offset adjustments.
V
DD
V
AD7510KD
SS
GND
A1
A2
A3
A4
200s
ZERO PULSE
Figure 45. Autozero Circuit
REV. E
–13–
AD524
ERROR BUDGET ANALYSIS
In many applications, differential linearity and resolution are of
prime importance. This would be so in cases where the absolute
value of a variable is less important than changes in value. In
these applications, only the irreducible errors (45 ppm = 0.004%)
are significant. Furthermore, if a system has an intelligent pro-
cessor monitoring the A-to-D output, the addition of a auto-
gain/autozero cycle will remove all reducible errors and may
eliminate the requirement for initial calibration. This will also
reduce errors to 0.004%.
To illustrate how instrumentation amplifier specifications are
applied, we will now examine a typical case where an AD524 is
required to amplify the output of an unbalanced transducer.
Figure 46 shows a differential transducer, unbalanced by 100 Ω,
supplying a 0 to 20 mV signal to an AD524C. The output of the
IA feeds a 14-bit A-to-D converter with a 0 to 2 volt input volt-
age range. The operating temperature range is –25°C to +85°C.
Therefore, the largest change in temperature ∆T within the
operating range is from ambient to +85°C (85°C – 25°C = 60°C).
+V
S
+10V
10k⍀
350⍀
350⍀
350⍀
350⍀
RG
1
14-BIT
ADC
0V TO 2V
F.S.
G = 100
AD524C
RG
2
–V
S
Figure 46. Typical Bridge Application
Table II. Error Budget Analysis of AD524CD in Bridge Application
Effect on
Absolute
Accuracy
Effect on
Absolute
Accuracy
Effect
on
AD524C
Error Source
Specifications Calculation
at TA = +25؇C at TA = +85؇C Resolution
Gain Error
Gain Instability
Gain Nonlinearity
Input Offset Voltage
Input Offset Voltage Drift
±0.25%
25 ppm
±0.003%
±50 µV, RTI
±0.5 µV/°C
–
±0.25% = 2500 ppm
(25 ppm/°C)(60°C) = 1500 ppm
±0.003% = 30 ppm
2500 ppm
–
–
2500 ppm
1500 ppm
–
–
–
30 ppm
–
±50 µV/20 mV = ±2500 ppm
(±0.5 µV/°C)(60°C) = 30 µV
30 µV/20 mV = 1500 ppm
±2.0 mV/20 mV = 1000 ppm
(±25 µV/°C)(60°C)= 1500 µV
1500 µV/20 mV = 750 ppm
(±15 nA)(100 Ω) = 1.5 µV
1.5 µV/20 mV = 75 ppm
(±100 pA/°C)(100 Ω)(60°C) = 0.6 µV
0.6 µV/20 mV= 30 ppm
(±10 nA)(100 Ω) = 1 µV
1 µV/20 mV = 50 ppm
(100 pA/°C)(100 Ω)(60°C) = 0.6 µV
0.6 µV/20 mV = 30 ppm
2500 ppm
2500 ppm
–
1500 ppm
1000 ppm
–
–
Output Offset Voltage*
Output Offset Voltage Drift* ±25 µV/°C
±2.0 mV
1000 ppm
–
750 ppm
75 ppm
30 ppm
50 ppm
30 ppm
87.5 ppm
50 ppm
444 ppm
–
–
–
–
–
–
–
–
Bias Current-Source
Imbalance Error
Bias Current-Source
Imbalance Drift
Offset Current-Source
Imbalance Error
Offset Current-Source
Imbalance Drift
Offset Current-Source
Resistance-Error
Offset Current-Source
Resistance-Drift
Common Mode Rejection
5 V dc
±15 nA
75 ppm
±100 pA/°C
±10 nA
–
50 ppm
±100 pA/°C
±10 nA
–
(10 nA)(175 Ω) = 3.5 µV
3.5 µV/20 mV = 87.5 ppm
(100 pA/°C)(175 Ω)(60°C) = 1 µV
1 µV/20 mV = 50 ppm
115 dB = 1.8 ppm × 5 V = 8.8 µV
8.8 µV/20 mV = 444 ppm
87.5 ppm
–
±100 pA/°C
115 dB
444 ppm
Noise, RTI
(0.1 Hz–10 Hz)
0.3 µV p-p
0.3 µV p-p/20 mV = 15 ppm
–
–
15 ppm
45 ppm
Total Error
6656.5 ppm
10516.5 ppm
*Output offset voltage and output offset voltage drift are given as RTI figures.
–14–
REV. E
AD524
Figure 47 shows a simple application, in which the variation of
the cold-junction voltage of a Type J thermocouple-iron(+)–
constantan–is compensated for by a voltage developed in series
by the temperature-sensitive output current of an AD590 semi-
conductor temperature sensor.
and the circuit near 25°C. If resistors with low tempcos are
used, compensation accuracy will be to within ±0.5°C, for
temperatures between +15°C and +35°C. Other thermocouple
types may be accommodated with the standard resistance values
shown in the table. For other ranges of ambient temperature,
the equation in the figure may be solved for the optimum values
of RT and RA.
R
A
REFERENCE
JUNCTION
NOMINAL
VALUE
+V
S
TYPE
7.5V
The microprocessor controlled data acquisition system shown in
Figure 48 includes both autozero and autogain capability. By
dedicating two of the differential inputs, one to ground and one
to the A/D reference, the proper program calibration cycles can
eliminate both initial accuracy errors and accuracy errors over
temperature. The autozero cycle, in this application, converts a
number that appears to be ground and then writes that same
number (8-bit) to the AD7524, which eliminates the zero error
since its output has an inverted scale. The autogain cycle con-
verts the A/D reference and compares it with full scale. A multi-
plicative correction factor is then computed and applied to
subsequent readings.
+15؇C < T < +35؇C
A
J
K
52.3⍀
41.2⍀
61.4⍀
40.2⍀
5.76⍀
I
A
2.5V
T
A
AD580
E
G = 100
+V
V
AD590
CU
T
A
S
S, R
AD524
R
A
IRON
E
O
V
52.3⍀
CONSTANTAN
T
MEASURING
JUNCTION
8.66k⍀
1k⍀
52.3⍀I + 2.5V
–V
S
A
E
= V – V +
T A
– 2.5V
O
R
T
52.3⍀
OUTPUT
AMPLIFIER
OR METER
1 +
R
V
T
NOMINAL VALUE
9135⍀
For a comprehensive study of instrumentation amplifier design
and applications, refer to the Instrumentation Amplifier Applica-
tion Guide, available free from Analog Devices.
Figure 47. Cold-Junction Compensation
The circuit is calibrated by adjusting RT for proper output voltage
with the measuring junction at a known reference temperature
V
REF
AD583
RG
RG
2
AD7507
V
AD524
N
I
AD574A
AGND
1
–V
REF
A0 A2
EN A1
20k⍀
20k⍀
10k⍀
5k⍀
AD7524
1/2
AD712
1/2
AD712
DECODE
LATCH
CONTROL
MICRO-
PROCESSOR
ADDRESS BUS
Figure 48. Microprocessor Controlled Data Acquisition System
REV. E
–15–
AD524
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Ceramic DIP
(D-16)
0.005 (0.13) MIN
16
0.080 (2.03) MAX
9
0.310 (7.87)
0.220 (5.59)
1
8
0.320 (8.13)
0.290 (7.37)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.840 (21.34) MAX
0.200 (5.08)
MAX
0.150
(3.81)
MAX
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
SEATING
PLANE
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.008 (0.20)
20-Terminal Leadless Chip Carrier
(E-20A)
0.200 (5.08)
BSC
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.358 (9.09)
0.100 (2.54) BSC
0.015 (0.38)
0.342 (8.69)
SQ
0.095 (2.41)
0.075 (1.90)
3
MIN
19
20
18
4
0.028 (0.71)
0.358
1
0.011 (0.28)
TOP
VIEW
0.022 (0.56)
(9.09)
MAX
SQ
BOTTOM
VIEW
0.007 (0.18)
R TYP
0.075 (1.91)
REF
0.050 (1.27)
BSC
14
13
8
9
45° TYP
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
0.150 (3.81)
BSC
16-Lead SOIC
(R-16)
0.4133 (10.50)
0.3977 (10.00)
16
9
1
8
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
PIN 1
x 45°
0.0118 (0.30)
0.0040 (0.10)
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
–16–
REV. E
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