5962-8853901EA2 [ADI]
Precision Instrumentation Amplifier; 精密仪表放大器器
| 型号： | 5962-8853901EA2 |
| 厂家： | 
ADI |
| 描述： | Precision Instrumentation Amplifier |
| 文件： | 总28页 (文件大小：614K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision
Instrumentation Amplifier
AD524
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Low noise: 0.3 μV p-p at 0.1 Hz to 10 Hz
Low nonlinearity: 0.003% (G = 1)
High CMRR: 120 dB (G = 1000)
1
PROTECTION
4.44kΩ
404Ω
– INPUT
AD524
13
12
G = 10
Low offset voltage: 50 μV
G = 100
V
Low offset voltage drift: 0.5 μV/°C
Gain bandwidth product: 25 MHz
Pin programmable gains of 1, 10, 100, 1000
Input protection, power-on/power-off
No external components required
Internally compensated
b
20kΩ
20kΩ
40Ω
SENSE
G = 1000 11
RG
20kΩ
20kΩ
20kΩ
16
3
1
2
OUTPUT
RG
20kΩ
REFERENCE
+ INPUT
2
PROTECTION
MIL-STD-883B and chips available
16-lead ceramic DIP and SOIC packages and 20-terminal
leadless chip carrier available
Figure 1.
Available in tape and reel in accordance with EIA-481A
standard
Standard military drawing also available
GENERAL DESCRIPTION
higher linearity C grade are specified from −25°C to +85°C.
The S grade guarantees performance to specification over the
extended temperature range −55°C to +125°C. The AD524 is
available in a 16-lead ceramic DIP, 16-lead SBDIP, 16-lead SOIC
wide packages, and 20-terminal leadless chip carrier.
The AD524 is a precision monolithic instrumentation amplifier
designed for data acquisition applications requiring high accu-
racy under worst-case operating conditions. An outstanding
combination of high linearity, high common-mode rejection,
low offset voltage drift, and low noise makes the AD524 suitable
for use in many data acquisition systems.
PRODUCT HIGHLIGHTS
The AD524 has an output offset voltage drift of less than
25 μV/°C, input offset voltage drift of less than 0.5 μV/°C, CMR
above 90 dB at unity gain (120 dB at G = 1000), and maximum
nonlinearity of 0.003% at G = 1. In addition to the outstanding
dc specifications, the AD524 also has a 25 kHz bandwidth
(G = 1000). To make it suitable for high speed data acquisition
systems, the AD524 has an output slew rate of 5 V/μs and settles
in 15 μs to 0.01% for gains of 1 to 100.
1. The AD524 has guaranteed low offset voltage, offset
voltage drift, and low noise for precision high gain
applications.
2. The AD524 is functionally complete with pin program-
mable gains of 1, 10, 100, and 1000, and single resistor
programmable for any gain.
3. Input and output offset nulling terminals are provided for
very high precision applications and to minimize offset
voltage changes in gain ranging applications.
As a complete amplifier, the AD524 does not require any exter-
nal components for fixed gains of 1, 10, 100 and 1000. For other
gain settings between 1 and 1000, only a single resistor is required.
The AD524 input is fully protected for both power-on and
power-off fault conditions.
4. The AD524 is input protected for both power-on and
power-off fault conditions.
5. The AD524 offers superior dynamic performance with a
gain bandwidth product of 25 MHz, full power response of
75 kHz and a settling time of 15 μs to 0.01% of a 20 V step
(G = 100).
The AD524 IC instrumentation amplifier is available in four
different versions of accuracy and operating temperature range.
The economical A grade, the low drift B grade, and lower drift,
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD524
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Offset and Output Offset................................................ 15
Gain.............................................................................................. 16
Input Bias Currents.................................................................... 17
Common-Mode Rejection........................................................ 17
Grounding................................................................................... 18
Sense Terminal............................................................................ 18
Reference Terminal .................................................................... 18
Programmable Gain................................................................... 20
Autozero Circuits ....................................................................... 20
Error Budget Analysis................................................................ 21
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 25
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 8
Connection Diagrams.................................................................. 8
ESD Caution.................................................................................. 8
Typical Performance Characteristics ............................................. 9
Test Circuits................................................................................. 14
Theory of Operation ...................................................................... 15
Input Protection.......................................................................... 15
REVISION HISTORY
11/07—Rev. E to Rev. F
Updated Format..................................................................Universal
Changes to General Description .................................................... 1
Changes to Figure 1.......................................................................... 1
Changes to Figure 3 and Figure 4 Captions .................................. 8
Changes to Error Budget Analysis Section ................................. 21
Changes to Ordering Guide .......................................................... 25
4/99—Rev. D to Rev. E
Rev. F | Page 2 of 28
AD524
SPECIFICATIONS
@ VS = 15 V, RL = 2 kΩ and TA = +25°C, unless otherwise noted.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at the final electrical
test. Results from those tests are used to calculate outgoing quality levels.
Table 1.
AD524A
Typ
AD524B
Typ
Parameter
Min
Max
Min
Max
Unit
GAIN
Gain Equation (External Resistor Gain Programming)
⎡
⎢
⎣
⎤
⎡
⎢
⎣
⎤
40,000
40,000
+1 ± 20%
+1 ± 20%
⎥
⎥
RG
RG
⎦
⎦
Gain Range (Pin Programmable)
Gain Error1
1 to 1000
1 to 1000
G = 1
G = 10
G = 100
G = 1000
%
%
%
%
±±0±5
±±025
±±05
±±0±ꢀ
±±0.5
±±0ꢀ5
±.0±
±20±
Nonlinearity
G = 1
G = 10, G = 100
G = 1000
0.01
0.01
0.01
0.00ꢀ
0.00ꢀ
0.01
%
%
%
Gain vs. Temperature
G = 1
G = 10
G = 100
G = 1000
ꢀ
ꢀ
ppm/°C
ppm/°C
ppm/°C
ppm/°C
1ꢀ
3ꢀ
100
10
2ꢀ
ꢀ0
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage
vs. Temperature
Output Offset Voltage
vs. Temperature
Offset Referred to the Input vs. Supply
G = 1
μV
25±
2
ꢀ
.±±
±075
ꢀ
μV/°C
mV
μV
100
5±
dB
dB
dB
dB
7±
85
95
.±±
75
95
.±5
..±
G = 10
G = 100
G = 1000
INPUT CURRENT
Input Bias Current
vs. Temperature
Input Offset Current
vs. Temperature
nA
pA/°C
nA
±5±
±ꢀ5
±25
±.5
100
100
100
100
pA/°C
Rev. F | Page 3 of 28
AD524
AD524A
Typ
AD524B
Typ
Parameter
Min
Max
Min
Max
Unit
INPUT
Input Impedance
Differential Resistance
Differential Capacitance
Common-Mode Resistance
Common-Mode Capacitance
Input Voltage Range
Maximum Differential Input Linear (VDL)2
Maximum Common-Mode Linear (VCM
109
10
109
10
Ω
pF
Ω
109
109
10
10
pF
10
10
V
V
2
)
G
2
G
2
⎛
⎜
⎞
⎛
⎜
⎞
.2 V −
× VD
.2 V −
× VD
⎟
⎠
⎟
⎠
⎝
⎝
Common-Mode Rejection DC to 60 Hz with 1 kΩ Source Imbalance
V
G = 1
G = 10
G = 100
G = 1000
dB
dB
dB
dB
7±
9±
.±±
..±
75
95
.±5
..5
OUTPUT RATING
VOUT, RL = 2 kΩ
DYNAMIC RESPONSE
Small Signal – 3 dB
G = 1
G = 10
G = 100
G = 1000
Slew Rate
10
10
V
1
1
MHz
kHz
kHz
kHz
V/μs
400
1ꢀ0
2ꢀ
400
1ꢀ0
2ꢀ
ꢀ.0
ꢀ.0
Settling Time to 0.01%, 20 V Step
G = 1 to 100
G = 1000
1ꢀ
7ꢀ
1ꢀ
7ꢀ
μs
μs
NOISE
Voltage Noise, 1 kHz
RTI
RTO
7
90
7
90
nV/√Hz
nV√Hz
RTI, 0.1 Hz to 10 Hz
G = 1
G = 10
G = 100, 1000
Current Noise
0.1 Hz to 10 Hz
SENSE INPUT
RIN
1ꢀ
2
0.3
1ꢀ
2
0.3
μV p-p
μV p-p
μV p-p
60
60
pA p-p
20
1ꢀ
20
1ꢀ
kΩ 20%
μA
V
IIN
Voltage Range
Gain to Output
REFERENCE INPUT
RIN
10
10
10
10
1
1
%
40
1ꢀ
40
1ꢀ
kΩ 20%
μA
V
IIN
Voltage Range
Gain to Output
1
1
%
Rev. F | Page 4 of 28
AD524
AD524A
Typ
AD524B
Typ
Parameter
Min
Max
Min
Max
Unit
TEMPERATURE RANGE
Specified Performance
Storage
–2ꢀ
–6ꢀ
+8ꢀ
+1ꢀ0
–2ꢀ
–6ꢀ
+8ꢀ
+1ꢀ0
°C
°C
POWER SUPPLY
Power Supply Range
Quiescent Current
1ꢀ
3.ꢀ
1ꢀ
3.ꢀ
V
mA
±ꢁ
±.8
50±
±ꢁ
±.8
50±
1 Does not include effects of external resistor, RG.
2 VOL is the maximum differential input voltage at G = 1 for specified nonlinearity.
VDL at the maximum = 10 V/G.
VD = actual differential input voltage.
Example: G = 10, VD = 0.ꢀ0.
V
CM = 12 V − (10/2 × 0.ꢀ0 V) = 9.ꢀ V.
@ VS = 15 V, RL = 2 kΩ and TA = +25°C, unless otherwise noted.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at the final electrical
test. Results from those tests are used to calculate outgoing quality levels.
Table 2.
AD524C
Typ
AD524S
Typ
Parameter
Min
Max
Min
Max
Unit
GAIN
Gain Equation (External Resistor Gain Programming)
⎡
⎢
⎣
⎤
⎡
⎢
⎣
⎤
40,000
40,000
+1 ± 20%
+1 ± 20%
⎥
⎥
RG
RG
⎦
⎦
Gain Range (Pin Programmable)
Gain Error1
1 to 1000
1 to 1000
G = 1
G = 10
G = 100
G = 1000
%
%
%
%
±±0±2
±±0.
±±025
±±05
±±0±5
±±025
±±05
±20±
Nonlinearity
G = 1
G = 10, G = 100
G = 1000
0.003
0.003
0.01
0.01
0.01
0.01
%
%
%
Gain vs. Temperature
G = 1
G = 10
G = 100
G = 1000
ꢀ
ꢀ
ppm/°C
ppm/°C
ppm/°C
ppm/°C
10
2ꢀ
ꢀ0
10
2ꢀ
ꢀ0
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage
vs. Temperature
Output Offset Voltage
vs. Temperature
Offset Referred to the Input vs. Supply
G = 1
μV
5±
.±±
20±
ꢀ0±
5±
μV/°C
mV
μV
±05
20±
25
dB
dB
dB
dB
8±
75
95
.±5
..±
G = 10
G = 100
G = 1000
.±±
..±
..5
Rev. F | Page ꢀ of 28
AD524
AD524C
Typ
AD524S
Typ
Parameter
Min
Max
±.5
±.±
Min
Max
±5±
±ꢀ5
Unit
INPUT CURRENT
Input Bias Current
vs. Temperature
Input Offset Current
vs. Temperature
nA
pA/°C
nA
100
100
100
100
pA/°C
INPUT
Input Impedance
Differential Resistance
Differential Capacitance
Common-Mode Resistance
Common-Mode Capacitance
Input Voltage Range
109
10
109
10
Ω
pF
Ω
109
109
10
10
pF
Maximum Differential Input Linear (VDL)2
10
10
V
V
2
Maximum Common-Mode Linear (VCM
)
G
2
G
2
⎛
⎜
⎞
⎛
⎜
⎞
.2 V −
× VD
.2 V −
× VD
⎟
⎠
⎟
⎠
⎝
⎝
Common-Mode Rejection DC to 60 Hz with 1 kΩ Source Imbalance
V
G = 1
G = 10
G = 100
G = 1000
dB
dB
dB
dB
8±
7±
9±
.±±
..±
.±±
..±
.2±
OUTPUT RATING
VOUT, RL = 2 kΩ
DYNAMIC RESPONSE
Small Signal – 3 dB
G = 1
G = 10
G = 100
G = 1000
Slew Rate
10
10
V
1
1
MHz
kHz
kHz
kHz
V/μs
400
1ꢀ0
2ꢀ
400
1ꢀ0
2ꢀ
ꢀ.0
ꢀ.0
Settling Time to 0.01%, 20 V Step
G = 1 to 100
G = 1000
1ꢀ
7ꢀ
1ꢀ
7ꢀ
μs
μs
NOISE
Voltage Noise, 1 kHz
RTI
RTO
7
90
7
90
nV/√Hz
nV√Hz
RTI, 0.1 Hz to 10 Hz
G = 1
G = 10
G = 100, 1000
Current Noise
0.1 Hz to 10 Hz
SENSE INPUT
RIN
1ꢀ
2
0.3
1ꢀ
2
0.3
μV p-p
μV p-p
μV p-p
60
60
pA p-p
20
1ꢀ
20
1ꢀ
kΩ 20%
μA
V
IIN
Voltage Range
Gain to Output
10
10
1
1
%
Rev. F | Page 6 of 28
AD524
AD524C
Typ
AD524S
Typ
Parameter
Min
Max
Min
Max
Unit
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
TEMPERATURE RANGE
Specified Performance
Storage
40
1ꢀ
40
1ꢀ
kΩ 20%
μA
V
10
10
1
1
%
–2ꢀ
–6ꢀ
+8ꢀ
+1ꢀ0
–ꢀꢀ
–6ꢀ
+8ꢀ
+1ꢀ0
°C
°C
POWER SUPPLY
Power Supply Range
Quiescent Current
1ꢀ
3.ꢀ
1ꢀ
3.ꢀ
V
mA
±ꢁ
±.8
50±
±ꢁ
±.8
50±
1 Does not include effects of external resistor RG.
2 VOL is the maximum differential input voltage at G = 1 for specified nonlinearity.
V
DL at the maximum = 10 V/G.
VD = actual differential input voltage.
Example: G = 10, VD = 0.ꢀ0.
VCM = 12 V − (10/2 × 0.ꢀ0 V) = 9.ꢀ V.
Rev. F | Page 7 of 28
AD524
ABSOLUTE MAXIMUM RATINGS
Table 3.
CONNECTION DIAGRAMS
16
15
14
13
12
11
1
2
3
4
5
6
7
8
RG
1
– INPUT
+ INPUT
Parameter
Rating
OUTPUT NULL
OUTPUT NULL
G = 10
Supply Voltage
18 V
RG
2
Internal Power Dissipation
Input Voltage1
4ꢀ0 mW
AD524
TOP VIEW
(Not to Scale)
INPUT NULL
INPUT NULL
REFERENCE
SHORT TO
RG FOR
2
G = 100
(Either Input Simultaneously) |VIN| + |VS|
Output Short-Circuit Duration
Storage Temperature Range
(R)
<36 V
Indefinite
DESIRED
GAIN
G = 1000
–V
S
10 SENSE
+V
S
9
OUTPUT
–6ꢀ°C to +12ꢀ°C
–6ꢀ°C to +1ꢀ0°C
(D, E)
4
5
15
14
–V
S
+V
S
Operating Temperature Range
ADꢀ24A/ADꢀ24B/ADꢀ24C
ADꢀ24S
INPUT
OUTPUT
–2ꢀ°C to +8ꢀ°C
–ꢀꢀ°C to +12ꢀ°C
+300°C
OFFSET NULL
OFFSET NULL
Figure 3. Ceramic (D) and
SOIC (RW-16 and D-16) Packages
Lead Temperature (Soldering, 60 sec)
1 Maximum input voltage specification refers to maximum voltage to which
either input terminal may be raised with or without device power applied.
For example, with 18 volt supplies maximum, VIN is 18 V; with zero supply
voltage maximum, VIN is 36 V.
3
2
1
20 19
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
18
17
16
15
14
4
5
6
7
8
OUTPUT NULL
G = 10
RG
2
INPUT NULL
NC
SHORT TO
AD524
TOP VIEW
NC
RG FOR
2
DESIRED
GAIN
INPUT NULL
REFERENCE
G = 100
G = 1000
(Not to Scale)
9
10 11 12 13
NC = NO CONNECT
OUTPUT
NULL
14
SENSE
10
G = 10
13
G = 100 G = 1000
12
11
OUTPUT
7
5
19
18
NULL
15
9
+V
–V
S
S
OUTPUT
INPUT
OFFSET NULL
OUTPUT
OFFSET NULL
8 +V
S
RG 16
1
Figure 4. Leadless Chip Carrier (E)
0.103
(2.61)
–INPUT
1
+INPUT
2
ESD CAUTION
7 –V
S
RG
2
3
6
4
5
REFERENCE
INPUT
NULL
INPUT
NULL
0.170 (4.33)
PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR
THE D-16 AND RW-16 16-LEAD CERAMIC PACKAGES.
Figure 2. Metallization Photograph
Contact factory for latest dimensions;
Dimensions shown in inches and (mm)
Rev. F | Page 8 of 28
AD524
TYPICAL PERFORMANCE CHARACTERISTICS
20
8
6
15
10
4
2
+25°C
5
0
0
0
5
10
15
20
0
5
10
15
20
SUPPLY VOLTAGE (±V)
SUPPLY VOLTAGE (±V)
Figure 5. Input Voltage Range vs. Supply Voltage, G = 1
Figure 8. Quiescent Current vs. Supply Voltage
20
16
14
12
15
10
8
10
5
6
4
2
0
0
0
5
10
15
20
0
5
10
15
20
SUPPLY VOLTAGE (±V)
SUPPLY VOLTAGE (±V)
Figure 6. Output Voltage Swing vs. Supply Voltage
Figure 9. Input Bias Current vs. Supply Voltage
30
20
10
40
30
20
10
0
–10
–20
–30
–40
0
10
100
1k
10k
–75
–25
25
75
125
LOAD RESISTANCE (Ω)
TEMPERATURE (°C)
Figure 7. Output Voltage Swing vs. Load Resistance
Figure 10. Input Bias Current vs. Temperature
Rev. F | Page 9 of 28
AD524
16
–140
–120
–100
–80
–60
–40
–20
0
G = 1000
G = 100
14
12
G = 10
G = 1
10
8
6
4
2
0
0
5
10
15
20
0
10
100
1k
10k
100k
1M
10M
INPUT VOLTAGE (±V)
FREQUENCY (Hz)
Figure 11. Input Bias Current vs. Input Voltage
Figure 14. CMRR vs. Frequency, RTI, Zero to 1000 Source Imbalance
30
0
1
G = 1, 10, 100
20
2
3
4
5
10
BANDWIDTH LIMITED
6
G = 1000
10k
G = 100
100k
G = 10
0
1k
0
1
2
3
4
5
6
7
8
1M
WARM-UP TIME (Minutes)
FREQUENCY (Hz)
Figure 12. Offset Voltage, RTI, Turn-On Drift
Figure 15. Large Signal Frequency Response
10
8
6
1000
100
10
4
2
0
1
G = 1000
1
10
100
1000
0
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
GAIN (V/V)
Figure 13. Gain vs. Frequency
Figure 16. Slew Rate vs. Gain
Rev. F | Page 10 of 28
AD524
160
100k
10k
1k
+V = 15V DC +
S
1V p-p SINEWAVE
140
120
100
80
60
100
40
20
0
0
1
10
100
1k
10k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Positive PSRR vs. Frequency
Figure 20. Input Current Noise vs. Frequency
160
0.1Hz TO 10Hz
–V = –15V DC +
S
1V p-p SINEWAVE
140
120
5mV
1s
100
80
60
40
20
0
10
100
1k
10k
100k
FREQUENCY (Hz)
VERTICAL SCALE; 1 DIVISION = 5µV
Figure 18. Negative PSRR vs. Frequency
Figure 21. Low Frequency Noise, G = 1 (System Gain = 1000)
1000
100
10
0.1Hz TO 10Hz
10mV
1s
G = 1
G = 10
G = 100, 1000
G = 1000
1
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
VERTICAL SCALE; 1 DIVISION = 0.1µV
Figure 19. RTI Noise Spectral Density vs. Gain
Figure 22. Low Frequency Noise, G = 1000 (System Gain = 100,000)
Rev. F | Page 11 of 28
AD524
–12 TO +12
–8 TO +8
–4 TO +4
1%
0.1%
0.01%
1mV
10V
10µs
OUTPUT
STEP (V)
+4 TO –4
+8 TO –8
1%
0.1%
0.01%
+12 TO –12
0
5
10
SETTLING TIME (µs)
15
20
Figure 23. Settling Time, Gain = 1
Figure 26. Large Signal Pulse Response and Settling Time, Gain = 10
–12 TO +12
0.1%
0.01%
1%
–8 TO +8
–4 TO +4
1mV
10V
10µs
OUTPUT
STEP (V)
+4 TO –4
+8 TO –8
1%
0.01%
15
0.1%
10
+12 TO –12
0
5
20
SETTLING TIME (µs)
Figure 24. Large Signal Pulse Response and Settling Time, Gain =1
Figure 27. Settling Time, Gain = 100
–12 TO +12
0.1%
0.01%
1%
–8 TO +8
–4 TO +4
1mV
10V
10µs
OUTPUT
STEP (V)
+4 TO –4
+8 TO –8
1%
5
0.1%
0.01%
+12 TO –12
0
10
SETTLING TIME (µs)
15
20
Figure 25. Settling Time, Gain = 10
Figure 28. Large Signal Pulse Response and Settling Time, Gain = 100
Rev. F | Page 12 of 28
AD524
–12 TO +12
–8 TO +8
–4 TO +4
1%
0.1%
0.01%
5mV
10V
20µs
OUTPUT
STEP (V)
+4 TO –4
+8 TO –8
1%
0.1%
0.01%
+12 TO –12
0
10
20
30
40
50
60
70
80
SETTLING TIME (µs)
Figure 29. Settling Time, Gain = 1000
Figure 30. Large Signal Pulse Response and Settling Time, Gain = 1000
Rev. F | Page 13 of 28
AD524
TEST CIRCUITS
10kΩ
1kΩ
10kΩ
0.1%
0.01% 10T
V
INPUT
20V p-p
OUT
100kΩ
0.1%
+V
S
1
16
13
12
11
3
–
+
RG
8
AD524
7
1
G = 10
G = 100
10
6
9
11kΩ
1kΩ 100Ω
0.1%
G = 1000
0.1% 0.1%
RG
2
2
–V
S
Figure 31. Settling Time Test Circuit
+V
S
I
I
2
1
V
B
50µA
50µA
R52
20kΩ
A1
A2
C4
SENSE
R53
20kΩ
+
+
C3
A3
V
R57
O
CH ,
2
20kΩ
R56
20kΩ
R54
CH , CH
3
4
R55
20kΩ
20kΩ
Q1, Q3
Q2, Q4
–IN
4.44kΩ
REFERENCE
+IN
CH
1
CH , CH ,
RG
2
CH
3
RG
2
1
404Ω
40Ω
4
G = 100
I
I
3
4
50µA
G = 1000
50µA
CH
1
–V
S
Figure 32. Simplified Circuit of Amplifier; Gain Is Defined as
((R56 + R57)/(RG)) +1; For a Gain of 1, RG Is an Open Circuit
Rev. F | Page 14 of 28
AD524
THEORY OF OPERATION
The AD524 is a monolithic instrumentation amplifier based
on the classic 3-op amp circuit. The advantage of monolithic
construction is the closely matched components that enhance
the performance of the input preamplifier. The preamplifier
section develops the programmed gain by the use of feedback
concepts. The programmed gain is developed by varying the
value of RG (smaller values increase the gain) while the feedback
forces the collector currents (Q1, Q2, Q3, and Q4) to be constant,
which impresses the input voltage across RG.
from excessive currents. Standard practice is to place series
limiting resistors in each input, but to limit input current to
below 5 mA with a full differential overload (36 V) requires
over 7kꢀ of resistance, which adds 10 nV√Hz of noise. To
provide both input protection and low noise, a special series
protection FET is used.
A unique FET design was used to provide a bidirectional
current limit, thereby protecting against both positive and
negative overloads. Under nonoverload conditions, three
channels (CH2, CH3, CH4) act as a resistance (≈1 kΩ) in series
with the input as before. During an overload in the positive
direction, a fourth channel, CH1, acts as a small resistance
(≈3 kΩ) in series with the gate, which draws only the leakage
current, and the FET limits IDSS. When the FET enhances under
a negative overload, the gate current must go through the small
FET formed by CH1 and when this FET goes into saturation,
the gate current is limited and the main FET goes into controlled
enhancement. The bidirectional limiting holds the maximum
input current to 3 mA over the 36 V range.
As RG is reduced to increase the programmed gain, the
transconductance of the input preamplifier increases to the
transconductance of the input transistors. This has three
important advantages. First, this approach allows the circuit
to achieve a very high open-loop gain of 3 × 108 at a programmed
gain of 1000, thus reducing gain-related errors to a negligible
30 ppm. Second, the gain bandwidth product, which is deter-
mined by C3 or C4 and the input transconductance, reaches
25 MHz. Third, the input voltage noise reduces to a value
determined by the collector current of the input transistors
for an RTI noise of 7 nV/√Hz at G = 1000.
INPUT OFFSET AND OUTPUT OFFSET
INPUT PROTECTION
Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may
be adjusted to zero, shifts in offset voltage due to temperature
variations causes errors. Intelligent systems can often correct
this factor with an autozero cycle, but there are many small-
signal high-gain applications that do not have this capability.
As interface amplifiers for data acquisition systems, instru-
mentation amplifiers are often subjected to input overloads,
that is, voltage levels in excess of the full scale for the selected
gain range. At low gains (10 or less), the gain resistor acts as a
current limiting element in series with the inputs. At high gains,
the lower value of RG does not adequately protect the inputs
+V
S
1
16
13
12
11
3
–
8
AD712
1µF
+V
8
10
100
s
10
6
16.2kΩ
9
3
2
AD524
+
1000
5
6
+
1/2
–
1
1/2
–
RG
2
7
1µF
9.09kΩ
1kΩ
4
7
2
+
1µF
16.2kΩ
1.82kΩ
G = 1, 10, 100
–V
S
–V
G = 1000
S
100Ω
1.62MΩ
Figure 33. Noise Test Circuit
Rev. F | Page 1ꢀ of 28
AD524
Voltage offset and drift comprise two components each; input
and output offset and offset drift. Input offset is the component
of offset that is directly proportional to gain, that is, input offset
as measured at the output at G = 100 is 100 times greater than at
G = 1. Output offset is independent of gain. At low gains, output
offset drift is dominant, at high gains, input offset drift dominates.
Therefore, the output offset voltage drift is normally specified as
drift at G = 1 (where input effects are insignificant), whereas
input offset voltage drift is given by drift specification at a high
gain (where output offset effects are negligible). All input
related numbers are referred to the input (RTI) that is the effect
on the output is G times larger. Voltage offset vs. power supply
is also specified at one or more gain settings and is also RTI.
The AD524 can be configured for gains other than those that
are internally preset; there are two methods to do this. The first
method uses just an external resistor connected between
Pin 3 and Pin 16 (see Figure 35), which programs the gain
according to the following formula:
40 kΩ
RG
=
G = −1
For best results, RG should be a precision resistor with a low
temperature coefficient. An external RG affects both gain
accuracy and gain drift due to the mismatch between it and
the internal thin-film resistors. Gain accuracy is determined
by the tolerance of the external RG and the absolute accuracy
of the internal resistors ( 20ꢁ). Gain drift is determined by the
mismatch of the temperature coefficient of RG and the tempera-
ture coefficient of the internal resistors (−50 ppm/°C typical).
By separating these errors, one can evaluate the total error
independent of the gain setting used. In a given gain configura-
tion, both errors can be combined to give a total error referred
to the input (RTI) or output (RTO) by the following formulas:
+V
S
1
16
13
12
11
3
–INPUT
8
RG
Total error RTI = input error + (output error/gain)
Total error RTO = (gain × input error) + output error
1
1.5kΩ
1kΩ
10
6
2.105kΩ
AD524
9
V
OUT
REFERENCE
+ 1 = 20 ±20%
As an illustration, a typical AD524 might have a +250 μV
output offset and a −50 μV input offset. In a unity gain
configuration, the total output offset would be 200 μV or
the sum of the two. At a gain of 100, the output offset would
be −4.75 mV or: +250 μV + 100(−50 μV) = −4.75 mV.
RG
2
7
2
+INPUT
40,000
2.105
G =
–V
S
Figure 35. Operating Connections for G = 20
The second method uses the internal resistors in parallel with
an external resistor (see Figure 36). This technique minimizes
the gain adjustment range and reduces the effects of tempera-
ture coefficient sensitivity.
The AD524 provides for both input and output offset adjustment.
This simplifies very high precision applications and minimizes
offset voltage changes in switched gain applications. In such
applications, the input offset is adjusted first at the highest
programmed gain, then the output offset is adjusted at G = 1.
+V
S
1
16
13
12
11
3
–INPUT
8
RG
GAIN
1
G = 10
10
6
The AD524 has internal high accuracy pretrimmed resistors
for pin programmable gains of 1, 10, 100, and 1000. One of the
preset gains can be selected by pin strapping the appropriate
gain terminal and RG2 together (for G = 1, RG2 is not connected).
4kΩ
V
9
AD524
OUT
RG
REFERENCE
+ 1 = 20 ±17%
2
7
2
+INPUT
*R|
40,000
4000||4444.44
G =
= 4444.44Ω
= 404.04Ω
= 40.04Ω
–V
S
G = 10
*R|
INPUT
OFFSET
NULL
+V
S
G = 100
*R|
G = 1000
*NOMINAL (±20%)
8
10kΩ
1
16
13
12
11
3
–INPUT
4
Figure 36. Operating Connections for G = 20, Low Gain
Temperature Coefficient Technique
RG
1
5
G = 10
G = 100
10
6
V
9
AD524
OUT
G = 1000
RG
2
OUTPUT
SIGNAL
COMMON
7
2
+INPUT
–V
S
Figure 34. Operating Connections for G = 100
Rev. F | Page 16 of 28
AD524
+V
8
S
The AD524 can also be configured to provide gain in the output
stage. Figure 37 shows an H pad attenuator connected
to the reference and sense lines of the AD524. R1, R2, and R3
should be made as low as possible to minimize the gain variation
and reduction of CMRR. Varying R2 precisely sets the gain
without affecting CMRR. CMRR is determined by the match
of R1 and R3.
2
3
+
–
11
12
13
16
1
10
6
9
AD524
7
LOAD
–V
S
TO POWER
SUPPLY
+V
S
GROUND
R1
2.26kΩ
1
16
13
12
11
3
–INPUT
Figure 40. Indirect Ground Returns for Bias Currents–AC-Coupled
8
RG
1
R2
G = 10
G = 100
Although instrumentation amplifiers have differential inputs,
there must be a return path for the bias currents. If this is not
provided, those currents charge stray capacitances, causing the
output to drift uncontrollably or to saturate. Therefore, when
amplifying floating input sources such as transformers and
thermocouples, as well as ac-coupled sources, there must still
be a dc path from each input to ground.
10
6
5kΩ
V
9
AD524
OUT
G = 1000
R
L
RG
2
7
R3
2.26kΩ
2
+INPUT
(R2||40kΩ) + R1 + R3
(R2||40kΩ)
–V
S
G =
(R1 + R2 + R3)||R ≥ 2kΩ
L
Figure 37. Gain of 2000
Table 4. Output Gain Resistor Values
COMMON-MODE REJECTION
Output Gain
R2
R., Rꢀ
Nominal Gain
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance. Common-mode
rejection ratio (CMRR) is a ratio expression whereas common-
mode rejection (CMR) is the logarithm of that ratio. For
example, a CMRR of 10,000 corresponds to a CMR of 80 dB.
2
ꢀ
10
ꢀ kΩ
1.0ꢀ kΩ
1 kΩ
2.26 kΩ
2.0ꢀ kΩ
4.42 kΩ
2.02
ꢀ.01
10.1
INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the
input transistors of a dc amplifier. Bias currents are an
additional source of input error and must be considered in
a total error budget. The bias currents, when multiplied by
the source resistance, appear as an offset voltage. What is of
concern in calculating bias current errors is the change in bias
current with respect to signal voltage and temperature. Input
offset current is the difference between the two input bias
currents. The effect of offset current is an input offset voltage
whose magnitude is the offset current times the source
impedance imbalance.
In an instrumentation amplifier, ac common-mode rejection is
only as good as the differential phase shift. Degradation of ac
common-mode rejection is caused by unequal drops across
differing track resistances and a differential phase shift due
to varied stray capacitances or cable capacitances. In many
applications, shielded cables are used to minimize noise. This
technique can create common-mode rejection errors unless the
shield is properly driven. Figure 41 and Figure 42 show active
data guards that are configured to improve ac common-mode
rejection by bootstrapping the capacitances of the input cabling,
thus minimizing differential phase shift.
+V
S
2
3
+
8
+V
S
–INPUT
G = 100
10
6
11
12
13
16
1
1
12
3
–
8
AD524
9
10
6
100Ω
AD711
9
7
AD524
V
LOAD
RG
2
OUT
–
–V
S
+INPUT
REFERENCE
7
TO POWER
SUPPLY
GROUND
2
+
–V
S
Figure 38. Indirect Ground Returns for Bias Currents—Transformer Coupled
Figure 41. Shield Driver, G ≥ 100
+V
S
+V
S
–INPUT
RG
1
–
2
3
+
8
AD712
1
8
100Ω
16
11
12
13
16
1
10
6
10
6
AD524
9
12
3
9
V
AD524
OUT
–V
S
7
LOAD
REFERENCE
100Ω
–
RG
7
2
2
+
–V
S
+INPUT
TO POWER
SUPPLY
GROUND
–V
S
Figure 42. Differential Shield Driver
Figure 39. Indirect Ground Returns for Bias Currents—Thermocouple
Rev. F | Page 17 of 28
AD524
GROUNDING
SENSE TERMINAL
Many data acquisition components have two or more ground
pins that are not connected together within the device. These
grounds must be tied together at one point, usually at the system
power-supply ground. Ideally, a single solid ground would be
desirable. However, because current flows through the ground
wires and etch stripes of the circuit cards, and because these
paths have resistance and inductance, hundreds of millivolts can
be generated between the system ground point and the data
acquisition components. Separate ground returns should be
provided to minimize the current flow in the path from the
sensitive points to the system ground point. In this way, supply
currents and logic-gate return currents are not summed into the
same return path as analog signals where they would cause
measurement errors.
The sense terminal is the feedback point for the instrument
amplifier’s output amplifier. Normally, it is connected to the
instrument amplifier output. If heavy load currents are to be
drawn through long leads, voltage drops due to current flowing
through lead resistance can cause errors. The sense terminal can
be wired to the instrument amplifier at the load, thus putting
the IxR drops inside the loop and virtually eliminating this
error source.
V+
(SENSE)
OUTPUT
CURRENT
V
+
2
3
8
IN
BOOSTER
10
6
9
X1
AD524
12
1
R
L
7
(REF)
V
–
IN
V–
Because the output voltage is developed with respect to the
potential on the reference terminal, an instrumentation
amplifier can solve many grounding problems.
Figure 44. AD524 Instrumentation Amplifier with Output Current Booster
Typically, IC instrumentation amplifiers are rated for a full
10 volt output swing into 2 kΩ. In some applications, however,
the need exists to drive more current into heavier loads.
Figure 44 shows how a high current booster may be connected
inside the loop of an instrumentation amplifier to provide the
required current boost without significantly degrading overall
performance. Nonlinearities and offset and gain inaccuracies of
the buffer are minimized by the loop gain of the AD524 output
amplifier. Offset drift of the buffer is similarly reduced.
ANALOG P.S.
+15V –15V
DIGITAL P.S.
+5V
C
C
0.1 0.1
µF µF
0.1 0.1
µF µF
1µF 1µF
1µF
DIG
COM
8
7
7
9
11 15
1
2
1
10
AD583
DIGITAL
DATA
OUTPUT
9
AD524
AD574A
SAMPLE
AND HOLD
REFERENCE TERMINAL
6
The reference terminal can be used to offset the output by up to
10 V. This is useful when the load is floating or does not share
a ground with the rest of the system. It also provides a direct
means of injecting a precise offset. It must be remembered that
the total output swing is 10 V to be shared between signal and
reference offset.
ANALOG
GROUND*
OUTPUT
REFERENCE
SIGNAL
GROUND
*IF INDEPENDENT; OTHERWISE, RETURN AMPLIFIER REFERENCE
TO MECCA AT ANALOG P.S. COMMON.
Figure 43. Basic Grounding Practice
When the AD524 is of the 3-amplifier configuration it
is necessary that nearly zero impedance be presented to the
reference terminal.
Any significant resistance from the reference terminal to
ground increases the gain of the noninverting signal path,
thereby upsetting the common-mode rejection of the AD524.
In the AD524, a reference source resistance unbalances the CMR
trim by the ratio of 20 kΩ/RREF. For example, if the reference
source impedance is 1 Ω, CMR is reduced to 86 dB (20 kΩ/1 Ω
= 86 dB). An operational amplifier can be used to provide that
low impedance reference point, as shown in Figure 45. The
input offset voltage characteristics of that amplifier adds directly
to the output offset voltage performance of the instrumentation
amplifier.
Rev. F | Page 18 of 28
AD524
+V
8
S
SENSE
2
3
+INPUT
–INPUT
+
10
SENSE
10
V
+
2
3
IN
R1
9
AD524
I
L
V
X
9
13
1
AD524
6
12
1
6
–
LOAD
REF
7
REF
V
–
IN
A2
AD711
–V
S
LOAD
V
V
IN
40,000
V
X
OFFSET
AD711
I
=
=
=
(1 +
)
L
R1
R1
R
G
Figure 45. Use of Reference Terminal to Provide Output Offset
Figure 46. Voltage-to-Current Converter
An instrumentation amplifier can be turned into a voltage-
to-current converter by taking advantage of the sense and
reference terminals, as shown in Figure 46.
By establishing a reference at the low side of a current setting
resistor, an output current may be defined as a function of input
voltage, gain, and the value of that resistor. Because only a small
current is demanded at the input of the buffer amplifier (A2)
the forced current, IL, largely flows through the load. Offset and
drift specifications of A2 must be added to the output offset and
drift specifications of the AD524.
1
16
15
14
13
12
11
10
9
–IN
+IN
PROTECTION
PROTECTION
OUTPUT
OFFSET
TRIM
G = 100
K2
G = 1000
K3
G = 10
K1
2
3
4
5
6
7
8
NC
R2
+V
S
10kΩ
INPUT
OFFSET
TRIM
4.44kΩ
404Ω
40Ω
R1
10kΩ
RELAY
SHIELDS
20kΩ
20kΩ
20kΩ
20kΩ
20kΩ
+5V
20kΩ
–V
S
A1
AD524
K1
D1
K2
D2
K3
D3
OUT
+V
S
1µF
35V
C2
C1
INPUTS
GAIN
A
B
1
2
3
4
5
6
7
16
1
2
3
4
5
6
7
16
K1 – K3 =
Y0
Y1
Y2
ANALOG
COMMON
THERMOSEN DM2C
4.5V COIL
RANGE
15
D1 – D3 = IN4148
14
13
7407N
BUFFER
DRIVER
74LS138
DECODER
GAIN TABLE
10µF
A
B
GAIN
10
1000
100
1
0
0
1
1
0
1
0
1
+5V
LOGIC
COMMON
NC = NO CONNECT
Figure 47. Three-Decade Gain Programmable Amplifier
Rev. F | Page 19 of 28
AD524
PROGRAMMABLE GAIN
+INPUT
PROTECTION
4.44kΩ
1
(–INPUT)
Figure 47 shows the AD524 being used as a software program-
mable gain amplifier. Gain switching can be accomplished with
mechanical switches such as DIP switches or reed relays. It should
be noted that the on resistance of the switch in series with the
internal gain resistor becomes part of the gain equation and has
an effect on gain accuracy.
AD524
G = 10 13
404Ω
G = 100 12
V
b
20kΩ
40Ω
10
G = 1000
11
20kΩ
20kΩ
20kΩ
16
3
RG
RG
1
2
9
6
V
OUT
20kΩ
20kΩ
The AD524 can also be connected for gain in the output stage.
Figure 48 shows an AD711 used as an active attenuator in the
output amplifier’s feedback loop. The active attenuation presents
very low impedance to the feedback resistors, therefore
minimizing the common-mode rejection ratio degradation.
–INPUT
2
PROTECTION
(+INPUT)
+V
S
1/2
AD712
17
3
2
1
4
14
7
DAC A
DB0
DB7
DATA
INPUTS
256:1
(+INPUT)
15
16
6
CS
1
2
3
4
16
15
14
13
12
11
10
9
–IN
+IN
PROTECTION
PROTECTION
AD7528
OUTPUT
OFFSET
NULL
WR
(–INPUT)
19
20
DAC A/DAC B
TO –V
+V
18
S
DAC B
5
R2
10kΩ
1/2
AD712
INPUT
OFFSET
NULL
4.44kΩ
10kΩ
20kΩ
20kΩ
20kΩ
20kΩ
404Ω
40Ω
5
6
7
8
20kΩ
Figure 49. Programmable Output Gain Using a DAC
–
+
Another method for developing the switching scheme is to
use a DAC. The AD7528 dual DAC, which acts essentially as
a pair of switched resistive attenuators having high analog
linearity and symmetrical bipolar transmission, is ideal in this
application. The multiplying DAC’s advantage is that it can
handle inputs of either polarity or zero without affecting the
programmed gain. The circuit shown uses an AD7528 to set
the gain (DAC A) and to perform a fine adjustment (DAC B).
20kΩ
–V
S
AD524
+V
S
V
OUT
1µF
35V
20kΩ
10pF
V
V
DD GND
SS
+V
–V
S
1
8
16
2
15
13
11
–
+
39.2kΩ
28.7kΩ
316kΩ
1kΩ
14
12
AD711
1kΩ
1kΩ
AUTOZERO CIRCUITS
S
9
10
AD7590
In many applications, it is necessary to provide very accurate
data in high gain configurations. At room temperature, the
offset effects can be nulled by the use of offset trim potenti-
ometers. Over the operating temperature range, however,
offset nulling becomes a problem. The circuit of Figure 50
shows a CMOS DAC operating in bipolar mode and connected
to the reference terminal to provide software controllable offset
adjustments.
3
4
5
6
7
V
A2 A3 A4 WR
DD
Figure 48. Programmable Output Gain
Rev. F | Page 20 of 28
AD524
+V
+V
8
S
S
+10V
2
16
13
12
11
3
+INPUT
+
8
10kΩ
RG
1
2
16
13
12
11
3
4
+
350Ω
350Ω
350Ω
350Ω
G = 10
10
6
RG
1
5
9
G = 100
14-BIT
ADC
0V TO 2V
F.S.
AD524
10
6
G = 100
9
AD524C
G = 1000
RG
2
7
RG
2
1
–INPUT
–
7
1
–
–V
S
39kΩ
V
REF
16
–V
S
–V
S
R3
AD589
+V
S
R5
20kΩ
20kΩ
C1
15
14
+V
Figure 52. Typical Bridge Application
MSB
4
S
1/2
AD712
DATA
INPUTS
R4
10kΩ
OUT1
OUT2
2
3
LSB
11
1
2
–
+
8
ERROR BUDGET ANALYSIS
AD7524
6
5
–
+
1
7
12
13
CS
To illustrate how instrumentation amplifier specifications are
applied, review a typical case where an AD524 is required to
amplify the output of an unbalanced transducer. Figure 52
shows a differential transducer, unbalanced by 100 Ω, supplying
a 0 mV to 20 mV signal to an AD524C. The output of the IA
feeds a 14-bit ADC with a 0 V to 2 V input voltage range. The
operating temperature range is −25°C to +85°C. Therefore, the
largest change in temperature, ΔT, within the operating range is
from ambient to +85°C (85°C − 25°C = 60°C).
4
1/2
AD712
WR
R6
5kΩ
3
–V
S
GND
Figure 50. Software Controllable Offset
In many applications, complex software algorithms for autozero
applications are not available. For those applications, Figure 51
provides a hardware solution.
+V
S
+
2
In many applications, differential linearity and resolution are of
prime importance in cases where the absolute value of a variable is
less important than changes in value. In these applications, only
the irreducible errors (45 ppm = 0.004ꢁ) are significant. Further-
more, if a system has an intelligent processor monitoring the
analog-to-digital output, the addition of an autogain/autozero
cycle removes all reducible errors and may eliminate the require-
ment for initial calibration. This also reduces errors to 0.004ꢁ.
8
15 16
RG
16
13
12
11
3
1
10
6
V
14
13
OUT
9
AD524
9
10
0.1µF LOW
LEAKAGE
CH
RG
2
7
–
1
1kΩ
–
+
–V
S
12 11
AD711
V
8
1
2
DD
V
AD7510KD
SS
GND
A1
A2
A3
A4
200µs
ZERO PULSE
Figure 51. Autozero Circuit
Rev. F | Page 21 of 28
AD524
Table 5. Error Budget Analysis
Effect on
Absolute
Accuracy
Effect on
Absolute
Accuracy
Effect
on
Resolution
AD524C
Specifications Calculation
Error Source
at TA = 25°C at TA = 85°C
Gain Error
Gain Instability
Gain Nonlinearity
Input Offset Voltage
Input Offset Voltage Drift
0.2ꢀ%
2ꢀ ppm
0.003%
ꢀ0 μV, RTI
0.ꢀ μV/°C
–
0.2ꢀ% = 2ꢀ00 ppm
(2ꢀ ppm/°C)(60°C) = 1ꢀ00 ppm
0.003% = 30 ppm
ꢀ0 μV/20 mV = 2ꢀ00 ppm
( 0.ꢀ μV/°C)(60°C) = 30 μV
30 μV/20 mV = 1ꢀ00 ppm
2ꢀ00 ppm
–
–
2ꢀ00 ppm
–
2ꢀ00 ppm
1ꢀ00 ppm
–
2ꢀ00 ppm
1ꢀ00 ppm
–
–
30 ppm
–
–
Output Offset Voltage1
Output Offset Voltage Drift1
2.0 mV
2ꢀ μV/°C
2.0 mV/20 mV = 1000 ppm
( 2ꢀ μV/°C)(60°C)= 1ꢀ00 μV
1ꢀ00 μV/20 mV = 7ꢀ0 ppm
1000 ppm
–
1000 ppm
7ꢀ0 ppm
–
–
Bias Current-Source
Imbalance Error
1ꢀ nA
( 1ꢀ nA)(100 Ω ) = 1.ꢀ μV
1.ꢀ μV/20 mV = 7ꢀ ppm
7ꢀ ppm
7ꢀ ppm
30 ppm
ꢀ0 ppm
30 ppm
87.ꢀ ppm
ꢀ0 ppm
444 ppm
–
–
Bias Current-Source
Imbalance Drift
100 pA/°C
10 nA
( 100 pA/°C)(100 Ω )(60°C) = 0.6 μV
0.6 μV/20 mV = 30 ppm
–
–
Offset Current-Source
Imbalance Error
( 10 nA)(100 Ω ) = 1 μV
1 μV/20 mV = ꢀ0 ppm
ꢀ0 ppm
–
Offset Current-Source
Imbalance Drift
100 pA/°C
10 nA
(100 pA/°C)(100 Ω )(60°C) = 0.6 μV
0.6 μV/20 mV = 30 ppm
–
–
Offset Current-Source
Resistance-Error
(10 nA)(17ꢀ Ω ) = 3.ꢀ μV
3.ꢀ μV/20 mV = 87.ꢀ ppm
87.ꢀ ppm
–
–
Offset Current-Source
Resistance-Drift
100 pA/°C
11ꢀ dB
(100 pA/°C)(17ꢀ Ω )(60°C) = 1 μV
1 μV/20 mV = ꢀ0 ppm
–
Common Mode Rejection ꢀ V DC
11ꢀ dB = 1.8 ppm × ꢀ V = 8.8 μV
8.8 μV/20 mV = 444 ppm
444 ppm
–
Noise, RTI (0.1 Hz to 10 Hz)
0.3 μV p-p
0.3 μV p-p/20 mV = 1ꢀ ppm
Total Error
–
1ꢀ ppm
66ꢀ6.ꢀ ppm
10ꢀ16.ꢀ ppm 4ꢀ ppm
1 Output offset voltage and output offset voltage drift are given as RTI figures.
Rev. F | Page 22 of 28
AD524
Figure 53 shows a simple application in which the variation
of the cold-junction voltage of a Type J thermocouple-iron
constantan is compensated for by a voltage developed in series
by the temperature-sensitive output current of an AD590
semiconductor temperature sensor.
Other thermocouple types may be accommodated with the
standard resistance values shown in Table 5. For other ranges
of ambient temperature, the equation in Figure 53 may be
solved for the optimum values of RT and RA.
The microprocessor controlled data acquisition system shown
in Figure 54 includes both autozero and autogain capability. By
dedicating two of the differential inputs, one to ground and one
to the A/D reference, the proper program calibration cycles can
eliminate both initial accuracy errors and accuracy errors over
temperature. The autozero cycle, in this application, converts a
number that appears to be ground and then writes that same
number (8-bit) to the AD7524, which eliminates the zero error.
Because its output has an inverted scale, the autogain cycle
converts the A/D reference and compares it with full scale. A
multiplicative correction factor is then computed and applied
to subsequent readings.
R
A
REFERENCE
JUNCTION
NOMINAL
VALUE
+V
S
7.5V
TYPE
+15°C < T < +35°C
A
J
K
52.3Ω
41.2Ω
61.4Ω
40.2Ω
5.76Ω
I
A
2.5V
T
A
AD580
E
G = 100
+V
V
AD590
CU
T
A
S AD524
S, R
+
R
A
IRON
E
O
52.3Ω
V
CONSTANTAN
T
–
MEASURING
JUNCTION
8.66kΩ
1kΩ
52.3ΩI + 2.5V
–V
A
S
E
= V – V +
T A
– 2.5V
O
R
T
52.3Ω
OUTPUT
AMPLIFIER
OR METER
1 +
R
~
= V
T
NOMINAL VALUE
9135Ω
For a comprehensive study of instrumentation amplifier
design and applications, refer to the Designer’s Guide to
Instrumentation Amplifiers (3rd Edition), available free from
Analog Devices, Inc.
Figure 53. Cold-Junction Compensation
The circuit is calibrated by adjusting RT for proper output
voltage with the measuring junction at a known reference
temperature and the circuit near 25°C. If resistors with low
temperature coefficients are used, compensation accuracy is
to within 0.5°C, for temperatures between +15°C and +35°C.
2
+
V
REF
AD583
16
13
12
11
3
RG
RG
2
1
10
6
AD7507
V
AD524
9
AD574A
IN
AGND
1
–
–V
REF
A0, A2,
EN, A1
20kΩ
20kΩ
–
+
10kΩ
–
+
AD7524
1/2
1/2
AD712
AD712
5kΩ
DECODE
LATCH
CONTROL
MICRO-
PROCESSOR
ADDRESS BUS
Figure 54. Microprocessor Controlled Data Acquisition System
Rev. F | Page 23 of 28
AD524
OUTLINE DIMENSIONS
0.005 (0.13) MIN
16
0.080 (2.03) MAX
9
0.310 (7.87)
PIN 1
1
0.220 (5.59)
8
0.320 (8.13)
0.290 (7.37)
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 55. 16-Lead Side-Brazed Ceramic Dual In-Line [SBDIP]
(D-16)
Dimensions shown in inches and (millimeters)
0.200 (5.08)
0.075 (1.91)
REF
REF
0.100 (2.54)
0.064 (1.63)
0.100 (2.54) REF
0.095 (2.41)
0.015 (0.38)
MIN
0.075 (1.90)
3
19
18
20
4
8
0.028 (0.71)
0.022 (0.56)
1
0.358 (9.09)
0.342 (8.69)
SQ
0.358
0.011 (0.28)
0.007 (0.18)
R TYP
(9.09)
MAX
SQ
BOTTOM
VIEW
0.050 (1.27)
BSC
14
0.075 (1.91)
13
9
REF
45° TYP
0.088 (2.24)
0.054 (1.37)
0.055 (1.40)
0.045 (1.14)
0.150 (3.81)
BSC
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 56. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20)
Dimensions shown in inches and (millimeters)
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.00
98)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 57. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
Rev. F | Page 24 of 28
AD524
ORDERING GUIDE
Model
ADꢀ24AD
ADꢀ24ADZ1
Temperature Range
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−ꢀꢀ°C to +12ꢀ°C
−ꢀꢀ°C to +12ꢀ°C
−ꢀꢀ°C to +12ꢀ°C
−ꢀꢀ°C to +12ꢀ°C
−ꢀꢀ°C to +12ꢀ°C
Package Description
16-Lead SBDIP
16-Lead SBDIP
Package Option
D-16
D-16
E-20
ADꢀ24AE
20-Terminal LCC
ADꢀ24AR-16
ADꢀ24AR-16-REEL
ADꢀ24AR-16-REEL7
ADꢀ24ARZ-161
ADꢀ24ARZ-16-REEL71
ADꢀ24BD
ADꢀ24BDZ1
ADꢀ24BE
ADꢀ24CD
ADꢀ24CDZ1
16-Lead SOIC_W
16-Lead SOIC_W, 13" Tape and Reel
16-Lead SOIC_W, 7" Tape and Reel
16-Lead SOIC_W
16-Lead SOIC_W, 7”Tape and Reel
16-Lead SBDIP
16-Lead SBDIP
20-Terminal LCC
16-Lead SBDIP
16-Lead SBDIP
RW-16
RW-16
RW-16
RW-16
RW-16
D-16
D-16
E-20
D-16
D-16
D-16
D-16
D-16
E-20
ADꢀ24SD
16-Lead SBDIP
16-Lead SBDIP
16-Lead SBDIP
20-Terminal LCC
ADꢀ24SD/883B
ꢀ962-88ꢀ3901EA2
ADꢀ24SE/883B
ADꢀ24SCHIPS
Die
1 Z = RoHS Compliant Part.
2 Refer to the official DESC drawing for tested specifications.
Rev. F | Page 2ꢀ of 28
AD524
NOTES
Rev. F | Page 26 of 28
AD524
NOTES
Rev. F | Page 27 of 28
AD524
NOTES
©2±±7 Analog Devices, Inc0 All rights reserved0 Trademarks and
registered trademarks are the property of their respective owners0
D±±5±±-±-../±7(F)
Rev. F | Page 28 of 28
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