125932-HMC674LP3E [ADI]
9.3 GHz Latched Comparator;
| 型号： | 125932-HMC674LP3E |
| 厂家： | 
ADI |
| 描述： | 9.3 GHz Latched Comparator |
| 文件： | 总14页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
9.3 GHz Latched Comparator
with RSPECL Output Stage
HMC674LC3C/HMC674LP3E
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
HMC674LC3C/HMC674LP3E
Equivalent input bandwidth: 9.3 GHz typical
Propagation delay: 85 ps typical
Overdrive and slew rate dispersion: 10 ps typical
Input signal minimum pulse width: 60 ps typical
Resistor programmable hysteresis
Differential latch control
Power dissipation: 140 mW typical
VTP
INP
1
2
3
4
12
11
10
9
V
CCO
50Ω
50Ω
Q
Q
INN
VTN
V
CCO
16-terminal, 3 mm × 3 mm, ceramic leadless chip carrier (LCC)
16-lead lead frame chip scale package (LFCSP)
PACKAGE
BASE
V
EE
APPLICATIONS
Figure 1. HMC674LC3C/HMC674LP3E Functional Block Diagram
Automatic test equipment (ATE) applications
High speed instrumentation
Digital receiver systems
Pulse spectroscopy
High speed trigger circuits
Clock and data restoration
GENERAL DESCRIPTION
The HMC674LC3C/HMC674LP3E are silicon germanium
(SiGe), monolithic, ultrafast comparators that feature reduced
swing positive emitter-coupled logic (RSPECL) output drivers
and latch inputs. These comparators support 10 Gbps operation
and provide 85 ps propagation delay and an input signal
minimum pulse width of 60 ps with 0.2 ps rms of random jitter
(RJ). Overdrive and slew rate dispersion is typically 10 ps, making
the HMC674LC3C/HMC674LP3E ideal for a wide range of
applications from ATE to broadband communications. The
RSPECL output stages directly drive 400 mV into a 50 Ω resistor
terminated to VTT = (VCCO − 2.0 V), where VTT is the PECL
termination voltage (see Figure 16). The HMC674LC3C/
HMC674LP3E feature a high speed latch and programmable
hysteresis. These devices can operate in either latch mode or as
a tracking comparator.
Rev. K
Document Feedback
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Technical Support
©2016 Analog Devices, Inc. All rights reserved.
www.analog.com
HMC674LC3C/HMC674LP3E
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................6
Pin Configurations and Function Descriptions............................7
Interface Schematics .....................................................................8
Typical Performance Characteristics ..............................................9
Theory of Operation ...................................................................... 10
Power Sequencing ...................................................................... 10
Applications Information .............................................................. 11
Evaluation Printed Circuit Board (PCB)................................. 11
Application Circuits ................................................................... 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Latch Enable (LE/ ) Specifications ......................................... 3
LE
DC Output Specifications ........................................................... 3
AC Specifications.......................................................................... 4
Power Supply Specifications........................................................ 4
Timing Descriptions .................................................................... 5
Absolute Maximum Ratings............................................................ 6
REVISION HISTORY
Two Hittite Mircrowave product data sheets have been
reformatted to the styles and standards of Analog Devices, Inc.,
and combined into one data sheet.
12/2016—v12.0616 (HMC674LC3C and HMC674LP3E) to
Rev. K
Updated Format..................................................................Universal
Changes to Title, Features Section, and General Description
Section................................................................................................ 1
Changes to Table 7............................................................................ 6
Changes to Table 8............................................................................ 7
Changes to Figure 10........................................................................ 9
Changed Operational Description Section to Theory of
Operation Section........................................................................... 10
Changes to Figure 15 and Table 9................................................. 12
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 13
Rev. K | Page 2 of 14
Data Sheet
HMC674LC3C/HMC674LP3E
SPECIFICATIONS
TA = 25°C, VCCI = 3.3 V, VCCO = 2.0 V, VEE = −3 V, V TT = 0 V, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
INPUT
Voltage Range
−2
+2
V
Differential Voltage
Offset Voltage (VOS)
Temperature Coefficient
Bias Current
Temperature Coefficient
Offset Current
Impedance
Common-Mode
Differential
−1.75
+1.75
V
5
15
15
50
4
50
350
15
48
80
1
mV
µV/°C
µA
nA/°C
µA
Ω
kΩ
kΩ
dB
Active Gain
Common-Mode Rejection Ratio (CMRR)
Hysteresis, RHYS = Infinity
dB
mV
LATCH ENABLE (LE/ ) SPECIFICATIONS
LE
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
LATCH ENABLE (LE/LE)
Input Impedance
To Output Delay
Minimum Pulse Width
Input Range
8
85
20
kΩ
ps
ps
V
Each pin
tPLOL, tPLOH
tPL
Input overdrive voltage (VOD) = 200 mV
VOD = 200 mV
VOD = 200 mV
1.6
2.4
LATCH ENABLE (LE/LE) TIME
Setup
Hold
tS
tH
45
ps
ps
VOD = 200 mV
−42
DC OUTPUT SPECIFICATIONS
VCCO = 2.00 V, VTT = 0 V, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
OUTPUT VOLTAGE
High Level
Low Level
VOH
VOL
1.03
0.65
440
1.09
0.71
760
1.14
0.81
980
V
V
Differential Swing
mV p-p
Rev. K | Page 3 of 14
HMC674LC3C/HMC674LP3E
Data Sheet
AC SPECIFICATIONS
Table 4.
Parameter
Min Typ Max
Unit
ps
ps/°C
ps
Test Conditions/Comments
PROPAGATION DELAY (tPDL, tPD, tPDH
Temperature Coefficient
Skew (Rising to Falling Transition)
VOD 1 DISPERSION
)
80
85
0.45
10
10
8
110
VOD = 500 mV
VOD = 500 mV
ps
50 mV < VOD < 1 V
PROPAGATION DELAY (tPD) vs. INPUT COMMON-MODE VOLTAGE (VCM
DISPERSION
)
ps
VOD = 500 mV,
−1.75 V < VCM < +1.75 V
NOISE (RETURN TO INPUT, RTI)
EQUIVALENT INPUT BANDWIDTH (BWEQ)2
5.9
9.3
nV/√Hz
GHz
8.6
12
JITTER
10 Gbps with 100 mV overdrive
Deterministic
Random
2
0.2
60
ps p-p
ps rms
ps
INPUT SIGNAL MINIMUM PULSE WIDTH
VCM = 0 V, 100 mV overdrive
From 20% to 80%
Q/Q TIME
Rise
Fall
24
15
ps
ps
1 VOD is the input overdrive voltage, for example, (VINP − VINN − VOS), where VOS is the input offset voltage.
2 Equivalent input bandwidth is calculated by
BWEQ = 0.22/ (TRCOMP2 −TRIN 2 )
where:
TRIN is the 20%/80% transition time of a quasi Gaussian signal applied to the comparator input.
TRCOMP is the effective transition time digitized by the comparator.
POWER SUPPLY SPECIFICATIONS
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
VOLTAGE
Power Supply Voltage Input Stage
Power Supply Voltage Output Stage
Negative Power Supply (−3 V)
VCCI
VCCO
VEE
3.135
1.8
−3.15
3.3
3.3
−3.0
3.465
3.465
−2.85
V
V
V
CURRENT
Supply Input
Supply Output
VEE
ICCI
ICCO
IEE
9
mA
mA
mA
mW
45
19
140
POWER DISSIPATION
PD
POWER SUPPLY REJECTION RATIO
PSRR
VCCI
VEE
38
38
dB
dB
Rev. K | Page 4 of 14
Data Sheet
HMC674LC3C/HMC674LP3E
TIMING DESCRIPTIONS
Table 6.
Parameter
Symbol
Description
Input to Output High Delay
tPDH
The propagation delay measured from the time the input signal crosses the reference
( the input offset voltage) to the 50% point of an output low to high transition.
Input to Output Low Delay
tPDL
tPLOH
tPLOL
tH
The propagation delay measured from the time the input signal crosses the reference
( the input offset voltage) to the 50% point of an output high to low transition.
Latch Enable (LE/LE) to Output High Delay
Latch Enable (LE/LE) to Output Low Delay
Minimum Hold Time
The propagation delay measured from the 50% point of the latch enable (LE/LE)
signal high to low transition to the 50% point of an output low to high transition.
The propagation delay measured from the 50% point of the latch enable (LE/LE)
signal high to low transition to the 50% point of an output high to low transition.
The minimum time after the positive transition of the latch enable (LE/LE) signal
that the input signal must remain unchanged to be acquired and held at the outputs.
The minimum time that the latch enable (LE/LE) signal must be low to acquire an
input signal change.
Minimum Latch Enable (LE/LE) Pulse Width tPL
Minimum Setup Time
Output Rise Time
tS
The minimum time before the positive transition of the latch enable (LE/LE) signal
that an input signal change must be present to be acquired and held at the outputs.
The amount of time required to transition from a low to a high output as measured
at the 20% and 80% points.
tR
Output Fall Time
tF
The amount of time required to transition from a high to a low output as measured
at the 20% and 80% points.
Input Overdrive Voltage
VOD
The difference between the input voltages (VINP and VINN).
Timing Diagram
LATCH
TRACK
LATCH
TRACK
LATCH
LATCH ENABLE (LE)
50%
LATCH ENABLE (LE)
tPL
tS
tH
V
IN
DIFFERENTIAL
INPUT VOLTAGE
V
± V
OS
CM
V
OD
tPDL
tPLOH
Q OUTPUT
50%
50%
tF
tPDH
Q OUTPUT
tR
tPLOL
Figure 2. Timing Diagram
Rev. K | Page 5 of 14
HMC674LC3C/HMC674LP3E
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 7.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
Supply Voltage
Input (VCCI to GND)
Output (VCCO to GND)
Positive Differential (VCCI to VCCO
VEE Supply to GND
Input Voltage
−0.5 V to +4 V
−0.5 V to +4 V
−0.5 V to +3.3 V
−3.3 V to +0.5 V
−2 V to +2 V
)
Differential
−2 V to +2 V
−0.5 V to VCCI + 0.5 V
VEE to GND
ESD CAUTION
Latch Enable (LE/LE)
Applied Voltage (HYS)
Current
Maximum Input
Output
20 mA
40 mA
Continuous Power Dissipation (PDISS), TA = 85°C
Derate 43.5 mW/°C Above 85°C
(HMC674LP3E)
Derate 20.4 mW/°C Above 85°C
(HMC674LC3C)
Junction Temperature
Maximum Peak Reflow Temperature1
1.74 W
0.816 W
125°C
MSL1 and MSL3
260°C
Thermal Resistance (θJC)
HMC674LP3E
23°C/W
HMC674LC3C
49°C/W
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity, Human Body Model (HBM)
−65°C to +150°C
−40°C to +85°C
Class 1A
1 See the Ordering Guide section.
Rev. K | Page 6 of 14
Data Sheet
HMC674LC3C/HMC674LP3E
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VTP 1
INP 2
INN 3
VTN 4
12 V
CCO
VTP 1
INP 2
INN 3
VTN 4
12 V
CCO
HMC674LC3C
11 Q
10 Q
HMC674LP3E
11 Q
10 Q
TOP VIEW
TOP VIEW
(Not to Scale)
(Not to Scale)
9
V
CCO
9
V
CCO
PACKAGE
BASE
PACKAGE
BASE
V
V
EE
EE
NOTES
NOTES
1. NIC = NOT INTERNALLY CONNECTED. CONNECT
THIS PIN TO GROUND FOR IMPROVED NOISE.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
1. NIC = NOT INTERNALLY CONNECTED. CONNECT
THIS PIN TO GROUND FOR IMPROVED NOISE.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO V
.
CONNECTED TO V
.
EE
EE
Figure 3. HMC674LC3C Pin Configuration
Figure 4. HMC674LP3E Pin Configuration
Table 8. HMC674LC3C/HMC674LP3E Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
5, 16
6
VTP
INP
INN
VTN
VCCI
LE
Termination Resistor Return Pin for VP Input. See Figure 5 for the interface schematic.
Noninverting Analog Input. See Figure 5 for the interface schematic.
Inverting Analog Input. See Figure 5 for the interface schematic.
Termination Resistor Return Pin for VN Input. See Figure 5 for the interface schematic.
Positive Supply Voltage Input Stage. See Figure 6 for the interface schematic.
Latch Enable Input Pin, Inverting Side. See the Theory of Operation section for additional information. See
Figure 6 for the interface schematic.
7
LE
Latch Enable Input Pin, Noninverting Side. See the Theory of Operation section for additional information. See
Figure 6 for the interface schematic.
8
9, 12
10
NIC
VCCO
Q
Not Internally Connected. Connect this pin to ground for improved noise.
Positive Supply Voltage for the Output Stage. See Figure 7 for the interface schematic.
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, INP, is greater than the
analog voltage at the inverting input, INN, provided that the comparator is in track mode. See the Theory of
Operation section for additional information. See Figure 7 for the interface schematic.
11
Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, INP, is greater than the
analog voltage at the inverting input, INN, provided that the comparator is in track mode. See the Theory of
Operation section for additional information. See Figure 7 for the interface schematic.
13
14
VEE
HYS
Negative Power Supply, −3 V. See Figure 6 for the interface schematic.
Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect this pin to VEE with a resistor to add
the desired amount of hysteresis. See Figure 12 to determine the correct size of the RHYS hysteresis control resistor.
See Figure 8 for the interface schematic.
15
RTN
Return for ESD Protection.
EPAD
Exposed Pad. The exposed pad must be connected to VEE.
Rev. K | Page 7 of 14
HMC674LC3C/HMC674LP3E
Data Sheet
INTERFACE SCHEMATICS
VTP,
VTN
V
CCO
50Ω
INP,
INN
Q,
Q
Figure 5. VTP, VTN and INP, INN Interface Schematic
Q
Figure 7. Q, Interface Schematic
V
CCI
LE, LE
V
EE
HYS
Figure 8. HYS Interface Schematic
LE
Figure 6. , LE Interface Schematic
Rev. K | Page 8 of 14
Data Sheet
HMC674LC3C/HMC674LP3E
TYPICAL PERFORMANCE CHARACTERISTICS
11
15.0
12.5
10.0
7.5
RISING EDGE
RISING EDGE
FALLING EDGE
FALLING EDGE
9
7
5
5.0
2.5
3
0
1
–2.5
–5.0
–1
0
10
20
30
40
50
60
70
80
90
100
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
OVERDRIVE VOLTAGE (mV)
COMMON-MODE VOLTAGE (V)
Figure 9. Dispersion vs. Overdrive Voltage
Figure 11. Normalized Propagation Delay (tPD) vs. Common-Mode Voltage
2.8
2.6
2.4
2.2
2.0
1.8
15
V
V
OH
OL
10
5
0
100
–45 –32 –19
–6
7
20
33
46
59
72
85
1k
10k
TEMPERATURE (°C)
RESISTANCE (Ω)
Figure 10. Output Voltage vs. Temperature
Figure 12. Comparator Hysteresis vs. RHYS Control Resistance
Rev. K | Page 9 of 14
HMC674LC3C/HMC674LP3E
Data Sheet
THEORY OF OPERATION
The HMC674LC3C/HMC674LP3E are latched comparators
with a 9.3 GHz equivalent input bandwidth. These devices are
comprised of three blocks: an input amplifier, a latch, and an
output buffer. The latching circuit is level sensitive and consists
of a single, high speed latch. The HMC674LC3C/HMC674LP3E
comparators support 10 Gbps operation. The input signal
minimum pulse width is 60 ps.
POWER SEQUENCING
As long as the input signal is not near the −2 V extreme, either
CC or VEE can be powered on first. However, if the input voltage is
V
more negative than −1.8 V, use the following power-up sequence:
1. VEE
2.
3.
V
V
CCI and VCCO (if VCCO = VCCI
CCO (if different than ground)
)
The HMC674LC3C/HMC674LP3E operate in either track
(transparent) mode, where the output follows the logical value
of the input, or latch (hold) mode, where the output value is held
to the logical value of the comparison result of the input just
Note that the power-down sequence is the reverse of this
sequence.
It is recommended to power up the HMC674LC3C or the
HMC674LP3E before applying the input signal and to remove the
input signal prior to powering either down. These recommendations
are important if any of the inputs are more negative than −1.8 V.
prior to (LE − ) going high. Select track mode operation by
LE
either setting (LE − ) low or by floating the LE and
LE
Select latch mode by setting (LE − ) high. The input impedance
LE
inputs.
LE
of the LE and
inputs is 8 kΩ; however, these inputs can be
LE
terminated with 50 Ω external resistors, if desired.
When the clock inputs are dc-coupled, they operate at an input
common-mode voltage of 2 V. In this case, any termination
resistors ideally return to 2 V. If the clock inputs are ac-coupled
to the HMC674LC3C/HMC674LP3E, return the input
termination resistors to ground.
Rev. K | Page 10 of 14
Data Sheet
HMC674LC3C/HMC674LP3E
APPLICATIONS INFORMATION
the package ground leads must be connected directly to the ground
plane similar to that shown in Figure 15. Use a sufficient number
of via holes to connect the top and bottom ground planes to
provide good RF grounding to 10 GHz. The evaluation PCB shown
in Figure 13 is available from Analog Devices, Inc., upon request.
EVALUATION PRINTED CIRCUIT BOARD (PCB)
Figure 13 shows the front side of the evaluation PCB, and
Figure 14 shows the back side of the evaluation PCB.
The evaluation PCB used in the application must use RF circuit
design techniques. Signal lines must have 50 Ω impedance, and
Figure 13. Front Side of the Evaluation PCB
Figure 14. Back Side of the Evaluation PCB
Rev. K | Page 11 of 14
HMC674LC3C/HMC674LP3E
Data Sheet
APPLICATION CIRCUITS
See Figure 15 for the typical application circuit, Table 9 for the bill of materials, and Figure 16 for the output interfacing application circuit.
TP3
HYS
TP4
C6
100pF
J1
J1
V
V
CCI
EE
C13
4.7µF
C7
330pF
C5
100pF
C1
100pF
C4
330pF
C12
4.7µF
TP1
VTP
JP1
C8
100pF
C2
100pF
1
2
3
4
12
11
10
9
J2
J4
Q
50Ω
50Ω
INP
J3
INN
J5
Q
TP2
VTN
C3
JP2
100pF
C9
100pF
PACKAGE
BASE
J1
J1
V
CCO
V
CCI
C11
330pF
C14
4.7µF
V
EE
C10
100pF
J8
GND
V
EE
J6
LE
J7
LE
Figure 15. Typical Application Circuit
Table 9. Bill of Materials for the Evaluation PCB (125929-3)
Item
Description
Eight position vertical header
2.92 mm, 40 GHz jacks
J1
J2 to J7
J8
JP1, JP2
Terminal strip, single row, 3-pin surface mount (SMT)
Two position vertical header
C1 to C3, C5, C6, C8 to C10
100 pF capacitors, 0402 package
C4, C7, C11
C12 to C14
TP1 to TP4
U1
330 pF capacitors, 0402 package
4.7 µF tantalum capacitors
DC pin, swage mount test points
HMC674LC3C/HMC674LP3E comparator
125929-31 evaluation PCB, circuit board material is Rogers 4350 or Arlon 25FR
PCB
1 Reference this number when ordering complete evaluation PCB.
V
= +2.0V
CCO
OSCILLOSCOPE INPUT
50Ω
Q
Q
CH1
50Ω
V
CM_OUT
~0.9V
50Ω
CH2
GND (V
)
TT
50Ω
GND (V
)
TT
V
= –3.0V
EE
Figure 16. Output Interfacing Application Circuit, Output to Oscilloscope
Rev. K | Page 12 of 14
Data Sheet
HMC674LC3C/HMC674LP3E
OUTLINE DIMENSIONS
3.03
2.90 SQ
2.77
0.36
0.30
0.24
PIN 1
INDICATOR
PIN 1
13
16
(0.32 × 0.32)
1
12
0.50
BSC
1.60
EXPOSED
PAD
1.50 SQ
1.40
9
4
8
5
BOTTOM VIEW
TOP VIEW
SIDE VIEW
1.50
REF
2.10 BSC
0.92 MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SEATING
PLANE
SECTION OF THIS DATA SHEET.
Figure 17. 16-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-16-1)
Dimensions shown in millimeters
3.10
3.00 SQ
2.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
4
12
EXPOSED
PAD
1.950
1.725 SQ
1.500
9
8
5
0.45
0.40
0.35
0.20 MIN
TOP VIEW
BOTTOM VIEW
1.00
0.90
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT WITH JEDEC STANDARDS MO-220-VEED-4.
Figure 18. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.90 mm Package Height
(HCP-16-1)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package Body
Material
MSL
Package
Package
Option
Model1
Lead Finish
Rating2 Description
Branding
HMC674LC3C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Alumina, White
Alumina, White
Alumina, White
Gold over Nickel
MSL3
MSL3
MSL3
16-Terminal LCC
16-Terminal LCC
16-Terminal LCC
E-16-1
E-16-1
E-16-1
H674
XXXX
H674
XXXX
H674
XXXX
HMC674LC3CTR
Gold over Nickel
Gold over Nickel
HMC674LC3CTR-R5
Rev. K | Page 13 of 14
HMC674LC3C/HMC674LP3E
Data Sheet
Temperature
Range
Package Body
Material
MSL
Package
Package
Option
Model1
Lead Finish
Rating2 Description
Branding
HMC674LP3E
−40°C to +85°C
Low Stress,
Injection
Molded Plastic
Low Stress,
Injection
100% Matte Sn
MSL1
MSL1
16-Lead LFCSP
16-Lead LFCSP
HCP-16-1 H674
XXXX
HMC674LP3ETR
−40°C to +85°C
100% Matte Sn
HCP-16-1 H674
XXXX
Molded Plastic
125932-HMC674LC3C
125932-HMC674LP3E
HMC674LC3C
Evaluation Board
HMC674LP3E
Evaluation Board
1 The HMC674LC3C, the HMC674LC3CTR, the HMC674LC3CTR-R5, the HMC674LP3E, and the HMC674LP3ETR are RoHS Compliant Parts.
2 See the Absolute Maximum Ratings section.
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D14861-0-12/16(K)
Rev. K | Page 14 of 14
相关型号：
125933U7R5AC0B
Aluminum Electrolytic Capacitor, Polarized, Aluminum (wet), 7.5V, 75% +Tol, 10% -Tol, 93000uF, Chassis Mount, CAN, ROHS COMPLIANT
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125933U7R5AC1A
Aluminum Electrolytic Capacitor, Polarized, Aluminum (wet), 7.5V, 75% +Tol, 10% -Tol, 93000uF, Chassis Mount, CAN, ROHS COMPLIANT
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Aluminum Electrolytic Capacitor, Polarized, Aluminum (wet), 15V, 75% +Tol, 10% -Tol, 9600uF, Chassis Mount
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125968-1
Reasons for reissue of this instruction sheet are provided in Section 7, REVISION SUMMARY.
TE
125969-1
Reasons for reissue of this instruction sheet are provided in Section 7, REVISION SUMMARY.
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