ACT88326VA102-T [ACTIVE-SEMI]
Advanced PMU with Bypass Switch, & Pushbutton Function;
| 型号： | ACT88326VA102-T |
| 厂家： | 
ACTIVE-SEMI, INC |
| 描述： | Advanced PMU with Bypass Switch, & Pushbutton Function |
| 文件： | 总41页 (文件大小：4232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACT88326VA
Rev 1.0, 29-May-2018
Advanced PMU with Bypass Switch, & Pushbutton Function
BENEFITS and FEATURES
GENERAL DESCRIPTION
TheACT88326 PMIC is an integrated ActivePMU power
management unit. It is highly flexible and can be
reconfigured via I2C for multiple applications without the
need for PCB changes. The low external component
count and high configurability significantly speeds time
to market. Examples of configurable options include
output voltage, startup time, slew rate, system level
sequencing, switching frequency, sleep modes,
operating modes etc. The core of the device includes 3
DC/DC step down converters using integrated power
FETs, and 2 low-dropout regulators (LDOs). Each
regulator can be configured for a wide range of output
voltages through the I2C interface.
Wide input voltage range
o
Vin = 2.7V to 5.5V
Complete integrated power solution
o
One 4A DC/DC Step-Down with Bypass
Mode
o
o
o
Two 3A DC/DC Step-Down Regulators
Two 300mA LDOs
High Power Load Switch Gate Driver with
Slew Rate Control
Space Savings
o
Fully integrated
o
o
High Fsw = 2.25MHz or 1.125MHz
Integrated sequencing
ACT88326 is programmed at the factory with a default
configuration. The default settings can be optimized for
a specific design through the I2C interface. Contact the
factory for specific default configurations.
Easy system level design
o
Configurable sequencing
o
o
Seamless sequencing with external supplies
Programmable Reset and Power Good
GPIO’s
The ACT88326 includes features that allow flexibility for
all system level configurations. The buck converter can
be reconfigured as a bypass switch. It also contains a
high power load switch controller. It’s external power
supply enable and power good interface allows
seamless sequencing with external power supplies.
Buck 1 Bypass Mode for 3.3V system level
compliance
Highly configurable
o
µP interface for status reporting and con-
trollability
The ACT88326 PMIC is available in a 2.7 x 3 mm 36 pin
WLCSP package.
o
o
o
o
Flexible Sequencing Options
I2C Interface – 1MHz
Multiple Sleep Modes
See ACT88325 for non-Pushbutton Startup
APPLICATIONS
• Solid-State Drives
• Microcontroller Applications
• FPGA
• Personal Navigation Devices
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ACT88326VA
Rev 1.0, 29-May-2018
Typical Application Diagram
BUCK1 4A
BUCK2 3A
2.7V ~ 5.5V Input
BUCK3 3A
LDO1 300mA
LDO2 300mA
ACT88326
SOC
PG
External
DC/DC
ENABLE
PWREN
SCL
SDA
nRESET
IRQ
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ACT88326VA
Rev 1.0, 29-May-2018
FUNCTIONAL BLOCK DIAGRAM
Push Button
50kΩ
1kΩ
PushButton1/
On/Off
PushButton2/
Manual Reset
Input Rail
VIN
nPB
10µF
FB_B1
Vref
IO Supply
1µH
VIN_IO
Buck1
SW_B1
2x22µF
1µF
Controller
SCL
SDA
FB_B1
PGND
Digital
Core
Digital
GPIO1
Controller
Input Rail
VIN
GPIO2
GPIO3
10µF
FB_B2
Vref
1µH
Buck2/
Bypass
Controller
SW_B2
FB_B2
External EN
22µF
GPIO4
SMPS
PG
PGND
VIN
Load Switch Gate
Drives
LSG
Load
Input Rail
AVIN
Supply
1µF
10µF
Vref
FB_B3
Vref
1µH
LDO1
Buck3
SW_B3
FB_B3
Controller
1µF
22µF
FB
PGND
AGND
Vref
LDO2
1µF
ACT88326
FB
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ACT88326VA
Rev 1.0, 29-May-2018
ORDERING INFORMATION
PART NUMBER
VBUCK1
VBUCK2
VBUCK3
VLDO1
VLDO2
VLSG
PACKAGE
ACT88326VA102-T
0.85V
1.35V
3.0V
1.8V
3.0V
ON
CSP
ACT88326VAxxx-T
Product Number
Package Code
Pin Count
Option Code
Tape and Reel
Note 1: Standard product options are identified in this table. Contact factory for custom options, minimum order quantity required.
Note 2: All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means semiconductor
products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
Note 3: Package Code designator “V” represents CSP
Note 4: Pin Count designator “A” represents 36 pins
Note 5: “xxx” represents the CMI (Code Matrix Index) option. The CMI identifies the IC’s default register settings
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ACT88326VA
Rev 1.0, 29-May-2018
PIN CONFIGURATION
A
B
LDO1
C
D
E
F
1
2
3
4
5
6
7
FB_B3
VIN_B3
SW_B3
SW_B3
PGND3
AGND
SDA
AVIN
LDO2
nPB
FB_B2
VIN_B2
SW_B2
PGND12
SW_B1
VIN_B1
FB_B1
VIN_B3
LSG
VIN_B2
SW_B2
PGND12
SW_B1
VIN_B1
GPIO4
VIN_B2
SW_B2
PGND12
SW_B1
VIN_B1
VIN_IO
GPIO3
SCL
GPIO2
GPIO1
Figure 1: Pin Configuration – Top View (bumps down) CSP 36 Balls 2.7mm x 3mm
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ACT88326VA
Rev 1.0, 29-May-2018
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
A1
B1
FB_B3
LDO1
Feedback for Buck3 Regulator. Connect directly to the Buck3 output capacitor.
Output for LDO1 Regulator
C1
AVIN
Dedicated VIN Power Input for LDO1 & LDO2 Regulators and Analog VIN Input
Output for LDO2 Regulator
D1
LDO2
E1
nPB
Multi-purpose push-button input used to start the IC. This is the PWREN pin on the ACT88325.
Feedback for Buck2 Regulator. Connect directly to the Buck2 output capacitor.
Dedicated Buck3 VIN Power Input. Connect the Buck3 input caps directly to these pins
Load Switch Gate Driver Output
F1
FB_B2
VIN_B3
LSG
A2, B2
C2
D2, E2, F2
A3, A4
D3, E3, F3
D4, E4, F4
A5
VIN_B2
SW_B3
SW_B2
PGND12
PGND3
SW_B1
AGND
GPIO3 / nIRQ
GPIO2
VIN_B1
SDA
Dedicated Buck2 VIN Power Input. Connect the Buck2 input caps directly to these pins.
Switch Pin for Buck3 Regulator
Switch Pin for Buck2 Regulator
Power Ground for Buck1 and Buck2. Connect the Buck1 and Buck2 input caps directly to these pins.
Power Ground for Buck3. Connect the Buck3 input caps directly to these pins.
Switch Pin for Buck1 Regulator
D5, E5, F5
A6
Analog Ground
B6
General Purpose I/O Port 3. Typically configured as an interrupt (IRQ) open drain output.
General Purpose I/O Port 2. Can be configured for several different functions.
Dedicated Buck1 VIN Power Input. Connect the Buck1 input caps directly to these pins.
I2C Data Input and Output
C6
D6, E6, F6
A7
B7
SCL
I2C Clock Input
General Purpose I/O Port 1. Typically configured as a dynamic voltage scaling input or voltage select
input.
C7
GPIO1 / DVS
D7
E7
F7
GPIO4 / nRESET
VIN_IO
General Purpose I/O Port 4. Typically configured as an nRESET open drain output
Digital Input Reference Voltage Input
FB_B1
Feedback for Buck1 Regulator. Connect directly to the Buck1 output capacitor.
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ACT88326VA
Rev 1.0, 29-May-2018
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
UNIT
All Pins to PGND12 unless stated otherwise below
VIN_xx to PGND12
-0.3 to 6
V
V
V
V
V
V
V
V
-0.3 to 6
SW_Bx to PGND12
-0.3 to VIN_xx + 1
-0.3 to AVIN + 0.3
-0.3V to VIN_IO + 0.3
-0.3 to VIN_xx + 0.3
-0.3 to VIN_xx + 0.3
-0.3 to + 0.3
39
nPB to AGND
GPIOx to AGND
FB_Bx to PGND
LDOx to PGND
AGND to PGND12
Junction to Ambient Thermal Resistance (Note 2)
Junction to Case Thermal Resistance (Note 2)
Operating Junction Temperature
Storage Temperature
°C/W
°C/W
°C
6.5
-40 to 150
-55 to 150
°C
Note1: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect
device reliability.
Note2: Measured on Active-Semi Evaluation Kit
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ACT88326VA
Rev 1.0, 29-May-2018
DIGITAL I/O ELECTRICAL CHARACTERISTICS
(VIN_IO = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GPIO1, GPIO2, GPIO4 Input Low
GPIO3 Input Low
VIN_IO = 1.8V
VIN_IO = 1.8V
VIN_IO = 1.8V
VIN_IO = 3.3V
VIN_IO = 3.3V
VIN_IO = 3.3V
Output = 5V
IOL = 10mA
0.40
0.25
V
V
GPIO1, GPIO2, GPIO3, GPIO4 Input High
GPIO1, GPIO2, GPIO4 Input Low
GPIO3 Input Low
1.25
2.3
1.0
V
0.40
V
GPIO1, GPIO2, GPIO3, GPIO4 Input High
GPIO1, GPIO2, GPIO3, GPIO4 Leakage Current
GPIO1, GPIO2, GPIO4 Output Low
GPIO3 Output Low
V
1
µA
V
0.35
0.35
IOL = 1mA
V
VIN_IO-
0.35
GPIO1, GPIO2 Output High
IOH = 1mA
V
GPIO4 Deglitch Time (falling)
15
10
µs
µs
V
GPIO4 Deglitch Time (rising)
VIN_IO Operating Range
1.5
VIN
2
nPB external resistor for Push-button function
nPB external resistor for Manual Reset function
nPB internal pullup resistor
AVIN = 3.3V
AVIN = 3.3V
AVIN = 3.3V
50
1
kΩ
kΩ
MΩ
V
0.6
0.75
nPB Manual Reset (MR) rising threshold
Push button presses shorter than this
time are ignored
nPB De-bounce Time
32
ms
PB WAIT TIME SET[1:0] = 00
PB WAIT TIME SET[1:0] = 01
PB WAIT TIME SET[1:0] = 10
PB WAIT TIME SET[1:0] = 11
0.032
0.5
1.0
nPB Activation Time
(duration for successful turn-on)
s
2.0
Pull down through 50kΩ, press and
release for power cycle
nPB Power Cycle with Push Button
nPB Power Off with Push Button
4
6
s
s
Pull down through 50kΩ, press and
hold until power off occurs (CMI
configurable option)
Pull down through 1kΩ, starts soft
reset
nPB Soft Reset Time
0.032
4
4
s
s
Pull down through 1kΩ, starts power
cycle or Manual reset
nPB Power Cycle or Manual Reset Time
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ACT88326VA
Rev 1.0, 29-May-2018
SYSTEM CONTROL ELECTRICAL CHARACTERISTICS
(VIN_IO = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input Supply Voltage Range: AVIN referenced to
AGND
2.7
5.5
2.7
V
UVLO Threshold Falling
UVLO Hysteresis
2.5
100
2.7
5.4
80
2.6
V
mV
V
System Monitor (SYSMON) Programmable Range
OV Threshold Rising
4.2
6.0
5.75
200
10
V
OV Hysteresis
320
mV
µA
µA
°C
°C
Operating Supply Current
Operating Supply Current
Thermal Shutdown
All Regulators Disabled
All Regulators Enabled but no load
Temperature rising
250
160
30
140
180
200
Thermal Shutdown Hysteresis
Time from VIN > UVLO threshold to Internal
Power-On Clear (POR)
Power Up Delay after initial VIN
Startup Delay after initial VIN
120
µs
µs
Time from VIN > UVLO threshold to start of
first regulator turning On. (zero delay)
1500
2000
2.37
Oscillator Frequency
2.13
2.7
2.25
200
MHz
mV
VIN UV Interrupt Threshold Falling
Referenced to rising threshold
Rising edge threshold can power up device.
Configurable in 100mV steps.
VIN UV Threshold Rising Programming Range
3.6
4.2
V
VIN UV Shutdown Threshold Falling
VIN OV Shutdown Threshold Rising
VIN OV Shutdown Threshold Falling
VIN Deglitch Time UV
2.6
5.75
5.5
V
V
V
100
200
µs
µs
VIN Deglitch Time OV
Time from GPIOx pin transition to time when
the first regulator turns ON with minimum turn
on delay configuration.
Transition time from Deep Sleep (DPSLP) State to
Active State
1
ms
µs
µs
Time from I2C command to clear sleep mode
to time when the first regulator turns ON with
minimum turn on delay configuration.
Transition time from Sleep State (SLEEP) to Active
State
100
120
Time from turn Off event to when the first
power rail turns off with minimum turn off delay
configuration
Time to first power rail turn off
Startup Delay Programmable Range
ONDLY=00
ONDLY=01
ONDLY=10
ONDLY=11
0
0.25
0.5
1.0
ms
Turn Off Delay Programmable Range
nRESET Programmable Range
Configurable in 0.25ms steps
0
7.75
100
ms
ms
Configurable to 20, 40, 60 or 100ms.
20
Note 1: All Under-voltage Lockout, Overvoltage measurements are referenced to the AVIN Input and AGND Pins.
Note 2: All POK Under-voltage and Overvoltage measurements are referenced to the VIN Input and PGNDx Pins.
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ACT88326VA
Rev 1.0, 29-May-2018
INTERNAL STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS REGULATOR: (BUCK1)
(VIN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Input Operating Voltage Range
2.7
0.6
0.8
5.5
3.0
4.0
V
V
V
Output Voltage Programming Range 1
Output Voltage Programming Range 2
See CMI section for programming details
See CMI section for programming details
Standby Supply Current, Low Power Mode
Enabled
VOUT_B1 = 103% setpoint, Enabled, VOUT_B1
setpoint = 1.0V, No Load
40
60
1
µA
µA
Shutdown Current
Regulator Disabled
VOUT_B1 = default CMI voltage, continuous
PWM mode
Output Voltage Accuracy
Output Voltage Accuracy
Line Regulation
-1
-2
VNOM
VNOM
0.1
1
2
%
%
VOUT_B1 = default CMI voltage, PFM mode
VOUT_B1 = default CMI voltage, PWM Reg-
%/V
ulation
Load Regulation
VOUT_B1 = at default CM, PWM Regulation
VOUT_B1 Rising
0.1
92.5
3
%/A
Power Good Threshold
Power Good Hysteresis
Overvoltage Fault Threshold
Overvoltage Fault Hysteresis
90
95
%VNOM
%VNOM
%VNOM
%VNOM
VOUT_B1 Falling
VOUT_B1 Rising
107.5
110
3
112.5
VOUT_B1 Falling
1.125 /
2.25
Switching Frequency
Soft-Start Period Tset
VOUT_B1 ≥ 20% of VNOM, Configurable
10% to 90% VNOM
-5%
+5%
750
MHz
µs
480
ILIM[1:0] = 00
ILIM[1:0] = 01
ILIM[1:0] = 10
ILIM[1:0] = 11
4.2
3.6
3.0
2.4
5.4
4.7
3.8
3.1
6.6
5.7
4.6
3.7
Current Limit, Cycle-by-Cycle
(accuracy is only valid for the specific CMI’s
default setting)
A
% compared to Current Limit, cycle-by-
cycle
Current Limit, Shutdown
Current Limit, Warning
112.5
67.5
122.5
75
132.5
82.5
%
%
% compared to Current Limit, cycle-by-
cycle
PMOS On-Resistance
NMOS On-Resistance
ISW = -1A, VIN = 5.0V
ISW = 1A, VIN = 5.0V
VIN = 5.5V, VSW = 0V
VIN = 5.5V, VSW = 5.5V
40
16
50
25
1
mΩ
mΩ
µA
SW Leakage Current
1
µA
Dynamic Voltage Scaling Rate
Output Pull Down Resistance
3.50
4.4
mV/µs
Ohms
Enabled when regulator disabled
8.75
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ACT88326VA
Rev 1.0, 29-May-2018
INTERNAL STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS REGULATOR: (BUCK1) –
BYPASS MODE
(VIN = 3.3V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Input Voltage for By-Pass Mode
PMOS On-Resistance
2.7
3.3
0.04
4.2
5.5
0.06
5.4
V
Ω
A
ISW = -1A, VIN = 3.3V, Max=125°C at TJunction
Triggers Interrupt on IRQ Pin
Internal PMOS Current Detection
2.8
4.7
Internal PMOS Current Detection
Deglitch Time
10
6.5
5
µs
A
Internal PMOS Current Shutdown
Shuts down after deglitch time and stays off for Off-Time
VIN = 3.3V Input, Cout = 47uF, Default setting ISS[1:0]=00
8.7
Internal PMOS Current Shutdown
Deglitch Time
µs
Internal PMOS Current Shutdown Off-
Time (Retry time)
14
ms
µs
Internal PMOS Soft start
500
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ACT88326VA
Rev 1.0, 29-May-2018
INTERNAL STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS REGULATOR: (BUCK2/3)
(AVIN = VIN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
MIN
2.7
TYP
MAX
5.5
UNIT
V
Input Operating Voltage Range
Buck2 Output Voltage Programming
Range 1
See CMI section for programming details
See CMI section for programming details
See CMI section for programming details
0.6
3.0
V
Buck2 Output Voltage Programming
Range 2
0.8
0.8
4.0
4.0
V
V
Buck3 Output Voltage Programming
Range
Standby Supply Current, Low Power
Mode Enabled
VOUTx = 103%, Regulator Enabled, No load, VOUTx
default CMI voltage
=
40
0.1
µA
µA
V
Shutdown Current
VIN = 5.0V, Regulator Disabled
1
VOUTx = default CMI voltage, IOUTx = 1A (continuous
PWM mode)
Output Voltage Accuracy
-1%
VNOM
1%
Line Regulation
VOUTx = default CMI voltage, PWM Regulation
0.1
0.1
92.5
3
%
Load Regulation
VOUTx = default CMI voltage, PWM Regulation
%
Power Good Threshold
Power Good Hysteresis
Overvoltage Fault Threshold
Overvoltage Fault Hysteresis
VOUTx Rising
VOUTx Falling
VOUTx Rising
VOUTx Falling
90
95
%VNOM
%VNOM
%VNOM
%VNOM
107.5
110
3
112.5
1.125 /
2.25
Switching Frequency
VOUTx ≥ 20% of VNOM
-5%
+5%
750
MHz
Soft-Start Period Tset
Startup Time
10% to 90% VNOM
480
700
µs
µs
Time from Enable to PG
ILIM[1:0] = 00
ILIM[1:0] = 01
ILIM[1:0] = 10
ILIM[1:0] = 11
3.7
3.1
2.6
2.2
4.6
3.9
3.2
2.6
5.4
4.5
3.8
3.1
Current Limit, Cycle-by-Cycle
(accuracy is only valid for the specific
CMI’s default setting)
A
Current Limit, Shutdown
Current Limit, Warning
PMOS On-Resistance
NMOS On-Resistance
% compared to Current Limit, cycle-by-cycle
% compared to Current Limit, cycle-by-cycle
ISW_Bx = -500mA, VIN = 5V
112.5
67.5
122.5
75
132.5
82.5
%
%
80
mΩ
mΩ
µA
ISW_Bx = 500mA, VIN = 5V
50
VIN = 5.5V, VSW_Bx = 0 or 0V
1
1
SW Leakage Current
VIN = 5.5V, VSW_Bx = 0 or 5.5V
µA
Dynamic Voltage Scaling Rate
Output Pull Down Resistance
3.50
9.4
mV/us
Ω
Enabled when regulator disabled
20
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ACT88326VA
Rev 1.0, 29-May-2018
LDO1-2 ELECTRICAL CHARACTERISTICS
(AVIN = VIN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Operating Voltage Range LDO1
Output Voltage Range
AVIN (Input Voltage) to the LDO1
2.7
0.6
0.8
270
-1
5.5
V
V
Option 1 Configurable in 9.375mV steps
Option 2 Configurable in 12.5mV steps
2.991
3.9875
V
Output Current
300
mA
%
Output Voltage Accuracy
AVIN - VLDOx_OUT > 0.4V
VNOM
1
AVIN - VLDOx_OUT > 0.4V
ILDOx_OUT = 1mA
Line Regulation
Load Regulation
0.03
0.2
%
%
I
LDOx_OUT = 1mA to 100mA,
0.5
VLDOx_OUT = default CMI
f = 1kHz, ILDOx_OUT = 20mA,
VLDOx_OUT = 1.8V, Note 1
40.8
31.2
53.6
dB
dB
dB
f = 10kHz, ILDOx_OUT = 20mA,
VLDOx_OUT = 1.8V, Note 1
Power Supply Rejection Ratio
f = 2.25MHz, ILDOx_OUT = 20mA,
VLDOx_OUT = 1.8V, Note 1
Supply Current per Output
Supply Current
Regulator Disabled
1
µA
µA
Regulator Enabled, No load
Time from soft start “ON” to PGOOD. VLDOx = 1.8V
Time from soft start “ON” to PGOOD. VLDOx = 3.3V
VLDOx_OUT Rising
15
225
300
92.5
3
20
140
140
90
350
430
95
µs
Soft-Start Period
µs
Power Good Threshold
Power Good Hysteresis
Overvoltage Fault Threshold
Overvoltage Fault Hysteresis
Discharge Resistance
Dropout Voltage
% VNOM
% VNOM
% VNOM
% VNOM
Ω
VLDOx_OUT Falling
VLDOx_OUT Rising
105
110
3
115
VLDOx_OUT Falling
50
125
150
ILDOx_OUT = 220mA, VLDOx_OUT = 2.7V
mV
ILIM [1:0] = 00
ILIM [1:0] = 01
ILIM [1:0] = 10
ILIM [1:0] = 11
190
250
330
465
Output Current Limit
-35%
+35%
400
mA
µs
Startup Time
Time from Enable to PG
300
Note 1: AVIN- VLDOx_OUT > 0.4V
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LDO2 LOAD SWITCH MODE ELECTRICAL CHARACTERISTICS – BYPASS MODE
(AVIN = VIN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Operating Voltage Range LDO2
PMOS On-Resistance
AVIN (Input Voltage) to the LDO2
2.7
5.5
0.5
V
0.3
mΩ
Internal PMOS Current Detection
Triggers Interrupt on IRQ Pin
Load Switch Enabled, No load
330
330
500
10
mA
µs
Internal PMOS Current Detection De-
glitch Time
Supply Current
25
55
µA
mA
Shuts down after deglitch time and stays off for Off-
Time
Internal PMOS Current Shutdown
500
Internal PMOS Current Shutdown
Deglitch Time
5
µs
Internal PMOS Current Shutdown Off
time (Retry time)
14
ms
Only used with 3.3V Input, Cout = 1uF, Default Setting
ISS [1:0] = 00.
Internal PMOS Soft start
10
mV/ µs
LOAD SWITCH GATE DRIVER ELECTRICAL CHARACTERISTICS
(VIN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Operating Voltage Range
2.7
5.5
V
V
Maximum Output - Gate Voltage
Gate fully on
2*VIN
800
400
260
200
Gate Node rising from 0 to 2V with 1nF output capaci-
tor. (Configurable)
Soft-Start Slew Rate
Gate Pull-up Current
us
µA
µA
µA
µA
µs
Ω
GATE1 SLEW = 00
GATE1 SLEW = 01
GATE1 SLEW = 10
GATE1 SLEW = 11
2.5
5
7.5
10
Fault Deglitch Time
Gate Discharge Resistance
Startup Delay
10
75
75
µs
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I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VIN_IO = 1.8V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SCL, SDA Input Low
SCL, SDA Input High
SCL, SDA Input Low
SCL, SDA Input High
SDA Leakage Current
VIN_IO = 1.8V
VIN_IO = 1.8V
VIN_IO = 3.3V
VIN_IO = 3.3V
SDA=5V
0.4
V
V
1.25
2.3
1.0
V
V
1
µA
SDA Output Low
IOL = 5mA
0.35
1000
V
SCL Clock Frequency, fSCL
SCL Low Period, tLOW
0
kHz
µs
0.5
SCL High Period, tHIGH
0.26
µs
SDA Data Setup Time, tSU
SDA Data Hold Time, tHD
Start Setup Time, tST
50
0
ns
ns
ns
ns
pF
ns
(Note1)
For Start Condition
For Stop Condition
260
260
Stop Setup Time, tSP
Capacitance on SCL or SDA Pin
SDA Fall Time SDA, Tof
10
Device requirement
120
Pulse Width of spikes must be suppressed
on SCL and SDA
0
50
ns
Note1: Comply with I2C timings for 1MHz operation - “Fast Mode Plus”.
Note2: No internal timeout for I2C operations, however, I2C communication state machine will be reset when entering Deep Sleep, Sleep,
OVUVFLT, and THERMAL states to clear any transactions that may have been occurring when entering the above states.
Note3: This is an I2C system specification only. Rise and fall time of SCL & SDA not controlled by the device.
Note4: Device Address is factory configurable to 7’h25, 7’h27, 7’h67, 7’h6B.
tSCL
SCL
tST
tHD
tSU
tSP
SDA
Start
Stop
condition
condition
Figure 2: I2C Data Transfer
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SYSTEM CONTROL INFORMATION
There is no timeout function in the I2C packet pro-
cessing state machine, however, any time the I2C state
machine receives a start bit command, it immediately
resets the packet processing, even if it is in the middle
of a valid packet. The I2C functionality is operational in
all states except RESET.
General
The ACT88326 is a single-chip integrated power man-
agement solution designed to power many processors
such as the Silicon Motion SM2258/59/62/63/63XT
solid state drive controllers and the Atmel SAMA5D pro-
cessors. It integrates three highly efficient buck regula-
tors, two LDOs, and an integrated load bypass switch.
Its high integration and high switching frequency result
in an extremely small footprint and low cost power solu-
tion. It contains a master controller that manages
startup sequencing, timing, voltages, slew rates, sleep
states, and fault conditions. I2C configurability allows
system level changes without the need for costly PCB
changes. The built-in load bypass switch enables full
sequencing configurability in 3.3V systems.
I2C commands are communicated using the SCL and
SDA pins. SCL is the I2C serial clock input. SDA is the
data input and output. SDA is open drain and must have
a pull-up resistor. Signals on these pins must meet
timing requirements in the Electrical Characteristics
Table.
I2C Registers
The ACT88326 contains an array of internal registers
that contain the IC’s basic instructions for setting up the
IC configuration, output voltages, sequencing, fault
thresholds, fault masks, etc. These registers are what
give the IC its operating flexibility. The two types of
registers are described below.
The ACT88326 master controller monitors all outputs
and reports faults via I2C and hardwired status signals.
Faults can be masked and fault levels and responses
are configurable via I2C.
Many of the ACT88326 pins and functions are configu-
rable. The IC’s default functionality is defined by the de-
fault CMI (Code Matrix Index), but much of this function-
ality can be changed via I2C. Several GPIOs can be
configured as enable inputs, reset outputs, dynamic
voltage (DVS) inputs, LED drivers, etc. The GPIO con-
figuration is specifically defined for each ACT88326 or-
derable part number. The first part of the datasheet de-
scribes basic IC functionality and default pin functions.
The end of the datasheet provides the configuration and
functionality specific to each CMI version. Contact
sales@active-semi.com for additional information about
other configurations.
Basic Volatile – These are R/W (Read and Write) and
RO (Read only). After the IC is powered, the user can
modify the R/W register values to change IC
functionality. Changes in functionality include things like
masking certain faults. The RO registers communicate
IC status such as fault conditions. Any changes to these
registers are lost when power is recycled. The default
values are fixed and cannot be changed by the factory
or the end user.
Basic Non-Volatile – These are R/W and RO. After the
IC is powered, the user can modify the R/W register
values to change IC functionality. Changes in
functionality include things like output voltage settings,
startup delay time, and current limit thresholds. Any
changes to these registers are lost when power is
recycled. The default values can be modified at the
factory to optimize IC functionality for specific
applications. Please consult sales@active-semi.com for
custom options and minimum order quantities.
I2C Serial Interface
To ensure compatibility with a wide range of systems,
the ACT88326 uses standard I2C commands. The
ACT88326 operates as a slave device, and can be fac-
tory configured to one of four 7-bit slave addresses. The
7-bit slave address is followed by an eighth bit, which
indicates whether the transaction is a read-operation or
a write-operation. Refer to each specific CMI for the IC’s
slave address
When modifying only certain bits within a register, take
care to not inadvertently change other bits.
Inadvertently changing register contents can lead to
unexpected device behavior.
7-Bit Slave Address
8-Bit Write
Address
0x4Ah
0x4Eh
0xCEh
8-Bit Read
Address
0x4Bh
0x4Fh
0xCFh
0x25h
0x27h
0x67h
0x6Bh
010 0101b
010 0111b
110 0111b
110 1011b
State Machine
0xD6h
0xD7h
Figure 1 shows the ACT88326 internal state machine.
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POWER OFF State
ACTIVE State
The POWER OFF state is a PMIC “safe state” or “shut-
down” state. In this state, all the regulator outputs are
turned off. LDO1 has the option to be configured as an
“always-on” regulator so it stays on in the POWER OFF
state.
The ACTIVE state is the normal operating state when
the input voltage is within the allowable range, all out-
puts are turned on, and no faults are present.
The ACT88326 enters the ACTIVE state from POWER
SEQUENCE START with a normal nPB startup, an I2C
startup, or a power cycle sequence.
The ACT88326 enters POWER OFF at initial power on
when input power is applied to the IC and VIN is within
a valid range defined by the VIN_UV and VIN_OV
thresholds. nRESET is asserted low and all volatile and
non-volatile registers are reset to defaults. If the input
voltage drops below the VIN_UV threshold voltage, the
IC transitions from any other state to the POWER OFF
state. It is important to note a transition to POWER OFF
due to VIN_UV returns all volatile and non-volatile reg-
isters to their default states.
It transitions from the THERMAL state directly to the
ACTIVE state when the die temperature drops back to
allowable limits. Note that when the outputs turn back
on during this transition, any outputs sequencing de-
pendent on VIN will turn on immediately. Any outputs
dependent on another output turn on with proper pro-
grammed delays.
SLEEP State
The SLEEP state is a low power mode for the operating
system. Each output can be programmed to be on or off
in the SLEEP state. The outputs follow their pro-
grammed sequencing delay times when turning on or
off as they enter or exit the SLEEP state. Buck1/2/3 can
be programmed to regulate to their VSET0 voltage,
VSET1 voltage, or be turned off in the SLEEP state.
LDO1/2 can be programmed to regulate to their VSET0
voltage or can be programmed to be turned off. Note
that LDO1/2 do not have a VSET1 voltage.
The ACT88326 can also enter POWER OFF from any
other state due to an nPB press that initiates the power
off sequence.
The ACT88326 momentarily enters POWER OFF dur-
ing a power cycle sequence.
The ACT88326 exits the POWER OFF state when the
I2C bit POWER OFF is cleared to 0, or the nPB pin is
pulled low for > 32ms.
The IC enters SLEEP state via I2C register bit SLEEP,
I2C register bit SLEEP MODE, and a GPIO input pin.
The IC’s specific CMI determines the specific combina-
tion of these three inputs to enter SLEEP state. The I2C
bit SLEEP MODE is set at factory and cannot be
changed by the user. It controls the logical combination
of the GPIO input and the SLEEP register bit to enter
SLEEP state.
POWER SEQUENCE START State
The POWER SEQUENCE START state is a transitional
state to power on the regulators. The IC is not intended
to operate in this state. When entering POWER SE-
QUENCE START from the SLEEP, DPSLP, and THER-
MAL states the IC transitions to the ACTIVE state when
all regulators are in regulation.
When entering POWER SEQUENCE START from the
POWER OFF state due to an nPB press, the IC remains
in POWER SEQUENCE START until nPB is released
AND the regulators are in regulation. If nPB is released
before the regulators are in regulation, the IC transitions
back to the POWER OFF state. If nPB is still pressed
and the regulators enter regulation and one of them has
a fault before nPB is released, the IC transitions back to
the POWER OFF state.
When SLEEP MODE is factory configured to 1, the log-
ical combination is an “OR” function and when SLEEP
MODE is factory configured to a 0, the logical combina-
tion is an “AND” function.
If no GPIOs are configured as a control input to enter
and exit SLEEP state then only the SLEEP register bit
controls the entry and exit of the SLEEP state.
Tables 1a and 1b shows the conditions to enter SLEEP
state. ACT88326’s I2C stays enabled in SLEEP state.
The IC exits the SLEEP state when the conditions to
enter SLEEP state are no longer present. Asserting nPB
low for > 32ms clears the SLEEP bit to 0 and the PMIC
exits SLEEP state.
When entering POWER SEQUENCE START from the
POWER OFF state due to a power cycle sequence, the
IC stays in POWER SEQUENCE START for 0.5s before
exiting to the ACTIVE state.
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be changed by the user. It controls the logical combina-
tion of the GPIO input and the DPSLP register bit to en-
ter DPSLP state.
When DPSLP MODE is factory configured to 1, the log-
ical combination is an “OR” function and when DPSLP
is factory configured to a 0, the logical combination is an
“AND” function.
If no GPIOs are configured as a control input to enter
and exit DPSLP state then only the DPSLP register bit
controls the entry and exit of the DPSLP state.
Table 2a and 2b show the conditions to enter DPSLP
state. ACT88326’s I2C stays enabled in DPSLP state.
The IC exits the DPSLP state when the conditions to
enter DPSLP state are no longer present. Asserting
nPB low for > 32ms clears the DPSLP bit to 0 and the
PMIC exits DPSLP state.
Table 1a. SLEEP Mode Truth Table (SLEEP MODE bit
is configured to 0)
Table 1b. SLEEP Mode Truth Table (SLEEP MODE bit
is configured to 1)
Table 2a. DPSLP Mode Truth Table (DPSLP MODE
factory bit is configured to 0)
DPSLP State
The DPSLP state is another low power operating mode
for the operating system. It is intended to be used in a
lower power configuration than the SLEEP mode. It is
similar to the SLEEP state, but DPSLP uses slightly dif-
ferent configurations to enter and exit this mode. Each
output can be programmed to be on or off in the DPSLP
state. This programming can be different and independ-
ent from the SLEEP state. The outputs follow their pro-
grammed sequencing delay times when turning on or
off as they enter or exit the DPSLP state.
The IC can enter DPSLP state via I2C register bit
DPSLP, I2C register bit DPSLP MODE, and a GPIO in-
put pin. The IC’s specific CMI determines the specific
combination of these three inputs to enter DPSLP state.
The I2C bit DPSLP MODE is set at factory and cannot
Table 2b. DPSLP Mode Truth Table (DPSLP MODE
factory bit is configured to 1)
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SLEEP
THERMAL
POWER SEQUENCE
START
ACTIVE
POWER OFF
DPSLP
(Deep Sleep)
Power Cycle (Red dashed line) automatically transitions
from ACTIVE to POWER OFF to POWER SEQENCE
START and back to ACTIVE state.
Figure 3: Pushbutton State Machine
THERMAL State
In the THERMAL state the chip has exceeded the ther-
mal shutdown temperature. To protect the device, all
the regulators are shut down and the reset pins are as-
serted low. This state can be disabled by setting register
0x01h bit5 (TMSK) = 1. TMSK prevents the interrupt
from going active, but does not prevent the IC from en-
tering the THERMAL State. The IC transitions directly
back to the ACTIVE state when the die temperature
cools down.
Startup/Shutdown
When power is applied, the IC enters the POWER OFF
state and stays there indefinitely. This results in a very
low power state. The IC starts up and sequences on the
regulators when the user actively initiates a power on by
either asserting nPB or by writing a 0 into the I2C
POWER OFF bit. When powering on with the nPB pin,
any fault that occurs before nPB is released transitions
the IC back to the POWER OFF state. Any faults that
occur after nPB is released and the IC is in the ACTIVE
state are handled per the proper fault detection proce-
dure as programmed by the IC’s specific CMI. Once in
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the ACTIVE state, the IC can stay in that state or auto-
matically transition to either the SLEEP or DPSLP state
depending on the status of the inputs in Tables 1 and 2.
turn off. Each output’s turn-off delay is configured via its
I2C bit OFF DELAY. Turn-off delays can be changed
after the IC is powered on, but they are volatile and reset
to the factory defaults when power is recycled.
Shutdown is typically accomplished by forcing the sys-
tem to transition to the DPSLP state. Shutdown can also
be accomplished with the nPB pin or by setting the I2C
POWER OFF bit to a 1.
Softstart Time. The softstart time is the time it takes an
output to ramp from 10% to 90% of its programmed
voltage. All buck converter softstart times are controlled
by a single I2C bit ALL_BUCKS_FASTER_SS. When
set to 0, the softstart times are 600µs. When set to 1,
the softstart times are 250µs. The default softstart time
can be changed after the IC is powered on, but it is
volatile and resets to the factory defaults when power is
recycled.
Sequencing
The ACT88326 provides the end user with extremely
versatile sequencing capability that can be optimized for
many different applications. Each of the five outputs has
four basic sequencing parameters: input trigger, turn-on
delay, turn-off delay, and output voltage. The buck
converters also have softstart time control. Each of
these parameters is controlled via the ICs internal
registers. The specifics for this IC as well as others are
detailed at the end of the datasheet. Contact
sales@active-semi.com for custom sequencing
configurations. Refer to the Active-Semi Application
Note AN111, ACT88326VA102 Register Definitions, for
full details on the I2C register map functionality and
programming ranges.
Output Voltage. The output voltage is each regulator’s
desired voltage. Each buck’s output voltage is
programmed via its I2C bits VSET0 and VSET1. The
output regulates to VSET0 in ACTIVE mode. They can
be programmed to regulate to VSET1 in DVS, SLEEP,
and DSPSLP modes. Each LDO has a single register,
VSET, to set its output voltage. Each output’s voltage
can be changed after the IC is powered on, but the new
setting is volatile and is reset to the factory defaults
when power is recycled. Output voltages can be
changed on the fly. If a large output voltage change is
required, it is best to make multiple smaller changes.
This prevents the IC from detecting an instantaneous
over or under voltage condition because the fault
thresholds are immediately changed, but the output
takes time to respond.
Input trigger. The input trigger for a regulator is the
event that turns that regulator on. Each output can have
a separate input trigger. The input trigger can be the
internal power ok (POK) signal from one of the other
regulators, the internal VIN POK signal, or an external
signal applied to an input pin such as EXT_PG or GPIO.
This flexibility allows a wide range of sequencing
possibilities, including having some of the outputs be
sequenced with an external power supply or a control
signal from the host. As an example, if the LDO1 input
trigger is Buck1, LDO1 will not turn on until Buck1 is in
regulation. Input triggers are defined at the factory and
can only be changed with a custom CMI configuration.
The GPIOx outputs can be connected to an internal
power supply’s POK signal and used to trigger external
supplies in the overall sequencing scheme. The GPIOx
inputs can also be connected to an external power
supply’s power good output and used as an input trigger
for an ACT88326 supply.
Dynamic Voltage Scaling
On-the-fly dynamic voltage scaling (DVS) for the three
buck converters is available via either the I2C interface
or a GPIO. DVS allows systems to save power by
quickly adjusting the microprocessor performance level
when the workload changes. Note that DVS is not a
different operating state. The IC operates in the ACTIVE
state, but just regulates the outputs to a different voltage.
Each buck converter operates at its VOUT0 voltage in
normal operation and operates at its VOUT1 voltage
when the DVS input trigger is active. DVS can be
implemented three ways.
Turn-on Delay. The turn-on delay is the time between
an input trigger going active and the output starting to
turn on. Each output’s turn-on delay is configured via its
I2C bit ON DELAY. Turn-on delays can be changed after
the IC is powered on, but they are volatile and reset to
the factory defaults when power is recycled.
The first method is to individually put each buck
converter in DVS by manually writing a new voltage
regulation setpoint into its VOUT0 register.
DVS can also be implemented for all buck converters at
one time via a single GPIO input. The IC’s specific CMI
determines the specific GPIO used for DVS. This setting
can be modified with a custom CMI.
Turn-off Delay. The turn-off delay is the time between
an input trigger going inactive and the output starting to
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DVS can be implemented for all buck converters at one
time via I2C. The user can select from two different
configurations to enter DVS via I2C. Note that DVS is
disabled when EN_DVS_I2C = 0.
input voltage drops below UVLO. I2C bit VSYSSTAT =
1 when VINx < SYSMON and 0 when VINx > SYSMON.
This fault can be masked with I2C bit VSYSMSK.
Fault Protection
1. Enable DVS via a single I2C write to
I2C_DVS_ON bit: With EN_DVS_I2C = 1
and SEL_DVS_IN = 0, the IC enters DVS
when I2C_DVS_ON = 1 and exits DVS
when it equals 0.
The ACT88326 contains several levels of fault protec-
tion, including the following:
Output Overvoltage
Output Undervoltage
Output Current Limit and short circuit
Thermal Warning
2. Enable DVS whenever the IC enters
SLEEP state: With EN_DVS_I2C = 1 and
SEL_DVS_IN = 1, any condition that puts
the IC into SLEEP state also puts the IC
into DVS mode. Note that I2C_DVS_ON bit
does not affect this configuration.
Thermal Shutdown
There are three types of I2C register bits associated with
each fault condition: fault flag bits, fault bits, and mask
bits. The fault flag bits display the real-time fault status.
Their status is valid regardless of whether or not that
fault is masked. The mask bits either block or allow the
fault to affect the fault bit. Each potential fault condition
can be masked via I2C if desired. Any unmasked fault
condition results in the fault bit going high, which asserts
the nIRQ pin. nIRQ is typically active low. The nIRQ pin
only de-asserts after the fault condition is no longer pre-
sent and the corresponding fault bit is read via I2C. Note
that masked faults can still be read in the fault flag bit.
Refer to Active-Semi Application Note describing the
Register Map for full details on I2C functionality and pro-
gramming ranges.
Note that the IC cannot be configured to enter DVS in
DPSLP state. Table 3 summarizes I2C DVS functionality.
EN_DVS_I2C
0
SEL_DVS_IN I2C_DVS_ON
DVS MODE
Off
x
0
0
1
x
0
1
x
1
1
1
Off
On
On in SLEEP
state
Table 3. I2C DVS Control
nIRQ (Interrupt)
For fault free operation, the user must ensure output
load conditions plus the current required to charge the
output capacitance during a DVS rising voltage
condition does not exceed the current limit setting of the
regulator. As with any power supply, changing an output
voltage too fast can require a current higher than the
current limit setting. The user must ensure that the
voltage step, slew rate, and load current conditions do
not result in an instantaneous loading that results in a
current limit condition.
The interrupt function is typically used to drive the inter-
rupt input of the system processor. Many of the
ACT88326's functions support interrupt-generation as a
result of various conditions. These are typically masked
by default, but may be unmasked via the I2C interface.
For more information about the available fault condi-
tions, refer to the appropriate sections of this datasheet.
nIRQ can be triggered from:
1. Die temperature warning generated
2. Any buck regulator exceeding peak current limit
for 16 cycles after soft start or a UV/OV condi-
tion.
Input Voltage Monitoring (SYSMON)
The ACT88326 monitors the input voltage on the VINx
pins to ensure it is within specified limits for system level
operation. The IC “wakes up” and allows I2C communi-
cation when VINx rises above UVLO (~2.7V). However,
the outputs do not turn on until VINx rises above the
SYSMON threshold. SYSMON is programmable be-
tween 2.7V and 4.2V. The IC then asserts the nIRQ pin
if VINx drops below SYSMON, but the outputs continue
to operate normally. The IC turns off all outputs if the
3. Any LDO regulator exceeding current limit for
more than 16uS after soft start or a UV/OV con-
dition.
4. Input goes above OVP threshold or falls below
the UV threshold.
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5. nPB being asserted low. The PB status register
bit and PB counter register can be used to
check the nPB time and take appropriate action.
an UV/OV fault condition, the IC shuts down all outputs
for 100ms and restarts with the programmed power up
sequence. If an output is in current limit, it is possible
that its voltage can drop below the UV threshold which
also shuts down all outputs. If that behavior is not
desired, mask the appropriate fault bit. Each output still
provides its real-time UV/OV fault status via its fault flag,
even if the fault is masked. Masking an OV/UV fault just
prevents the fault from being reported via the IRQ pin.
A UV/OV fault condition pulls the nRESET pin low. Note
that the IC’s specific CMI sets the defaults for which
regulators mask the UV and OV fault conditions.
If any of these faults occur the nIRQ output is asserted
active low. After nIRQ pin is asserted, an I2C reading
operation of the interrupt status registers clears the in-
terrupt provided the interrupting condition is removed. If
the interrupting condition is still present, nIRQ stays as-
serted and the interrupt status bit stays set.
The ICs specific CMI determines which GPIOx is used
for the nIRQ pin. nIRQ is an open-drain output and
should be pulled up to an appropriate supply voltage
with a 10kΩ or greater pull-up resistor.
Output Current Limit
nRESET
The ACT88326 incorporates a three level overcurrent
protection scheme for the buck converters and a single
level scheme for the LDOs. For the buck converters, the
overcurrent current threshold refers to the peak switch
current. The first protection level is when a buck
converter’s peak switch current reaches 75% of the
Cycle-by-Cycle current limit threshold for greater than
16 switching cycles. Under this condition, the IC reports
the fault via the appropriate fault flag bit. If the fault is
unmasked, it asserts the nIRQ pin. The next level is
when the current increases to the Cycle-by-Cycle
threshold. The buck converter limits the peak switch
current in each switching cycle. This reduces the
effective duty cycle and causes the output voltage to
drop, potentially creating an undervoltage condition.
When the overcurrent condition results in an UV
condition, and UV is not masked, the IC turns off all
supplies for 100ms and restarts. The third level is when
the peak switch current reaches 122% of the Cycle-by-
Cycle current limit threshold. This immediately shuts
down the regulator and waits 14ms before restarting.
The ACT88326 provides a reset function to issue a
master reset to the system CPU/controller. nRESET is
immediately asserted low when either the VIN voltage
is above or below the UV or OV thresholds or any power
supply that is connected to the nRESET functionality
goes below its Power Good threshold. The IC’s specific
CMI configures which power supplies are connected to
the nRESET functionality. After startup, nRESET de-as-
serts after a programmable delay time when VIN and all
connected power supply outputs are above their re-
spective UVLO thresholds. The reset delay time, 20ms
to 100ms, is controlled by the I2C TRST_DLY register
bits. The IC’s CMI programs the specific GPIOx pin
used for the reset functionality. The CMI also programs
which regulators outputs are monitored for the reset
functionality.
EXT_EN
The ACT88326 provides an external input trigger,
EXT_PG, for startup sequencing. EXT_PG can be used
as the startup trigger for one or of the power supplies.
EXT_EN and EXT_PG allow the IC to fully incorporate
one or more external power supplies into the startup se-
quence. The IC’s CMI programs the specific GPIOx pin
used for the EXT_EN functionality.
For LDOs, the overcurrent thresholds are set by each
LDO’s Output Current Limit setting. When the output
current reaches the Current Limit threshold, the LDO
limits the output current. This reduces the output
voltage, creating an undervoltage condition, causing all
supplies to turn off for 100ms before restarting.
EXT_PG
The ACT88326 provides an external input trigger,
EXT_PG, for startup sequencing. EXT_PG can be used
as the startup trigger for one or of the power supplies.
EXT_EN and EXT_PG allow the IC to fully incorporate
one or more external power supplies into the startup se-
quence. The IC’s CMI programs the specific GPIOx pin
used for the EXT_EN functionality.
The overcurrent fault limits for the buck converters are
adjustable via I2C. LDO current limit is fixed.
Overcurrent fault reporting can be masked via I2C, but
the overcurrent limits are always active and will shut
down the IC when exceeded.
Thermal Warning and Thermal Shutdown
Output Under/Over Voltage
The ACT88326 monitors its internal die temperature
and reports a warning via nIRQ when the temperature
The ACT88326 monitors the output voltages for under
voltage and over voltage conditions. If an output enters
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rises above the Thermal Interrupt Threshold of typically
135 deg C. It reports a fault when the temperature rises
above the Thermal Shutdown Temperature of typically
160 deg C. A temperature fault transitions the IC to the
THERMAL state and shuts down all outputs unless the
fault is masked. Both the fault and the warning can be
masked via I2C. The temperature warning and fault
flags still provide real-time status even if the faults are
masked. Masking just prevents the faults from being re-
ported via the nIRQ pin.
the I2C bit PB WAIT TIME SET. After the programed time,
the IC enters the ACTIVE state and operates normally.
If nPB is deasserted before the required time, the IC
automatically turns all outputs off and goes back to the
POWER OFF state. If a fault is detected before nPB is
released, the IC automatically turns all outputs off and
goes back to the POWER OFF state. Note that nPB can
be asserted indefinitely, but the IC does enter the
ACTIVE state until it is released.
Power Cycle1 – This sequence momentarily turns all
outputs off and automatically restarts them. Initiate
Power Cycle1 by momentarily pulling nPB to ground
through a 50kΩ resistor for >4s. When nPB transitions
back high, the IC transitions from its current operating
state to the POWER OFF state for 0.5s. It then
transitions to the POWER SEQUENCE START state for
0.5s before going to the ACTIVE state. Note that I2C
register bit EN_PB_PWRCYCL must be set to 1 to
enable the Power Cycle1 function. If nPB is pulled low
for <4s, no action is taken.
Pin Descriptions
Many of the ACT88326 input and output pins are con-
figurable via CMI configurations. The following descrip-
tions are refer to basic pin functions and capabilities.
Refer to the CMI Options section in the back of the
datasheet for specific pin functionality for each CMI.
VIN_Bx
VIN_Bx pins are the dedicated input power to the buck
converters. Each buck converter must be bypassed di-
rectly to its PGNDx pin on the top PCB layer with a 10uF
capacitor.
Power Off – This sequence turns all outputs off, and
they stay off until the user actively initiates a Power On
sequence. Initiate Power Off by pulling nPB to ground
through a 50kΩ resistor for >6s. After 6s, the IC
transitions from its current operating state to the
POWER OFF state and turns all outputs off. Once in the
POWER OFF state and nPB is released high, the IC
follows normal programmed functionality to leave
POWER OFF. Note that I2C register bit
EN_PB_PWROFF must be set to 1 to enable the Power
Off function. If nPB is pulled low for <6s, no action is
taken.
AVIN
AVIN is the input power to the LDOs. It also powers the
IC’s analog circuitry. AVIN must be bypassed directly to
AGND on the top PCB layer with a 1uF ceramic capac-
itor.
VIN_IO
This is the bias supply input to the IC’s digital circuitry.
It powers the GPIO pins. VIN_IO is typically connected
to the VIN_Bx pins, but can be powered from a different
voltage rail if desired. VIN_IO should be bypassed to
PGNDx with a 1uF ceramic capacitor.
Soft Reset – This sequence pulls nRESET low to reset
the system processor, but all ACT88326 outputs stay
turned on. To initiate Soft Reset, pull nPB to ground
through a 1kΩ resistor for 32ms to 4s. nRESET asserts
low after 32ms. When nPB transitions back high, the IC
deasserts the nRESET pin high. The output voltages do
not power cycle during a Soft Reset.
nPB
nPB is the push button input pin and provides multiple
system level functions based on its impedance to
ground and “press” time. Power On and Power Cycle1
are typically implemented with a single normally open,
momentary pushbutton switch to ground through 50kΩ.
Power Off and Power Cycle2 are typically implemented
with a single normally open, momentary pushbutton
switch or a “pin hole” pushbutton to ground through 1kΩ.
Power Cycle2 – This sequence momentarily turns all
outputs off and automatically restarts them. Initiate
Power Cycle1 by momentarily pulling nPB to ground
through a 1kΩ resistor for >4s. When nPB transitions
back high, the IC transitions from its current operating
state to the POWER OFF state for 0.5s. It then
transitions to the POWER SEQUENCE START state for
0.5s before going to the ACTIVE state. Unlike Power
Cycle1, the Power Cycle2 sequence does not require
any I2C register settings.
Power On – This sequence starts up the IC and turns
the outputs on. Initiate Power On by momentarily pulling
nPB to ground through a 50kΩ resistor. The IC
automatically starts turning on the outputs after 32ms.
All outputs must be in regulation and the nPB must be
asserted low for longer than the time programmed by
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If EN_PB_PWRCYCL and EN_PB_PWROFF are both
programmed to 1, asserting nPB for 4s-6s initiates the
Power Cycle1 sequence. Asserting nPB for >6s initiates
the Power Off sequence. If these bits are both
programmed to 0, both Power Cycle1 and Power Off are
disabled. These bits are factory set to a specific CMI
and cannot be changed.
SCL, SDA
These are the I2C clock and data pins to the IC. They
have standard I2C functionality.
PGNDx
The PGNDx pins are the buck converter power ground
pins. They connect directly to the buck converters’ low
side FETs. Buck1 and Buck2 use pins D4, E4, and F4
(PGND12). Buck3 uses pin A5 (PGND3).
Table 4 describes the functions available with the multi-
purpose push button pin (nPB pin).
SWx
SWx are the switch nodes for the buck converters. They
connect directly to the buck inductor on the top layer.
FB_Bx
These are the feedback pins for the buck regulators.
They should be kelvin connected to the buck output ca-
pacitors.
LSG
LSG is the load switch FET gate drive pin.
LDOx
These are the LDO output pins. Each LDO output must
be bypassed to AGND with a 1uF capacitor.
AGND
AGND is the ground pin for the IC’s analog circuitry and
LDOs. AGND must be connected to the IC’s PGNDx
pins. The connection between AGND and the PGNDx
pins should not have high currents flowing through it.
Table 4: Summary of nPB Functions
GPIOx
The ACT88326 has four GPIO pins. Each GPIO is pro-
grammed for a specific function by the IC’s CMI. The
available functions are input triggers for sequencing
(EXT_PG), output triggers for sequencing (EXT_EN),
nRESET, nIRQ, DVS, voltage select pins for the voltage
regulators, LED drivers, and GPIO.
Step-down DC/DC Converters
General Description
The ACT88326 contains three fully integrated step-
down converters. Buck1 is a 4A output, Buck2 and
Buck3 are 3A outputs. All buck converters are fixed
frequency, current-mode controlled, synchronous PWM
converters that achieve peak efficiencies of up to 95%.
The buck converters switch at 1.125MHz or 2.25MHz
and are internally compensated, requiring only three
small external components (Cin, Cout, and L) for
operation. The buck regulators minimize noise in
sensitive applications with the use of a switching phase
delay and offset. Additionally, all regulators are available
with a variety of standard and custom output voltages,
and may be software-controlled via the I2C interface for
systems that require advanced power management
functions.
GPIO1 (pin D7). GPIO1 can be programmed for any of
the above functions except the LED drivers. It can be
programmed as an input or an open drain or push-pull
output.
GPIO2 (pin D6). GPIO2 is the same as GPIO1
GPIO3 (pin E6). GPIO3 can be programmed for all the
above functions including the LED drivers. It can be pro-
grammed as an input or an open drain output.
GPIO4 (pin C7). GPIO4 is the same as GPIO3
The GPIOs are 5.5V tolerant meaning they can go to
5.5V even if VIN_IO is less than 5.5V.
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The ACT88326 buck regulators are highly configurable
and can be quickly and easily reconfigured via I2C. This
allows them to support changes in hardware
requirements without the need for PCB changes.
Examples of I2C functionality are given below:
1. This results in slightly lower efficiency at light loads,
but improves transient response.
Synchronous Rectification
Buck1/2/3 each feature integrated synchronous rectifi-
ers (or LS FET drivers), maximizing efficiency and min-
imizing the total solution size and cost by eliminating the
need for external rectifiers.
Real-time power good, OV, and current limit status
Ability to mask individual faults
Dynamically change output voltage
On/Off control
Soft-Start
Buck1/2/3 include internal 600us soft-start ramps which
limit the rate of change of the output voltage, minimizing
input inrush current and ensuring that the output powers
up in a monotonic manner that is independent of loading
on the outputs. This circuitry is effective any time the
regulator is enabled, as well as after responding to a
short-circuit or other fault condition. A single I2C register,
ALL_BUCKS_FASTER_SS, adjusts softstart between
600us when = 0 and 250us when = 1.
Softstart ramp
Slew rate control
Switching delay and phase control
Low power mode
Overcurrent thresholds
Refer to theActive-Semi Application Note describing the
Register Map for full details on I2C functionality and
programming ranges.
Output Voltage Setting
Buck1/2/3 regulate to the voltage defined by I2C register
VSET0 in normal operation and by VSET1 in DVS mode.
The ACT88326 has two output voltage programing
ranges.
100% Duty Cycle Operation
Output range 1 is available to Buck1/2. This range can
be programmed between 0.6V and 2.991V in 9.376mV
steps.
All buck converters are capable of 100% duty cycle op-
eration. During 100% duty cycle operation, the high-side
power MOSFETs are held on continuously, providing a
direct connection from the input to the output (through
the inductor), ensuring the lowest possible dropout volt-
age in battery powered applications.
Vbuck1=0.6 + VOUTx * 0.009376V
Where VOUTx is the decimal equivalent of the value in
each regulator’s I2C VOUTx register. The VOUTx regis-
ters contain an unsigned 8-bit binary value. As an ex-
ample, if Buck 1’s VOUT0 register contains 01000000b
(128 decimal), the output voltage is 1.8V.
Operating Mode
By default, all buck converters operate in fixed-fre-
quency PWM mode at medium to heavy loads, then
transition to a proprietary power-saving mode at light
loads in order to save power. Power-save mode re-
duces conduction losses by preventing the inductor cur-
rent from going negative.
Output range 2 is available to Buck1/2/3. This range can
be programmed between 0.8V to 3.9875V in 12.5mV
steps.
Vbuck1 = 0.8V + VOUTx * 0.0125V
To further optimize efficiency, a low power mode, LPM,
is available that provides even higher efficiency with
very small load currents. LPM minimizes quiescent cur-
rent at the expense of slightly larger transient response.
LPM is user controllable and can be enabled and disa-
bled dynamically to allow the customer to optimize the
balance between power consumption and transient re-
sponse. LPM is enabled when I2C bits DISLPM = 0 and
LP_MODE = 1.
See each IC’s CMI for its programing range. Note that
and IC’s default programming range cannot be changed.
Changing the programming range may result in unex-
pected IC behavior.
Active Semi recommends that the buck converter’s out-
put voltage be kept within +/- 25% of the default output
voltage to maintain accuracy. Voltage changes larger
than +/- 25% may require different factory trim settings
(new CMI) to maintain accuracy.
The buck converters can also be forced to operate in
PWM mode at light load by setting I2C bit ForcePWM =
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asserts low and remains asserted until either the regu-
lator is turned off or goes back into regulation, and the
POK [ ] bit has been read via I2C.
DVS
Each buck converter supports Dynamic Voltage Scaling
(DVS). In normal operation for most CMI options, each
output regulates to the voltage programmed by its
VSET0 I2C register. During DVS, each output can be
programmed to regulate to its VSET1 voltage.
Optimizing Noise
Each buck converter contains several features available
via I2C to further optimize functionality. The top P-ch
FET’s turn-on timing can be shifted approximately
110ns from the master clock edge via the PHASE_DE-
LAY I2C bit. It can also be aligned to the rising or falling
clock edge via the PHASE I2C bit.
During the voltage transition between VSET0 to VSET1
and VSET1 to VSET0, the I2C bit FORCEPWM is set to
1 to force the buck converters into PWM mode. This en-
sures that the output transition to the new voltage level
as quickly as possible. The outputs transition between
the two set points at a defined slew rate to minimize in-
rush currents. Note that VSET0 must be set higher than
VSET1. Violating this requirement results in an OV fault
during DVS.
Minimum On-Time
The ACT88326 minimum on-time is approximately
125ns. If a buck converter’s calculated on-time is less
than 125ns with 2.25MHz operation, then the buck con-
verter must be operated at 1.125MHz. Active Semi will
generate the IC CMIs to ensure that the buck converters
do not run into the minimum on-time limitations. The fol-
lowing equation calculates the on-time.
For fault free operation, the user must ensure output
load conditions plus the current required to charge the
output capacitance during a DVS rising voltage
condition does not exceed the current limit setting of the
regulator. As with any power supply, changing an output
voltage too fast can require a current higher than the
current limit setting. The user must ensure that the
voltage step, slew rate, and load current conditions do
not result in an instantaneous loading that results in a
current limit condition. See paragraph Dynamic Voltage
Scaling for options to enter and exit DVS.
ꢄꢁꢅꢆ
ꢀꢁꢂ
ꢃ
ꢄ
ꢇꢂ ∗ꢈꢉ
ꢊꢋ
Where Vout is the output voltage, VIN is the input volt-
age, and FSW is the switching frequency.
Overcurrent and Short Circuit Protection
Each buck converter provides overcurrent and short cir-
cuit protection with built in foldback protection. Overcur-
rent protection is achieved with cycle-by-cycle current
limiting. The peak current threshold is set by the
ILIM_SET I2C bits.
Enable / Disable Control
During normal operation, each buck may be enabled or
disabled via the I2C interface by writing to that regula-
tor's ON bit. Note that disabling a regulator that is used
as an input trigger to another regulator may or may not
disable the other regulators following it, depending on
the specific CMI settings. Each buck converter has a
load discharge function designed to quickly pull the out-
put voltage to ground when the converter is disabled.
The circuit connects an internal resistor (4.4ohm for
Buck1 and 9.4ohms for Buck2/3) from the output to
PGND when the converter is disabled.
If the peak current reaches 75% of the programmed
threshold for 16 consecutive switching cycles, the IC as-
serts nIRQ low and changes I2C bit ILIM_WARN = 1,
but continues to operate normally.
If the peak current reaches the programmed threshold,
the IC turns off the power FET for that switching cycle.
If the peak current reaches the threshold 16 consecutive
switching cycles, the IC asserts nIRQ low. This condi-
tion typically results in shutdown due to an UV condition
due to the shortened switching cycle.
POK and Output Fault Interrupt
Each DC/DC features a power-OK status bit, POK,
which can be read by the system microprocessor via the
I2C interface. If an output voltage is lower than the POK
threshold, typically 7% below the programmed regula-
tion voltage, that regulator’s POK bit will be 0.
A short circuit condition that results in the peak switch
current being 122.5% of ILIM_SET immediately shuts
down the supply and asserts nIRQ low if the fault bit is
not masked. The supply tries to restart in 14ms. If the
fault condition is not masked, the IC transitions to the
OVUV State, turns off all supplies, and restarts the sys-
tem in 100ms.
If a DC/DC's nFLTMSK[ ] bit is set to 1, the ACT88326
will interrupt the processor if the DC/DC's output voltage
falls below the power-OK threshold. In this case, nIRQ
The buck converters also have built in current foldback
protection. After softstart is complete, if a short circuit or
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overload condition causes the output to go out of regu-
lation for > 28us, the IC reduces the peak-to-peak cur-
rent limit to 1.5A. This reduces system level power dis-
sipation in short circuit or overload conditions. If the load
current drops low enough to allow the output voltage to
enter regulation with the reduced peak-to-peak current
limit, the output restarts and the IC resets the peak-to-
peak current limit to the default value
capacitor placement is critical for proper operation.
Each buck’s input capacitor must be placed as close to
the IC as possible. The traces from VIN to the capacitor
and from the capacitor to PGND should as short and
wide as possible.
Inductor Selection
The Buck converters utilize current-mode control and a
proprietary internal compensation scheme to
simultaneously simplify external component selection
and optimize transient performance over their full
operating range. The ACT88326 is optimized for
operation with 1.0μH inductors, but can be used with
inductor values 1uH to 2.2uH. Choose an inductor with
a low DC-resistance, and avoid inductor saturation by
choosing inductors with DC ratings that exceed the
maximum output current by at least 30%. The following
equation calculates the inductor ripple current.
If a buck converter reaches overcurrent or short circuit
protection, the status is reported in the ILIM I2C regis-
ters. The contents of these registers are latched until
read via I2C. Overcurrent and short circuit conditions
can be masked via the I2C bit ILIM_FLTMSK. The IC’s
specific CMI determines which regulators mask the cur-
rent limit fault.
Compensation
The buck converters utilize current-mode control and a
proprietary internal compensation scheme to simultane-
ously simplify external component selection and opti-
mize transient performance over their full operating
range. No compensation design is required; simply fol-
low a few simple guide lines described below when
choosing external components.
ꢄ
ꢒ1 ꢓ ꢁꢅꢆꢔ ∗ꢈꢄꢁꢅꢆ
ꢄ
ꢇꢂ
∆ꢌꢘ ꢈꢃꢈ
ꢈꢈꢈꢈꢈ
ꢉꢊꢋ ∗ ꢙ
Where VOUT is the output voltage, VIN is the input voltage,
FSW is the switching frequency, and L is the inductor
value.
Input Capacitor Selection
Each buck converter has a dedicated input pin and
power ground pin. Each buck converter should have a
dedicated input capacitor that is optimally placed to
minimize the power routing loops for each buck
converter. Note that even though each buck converter
has separate inputs, all buck converter inputs must be
connected to the same voltage potential.
Output Capacitor Selection
The ACT88326 is designed to use small, low ESR,
ceramic output capacitors. Buck1 typically requires
2x22uF or a single 47uF output capacitor while Buck2
and Buck3 require a 22uF output capacitor each. In
order to ensure stability, the Buck1 effective
capacitance must be greater than 20uF while Buck2
and Buck3 effective capacitance must be greater than
12uF. The output capacitance can be increased to
reduce output voltage ripple and improve load
transients if needed. Design for an output ripple voltage
less than 1% of the output voltage. The following
equation calculates the output voltage ripple as a
function of output capacitance.
Each regulator requires a high quality, low-ESR,
ceramic input capacitor. 10uF capacitors are typically
suitable, but this value can be increased without limit.
Smaller capacitor values can be used with lighter output
loads. Choose the input capacitor value to keep the
input voltage ripple less than 50mV.
ꢄꢍꢎꢏ
ꢄꢐꢑ
ꢄꢍꢎꢏ
ꢄꢐꢑ
∗ ꢒ1 ꢓ
ꢔ
∆ꢌꢘ
Vrippleꢈ ꢃ ꢌꢍꢎꢏ ∗
VRIPPLE ꢃꢈꢈ
ꢈ
ꢉꢕꢖ ∗ ꢗꢐꢑ
8 ∗ ꢉꢊꢋ ∗ ꢗꢁꢅꢆ
Be sure to consider the capacitor’s DC bias effects and
maximum ripple current rating when using capacitors
smaller than 0805.
Where ΔIL is the inductor ripple current, FSW is the
switching frequency, and COUT is the output capacitance
after taking DC bias into account.
A capacitor’s actual capacitance is strongly affected by
its DC bias characteristics. The input capacitor is
typically an X5R, X7R, or similar dielectric. Use of Y5U,
Z5U, or similar dielectrics is not recommended. Input
Be sure to consider the capacitor’s DC bias effects and
maximum ripple current rating when using capacitors
smaller than 0805.
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A capacitor’s actual capacitance is strongly affected by
its DC bias characteristics. The output capacitor is
typically an X5R, X7R, or similar dielectric. Use of Y5U,
Z5U, or similar dielectrics are not recommended due to
their wide variation in capacitance over temperature and
voltage ranges.
The LDOs require only two small external components
(Cin, Cout) for operation. They ship with default output
voltages that can be modified via the I2C interface for
systems that require advanced power management
functions.
Soft-Start
Buck1 Bypass mode
Each LDO contains a softstart circuit that limits the rate
of change of the output voltage, minimizing input inrush
current and ensuring that the outputs power up mono-
tonically. This circuitry is effective any time the LDO is
enabled, as well as after responding to a short circuit or
other fault condition. Each LDO’s softstart time is fixed
to 275us.
General Description
Buck1 is configurable as a bypass switch for systems
with a 3.3V bus voltage. The bypass switch provides full
sequencing capability by allowing the 3.3V bus to be
used as the input to the other supplies and still be
properly sequenced to the downstream load. In bypass
mode, the Buck1 P-ch FET acts as a switch and the N-
ch FET is disabled. The bypass switch turns on the 3.3V
rail with the programmed delay and softstart time.
Output Voltage Setting
The LDOs regulate to the voltage defined by their I2C
registers LDO1_VSET and LDO2_VSET. The LDOs do
not have a second VSET register like the buck convert-
ers. The LDOs can be configured with two different out-
put voltage range settings. I2C register bit VREF_CTRL
controls the two settings. This bit is factory set and is
not user configurable.
In bypass mode, the ACT88326 Buck 1 I2C registers are
reconfigured to the following.
1. ILIM bit is the output of the PMOS Current De-
tection circuit. In an overcurrent condition, ILIM
triggers the nIRQ output. ILIM is latched until
read via I2C. ILIM can be masked with the
ILIM_FLTMSK register.
VREF_CTRL = 0
0.8
VREF_CTRL = 1
0.6
Vref (V)
2. The UV register bit is reconfigured to the output
of the PMOS Current Shutdown circuit. This is
set to 5.6A typical. If the bypass switch current
exceeds 5.6A, it limits the current which triggers
an under voltage fault condition and moves the
IC into the OVUV FAULT state. This immedi-
ately shuts down all regulators including the by-
pass switch. The system restarts in 100mS, fol-
lowing the programmed startup sequencing.
This fault can be masked with I2C bit UV_FLT-
MASK. This fault is latched in the UV_REG I2C
bit.
Vout Range (V)
Vout Step Size (mV)
0.8 – 3.9875
12.5
0.6 – 2.991
9.375
The following equation determines the LDO output volt-
ages when VREF_CTRL = 0.
VLDOx = 0.8V + LDOx_VSET * 0.0125V
The following equation determines the LDO output volt-
ages when VREF_CTRL = 1.
VLDOx = 0.6V + LDOx_VSET * 0.009375V
Active Semi recommends that the LDO’s output voltage
be kept within +/- 25% of the default output voltage to
maintain accuracy. Voltage changes larger than +/- 25%
may require different factory trim settings (new CMI) to
maintain accuracy.
3. OV is disabled. There is no overvoltage detec-
tion circuitry on the output of the bypass switch.
LDO Converters
General Description
Enable / Disable Control
The ACT88326 contains two fully integrated, 300mA,
low dropout linear regulators (LDO). LDOs have been
optimized to achieve low dropout and high PSRR. The
LDOs can also be configured in load switch mode to
behave like load switches.
During normal operation, each LDO may be enabled or
disabled via the I2C interface by writing to that regula-
tor's ON bit. Note that disabling an LDO that is used as
an input trigger to another regulator may or may not dis-
able the other regulators following it, depending on the
specific CMI settings. Each LDO has a load discharge
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function designed to quickly pull the output voltage to
ground when the LDO is disabled. The circuit connects
an internal resistor (50ohm) from the output to AGND
when the LDO is disabled.
Output Capacitor Selection
Each LDO requires a high quality, low-ESR, ceramic
output capacitor. A 1uF is typically suitable, but this
value can be increased without limit. The input capacitor
is should be a X5R, X7R, or similar dielectric. The LDO
POK and Output Fault Interrupt
effective output capacitance must be greater than 0.7uF
.
Each LDO features a power-OK status bit, POK, which
can be read by the system microprocessor via the I2C
interface. If an output voltage is lower than the POK
threshold, typically 11% below the programmed regula-
tion voltage, that regulator’s POK bit will be 0.
Load Switch Mode
LDO1 and LDO2 can be configured as a load switch. In
this mode, the device still monitors the output voltage
and current, and protects the output when it is over the
allowable limits. When in load switch mode, the LDOs
pass the input voltage directly to the output voltage. Put
the LDOs into load switch mode by setting I2C bits
LDO1_LSW_MODE and LDO2_LSW_MODE in
register 0xECh to 1.
If an LDO's nFLTMSK[ ] bit is set to 1, the ACT88326
will interrupt the processor if that LDO’s output voltage
falls below the power-OK threshold. In this case, nIRQ
asserts low and remains asserted until either the LDO
is turned off or goes back into regulation, and the POK
[ ] bit has been read via I2C.
Overcurrent and Short Circuit Protection
Each LDO provides overcurrent detection and short cir-
cuit protection featuring a current-limit foldback function.
When current limit is reached, the IC can either shut the
output off or limit the output current until the overload
condition is removed. This is controlled by I2C bits
LDOx_ILIM_SHUTDOWN_DIS.
LOAD SWITCH
General Description
The ACT88326 features a Load Switch gate driver, LSG,
to power an external n-ch FET. The Load Switch allows
a common power rail to be switched on/off to create a
power “island” for system loads. This “island” can be
turned off to minimize power consumption when those
loads are not needed. The Load Switch can also be in-
corporated into the ICs startup sequencing with pro-
grammable turn-on and turn-off delay times. It can also
be programed to be turned on or off in SLEEP and
DPSLP states.
The overcurrent threshold is set by the ILIM1 and ILIM2
I2C bits. In both an overload and a short circuit condition,
the LDO limits the output current which causes the out-
put voltage to drop. This can result in an undervoltage
fault in addition to the current limit fault. If an LDO load
reaches overcurrent detection threshold, the status is
reported in the ILIM_LDOx I2C registers. The contents
of these registers are latched until read via I2C. When
the current limiting results in a drop in output voltage
that triggers an undervoltage condition, the IC shuts
down all power supplies, asserts nIRQ low, and enters
the UVLOFLT state provided the faults are not masked.
Once in the OVUVFLT state, the IC restarts in 100ms
and starts up with default sequencing. Overcurrent and
short circuit conditions can be masked via the I2C bit
ILIMFLTMSK_LDOx. When masked, the LDO still shuts
down or limits current (based on the LDOx_ILIM_SHUT-
DOWN_DIS bit). In this condition, it does not enter the
OVUVFLT state due to the faults being masked. If it
shuts down, it automatically restarts in 14ms.
Softstart
The LSG incorporates a programmable slew rate to
control the turn-on speed of the external FET. The LSG
output consists of a current source to linearly charge the
external FET gate voltage. The slew rate is controlled
via the I2C bits GATE1_SLEW[1:0]. The current source
is programmable between 2.5uA and 10uA in 2.5uA in-
crements. The slew rate is
ꢌꢘꢊꢚ
SLEW ꢃꢈ
ꢈ
ꢗꢛꢜꢆ_ꢚꢝꢆꢜ
Where SLEW is the LSG slew rate in V/s, ILSG is the gate
drive current in Amps, and CFET_GATE is the external FET
gate capacitance in Farads. Adding a discrete gate ca-
pacitor will provide more consistent Load Switch turn on
characteristics.
Input Capacitor Selection
The AVIN pins supplies the input power to both LDO.
AVIN requires a high quality, low-ESR, ceramic input
capacitor. A 1uF is typically suitable, but this value can
be increased without limit. The input capacitor is should
be a X5R, X7R, or similar dielectric.
LSG has an active 75 ohm pulldown resistor when dis-
abled to quickly turn off the external FET.
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3. Place the LDO input capacitor close to the AVIN
pin. Connect the capacitor directly to AVIN and
AGND on the top layer.
Current Limit
Because LSG only connects to the external FET gate,
Load Switch does not have a current limit function. The
input to the Load Switch should come from an
ACT88326 Buck, LDO, or other current limited source.
4. The Buck output capacitors should be placed
by the inductor and connected directly to the in-
ductor and ground plane with short and wide
traces. The output capacitor ground should
make a short connection to the input capacitor
ground. If required, use multiple vias.
Load Switch POK
The load switch internal Power OK, POK, signal can be
used in the sequencing of other power supplies. The
load switch POK signal goes active when the load
switch gate drive voltage at the LSG pin is greater than
VIN + 1V and VIN – VOUT < 100mV. Note that the ac-
tual load switch may or may not be fully on at this time
depending on the FET used for the load switch or any
additional filtering or delay circuitry connected to LSG.
5. Each regulator’s FB_Bx should be Kelvin con-
nected to its output capacitor through the short-
est possible route, while keeping sufficient dis-
tance from switching nodes to prevent noise in-
jection. The IC regulates the output voltage to
this Kelvin connection.
PC board layout guidance
6. The PGNDx and AGND ground pins must be
electrically connected together. Because the
AGND ground plane is used for analog, digital,
and LDO grounds, it does not need to be com-
pletely isolated from the rest of the PCB
grounds. However, take care to avoid routing
the buck converter switching currents through
the analog ground connections.
Proper parts placement and PCB layout are critical to
the operation of switching power supplies. Follow the
following layout guidelines when designing the
ACT88326 PCB. Refer to the Active-Semi ACT88326
Evaluation Kits for layout examples
1. Place the buck input capacitors as close as
possible to the IC. Refer to the Pin Descriptions
for each buck converter’s dedicated VINx and
PGNDx pins. Connect the input capacitors di-
rectly to the corresponding VINx and PGNDx
power ground pin on the top layer. Routing
these traces on the top layer eliminates the
need for vias.
7. Connect the VIN_IO input capacitor to the
AGND ground pin.
8. Remember that all open drain outputs need
pull-up resistors.
9. Figure 4 shows the recommended power and
signal connections and routing from under the
IC. Refer to the ACT88326 evaluation kit for a
full, detailed routing example.
2. Minimize the switch node trace length between
each SW_Bx pin and the inductor. Optimal
switch node routing is to run the trace between
the input capacitor’s pads. Using 0805 sized in-
put capacitors is recommended. Avoid routing
sensitive analog signals near these high fre-
quency, high dV/dt traces.
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FB_B3
VIN_B3
SW_B3
SW_B3
PGND
AGND
SDA
PWREN
VIN_B2
SW_B2
PGND
FB_B2
VIN_B2
SW_B2
PGND
LDO1
AVIN
LSG
LDO2
VIN_B2
SW_B2
PGND
VIN_B3
SW_B1
VIN_B1
GPIO4
SW_B1
VIN_B1
FB_B1
SW_B1
VIN_B1
VIN_IO
GPIO2
GPIO1
GPIO3
SCL
Figure 4: Recommended Routing
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Typical Operating Characteristics
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ACT88326VA
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The following components have been used with the ACT88326.
REFERENCE
DESCRIPTION
22uF, 10V, X5R
22uF, 10V, X5R
1uF, 10V, X5R
2x22uF, 10V, X5R
22uF, 10V, X5R
1uF, 10V, X5R
1uH, 12mΩ
MANUFACTURER
Standard
Input Capacitor, Buck1
Input Capacitor, Buck2/3
Input Capacitor, LDO1/2
Output Capacitor, Buck1
Output Capacitor, Buck2/3
Output Capacitor, LDO1/2
Inductor, Buck1
Standard
Standard
Standard
Standard
Standard
Wurth 74438356010
Wurth 74438323010
Standard
Inductor, Buck2/3/4
VIN_IO
1uH, 63mΩ
1uF, 10V, X5R
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CMI OPTIONS
This section provides the basic default configuration settings for each available ACT88326 CMI option. IC functionality
in this section supersedes functionality in the main datasheet. Generating the desired functionality for a custom CMI
sometimes requires reassigning internal resources, resulting in removal of base IC functionality. The following sections
attempt to describe any removed functionality from the base IC functionality. The user is required to fully test all required
functionality to ensure the CMI fully meets their requirements.
CMI 102: ACT88326VA102-T
CMI 102 is optimized for the Ambarella H22 processor for use in video applications.
Voltage and Currents
Active
Mode
Voltage
(V)
Sleep
Mode
Voltage
(V)
DPSLP Mode DVS Voltage
Current
Limit (A)
Rail
Buck1
Buck2
Buck3
LDO1
LDO2
LS1
Voltage (V)
(V)
Fsw (kHz)
1125
1125
2250
n/a
0.85
1.35
3.0
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
3.1
2.6
2.6
1.8
0.465
0.465
n/a
3.0
n/a
On
n/a
Startup and Sequencing
Sequence
Order
Sequencing
Input Trigger
StartUp
Delay (us)
Soft-Start
(us)
Shutdown
Delay (ms)
Rail
Buck1
Buck2
Buck3
LDO1
LDO2
LS1
1
2
3
3
4
4
UVLO
0
480
480
7.75
6.75
5.75
5.75
4.75
4.75
Buck1
1000
1000
1000
1000
n/a
Buck2
480
Buck2
225
LDO1
300
LDO1
2.5uA
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CMI 102 Startup
1ms
Buck1
GPIO1
GPIO3
Buck2
Buck3
LDO1
1ms
1ms
1ms
1ms
1ms
1ms
LDO2
LSG1
4ms
100ms
nRESET
I2C Address
The ACT88326 7-bit I2C address is 0x25h. Use address 0x4Ah when writing and 0x4Bh when reading.
GPIO1 (pin C7) – EXT_EN1
GPIO1 is configured as an open drain output to enable an external power supply. At power up, GPIO1 goes high when
Buck1 goes high. After power up, GPIO1 can be controlled via I2C to enable and disable the external power supply.
GPIO2 (pin C6) – EXT_EN2
GPIO2 is configured as an open drain output to enable an external power supply. At power up, GPIO2 goes high when
Buck1 goes high. After power up, GPIO2 can be controlled via I2C to enable and disable the external power supply.
GPIO3 (pin B6) – nIRQ
GPIO3 is configured as an open drain nIRQ output.
GPIO4 (pin D7) – nRESET
GPIO4 is configured as an open drain nRESET output. nRESET goes open drain 100ms after LDO2 goes into regulation.
During a turn off sequence, nRESET goes low 4ms before the outputs start to turn off.
SLEEP MODE
I2C default settings are SLEEP_MODE=0, SLEEP_EN=0, and SLEEP=0. This disables SLEEP mode. Refer to the
SLEEP State paragraph for details on how to enter SLEEP Mode.
DPSLP MODE
I2C default settings are DPSLP_MODE=1, DPSLP_EN=0, and DPSLP=0. This disables DPSLP mode. Refer to the
DPSLP State paragraph for details on how to enter DPSLP Mode.
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DVS
DVS using a GPIOx input is disabled. However, each output’s voltage can be individually controlled by changing its
VSET0 register contents via I2C.
VSYSMON
VSYSMON = 3.6V
Buck1 Voltage Setting
Buck1 reference voltage is 0.8V
Buck2 Voltage Setting
Buck2 reference voltage is 0.8V.
Buck3 Voltage Setting
Buck3 reference voltage is 0.8V.
LDO Voltage Setting
The LDO reference voltage is 0.8V.
Power Cycle1
EN_PB_PWRCYCL bit = 0. This disables the Power Cycle1 sequence.
Shutdown
EN_PB_PWRSHDN bit = 1. This enables the Power Off sequence that turns off all outputs and puts the IC into the
POWER OFF state when nPB is pulled low through 50kΩ for >
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PACKAGE OUTLINE AND DIMENSIONS – 36 BALL WLCSP
Top View
Bottom View
Side View
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