ACT8840QM17A-T [ACTIVE-SEMI]
Advanced PMU for Single-core Application Processors;
| 型号： | ACT8840QM17A-T |
| 厂家： | 
ACTIVE-SEMI, INC |
| 描述： | Advanced PMU for Single-core Application Processors |
| 文件： | 总38页 (文件大小：682K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACT8840
Rev 1, 07-Feb-14
Advanced PMU for Single-core Application Processors
FEATURES
GENERAL DESCRIPTION
The ACT8840 is a complete, cost effective, and
highly-efficient ActivePMUTM power management
solution optimized for the power, voltage
sequencing and control requirements of general
Single-core application processor.
INTEGRATED POWER SUPPLIES
• Four DC/DC Step-Down (Buck) Regulators
− 2 x 1.8A, 2 x 1.3A
• Five Low-Noise LDOs
− 2 x 150mA, 3 x 350mA
The ACT8840 features four fixed-frequency,
current-mode, synchronous PWM step-down
converters that achieve peak efficiencies of up to
97%. These regulators operate with a fixed
frequency of 2.25MHz, minimizing noise in sensitive
applications and allowing the use of small external
components. These buck regulators supply up to
1.8A of output current and can fully satisfy the
power and control requirements of the single-core
application processor. Dynamic Voltage Scaling
(DVS) is supported either by dedicated control pins,
or through I2C interface to optimize the energy-per-
task performance for the processor. This device
also include eight low-noise LDOs (up to 350mA
per LDO), one always-ON LDO and an integrated
backup battery charger to provide a complete
power system for the processor.
• Three Low-Input Voltage LDOs
− 1 x 150mA, 2 x 350mA
• One Low IQ Keep-Alive LDO
• Backup Battery Charger
SYSTEM CONTROL AND INTERFACE
• Six General Purpose I/O with PWM Drivers
• I2C Serial Interface
• Interrupt Controller
SYSTEM MANAGEMENT
• Reset Interface and Sequencing Controller
− Power on Reset
− Soft / Hard Reset
− Watchdog Supervision
− Multiple Sleep Modes
The power sequence and reset controller provides
power-on reset, SW-initiated reset, and power cycle
reset for the processor. It also features the
watchdog supervisory function. Multiple sleep
modes with autonomous sleep and wake-up
sequence control are supported.
• Thermal Management Subsystem
The thermal management and protection
subsystem allows the host processor to manage the
power dissipation of the PMU and the overall
system dynamically. The PMU provides a thermal
warning to the host processor when the
temperature reaches a certain threshold such that
the system can turn off some of the non-essential
functions, reduce the clock frequency and etc to
manage the system temperature.
APPLICATIONS
• Tablet PC
• Mobile Internet Devices (MID)
• Ebooks
• Personal Navigation Devices
The ACT8840 is available in a compact, Pb-Free
and RoHS-compliant TQFN66-48 package.
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2014 Active-Semi, Inc.
ACT8840
Rev 1, 07-Feb-14
TABLE OF CONTENTS
General Information.....................................................................................................................................p. 01
Functional Block Diagram............................................................................................................................p. 03
Ordering Information....................................................................................................................................p. 04
Pin Configuration .........................................................................................................................................p. 04
Pin Descriptions...........................................................................................................................................p. 05
Absolute Maximum Ratings.........................................................................................................................p. 07
I2C Interface Electrical Characteristics ........................................................................................................p. 08
Global Register Map....................................................................................................................................p. 09
Register and Bit Descriptions ......................................................................................................................p. 11
System Control Electrical Characteristics....................................................................................................p. 17
Step-Down DC/DC Electrical Characteristics..............................................................................................p. 18
Low-Noise LDO Electrical Characteristics...................................................................................................p. 19
Low-Input Voltage LDO Electrical Characteristics.......................................................................................p. 20
Low-Power (Always-On) LDO Electrical Characteristics.............................................................................p. 21
PWM LED Driver Electrical Characteristics.................................................................................................p. 21
Typical Performance Characteristics……………………………………………………………………………..p. 22
System Control Information .........................................................................................................................p. 28
Interfacing with the Telechips TCC88xx Processors .......................................................................p. 28
Control Signals.................................................................................................................................p. 29
Push-Button Control.........................................................................................................................p. 30
Control Sequences...........................................................................................................................p. 30
Watch-Dog Supervision ...................................................................................................................p. 30
Software-Initiated Power Cycle........................................................................................................p. 30
Functional Description .................................................................................................................................p. 32
I2C Interface .....................................................................................................................................p. 32
Housekeeping Functions..................................................................................................................p. 32
Thermal Protection...........................................................................................................................p. 32
Step-Down DC/DC Regulators ....................................................................................................................p. 33
General Description..........................................................................................................................p. 33
100% Duty Cycle Operation.............................................................................................................p. 33
Operating Mode................................................................................................................................p. 33
Synchronous Rectification................................................................................................................p. 33
Soft-Start ..........................................................................................................................................p. 33
Compensation ..................................................................................................................................p. 33
Configuration Options.......................................................................................................................p. 33
OK[ ] and Output Fault Interrupt.......................................................................................................p. 34
PCB Layout Considerations.............................................................................................................p. 34
Low-Noise, Low-Dropout Linear Regulators................................................................................................p. 35
General Description..........................................................................................................................p. 35
Output Current Limit.........................................................................................................................p. 35
Compensation ..................................................................................................................................p. 35
Configuration Options.......................................................................................................................p. 35
OK[ ] and Output Fault Interrupt.......................................................................................................p. 35
PCB Layout Considerations.............................................................................................................p. 35
Always-On LDO (REG13)............................................................................................................................p. 36
General Description..........................................................................................................................p. 36
Reverse-Current Protection .............................................................................................................p. 36
Typical Application ...........................................................................................................................p. 36
PWM LED Drivers........................................................................................................................................p. 37
PWM Frequence Selection ..............................................................................................................p. 37
PWM Duty Cycle Selection ..............................................................................................................p. 37
TQFN66-48 Package Outline and Dimensions ...........................................................................................p. 38
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I2CTM is a trademark of NXP.
Copyright © 2014 Active-Semi, Inc.
ACT8840
Rev 1, 07-Feb-14
FUNCTIONAL BLOCK DIAGRAM
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2014 Active-Semi, Inc.
ACT8840
Rev 1, 07-Feb-14
ORDERING INFORMATIONc
PART NUMBER VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 VOUT13
ACT8840QM188-T 3.3V 1.25V 1.8V 1.1V 1.1V 1.1V 3.3V 1.1V 2.8V 3.3V 1.8V 3.3V
ACT8840QM244-T 1.5V 1.25V 1.2V 3.0V 3.0V 3.3V 3.3V 3.3V 1.2V 1.2V 1.8V 1.8V
3.0V
3.3V
PACKAGE
PINS TEMPERATURE RANGE
48 -40°C to +85°C
TQFN66-48
c: All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means
semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
2: The Power Domains and Power Control Sequence… etc. in this Data Sheet are all described to support ACT8840QM188-T.
ACT8840QM244-T is programmed for TCC88xx Applications; please refer to its appendix.
ACT8840QM_ __-T
Active-Semi
Product Number
Package Code
Pin Count
Option Code
Tape and Reel
PIN CONFIGURATION
TOP VIEW
Thin - QFN (TQFN66-48)
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ACT8840
Rev 1, 07-Feb-14
PIN DESCRIPTIONS
PIN
1, 2
3
NAME
DESCRIPTION
SW3
Switch Node for REG3.
Power Ground for REG3. Connect GP14, GP2, GP3, and GA together at a single
point as close to the IC as possible.
GP3
4
OUT10
OUT11
INL3
REG10 output. Bypass it to ground with a 2.2µF capacitor.
REG11 output. Bypass it to ground with a 2.2µF capacitor.
Power input for REG10, REG11 and REG12.
5
6
7
OUT12
REG12 output. Bypass it to ground with a 2.2µF capacitor.
Output Voltage Selection for REG2 and REG4. Drive to logic low to select default
output voltage. Drive to logic high to select secondary output voltage.
8
9
VSEL
Active-Low Open-Drain Push-Button Status Output. nPBSTAT is asserted low
whenever the nPBIN is pushed, and is high-Z otherwise.
nPBSTAT
Power ground for REG2. Connect GP14, GP2, GP3, and GA together at a single
point as close to the IC as possible.
10
GP2
SW2
VP2
11, 12
13, 14
Switch Node for REG2.
Power input for REG2. Bypass to GP2 with a high quality ceramic capacitor placed as
close to the IC as possible.
15
16
17
OUT2
PWREN
REFBP
Output Voltage Sense for REG2.
Power enable input.
Reference Bypass. Connect a 0.047μF ceramic capacitor from REFBP to GA. This
pin is discharged to GA in shutdown.
18
19
20
21
22
23
24
25
INL2
OUT9
GA
Power Input for REG8, REG9.
REG9 output. Bypass it to ground with a 2.2µF capacitor.
Analog Ground.
OUT4
OUT8
SDA
SCL
Output voltage sense for REG4.
REG8 output. Bypass it to ground with a 2.2µF capacitor.
Data Input for I2C Serial Interface. Data is read on the rising edge of SCL.
Clock Input for I2C Serial Interface.
Power input for REG4. Bypass to GP14 with a high quality ceramic capacitor placed
as close to the IC as possible.
VP4
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ACT8840
Rev 1, 07-Feb-14
PIN DESCRIPTIONS CONT’D
PIN
NAME
DESCRIPTION
26
SW4
Switch Node for REG4.
Power Ground for REG1 and REG4. Connect GP14, GP2, GP3, and GA together at a
single point as close to the IC as possible.
27
GP14
28
29
SW1
Switch Node for REG1.
OUT1
Output Voltage Sense for REG1.
Power Input for REG1. Bypass to GP14 with a high quality ceramic capacitor placed
as close to the IC as possible.
30
31
VP1
Master Enable Input. Drive nPBIN to GA through a 50kΩ resistor to enable the IC,
drive nPBIN directly to GA to assert a Manual-Reset condition.
nPBIN
32
33
34
PWRHLD
nRSTO
nIRQ
Power hold Input.
Open-Drain Reset Output.
Open-Drain Interrupt Output.
General Purpose I/O #6. Configured as PWM LED driver output for up to 6mA current
with programmable frequency and duty cycle. See the PWM LED Drive section for
more information.
35
36
GPIO6
GPIO5
General Purpose I/O #5. Configured as PWM LED driver output for up to 6mA current
with programmable frequency and duty cycle. See the PWM LED Driver section for
more information.
37
38
OUT13
OUT7
REG13 output. Bypass it to ground with a 2.2µF capacitor.
REG7 output. Bypass it to ground with a 2.2µF capacitor.
General Purpose I/O #4. Configured as PWM LED driver output for up to 6mA current
with programmable frequency and duty cycle. See the PWM LED Driver section for
more information.
39
GPIO4
40
41
42
OUT6
INL1
REG6 output. Bypass it to ground with a 2.2µF capacitor.
Power Input for REG5, REG6, REG7.
OUT5
REG5 output. Bypass it to ground with a 2.2µF capacitor.
General Purpose I/O #3. Configured as PWM LED driver output for up to 6mA current
with programmable frequency and duty cycle. See the PWM LED Drier section for
more information.
43
44
45
GPIO3
GPIO2
GPIO1
General Purpose I/O #2. Configured as PWM LED driver output for up to 6mA current
with programmable frequency and duty cycle. See the PWM LED Drier section for
more information.
General Purpose I/O #1. Configured as PWM LED driver output for up to 6mA current
with programmable frequency and duty cycle. See the PWM LED Drier section for
more information.
46
47,48
EP
OUT3
VP3
EP
Output Voltage Sense for REG3.
Power input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as
close to the IC as possible.
Exposed Pad. Must be soldered to ground on PCB.
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Copyright © 2014 Active-Semi, Inc.
ACT8840
Rev 1, 07-Feb-14
ABSOLUTE MAXIMUM RATINGSc
PARAMETER
VALUE
UNIT
INL1, INL2, INL3 to GA; VP1, SW1, OUT1 to GP14; VP2, SW2, OUT2 to GP2; VP3,
SW3, OUT3 to GP3; VP4, SW4, OUT4 to GP14
-0.3 to 6
V
GP14, GP2, GP3 to GA
-0.3 to + 0.3
V
V
OUT5, OUT6, OUT7, OUT13 to GA
-0.3 to INL1 + 0.3
OUT8, OUT9, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, VSELR2, nPBIN,
nRSTO, nIRQ, nPBSTAT, PWREN, PWRHLD, REFBP, SCL, SDA to GA
-0.3 to INL2 + 0.3
V
OUT10, OUT11, OUT12 to GA
Junction to Ambient Thermal Resistance
Operating Ambient Temperature Range
Operating Junction Temperature
Storage Temperature
-0.3 to INL3 + 0.3
21
V
°C/W
°C
-40 to 85
-40 to 125
-55 to 150
300
°C
°C
Lead Temperature (Soldering, 10 sec)
°C
c: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may
affect device reliability.
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ACT8840
Rev 1, 07-Feb-14
I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VINL2 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
SCL, SDA Input Low
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VINL2 = 3.1V to 5.5V, TA = -40ºC to 85ºC
0.35
SCL, SDA Input High
SDA Leakage Current
SCL Leakage Current
SDA Output Low
V
INL2 = 3.1V to 5.5V, TA = -40ºC to 85ºC
1.55
V
1
1
µA
µA
V
I
OL = 5mA
0.35
SCL Clock Period, tSCL
SDA Data Setup Time, tSU
SDA Data Hold Time, tHD
Start Setup Time, tST
Stop Setup Time, tSP
1.5
100
300
100
100
µs
ns
ns
ns
ns
For Start Condition
For Stop Condition
Figure 1:
I2C Compatible Serial Bus Timing
tSCL
SCL
SDA
tST
tHD
tSU
tSP
Start
condition
Stop
condition
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ACT8840
Rev 1, 07-Feb-14
GLOBAL REGISTER MAP
BITS
BLOCK ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
NAME
DEFAULTc
NAME
nBATLEVMSK nBATSTAT VBATDAT
Reserved
BATLEV[3] BATLEV[2] BATLEV[1]
BATLEV[0]
SYS
0x00
0x01
0x10
0x12
0x20
0x21
0x22
0x30
0x31
0x32
0x40
0x41
0x42
0x50
0x51
0x58
0x59
0x60
0x61
0
R
R
0
0
0
0
0
nTMSK
TSTAT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SYS
DEFAULTc
0
R
0
0
0
0
0
0
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
REG1
REG1
REG2
REG2
REG2
REG3
REG3
REG3
REG4
REG4
REG4
REG5
REG5
REG6
REG6
REG7
REG7
DEFAULTc
NAME
DEFAULTc
0
0
1
1
1
0
0
1
ON
Reserved
Reserved
Reserved
Reserved
PHASE
nFLTMSK
OK
1
1
0
0
0
0
0
R
NAME
Reserved
Reserved
VSET0[5]
VSET0[4]
VSET0[3]
VSET0[2]
VSET0[1]
VSET0[0]
DEFAULTc
NAME
DEFAULTc
0
0
0
1
1
0
0
1
Reserved
Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
0
0
0
0
1
1
1
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
PHASE
nFLTMSK
OK
DEFAULTc
NAME
DEFAULTc
1
1
0
1
0
0
0
R
Reserved
Reserved
VSET0[5]
VSET0[4]
VSET0[3]
VSET0[2]
VSET0[1]
VSET0[0]
0
0
1
0
0
1
0
0
NAME
Reserved
Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
DEFAULTc
NAME
DEFAULTc
0
0
1
0
0
1
0
0
ON
Reserved
Reserved
Reserved
Reserved
PHASE
nFLTMSK
OK
1
1
0
0
0
1
0
R
NAME
Reserved
Reserved
VSET0[5]
VSET0[4]
VSET0[3]
VSET0[2]
VSET0[1]
VSET0[0]
DEFAULTc
NAME
DEFAULTc
0
0
0
1
0
1
0
0
Reserved
Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
0
0
0
1
0
0
0
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
PHASE
nFLTMSK
OK
DEFAULTc
NAME
DEFAULTc
1
1
0
1
0
1
0
R
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
1
0
1
0
1
0
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
DEFAULTc
NAME
DEFAULTc
1
1
0
1
0
1
0
R
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
0
0
1
0
1
0
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
DEFAULTc
NAME
DEFAULTc
1
1
0
0
0
1
0
R
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
ON
1
1
Reserved
1
1
Reserved
0
1
Reserved
1
1
Reserved
0
0
DIS
1
0
nFLTMSK
0
1
OK
R
NAME
DEFAULTc
NAME
DEFAULTc
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
REG8
REG8
0x68
0x69
0
ON
1
1
Reserved
1
0
Reserved
0
1
Reserved
1
0
Reserved
0
1
DIS
1
0
nFLTMSK
0
0
OK
R
DEFAULTc
c: Default values of ACT8840QM188-T.
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ACT8840
Rev 1, 07-Feb-14
GLOBAL REGISTER MAP CONT’D
BITS
BLOCK ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
NAME
DEFAULTc
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
REG9
REG9
REG10
REG10
REG11
REG11
REG12
REG12
REG13
PB
0x70
0x71
0x80
0x81
0x90
0x91
0xA0
0xA1
0xB1
0xC0
0xC1
0xC2
0xC3
0xC5
0xE3
0
1
1
1
0
1
0
0
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
DEFAULTc
1
1
0
0
0
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULTc
NAME
DEFAULTc
0
1
1
1
1
0
0
1
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
1
1
0
1
0
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULTc
NAME
DEFAULTc
0
1
1
0
0
1
0
0
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
1
1
0
1
0
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULTc
NAME
DEFAULTc
0
1
1
1
1
0
0
1
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
1
1
0
1
0
1
0
R
NAME
ON
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DEFAULTc
NAME
DEFAULTc
1
0
PBDMSK
0
0
Reserved
0
0
Reserved
0
0
Reserved
0
0
Reserved
0
0
WDSREN
0
0
PBAMSK
WDPCEN
0
0
NAME
INTADR [7]
INTADR [6] INTADR [5] INTADR [4] INTADR [3] INTADR [2] INTADR [1]
INTADR [0]
PB
DEFAULTc
NAME
DEFAULTc
R
R
R
R
R
R
R
R
PBASTAT
PBDSTAT
PBDAT
Reserved
Reserved
Reserved
Reserved
Reserved
PB
R
R
R
R
R
R
R
R
NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SIPC
PB
DEFAULTc
NAME
DEFAULTc
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCSTAT
SRSTAT
PB
0
0
0
0
0
0
R
R
NAME
PWM6EN
FRE6[2]
FRE6[1]
FRE6[0]
DUTY6[3]
DUTY6[2]
DUTY6[1]
DUTY6[0]
GPIO6
DEFAULTc
NAME
0
0
0
0
0
0
0
0
PWM5EN
FRE5[2]
FRE5[1]
FRE5[0]
DUTY5[3]
DUTY5[2]
DUTY5[1]
DUTY5[0]
GPIO5
GPIO3
GPIO4
GPIO1
GPIO2
0xE4
0xF4
0xF5
0xE5
0xF3
DEFAULTc
0
0
FRE3[2]
0
0
FRE3[1]
0
0
FRE3[0]
0
0
0
0
0
NAME
PWM3EN
DUTY3[3]
DUTY3[2]
DUTY3[1]
DUTY3[0]
DEFAULTc
NAME
DEFAULTc
0
PWM4EN
0
0
DUTY4[3]
0
0
DUTY4[2]
0
0
DUTY4[1]
0
0
DUTY4[0]
0
FRE4[2]
0
FRE4[1]
0
FRE4[0]
0
NAME
PWM1EN
FRE1[2]
FRE1[1]
FRE1[0]
DUTY1[3]
DUTY1[2]
DUTY1[1]
DUTY1[0]
DEFAULTc
NAME
DEFAULTc
0
PWM2EN
0
0
FRE2[2]
0
0
FRE2[1]
0
0
FRE2[0]
0
0
DUTY2[3]
0
0
DUTY2[2]
0
0
DUTY2[1]
0
0
DUTY2[0]
0
c: Default values of ACT8840QM188-T.
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ACT8840
Rev 1, 07-Feb-14
REGISTER AND BIT DESCRIPTIONS
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
Battery Voltage Level Interrupt Mask. Set this bit to 1 to unmask
the interrupt. See the Programmable Battery Voltage Monitor
section for more information
SYS
SYS
0x00
0x00
[7] nBATLEVMSK
R/W
Battery Voltage Status. Value is 1 when BATLEV interrupt is
generated, value is 0 otherwise.
[6]
nBATSTAT
R
Battery Voltage Monitor real time status. Value is 1 when VBAT
< BATLEV, value is 0 otherwise.
SYS
SYS
0x00
0x00
[5]
[4]
VBATDAT
-
R
R/W
Reserved.
Battery Voltage Detect Threshold. Defines the BATLEV voltage
threshold. See the Programmable Battary Voltage Monitor
section for more information.
SYS
0x00
[3:0]
BATLEV
R/W
SYS
SYS
0x01
0x01
[7]
[6]
nTMSK
TSTAT
R/W
R
Thermal Interrupt Mask. Set this bit to 1 to unmask the interrupt.
Thermal Interrupt Status. Value is 1 when a thermal interrupt is
generated, value is 0 otherwise.
SYS
0x01
0x10
[5:0]
[7:6]
-
R/W
R
Reserved.
Reserved.
REG1
-
Primary Output Voltage Selection. See the Output Voltage
Programming section for more information
REG1
0x10
[5:0]
VSET0
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG1
REG1
0x12
0x12
[7]
ON
-
R/W
R
[6:3]
Reserved.
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG1
REG1
0x12
0x12
[2]
[1]
PHASE
R/W
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
nFLTMSK
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG1
REG2
0x12
0x20
[0]
OK
-
R
R
[7:6]
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven
low. See the Output Voltage Programming section for more
information
REG2
REG2
REG2
0x20
0x21
0x21
[5:0]
[7:6]
[5:0]
VSET0
-
R/W
R
Reserved.
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Programming section for more
information.
VSET1
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG2
REG2
0x22
0x22
[7]
ON
-
R/W
R
[6:3]
Reserved.
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG2
REG2
0x22
0x22
[2]
[1]
PHASE
R/W
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
nFLTMSK
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG2
REG3
0x22
0x30
[0]
OK
-
R
R
[7:6]
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven
low. See the Output Voltage Programming section for more
information
REG3
0x30
[5:0]
VSET0
R/W
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Rev 1, 07-Feb-14
REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG3
REG3
0x32
0x32
[7]
ON
-
R/W
[6:3]
R
Reserved.
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG3
REG3
0x32
0x32
[2]
[1]
PHASE
R/W
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
nFLTMSK
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG3
REG4
0x32
0x40
[0]
OK
-
R
R
[7:6]
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven low.
See the Output Voltage Programming section for more
information
REG4
REG4
REG4
0x40
0x41
0x41
[5:0]
[7:6]
[5:0]
VSET0
-
R/W
R
Reserved.
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Programming section for more
information.
VSET1
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG4
REG4
0x42
0x42
[7]
ON
-
R/W
R
[6:3]
Reserved.
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG4
REG4
0x42
0x42
[2]
[1]
PHASE
R/W
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
nFLTMSK
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG4
REG5
REG5
0x42
0x50
0x50
[0]
OK
-
R
R
[7:6]
[5:0]
Reserved.
Output Voltage Selection. See the Output Voltage Programming
section for more information.
VSET
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG5
REG5
0x51
0x51
[7]
ON
-
R/W
R
[6:3]
Reserved.
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG5
REG5
0x51
0x51
[2]
[1]
DIS
R/W
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
nFLTMSK
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG5
REG6
REG6
0x51
0x58
0x58
[0]
OK
-
R
R
[7:6]
[5:0]
Reserved.
Output Voltage Selection. See the Output Voltage Programming
section for more information.
VSET
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG6
REG6
0x59
0x59
[7]
ON
-
R/W
R
[6:3]
Reserved.
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG6
0x59
[2]
DIS
R/W
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ACT8840
Rev 1, 07-Feb-14
REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG6
0x59
[1]
nFLTMSK
R/W
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG6
REG7
REG7
0x59
0x60
0x60
[0]
OK
-
R
R
[7:6]
[5:0]
Reserved.
Output Voltage Selection. See the Output Voltage Programming
section for more information.
VSET
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG7
REG7
0x61
0x61
[7]
ON
-
R/W
R
[6:3]
Reserved.
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG7
REG7
0x61
0x61
[2]
[1]
DIS
R/W
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
nFLTMSK
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG7
REG8
REG8
0x61
0x68
0x68
[0]
OK
-
R
R
[7:6]
[5:0]
Reserved.
Output Voltage Selection. See the Output Voltage Programming
section for more information.
VSET
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG8
REG8
0x69
0x69
[7]
ON
-
R/W
R
[6:3]
Reserved.
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG8
REG8
0x69
0x69
[2]
[1]
DIS
R/W
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
nFLTMSK
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG8
REG9
REG9
0x69
0x70
0x70
[0]
OK
-
R
R
[7:6]
[5:0]
Reserved.
Output Voltage Selection. See the Output Voltage Programming
section for more information.
VSET
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG9
REG9
0x71
0x71
[7]
ON
-
R/W
R
[6:3]
Reserved.
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG9
REG9
0x71
0x71
[2]
[1]
DIS
R/W
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
nFLTMSK
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG9
REG10
REG10
0x71
0x80
0x80
[0]
OK
-
R
R
[7:6]
[5:0]
Reserved.
Output Voltage Selection. See the Output Voltage Programming
section for more information.
VSET
R/W
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REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG10
REG10
0x81
0x81
[7]
ON
R/W
[6:3]
-
R
Reserved.
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG10
REG10
0x81
0x81
[2]
[1]
DIS
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
nFLTMSK
R/W
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG10
REG11
REG11
0x81
0x90
0x90
[0]
OK
-
R
R
[7:6]
[5:0]
Reserved.
Output Voltage Selection. See the Output Voltage Programming
section for more information.
VSET
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG11
REG11
0x91
0x91
[7]
ON
-
R/W
R
[6:3]
Reserved.
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG11
REG11
0x91
0x91
[2]
[1]
DIS
R/W
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
nFLTMSK
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG11
REG12
REG12
0x91
0xA0
0xA0
[0]
OK
-
R
R
[7:6]
[5:0]
Reserved.
Output Voltage Selection. See the Output Voltage Programming
section for more information.
VSET
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG12
REG12
0xA1
0xA1
[7]
ON
-
R/W
R
[6:3]
Reserved.
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG12
0xA1
[2]
DIS
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG12
REG12
0xA1
0xA1
[1]
[0]
nFLTMSK
OK
R/W
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG13
REG13
PB
0xB1
0xB1
0xC0
[7]
[6:0]
7
ON
R/W
R
-
Reserved.
nPBIN Assertion Interrupt Control. Set this bit to 1 to generate
an interrupt when nPBIN is asserted.
nPBAMSK
R/W
nPBIN De-assertion Interrupt Control. Set this bit to 1 to
generate an interrupt when nPBIN is de-asserted.
PB
0xC0
6
nPBDMSK
R/W
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REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
PB
PB
0xC0
0xC0
[5:2]
1
-
R
Reserved.
Watchdog Soft-Reset Enable. Set this bit to 1 to enable
watchdog function. When the watchdog timer expires, the PMU
commences a soft-reset routine. This bit is automatically reset to
0 when entering sleep mode.
WDSREN
R/W
Watchdog Power-Cycle Enable. Set this bit to 1 to enable
watchdog function. When watchdog timer expires, the PMU
commence a power cycle. This bit is automatically reset to 0
when entering sleep mode.
PB
PB
0xC0
0xC1
0
WDPCEN
INTADR
R/W
R
Interrupt Address. It holds the address of the block that triggers
the interrupt. This byte defaults to 0xFF and is automatically set
to 0xFF after being read. Bit 7 is the MSB while Bit 0 is the LSB.
[7:0]
nPBIN Assertion Interrupt Status. The value of this bit is 1 if the
nPBIN Assertion Interrupt is triggered.
PB
PB
0xC2
0xC2
7
6
PBASTAT
PBDSTAT
R
R
nPBIN De-assertion Interrupt Status. The value of this bit is 1 if
the nPBIN De-assertion Interrupt is triggered.
nPBIN Status bit. This bit contains the real-time status of the
nPBIN pin. The value of this bit is 1 if nPBIN is asserted, and is 0
if nPBIN is de-asserted.
PB
0xC2
5
PBASTAT
R
PB
PB
0xC2
0xC3
[4:0]
[7:1]
-
-
R
R
Reserved.
Reserved.
Software Initiated Power Cycle. When this bit is set, the PMU
commences a power cycle after 8ms delay.
PB
PB
PB
0xC3
0xC5
0xC5
0
[7:2]
1
SIPC
-
R/W
R
Reserved.
Power-cycle Flag. The value of this bit is 1 after a power cycle.
This bit is automatically cleared to 0 after read.
PCSTAT
R/W
Soft-reset Flag. The value of this bit is 1 after a soft-reset. This
bit is automatically cleared to 0 after read.
PB
0xC5
0xE3
0xE3
0
SRSTAT
PWM6EN
FRE6
R/W
R/W
R/W
GPIO6
GPIO6
[7]
PWM Function Enable. Set 1 to enable PWM function of GPIO6.
PWM Frequency Selection Bits for GPIO6. See the Table 6 for
code to frequency cross.
[6:4]
Duty Cycle Selection Bits for GPIO6. See the Table 7 for code to
duty cross.
GPIO6
GPIO5
GPIO5
0xE3
0xE4
0xE4
[3:0]
[7]
DUTY6
PWM5EN
FRE5
R/W
R/W
R/W
PWM Function Enable. Set 1 to enable PWM function of GPIO5.
PWM Frequency Selection Bits for GPIO5. See the Table 6 for
code to frequency cross.
[6:4]
Duty Cycle Selection Bits for GPIO5. See the Table 7 for code to
duty cross.
GPIO5
GPIO3
GPIO3
0xE4
0xF4
0xF4
[3:0]
[7]
DUTY5
PWM3EN
FRE3
R/W
R/W
R/W
PWM Function Enable. Set 1 to enable PWM function of GPIO3.
PWM Frequency Selection Bits for GPIO3. See the Table 6 for
code to frequency cross.
[6:4]
Duty Cycle Selection Bits for GPIO3. See the Table 7 for code to
duty cross.
GPIO3
GPIO4
GPIO4
0xF4
0xF5
0xF5
[3:0]
[7]
DUTY3
PWM4EN
FRE4
R/W
R/W
R/W
PWM Function Enable. Set 1 to enable PWM function of GPIO4.
PWM Frequency Selection Bits for GPIO4. See the Table 6 for
code to frequency cross.
[6:4]
Duty Cycle Selection Bits for GPIO4. See the Table 7 for code to
duty cross.
GPIO4
0xF5
[3:0]
DUTY4
R/W
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ACT8840
Rev 1, 07-Feb-14
REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
GPIO1
GPIO1
0xE5
0xE5
[7]
PWM1EN
R/W
PWM Function Enable. Set 1 to enable PWM function of GPIO1.
PWM Frequency Selection Bits for GPIO1. See the Table 6 for
code to frequency cross.
[6:4]
FRE1
R/W
Duty Cycle Selection Bits for GPIO1. See the Table 7 for code to
duty cross.
GPIO1
GPIO2
GPIO2
0xE5
0xF3
0xF3
[3:0]
[7]
DUTY1
PWM2EN
FRE2
R/W
R/W
R/W
PWM Function Enable. Set 1 to enable PWM function of GPIO2.
PWM Frequency Selection Bits for GPIO2. See the Table 6 for
code to frequency cross.
[6:4]
Duty Cycle Selection Bits for GPIO2. See the Table 7 for code to
duty cross.
GPIO2
0xF3
[3:0]
DUTY2
R/W
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ACT8840
Rev 1, 07-Feb-14
SYSTEM CONTROL ELECTRICAL CHARACTERISTICS
(VINL2 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
Input Voltage Range
TEST CONDITIONS
MIN
3.0
TYP
MAX
5.5
UNIT
V
UVLO Threshold Voltage
UVLO Hysteresis
V
INL2 Rising
INL2 Hysteresis
2.6
2.8
200
0.6
3.0
V
V
mV
mA
µA
MHz
V
Operating Supply Current
Shutdown Supply Current
Oscillator Frequency
All Regulators Enabled but no load
All Regulators Disabled except REG13
1.2
20
10
2.0
1.4
2.25
2.5
Logic High Input Voltage
Logic Low Input Voltage
Leakage Current
0.4
1
V
V[nIRQ] = V[nRSTO] = 4.2V
nIRQ, nRSTO, ISINK = 5mA
Temperature rising
µA
V
Low Level Output Voltage
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
0.3
160
20
°C
°C
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ACT8840
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STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = VVP4 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
Operating Voltage Range
UVLO Threshold
CONDITIONS
MIN
2.7
TYP
MAX
5.5
UNIT
V
Input Voltage Rising
Input Voltage Falling
2.5
2.6
100
72
0
2.7
V
UVLO Hysteresis
mV
µA
Standby Supply Current
Shutdown Current
V
V
V
OUT = 103%, Regulator Enabled
VP = 5.5V, Regulator Disabled
OUT ≥ 1.0V, IOUT = 10mA
100
2
µA
c
-1%
-10
VNOM
1%
10
V
Output Voltage Accuracy
VOUT < 1.0V, IOUT = 10mA
VVP = Max (VNOM1 +1V, 3.2V) to 5.5V
IOUT = 10mA to IMAX2
mV
%/V
%/A
%/A
%VNOM
%VNOM
MHz
kHz
µs
Line Regulation
0.15
1.70
1.00
93
Load Regulation REG1/4
Load Regulation REG2/3
Power Good Threshold
Power Good Hysteresis
IOUT = 10mA to IMAX2
V
OUT Rising
VOUT Falling
OUT ≥ 20% of VNOM
2
V
2
2.25
550
400
75
2.5
Switching Frequency
VOUT = 0V
Soft-Start Period
Minimum On-Time
REG1 AND REG4
Maximum Output Current
Current Limit
ns
1.3
1.6
A
A
2.1
0.14
0.08
0
2.6
2
PMOS On-Resistance
NMOS On-Resistance
SW Leakage Current
Input Capacitor
ISW = -100mA
ꢀ
ISW = 100mA
ꢀ
V
VP = 5.5V, VSW = 0 or 5.5V
µA
µF
µF
µH
4.7
33
Output Capacitor
Power Inductor
1.0
2.2
3.3
3.4
2
REG2 AND REG3
Maximum Output Current
Current Limit
1.8
2.3
A
A
2.8
0.095
0.08
0
PMOS On-Resistance
NMOS On-Resistance
SW Leakage Current
Input Capacitor
I
SW = -100mA
ISW = 100mA
VP = 5.5V, VSW = 0 or 5.5V
ꢀ
ꢀ
V
µA
µF
µF
µH
10
Output Capacitor
Power Inductor
44
0.5
1
2.2
c: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
2: IMAX Maximum Output Current.
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ACT8840
Rev 1, 07-Feb-14
LOW-NOISE LDO ELECTRICAL CHARACTERISTICS
(VINL1 = VINL2 = 3.6V, COUT5 = COUT6 = COUT7 = COUT8 = COUT9 = 2.2µF, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
2.5
-1
TYP
MAX
5.5
1
UNIT
V
Operating Voltage Range
c
VOUT ≥ 1.0V, IOUT = 10mA
VNOM
%
Output Voltage Accuracy
V
OUT < 1.0V, IOUT = 10mA
-10
10
mV
Line Regulation
Load Regulation
V
INL = Max (VOUT + 0.5V, 3.6V) to 5.5V
0.5
0.1
75
65
25
0
mV
V/A
IOUT = 1mA to IMAX2
f = 1kHz, IOUT = 20mA, VOUT = 1.2V
f = 10kHz, IOUT = 20mA, VOUT = 1.2V
Regulator Enabled
Power Supply Rejection Ratio
Supply Current per Output
dB
µA
Regulator Disabled
2
Soft-Start Period
VOUT = 3.0V
VOUT Rising
VOUT Falling
140
92
3.5
µs
%
%
Power Good Threshold
Power Good Hysteresis
I
OUT = 20mA, f = 10Hz to 100kHz, VOUT =
Output Noise
30
µVRMS
1.2V
Discharge Resistance
LDO Disabled, DIS[ ] = 1
1.5
kꢀ
LDO rated at 150mA (REG5 & REG6)
Dropout Voltagee
Maximum Output Current
Current Limitf
IOUT = 80mA, VOUT > 3.1V
140
280
280
mV
mA
mA
150
180
VOUT = 95% of regulation voltage
Recommend Output Capacitor
2.2
µF
LDO rated at 350mA (REG7, REG8 & REG9)
Dropout Voltagee
IOUT = 160mA, VOUT > 3.1V
140
mV
mA
mA
µF
Maximum Output Current
Current Limitf
350
400
VOUT = 95% of regulation voltage
Recommend Output Capacitor
2.2
c: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
2: IMAX Maximum Output Current.
3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage (for 3.1V output voltage or higher).
f: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage.
Under heavy overload conditions the output current limit folds back by 50% (typ.).
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ACT8840
Rev 1, 07-Feb-14
LOW-INPUT VOLTAGE LDO ELECTRICAL CHARACTERISTICS
(VINL3 = 3.6V, COUT10 = COUT11 = COUT12 = 2.2µF, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
1.7
-1
TYP
MAX
5.5
1
UNIT
V
Operating Voltage Range
c
VOUT ≥ 1.0V, IOUT = 10mA
OUT < 1.0V, IOUT = 10mA
VINL = Max (VOUT + 0.5V, 3.6V) to 5.5V
OUT = 1mA to IMAX2
VNOM
%
Output Voltage Accuracy
V
-10
10
mV
Line Regulation
Load Regulation
0.5
0.1
50
40
22
0
mV
V/A
I
f = 1kHz, IOUT = 20mA, VOUT = 1.2V
f = 10kHz, IOUT = 20mA, VOUT = 1.2V
Regulator Enabled
Power Supply Rejection Ratio
Supply Current per Output
dB
µA
Regulator Disabled
2
Soft-Start Period
VOUT = 3.0V
VOUT Rising
VOUT Falling
100
92
3.5
µs
%
%
Power Good Threshold
Power Good Hysteresis
I
OUT = 20mA, f = 10Hz to 100kHz, VOUT =
Output Noise
30
µVRMS
1.2V
Discharge Resistance
LDO rated at 150mA (REG10)
Dropout Voltagee
LDO Disabled, DIS[ ] = 1
1.5
kꢀ
IOUT = 80mA, VOUT > 3.1V
100
200
200
mV
mA
mA
µF
Maximum Output Current
Current Limitf
150
180
VOUT = 95% of regulation voltage
Recommend Output Capacitor
2.2
LDO rated at 350mA (REG11 & REG12)
Dropout Voltagee
IOUT = 160mA, VOUT > 3.1V
100
mV
mA
mA
µF
Maximum Output Current
Current Limitf
350
400
VOUT = 95% of regulation voltage
Recommend Output Capacitor
2.2
c: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
2: IMAX Maximum Output Current.
3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage (for 3.1V output voltage or higher).
f: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage.
Under heavy overload conditions the output current limit folds back by 50% (typ.).
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ACT8840
Rev 1, 07-Feb-14
LOW-POWER(ALWAYS-ON) LDO ELECTRICAL CHARACTERISTICS
(VINL1 = 3.6V, COUT13 = 1µF, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REG13
Operating Voltage Range
Output Voltage Accuracy
Line Regulation
2.5
-3
5.5
3
V
c
VNOM
13
%
VINL1 = Max (VOUT + 0.2V, 2.5V) to 5.5V
mV
µA
mA
µF
Supply Current from VINL1
Maximum Output current
Recommend Output Capacitor
5
50
0.47
PWM LED DRIVER ELECTRICAL CHARACTERISTICS
(VINL2 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
Output Current
TEST CONDITIONS
100% Duty Cycle
MIN
TYP
MAX
16
UNIT
mA
V
6
10
Output Low Voltage
Leakage Current
Feed in with 6mA
0.35
1
Sinking from 5.5V source
FRE[2:0] = 000
µA
Hz
%
PWM Frequency
0.25
PWM Duty Adjustment
DUTY[3:0] = 0000 to 1111
6.25
100
c: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
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ACT8840
Rev 1, 07-Feb-14
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C, unless otherwise specified.)
Frequency vs. Temperature
VREF vs. Temperature
2.360
1.204
2.340
1.200
2.320
2.300
1.196
2.280
2.260
1.192
2.240
1.188
1.184
2.220
2.200
2.180
-40 -20
0
20
40
60
80 100 120 140
-40 -20
0
20
40
60
80 100 120 140
Temperature (°C)
Temperature (°C)
Startup of nPBIN, nRSTO, OUT6
Startup of OUT6/2/4/8
CH1
CH1
CH2
CH3
CH4
CH2
CH3
CH1: VOUT6, 1V/div
CH2: VOUT2, 1V/div
CH3: VOUT4, 1V/div
CH4: VOUT8, 1V/div
TIME: 1ms/div
CH1: VnPBIN, 2V/div
CH2: VnRSTO, 2V/div
CH3: VOUT6, 1V/div
TIME: 20ms/div
Startup of OUT8/1/3/9/10
Startup of OUT8/5/7/11/12
CH1
CH2
CH1
CH2
CH3
CH3
CH4
CH4
CH5
CH5
CH1: VOUT8, 1V/div
CH2: VOUT5, 1V/div
CH3: VOUT7, 2V/div
CH4: VOUT11, 2V/div
CH5: VOUT12, 2V/div
TIME: 1ms/div
CH1: VOUT8, 1V/div
CH2: VOUT1, 2V/div
CH3: VOUT3, 1V/div
CH4: VOUT9, 2V/div
CH5: VOUT10, 2V/div
TIME: 1ms/div
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ACT8840
Rev 1, 07-Feb-14
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
Sleep of PWREN, OUT1/3/9
Sleep of PWREN, OUT2/4/6
CH1
CH1
CH2
CH3
CH2
CH3
CH4
CH4
CH1: VPWREN, 3V/div
CH2: VOUT2, 1V/div
CH3: VOUT4, 1V/div
CH4: VOUT6, 1V/div
TIME: 4ms/div
CH1: VPWREN, 3V/div
CH2: VOUT1, 2V/div
CH3: VOUT3, 1V/div
CH4: VOUT9, 2V/div
TIME: 4ms/div
Sleep of PWREN, OUT5/7/8
Sleep of PWREN, OUT10/11/12
CH1
CH2
CH1
CH2
CH3
CH3
CH4
CH4
CH1: VPWREN, 3V/div
CH2: VOUT5, 1V/div
CH3: VOUT7, 2V/div
CH4: VOUT8, 10V/div
TIME: 4ms/div
CH1: VPWREN, 3V/div
CH2: VOUT10, 2V/div
CH3: VOUT11, 2V/div
CH4: VOUT12, 3V/div
TIME: 4ms/div
Shutdown of PWRHLD, OUT1/3/5
nPBIN and nPBSTAT
CH1
CH2
CH1
CH2
CH3
CH4
CH1: VPWRHLD, 2V/div
CH2: VOUT1, 2V/div
CH3: VOUT3, 2V/div
CH4: VOUT5, 1V/div
TIME: 1ms/div
CH1: VnPBIN, 2V/div
CH2: VnPBSTAT, 2V/div
TIME: 10ms/div
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ACT8840
Rev 1, 07-Feb-14
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
Shutdown of PWRHLD, OUT2/4/8
Shutdown of PWRHLD, OUT6/11/12
CH1
CH2
CH1
CH2
CH3
CH3
CH4
CH4
CH1: VPWRHLD, 3V/div
CH2: VOUT6, 1V/div
CH3: VOUT11, 1V/div
CH4: VOUT12, 3V/div
TIME: 1ms/div
CH1: VPWRHLD, 2V/div
CH2: VOUT2, 500mV/div
CH3: VOUT4, 1V/div
CH4: VOUT8, 1V/div
TIME: 1ms/div
Shutdown of PWRHLD, OUT7/9/10
REG1 Efficiency vs. Output Current
100
80
60
40
20
0
VOUT = 1.2V
VIN = 3.6V
CH1
CH2
VIN = 5.0V
VIN = 4.0V
CH3
CH4
0
1
10
100
1000
10000
CH1: VPWRHLD, 3V/div
CH2: VOUT7, 3V/div
CH3: VOUT9, 3V/div
CH4: VOUT10, 3V/div
TIME: 1ms/div
Output Current (mA)
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ACT8840
Rev 1, 07-Feb-14
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG2 Efficiency vs. Output Current
REG3 Efficiency vs. Output Current
100
80
60
40
20
0
100
80
60
40
20
0
VOUT = 1.1V
VIN = 3.6V
VOUT = 1.2V
VIN = 3.6V
VIN = 5.0V
VIN = 5.0V
VIN = 4.0V
VIN = 4.0V
0
1
10
100
1000
10000
0
1
10
100
1000
10000
Output Current (mA)
Output Current (mA)
REG4 Efficiency vs. Output Current
REG10 @ 10mA vs. Temperature
100
80
60
40
20
0
1.205
1.200
1.195
1.190
1.185
1.180
VOUT = 1.1V
VIN = 3.6V
VIN = 5.0V
VIN = 4.0V
0
1
10
100
1000
10000
-40 -20
0
20
40
60
80 100 120 140
Output Current (mA)
Temperature (°C)
VOUT10 @ 150mA vs. Temperature
REG5/6 Dropout Voltage vs. IOUT
400
350
300
250
200
150
100
50
1.186
1.182
1.178
1.174
1.170
0
-40 -20
0
20
40
60
80 100 120 140
0
50
100
150
200
250
Temperature (°C)
Output Current (mA)
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ACT8840
Rev 1, 07-Feb-14
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG5 VOUT vs. IOUT
REG6 VOUT vs. IOUT
1.200
1.160
1.120
1.080
1.040
1.000
1.200
1.160
1.120
1.080
1.040
1.000
0
40
80
120
160
200
0
40
80
120
160
200
Output Current (mA)
Output Current (mA)
REG7/8/9 Dropout Voltage vs. IOUT
REG7 VOUT vs. IOUT
3.400
3.360
3.320
3.280
3.240
3.200
400
300
200
100
0
0
50
100
150
200
250
300
350
0
50
100
150
200 250 300 350 400
Output Current (mA)
Output Current (mA)
REG8 VOUT vs. IOUT
REG9 VOUT vs. IOUT
1.900
1.860
1.820
1.780
1.740
1.700
3.310
3.300
3.290
3.280
3.270
3.260
3.250
0
50
100
150
200
250
300
350
0
50
100
150
200 250 300 350 400
Output Current (mA)
Output Current (mA)
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ACT8840
Rev 1, 07-Feb-14
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG10 Dropout Voltage vs. IOUT
REG10 VOUT vs. IOUT
250
200
150
100
50
1.300
1.260
1.220
1.180
1.140
1.000
0
0
50
100
150
200
0
40
80
120
160
200
Output Current (mA)
Output Current (mA)
REG11 Dropout Voltage vs. IOUT
REG11 VOUT vs. IOUT
250
200
150
100
50
1.200
1.160
1.120
1.080
1.040
1.000
0
0
50
100
150
200
250
300
350
0
100
200
300
400
Output Current (mA)
Output Current (mA)
REG12 Dropout Voltage vs. IOUT
REG12 VOUT vs. IOUT
250
200
150
100
50
1.900
1.860
1.820
1.780
1.740
1.700
0
0
100
200
300
400
0
50
100
150
200
250
300
350
Output Current (mA)
Output Current (mA)
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ACT8840
Rev 1, 07-Feb-14
SYSTEM CONTROL INFORMATION
Interfacing with the Telechips TCC88xx Processors
The ACT8840 is optimized for the general Single-
core processors, supporting both the power
domains as well as the signal interface. The
following paragraphs describe how to design
ACT8840 with the general Single-core processors.
configurations for powering these processors, one
of the most common configurations is detailed in
this datasheet.
While the ACT8840 supports many possible
Table 1:
ACT8840 Power Domains
ACT8840
REGULATOR
DEFAULT
VOLTAGE CURRENT ORDER
MAX
POWER UP
POWER OFF
ORDER
POWER DOMAIN
ON/OFF @ SLEEP
TYPE
VDD_M0
PVDD_MEM
VDD_EXT0~2
VDD_LCD
VDD_AUD
REG1
3.3V
1.3A
3
ON
1
DC/DC Step Down
VDD_SYS0~1
VDD_CKO
VDD_KEY
VDD_MODEM
VDD_IO
REG2
REG3
REG4
VDD_ARM
1.25V
1.8V
1.1V
1.8A
1.8A
1.3A
2
3
2
OFF
ON
2
1
2
DC/DC Step Down
DC/DC Step Down
DC/DC Step Down
VDD_M1~2
VDD_MEM1~2
VDD_INT
OFF
VDD_UOTG_D
VDD_UHOST_D
REG5
REG6
REG7
1.1V
1.1V
3.3V
150mA
150mA
350mA
3
1
3
OFF
ON
1
3
1
Low-Noise LDO
Low-Noise LDO
Low-Noise LDO
VDD_ALIVE
VDD_UOTG_A
VDD_UHOST_A
OFF
VDD_APLL
VDD_MPLL
VDD_VPLL
VDD_EPLL
VDD_HDMI
REG8
1.1V
350mA
2
OFF
2
Low-Noise LDO
VDD_HDMI_PLL
VDD_MIPI_D
VDD_MIPI_PLL
REG9
REG10
REG11
VDD_CAM
VDD_ADC
2.8V
3.3V
1.8V
350mA
150mA
350mA
3
3
3
ON
OFF
OFF
1
1
1
Low-Noise LDO
Low Input-Voltage LDO
Low Input-Voltage LDO
VDD_MIPI_A
VDD_DAC
VDD_DAC_A
VDD_HDMI_OSC
REG12
REG13
3.3V
3.0V
350mA
50mA
3
0
OFF
ON
1
0
Low Input-Voltage LDO
Always-ON LDO
VDD_RTC
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ACT8840
Rev 1, 07-Feb-14
Figure 2:
Control Signals
nPBIN Input
Enable Inputs
The ACT8840 features a variety of control inputs,
which are used to enable and disable outputs
depending upon the desired mode of operation.
PWREN, PWRHLD are logic inputs, while nPBIN is
a unique, multi-function input.
nPBIN Multi-Function Input
The ACT8840 features the nPBIN multi-function
pin, which combines system enable/disable control
with a hardware reset function. Select either of the
two pin functions by asserting this pin, either
through a direct connection to GA, or through a
50kꢀ resistor to GA, as shown in Figure 2.
nRSTO Output
Manual Reset Function
nRSTO is an open-drain output which asserts low
upon startup or when manual reset is asserted via
the nPBIN input. When asserted on startup, nRSTO
remains low until reset time-out period expires.
When asserted due to manual-reset, nRSTO
immediately asserts low, then remains asserted low
until the nPBIN input is de-asserted and the reset
time-out period expires.
The second major function of the nPBIN input is to
provide a manual-reset input for the processor. To
manually-reset the processor, drive nPBIN directly
to GA through a low impedance (less than 2.5kꢀ).
An internal timer detects the duration of the MR
event:
Short Press / Soft-Reset:
Connect a 10kꢀ or greater pull-up resistor from
nRSTO to an appropriate voltage supply.
If the MR is asserted for less than 4s, ACT8840
commences a soft-reset operation where nRSTO
immediately asserts low, then remains asserted low
until the nPBIN input is de-asserted and the reset
time-out period expires. A status bit, SRSTAT[ ] , is
set after a soft-reset event. The SRSTAT[ ] bit is
automatically cleared to 0 after read. After Short
Press, set WDSREN[ ] to 1 about 1s after nRSTO
de-assert then clear WDSREN[ ] for properly
shutdown sequence.
nIRQ Output
nIRQ is an open-drain output that asserts low any
time an interrupt is generated. Connect a 10kꢀ or
greater pull-up resistor from nIRQ to an appropriate
voltage supply. nIRQ is typically used to drive the
interrupt input of the system processor.
Many of the ACT8840's functions support interrupt-
generation as a result of various conditions. These
are typically masked by default, but may be
unmasked via the I2C interface. For more
information about the available fault conditions,
refer to the appropriate sections of this datasheet.
Long Press / Power-cycle:
If the MR is asserted for more than 4s, ACT8840
commences a power cycle routine in which case all
regulators are turned off and then turned back on. A
status bit, PCSTAT[ ], is set after the power cycle.
The PCSTAT[ ] bit is automatically cleared to 0 after
read.
nPBSTAT Output
nPBSTAT is an open-drain output that reflects the
state of the nPBIN input; nPBSTAT is asserted low
whenever nPBIN is asserted, and is high-Z
otherwise. This output is typically used as an
interrupt signal to the processor, to initiate a
software-programmable routine such as operating
mode selection or to open a menu. Connect
nPBSTAT to an appropriate supply voltage through
a 10kꢀ or greater resistor.
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activity for the PMU. In the case where the system
software stops responding and that there is no I2C
transactions for 4s, the watchdog timer expires. As
a result, the PMU either perform a soft-reset or
power cycle, depending on whether WDSREN [ ] or
WDPCEN [ ] is set.
Push-Button Control
The ACT8840 is designed to initiate a system
enable sequence when the nPBIN multi-function
input is asserted. Once this occurs, a power-on
sequence commences, as described below. The
power-on sequence must complete and the
microprocessor must take control (by asserting
PWRHLD) before nPBIN is de-asserted. If the
microprocessor is unable to complete its power-up
routine successfully before the user releases the
push-button, the ACT8840 automatically shuts the
system down. This provides protection against
accidental or momentary assertions of the push-
button. If desired, longer “push-and-hold” times can
be implemented by simply adding an additional time
delay before asserting PWREN or PWRHLD.
Software-Initiated Power Cycle
ACT8840 supports software-initiated power cycle.
Once the SIPC[ ] bit is set, the PMU waits for 8ms
and then initiate a power cycle to restart the entire
system.
Control Sequences
The ACT8840 features
a
variety of control
sequences that are optimized for supporting system
enable and disable.
Enabling/Disabling Sequence
A typical enable sequence is initiated whenever the
nPBIN is asserted low via 50Kꢀ resistance. The
power control diagram is shown in Figure 3. During
the boot sequence, the microprocessor must assert
PWRHLD, and PWREN, to ensure that the system
remains powered after nPBIN is released. Once the
power-up routine is completed, the system remains
enabled after the push-button is released as long as
either PWRHLD is asserted high. If the processor
does not assert PWRHLD before the user releases
the push-button, the boot-up sequence is
terminated and all regulators are disabled. This
provides protection against "false-enable", when the
push-button is accidentally depressed, and also
ensures that the system remains enabled only if the
processor successfully completes the boot-up
sequence.
As with the enable sequence, a typical disable
sequence is initiated when the user presses the
push-button, which interrupts the processor via the
nPBSTAT output. The actual disable sequence is
completely software-controlled, but typically
involved initiating various “clean-up” processes
before the processor finally de-asserts PWRHLD.
Watch-Dog Supervision
The ACT8840 features a watchdog supervisory
function. An internal watchdog timer of 4s is
unmasked by setting either WDSREN[
]
or
WDPCEN [ ] bit to one. Once enabled, the
watchdog timer is reset whenever there is I2C
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Figure 3:
Power Control Sequence
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FUNCTIONAL DESCRIPTION
I2C Interface
Table 2:
BATLEV Falling Threshold
The ACT8840 features an I2C interface that allows
advanced programming capability to enhance overall
system performance. To ensure compatibility with a
wide range of system processors, the I2C interface
supports clock speeds of up to 400kHz (“Fast-Mode”
operation) and uses standard I2C commands. I2C
write-byte commands are used to program the
ACT8840, and I2C read-byte commands are used to
read the ACT8840’s internal registers. The ACT8840
always operates as a slave device, and is addressed
using a 7-bit slave address followed by an eighth bit,
which indicates whether the transaction is a read-
operation or a write-operation, [1011010x].
BATLEV[3:0]
BATLEV Falling
Threshold
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
SDA is a bi-directional data line and SCL is a clock
input. The master device initiates a transaction by
issuing a START condition, defined by SDA
transitioning from high to low while SCL is high. Data
is transferred in 8-bit packets, beginning with the
MSB, and is clocked-in on the rising edge of SCL.
Each packet of data is followed by an “Acknowledge”
(ACK) bit, used to confirm that the data was
transmitted successfully.
For more information regarding the I2C 2-wire serial
interface, go to the NXP website: http://www.nxp.com.
Housekeeping Functions
Programmable battery Voltage Monitor
The ACT8840 features a programmable battery-
voltage monitor, which monitors the voltage at INL2
(which should be connected directly to the battery)
and compares it to a programmable threshold
voltage. The VBATMON comparator is designed to
be immune to noise resulting from switching, load
transients, etc. The BATMON comparator is disable
by default; to enable it, set the BATLEV[3:0] register
to one of the value in Table 2. Note that there is a
200mV hysteresis between the rising and falling
threshold for the comparator. The VBATDAT [-] bit
reflects the output of the BATMON comparator. The
value of VBATDAT[ ] is 1 when VINL2 < BATLEV;
value is 0 otherwise.
Thermal Protection
The ACT8840 integrates thermal shutdown
protection circuitry to prevent damage resulting
from excessive thermal stress, as may be
encountered under fault conditions.
Thermal Interrupt
If the thermal interrupt is unmasked (by setting
nTMSK[ ] to 1), ACT8840 can generate an interrupt
when the die temperature reaches 120°C (typ.).
Thermal Protection
The VBATMON comparator can generate an
interrupt when VINL2 is lower than BATLEV[ ] voltage.
The interrupt is masked by default by can be
unmasked by setting VBATMSK[ ] = 1.
If the ACT8840 die temperature exceeds 160°C, the
thermal protection circuitry disables all regulators
and prevents the regulators from being enabled until
the IC temperature drops by 20°C (typ.).
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STEP-DOWN DC/DC REGULATORS
Input Capacitor Selection
General Description
The input capacitor reduces peak currents and noise
induced upon the voltage source. A 10μF ceramic
capacitor is recommended for each regulator in most
applications.
REG1, REG2, REG3, and REG4 are fixed-frequency,
current-mode, synchronous PWM step-down
converters that achieves peak efficiencies of up to
97%. These regulators operate with a fixed frequency
of 2.25MHz, minimizing noise in sensitive
applications and allowing the use of small external
components. Additionally, REG1, REG2, REG3, and
REG4 are available with a variety of standard and
custom output voltages, and may be software-
controlled via the I2C interface for systems that
require advanced power management functions.
Output Capacitor Selection
REG1, REG2, REG3, and REG4 were designed to
take advantage of the benefits of ceramic capacitors,
namely small size and very-low ESR. REG1, REG2,
REG3 and REG4 are designed to operate with 33uF
or 44uF output capacitor over most of their output
voltage ranges, although more capacitance may be
desired depending on the duty cycle and load step
requirements.
100% Duty Cycle Operation
REG1, REG2, REG3, and REG4 are capable of
operating at up to 100% duty cycle. During 100%
duty cycle operation, the high-side power MOSFETs
Two of the most common dielectrics are Y5V and
X5R. Whereas Y5V dielectrics are inexpensive and
can provide high capacitance in small packages, their
capacitance varies greatly over their voltage and
temperature ranges and are not recommended for
DC/DC applications. X5R and X7R dielectrics are
more suitable for output capacitor applications, as
their characteristics are more stable over their
operating ranges, and are highly recommended.
are held on continuously, providing
a
direct
connection from the input to the output (through the
inductor), ensuring the lowest possible dropout
voltage in battery powered applications.
Operating Mode
By default, REG1, REG2, REG3, and REG4 operate
in fixed-frequency PWM mode at medium to heavy
loads, then transition to a proprietary power-saving
mode at light loads in order to save power.
Inductor Selection
REG1, REG2, REG3, and REG4 utilize current-mode
control and a proprietary internal compensation
scheme to simultaneously simplify external
component selection and optimize transient
performance over their full operating range. These
devices were optimized for operation with 2.2μH or
1μH inductors. Choose an inductor with a low DC-
resistance, and avoid inductor saturation by choosing
inductors with DC ratings that exceed the maximum
output current by at least 30%.
Synchronous Rectification
REG1, REG2, REG3, and REG4 each feature
integrated synchronous rectifiers, maximizing
efficiency and minimizing the total solution size and
cost by eliminating the need for external rectifiers.
Soft-Start
REG1, REG2, REG3, and REG4 include internal 400
us soft-start ramps which limit the rate of change of
the output voltage, minimizing input inrush current
and ensuring that the output powers up in a
monotonic manner that is independent of loading on
the outputs. This circuitry is effective any time the
regulator is enabled, as well as after responding to a
short-circuit or other fault condition.
Configuration Options
Output Voltage Programming
By default, each regulator powers up and regulates to
its default output voltage. For REG2, REG3 and
REG4, the output voltage is selectable by setting
corresponding VSEL pin that when VSEL is low,
output voltage is programmed by VSET0[-] bits, and
when VSEL is high, output voltage is programmed by
VSET1[-] bits. Also, once the system is enabled,
each regulator's output voltage may be independently
programmed to a different value. Program the output
voltages via the I2C serial interface by writing to the
regulator's VSET0[-] register if VSEL is low or
VSET1[-] register if VSEL is high as shown in Table
3.
Compensation
REG1, REG2, REG3, and REG4 utilize current-mode
control and a proprietary internal compensation
scheme to simultaneously simplify external
component selection and optimize transient
performance over their full operating range. No
compensation design is required; simply follow a few
simple guide lines described below when choosing
external components.
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gradients in the ground plane, both of which can
result in instability or regulation errors.
Enable / Disable Control
During normal operation, each buck may be enabled
or disabled via the I2C interface by writing to that
regulator's ON[ ] bit.
Step-down DC/DCs exhibit discontinuous input
current, so the input capacitors should be placed as
close as possible to the IC, and avoiding the use of
via if possible. The inductor, input filter capacitor, and
output filter capacitor should be connected as close
together as possible, with short, direct, and wide
traces. The ground nodes for each regulator's power
loop should be connected at a single point in a star-
ground configuration, and this point should be
connected to the backside ground plane with multiple
via. The output node for each regulator should be
connected to its corresponding OUTx pin through the
shortest possible route, while keeping sufficient
distance from switching nodes to prevent noise
injection. Finally, the exposed pad should be directly
connected to the backside ground plane using
multiple via to achieve low electrical and thermal
resistance.
OK[ ] and Output Fault Interrupt
Each DC/DC features a power-OK status bit that can
be read by the system microprocessor via the I2C
interface. If an output voltage is lower than the power-
OK threshold, typically 7% below the programmed
regulation voltage, that regulator's OK[ ] bit will be 0.
If a DC/DC's nFLTMSK[-] bit is set to 1, the ACT8840
will interrupt the processor if that DC/DC's output
voltage falls below the power-OK threshold. In this
case, nIRQ will assert low and remain asserted until
either the regulator is turned off or back in regulation,
and the OK[ ] bit has been read via I2C.
PCB Layout Considerations
High switching frequencies and large peak currents
make PC board layout an important part of step-down
DC/DC converter design. A good design minimizes
excessive EMI on the feedback paths and voltage
Table 3:
REGx/VSET[ ] Output Voltage Setting
REGx/VSET[5:3]
REGx/VSET[2:0]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
0.600
0.625
0.650
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.250
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
2.100
2.150
2.200
2.250
2.300
2.350
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
3.300
3.400
3.500
3.600
3.700
3.800
3.900
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LOW-NOISE, LOW-DROPOUT LINEAR REGULATORS
General Description
Output Discharge
Each of the LDOs features an optional output
discharge function, which discharges the output to
ground through a 1.5kꢀ resistance when the LDO is
disabled. This feature may be enabled or disabled
by setting DIS[-]; set DIS[-] to 1 to enable this
function, clear DIS[-] to 0 to disable it.
ACT8840 features eight low-noise, low-dropout
linear regulators (LDOs) that supply up to 350mA.
Three of these LDOs (REG10, REG11, and
REG12) supports extended input voltage range
down to 1.7V. Each LDO has been optimized to
achieve low noise and high-PSRR.
OK[ ] and Output Fault Interrupt
Output Current Limit
Each LDO features a power-OK status bit that can
be read by the system microprocessor via the
interface. If an output voltage is lower than the
power-OK threshold, typically 11% below the
programmed regulation voltage, the value of that
regulator's OK[-] bit will be 0.
Each LDO contains current-limit circuitry featuring a
current-limit fold-back function. During normal and
moderate overload conditions, the regulators can
support more than their rated output currents.
During extreme overload conditions, however, the
current limit is reduced by approximately 30%,
reducing power dissipation within the IC.
If a LDO's nFLTMSK[-] bit is set to 1, the ACT8840
will interrupt the processor if that LDO's output
voltage falls below the power-OK threshold. In this
case, nIRQ will assert low and remain asserted until
either the regulator is turned off or back in
regulation, and the OK[-] bit has been read via I2C.
Compensation
The LDOs are internally compensated and require
very little design effort, simply select input and
output capacitors according to the guidelines below.
Input Capacitor Selection
PCB Layout Considerations
Each LDO requires a small ceramic input capacitor
to supply current to support fast transients at the
input of the LDO. Bypassing each INL pin to GA
with 1μF. High quality ceramic capacitors such as
X7R and X5R dielectric types are strongly
recommended.
The ACT8840’s LDOs provide good DC, AC, and
noise performance over a wide range of operating
conditions, and are relatively insensitive to layout
considerations. When designing a PCB, however,
careful layout is necessary to prevent other circuitry
from degrading LDO performance.
A good design places input and output capacitors
as close to the LDO inputs and output as possible,
and utilizes a star-ground configuration for all
regulators to prevent noise-coupling through
ground. Output traces should be routed to avoid
close proximity to noisy nodes, particularly the SW
nodes of the DC/DCs.
Output Capacitor Selection
Each LDO requires a small 2.2μF ceramic output
capacitor for stability . For best performance, each
output capacitor should be connected directly
between the output and GA pins, as close to the
output as possible, and with a short, direct
connection. High quality ceramic capacitors such as
X7R and X5R dielectric types are strongly
recommended.
REFBP is a noise-filtered reference, and internally
has a direct connection to the linear regulator
controller. Any noise injected onto REFBP will
directly affect the outputs of the linear regulators,
and therefore special care should be taken to
ensure that no noise is injected to the outputs via
REFBP. As with the LDO output capacitors, the
REFBP bypass capacitor should be placed as close
to the IC as possible, with short, direct connections
to the star-ground. Avoid the use of via whenever
possible. Noisy nodes, such as from the DC/DCs,
should be routed as far away from REFBP as
possible.
Configuration Options
Output Voltage Programming
By default, each LDO powers up and regulates to
its default output voltage. Once the system is
enabled, each output voltage may be independently
programmed to a different value by writing to the
regulator's VSET[-] register via the I2C serial
interface as shown in Table 3.
Enable / Disable Control
During normal operation, each LDO may be
enabled or disabled via the I2C interface by writing
to that LDO's ON[ ] bit.
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ALWAYS-ON LDO (REG13)
General Description
REG13 is an always-on, low-dropout linear
regulator (LDO) that is optimized for RTC and
backup-battery applications. REG13 features low-
quiescent supply current, current-limit protection,
and reverse-current protection, and is ideally suited
for always-on power supply applications, such as
for a real-time clock, or as a backup-battery or
super-cap charger.
Reverse-Current Protection
REG13 features internal circuitry that limits the
reverse supply current to less than 1µA when the
input voltage falls below the output voltage, as can
be encountered in backup-battery charging
applications. REG13's internal circuitry monitors the
input and the output, and disconnects internal
circuitry and parasitic diodes when the input voltage
falls below the output voltage, greatly minimizing
backup battery discharge.
Typical Application
Voltage Regulators
REG13 is ideally suited for always-on voltage-
regulation applications, such as for real-time clock
and memory keep-alive applications. This regulator
requires only a small ceramic capacitor with a
minimum capacitance of 0.47μF for stability. For
best performance, the output capacitor should be
connected directly between the output and GA, with
a short and direct connection.
Figure 4:
Typical Application of RTC LDO
Backup Battery Charging
REG13 features a constant current-limit, which
protects the IC under output short-circuit conditions
as well as provides a constant charge current, when
operating as a backup battery charger.
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PWM LED DRIVERS
Table 5:
GPIOx/DUTY[ ] PWM Frequency Setting
The GPIO1, the GPIO2, the GPIO3, the GPIO4, the
GPIO5, and the GPIO6 are configured as PWM
LED drivers, which could support up to 6mA current
with programmable frequency and duty cycle. Set
PWMxEN[ ] bit to “1” to enable PWM function of
GPIOx.
GPIOx/DUTY[3:0]
0000
PWM Duty Cycle [%]
6.25
12.5
18.75
25
0001
PWM Frequence Selection
0010
Each LED driver may be independently
programmed to a different frequency by writing to
the GPIO’s FRE[2:0] register via the I2C serial
interface as shown in Table 4.
0011
0100
31.25
37.5
43.75
50
0101
Table 4:
0110
GPIOx/FRE[ ] PWM Frequency Setting
0111
GPIOx/FRE[2:0]
PWM Frequency [Hz]
1000
56.25
62.5
68.75
75
000
001
010
011
100
101
0.25
0.5
1
1001
1010
1011
2
1100
81.25
87.5
93.75
100
128
256
1101
1110
1111
PWM Duty Cycle Selection
Each LED driver may be independently
programmed to a different duty cycle by writing to
the GPIO’s DUTY[3:0] register via the I2C serial
interface as shown in Table 5.
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ACT8840
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TQFN66-48 PACKAGE OUTLINE AND DIMENSIONS
DIMENSION IN
MILLIMETERS
DIMENSION IN
INCHES
SYMBOL
MIN
MAX
MIN
MAX
A
A1
A2
b
0.700
0.800
0.032
0.036
0.200 REF
0.008 REF
0.000
0.150
0.000
0.006
0.050
0.250
0.002
0.010
D
6.00
6.00
0.24
0.24
E
D2
E2
e
4.15
4.15
4.40
4.40
0.166
0.166
0.176
0.176
0.400 BSC
0.300 0.500
0.300
0.016 BSC
0.012 0.020
0.012
L
R
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product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use
as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of
the use of any product or circuit described in this datasheet, nor does it convey any patent license.
Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact
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is a registered trademark of Active-Semi.
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