U62H256ASK35LLG1 [ZMD]
AUTOMOTIVE FAST 32K X 8 SRAM; 汽车高速32K ×8 SRAM型号: | U62H256ASK35LLG1 |
厂家: | Zentrum Mikroelektronik Dresden AG |
描述: | AUTOMOTIVE FAST 32K X 8 SRAM |
文件: | 总10页 (文件大小:162K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
U62H256A
Automotive Fast 32K x 8 SRAM
Features
Description
! 32768 x 8 bit static CMOS RAM
! 35 and 55 ns Access Time
! Common data inputs and
data outputs
The U62H256A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
go High-Z until the new information
is available. The data outputs have
no preferred state. The Read cycle
is finished by the falling edge of W,
or by the rising edge of E, respec-
tively.
! Three-state outputs
! Typ. operating supply current
35 ns: 45 mA
- Read
- Write
- Standby
- Data Retention
The memory array is based on a
6-transistor cell.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
55 ns: 30 mA
! Standby current < 50 µA at 125 °C The circuit is activated by the fal-
! TTL/CMOS-compatible
! Power supply voltage 5 V
! Operating temperature range
-40 °C to 85 °C
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word will be available at the
outputs DQ0-DQ7. After the
address change, the data outputs
-40 °C to 125 °C
! QS 9000 Quality Standard
! ESD protection > 2000 V
(MIL STD 883C M3015.7)
! Latch-up immunity >100 mA
! Package: SOP28 (300/330 mil)
Pin Configuration
Pin Description
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A14
A12
A7
2
W
3
A13
A8
Signal Name Signal Description
A6
4
A5
5
A9
A0 - A14
Address Inputs
DQ0 - DQ7
Data In/Out
A4
6
A11
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
E
G
W
VCC
A3
7
G
SOP
A2
8
A10
A1
9
E
DQ7
A0
10
11
12
13
14
VSS
DQ0
DQ1
DQ2
VSS
DQ6
DQ5
DQ4
DQ3
Top View
April 20, 2004
1
U62H256A
Block Diagram
A6
A7
Memory Cell
Array
A8
A9
A10
A11
A12
A13
A14
512 Rows x
64 x 8 Columns
A0
A1
A2
A3
A4
A5
DQ0
DQ1
Sense Amplifier/
Write Control Logic
DQ2
DQ3
DQ4
DQ5
Address
Change
Detector
Clock
DQ6
DQ7
Generator
VCC
VSS
E
W
G
Truth Table
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
Internal Read
Read
H
L
L
L
*
*
H
L
*
High-Z
H
H
L
High-Z
Data Outputs Low-Z
Data Inputs High-Z
Write
H or L
*
2
April 20, 2004
U62H256A
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage.
a
Absolute Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.5
-0.5
-
7
VCC + 0.5
VCC + 0.5
1
V
V
b
b
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
W
°C
K-Type
A-Type
-40
-40
85
125
Storage Temperature
Tstg
-65
150
°C
Output Short-Circuit Current
at VCC = 5 V and VO = 0 V c
| IOS
|
200
mA
a
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at condition above those indicated in the operational sections of this specification isnot implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability
b
c
Maximum voltage is 7 V
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Recommended
Symbol
VCC
Conditions
Min.
4.5
Max.
5.5
Unit
V
Operating Conditions
Power Supply Voltage
d
Input Low Voltage
VIL
-0.3
2.2
0.8
V
Input High Voltage
VIH
VCC + 0.3
V
d
-2 V at Pulse Width 10 ns
April 20, 2004
3
U62H256A
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
ICC(OP)
VCC
VIL
= 5.5 V
= 0.8 V
= 2.2 V
= 35 ns
= 55 ns
VIH
tcW
tcW
90
70
mA
mA
Supply Current - Standby Mode
(CMOS level)
ICC(SB)
VCC
VE
= 5.5 V
= VCC - 0.2 V
K-Type
A-Type
10
50
µA
µA
Supply Current - Standby Mode
(TTL level)
ICC(SB)1
VCC
VE
= 5.5 V
= 2.2 V
1
mA
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
= 4.5 V
2.4
V
V
= -4.0 mA
= 4.5 V
VCC
IOL
0.4
2
= 8.0 mA
Input High Leakage Current
Input Low Leakage Current
IIH
IIL
VCC
VIH
= 5.5 V
= 5.5 V
= 5.5 V
µA
µA
VCC
VIL
-2
8
=
0 V
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V
-4
2
mA
mA
Output Leakage Current
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 5.5 V
= 5.5 V
= 5.5 V
µA
µA
Low at Three-State Outputs
-2
=
0 V
4
April 20, 2004
U62H256A
Symbol
35
55
Switching Characteristics
Read Cycle
Unit
Max.
Min.
Max.
Min.
Alt.
tRC
tAA
tACE
tOE
IEC
tcR
Read Cycle Time
35
55
ns
Address Access Time to Data Valid
Chip Enable Access Time to Data Valid
G LOW to Data Valid
ta(A)
35
35
15
15
12
55
55
25
20
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta(E)
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
E HIGH to Output in High-Z
G HIGH to Output in High-Z
E LOW to Output in Low-Z
G LOW to Output in Low-Z
Output Hold Time from Address Change
E LOW to Power-Up Time
tHZCE
tHZOE
tLZCE
tLZOE
tOH
3
0
3
0
3
0
3
0
tPU
E HIGH to Power-Down Time
tPD
35
55
Symbol
35
55
Switching Characteristics
Write Cycle
Unit
Alt.
tWC
IEC
tcW
Min.
35
20
20
0
Max.
Min.
55
35
35
0
Max.
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
tWP
tw(W)
tsu(W)
tsu(A)
Write Setup Time
tWP
Address Setup Time
tAS
t
Address Valid to End of Write
Chip Enable Setup Time
Pulse Width Chip Enable to End of Write
Data Setup Time
tAW
25
25
25
15
0
40
40
40
25
0
su(A-WH)
tCW
tsu(E)
tCW
tw(E)
tsu(D)
th(D)
tDS
Data Hold Time
tDH
Address Hold from End of Write
W LOW to Output in High-Z
G HIGH to Output in High-Z
W HIGH to Output in Low-Z
G LOW to Output in Low-Z
tAH
th(A)
0
0
tHZWE
tHZOE
tLZWE
tLZOE
tdis(W)
tdis(G)
ten(W)
ten(G)
15
12
20
15
0
0
0
0
April 20, 2004
5
U62H256A
Data Retention Mode
E - controlled
VCC
4.5 V
VCC(DR) ≥ 2 V
2.2 V
2.2 V
tsu(DR)
trec
Data Retention
E
0 V
V
- 0.2 V ≤ V
≤ V
+ 0.3 V
CC(DR)
CC(DR)
E(DR)
Data Retention
Characteristics
Symbol
Conditions
Min. Typ. Max.
Unit
Alt.
IEC
Data Retention Supply Voltage
Data Retention Supply Current
VCC(DR)
2
5.5
V
ICC(DR) VCC(DR) = 3 V
VE
= VCC(DR) - 0.2 V
K-Type
A-Type
6
µA
µA
30
Data Retention Setup Time
Operating Recovery Time
tCDR
tR
tsu(DR) See Data Retention
0
ns
ns
Waveforms (above)
trec
tcR
Test Configuration for Functional Check
5 V
VCC
A0
A1
A2
A3
DQ0
DQ1
DQ2
A4
481
A5
A6
VIH
VIL
A7
DQ3
A8
A9
DQ4
DQ5
DQ6
DQ7
A10
A11
A12
A13
A14
VO
30 pF e
E
W
G
255
VSS
e
In measurement of t
,t
, t
, t
, t
the capacitance is 5 pF.
dis(E) dis(W) en(E) en(W) en(G)
6
April 20, 2004
U62H256A
Capacitance
Conditions
Symbol
Min.
Max.
Unit
Input Capacitance
VCC
= 5.0 V
= VSS
CI
7
pF
VI
f
= 1 MHz
= 25 °C
Output Capacitance
Co
7
pF
T
a
All pins not under test must be connected with ground by capacitors.
Ordering Code
Example
U62H256A
S
K
35 LL
Type
Leadfree Option
blank= Standard Package
Package
G1 = Leadfree Green Package f
S = SOP28 (300 mil)
S2 = SOP28 (330 mil) Type 2
Power Consumption
blank= Standard (only A-Type)
Operating Temperature Range
K = -40 to 85 °C
LL
= Very Low Power (only K-Type)
Access Time
35 = 35 ns
55 = 55 ns
A = -40 to 125 °C
f on special request
Device Marking (example)
ZMD
Product specification
Date of manufacture
U62H256ASK
35LL C 0425
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
Assembly location and
trace code
1 ZZ
G1
Internal Code
Leadfree Green Package
April 20, 2004
7
U62H256A
Read Cycle 1: Ai-controlled (during Read Cycle : E = G = VIL, W = VIH)
tcR
Ai
Address Valid
ta(A)
DQi
Previous Data Valid
tv(A)
Output Data Valid
Output
Read Cycle 2: G-, E-controlled (during Read Cycle: W = VIH)
tcR
Ai
E
Address Valid
ta(E)
tdis(E)
tsu(A)
ten(E)
ta(G)
tdis(G)
G
ten(G)
DQi
High-Z
tPU
Output Data Valid
tPD
Output
ICC(OP)
ICC(SB)
50 %
50 %
8
April 20, 2004
U62H256A
Write Cycle1: W-controlled
tcW
Ai
Address Valid
tsu(E)
th(A)
E
tsu(A-WH)
tw(W)
W
tsu(A)
tsu(D)
th(D)
DQi
Input Data Valid
Input
tdis(W)
ten(W)
DQi
High-Z
Output
G
Write Cycle 2: E-controlled
tcW
Ai
E
Address Valid
tsu(A)
th(A)
tw(E)
tsu(W)
W
th(D)
tsu(D)
DQi
Input Data Valid
tdis(W)
Input
ten
(E)
High-Z
DQi
tdis(G)
Output
G
undefined
L- to H-level
H- to L-level
The information describes the type of component and shall not be considered as assured characteristics.Terms of
delivery and rights to change design reserved.
April 20, 2004
9
U62H256A
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
April 20, 2004
Zentrum Mikroelektronik Dresden AG
Grenzstraße 28 • D-01109 Dresden •P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de
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