Z8F0430 [ZILOG]
High-Performance 8-Bit Microcontrollers; 高性能8位微控制器
| 型号： | Z8F0430 |
| 厂家： | 
ZILOG, INC. |
| 描述： | High-Performance 8-Bit Microcontrollers |
| 文件： | 总257页 (文件大小：1209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High-Performance 8-Bit Microcontrollers
Z8 Encore!® F0830 Series
Product Specification
PS025113-1212
Copyright ©2012 Zilog®, Inc. All rights reserved.
www.zilog.com
Z8 Encore!® F0830 Series
Product Specification
ii
DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
Warning:
LIFE SUPPORT POLICY
ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti-
cal component is any component in a life support device or system whose failure to perform can be reason-
ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2012 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES or TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES or TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
Z8, Z8 Encore! and Z8 Encore! XP are trademarks or registered trademarks of Zilog, Inc. All other product
or service names are the property of their respective owners.
PS025113-1212
Disclaimer
Z8 Encore!® F0830 Series
Product Specification
iii
Revision History
Each instance in this document’s revision history reflects a change from its previous edi-
tion. For more details, refer to the corresponding page(s) or appropriate links furnished in
the table below.
Revision
Date Level
Page
No.
Chapter/Section
Description
Dec
2012
13
GPIO
Modified GPIO Port D0 language in Shared 35, 36
Reset Pin section and Port Alternate Func-
tion Mapping table.
Sep
12
LED Drive Enable Register
Clarified statement surrounding the Alternate 51,
2011
Function Register as it relates to the LED
115,
function; revised Sector Based Flash Protec- 199
tion description; revised Packaging chapter.
Dec
2007
11
10
n/a
Updated all instances of Z8 Encore! XP
F0830 to Z8 Encore! F0830.
All
Nov
2007
DC Characteristics, On-Chip
Peripheral AC and DC Electri-
cal Characteristics
Updated Tables 116 and and 122.
185,
193
Sep
2007
09
Timers, PWM SINGLE OUT-
PUT Mode, PWM DUAL OUT-
PUT Mode, Analog-to-Digital
Converter, Reference Buffer.
Updated Figures 2 and 4, Table 4.
8, 9,
11, 68,
74, 75,
98,
101
Apr
2007
08
07
Optimizing NVDS Memory
Usage for Execution Speed,
On-Chip Peripheral AC and DC and Table 122 in Electrical Characteristics
Electrical Characteristics chapter. Other style updates.
Added a note under Table 93 in Nonvolatile 137,
Data Storage chapter. Updated Table 121
193,
193
Dec
General Purpose Input/Output Added PD0 in Table 16.
38
2006
Overview, Interrupt Controller Changed the number of interrupts to 17.
1,5, 53
136
Nonvolatile Data Storage
Updated chapter.
Oscillator Control Register Defi- Updated Tables 117 and 122. Added
nitions, AC Characteristics, On- Figure 24.
Chip Peripheral AC and DC
156,
189,
193
Electrical Characteristics
Ordering Information
n/a
Updated Part Number Suffix Designations.
205
All
Removed Preliminary stamp from footer.
PS025113-1212
Revision History
Z8 Encore!® F0830 Series
Product Specification
iv
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
General Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Nonvolatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
External Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Acronyms and Expansions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reset and Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PS025113-1212
Table of Contents
Z8 Encore!® F0830 Series
Product Specification
v
Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
External Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
External Reset Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Stop Mode Recovery using WDT Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Stop Mode Recovery using GPIO Port Pin Transition . . . . . . . . . . . . . . . . . . . . . . . 27
Stop Mode Recovery Using the External RESET Pin . . . . . . . . . . . . . . . . . . . . . . . 28
Debug Pin Driven Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reset Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Peripheral Level Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
General Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
GPIO Port Availability by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Direct LED Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Shared Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Crystal Oscillator Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5V Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
External Clock Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Port A–D Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Port A–D Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Port A–D Data Direction Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Port A–D Alternate Function Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Port A–C Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port A–D Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
LED Drive Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LED Drive Level High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LED Drive Level Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
PS025113-1212
Table of Contents
Z8 Encore!® F0830 Series
Product Specification
vi
Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Shared Interrupt Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Timer Pin Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Timer 0–1 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Timer 0–1 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Timer 0–1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Watchdog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Watchdog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Watchdog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Watchdog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Watchdog Timer Reload Upper, High and Low Byte Registers . . . . . . . . . . . . . . . 96
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
ADC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Reference Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Internal Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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Table of Contents
Z8 Encore!® F0830 Series
Product Specification
vii
Calibration and Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
ADC Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Sample Settling Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Sample Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Comparator Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Data Memory Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Flash Operation Timing Using the Flash Frequency Registers . . . . . . . . . . . . . . . 114
Flash Code Protection Against External Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Flash Code Protection Against Accidental Program and Erasure . . . . . . . . . . . . . 114
Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
NVDS Operational Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Flash Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Option Bit Configuration by Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Option Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Flash Option Bit Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Trim Bit Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Trim Bit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Flash Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Trim Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Nonvolatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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Z8 Encore!® F0830 Series
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Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
NVDS Code Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Power Failure Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Optimizing NVDS Memory Usage for Execution Speed . . . . . . . . . . . . . . . . . . . . 137
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
DEBUG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
OCD Autobaud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Runtime Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
On-Chip Debugger Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
System Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Clock Failure Detection and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Oscillator Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Oscillator Operation with an External RC Network . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Op Code Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
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Z8 Encore!® F0830 Series
Product Specification
ix
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 190
General Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . . . . . . . 195
General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Appendix A. Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
General Purpose RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Low Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
LED Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Comparator 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
GPIO Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Trim Bit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Flash Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
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Z8 Encore!® F0830 Series
Product Specification
x
List of Figures
Figure 1. Z8 Encore! F0830 Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Z8F0830 Series in 20-Pin SOIC, SSOP, PDIP Package . . . . . . . . . . . . . . . . 8
Figure 3. Z8F0830 Series in 28-Pin SOIC, SSOP, PDIP Package . . . . . . . . . . . . . . . . 8
Figure 4. Z8F0830 Series in 20-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Z8F0830 Series in 28-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 10. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 11. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 12. ADC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 13. ADC Convert Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 14. 1K Flash with NVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 15. 2K Flash with NVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 16. 4K Flash with NVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 17. 8K Flash with NVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 18. 12K Flash without NVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 19. Flash Controller Operation Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 20. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 21. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface,
#1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 22. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface,
#2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 23. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 24. Oscillator Control Clock Switching Flow Chart . . . . . . . . . . . . . . . . . . . . 156
Figure 25. Recommended 20MHz Crystal Oscillator Configuration . . . . . . . . . . . . . 158
Figure 26. Connecting the On-Chip Oscillator to an External RC Network . . . . . . . . 159
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List of Figures
Z8 Encore!® F0830 Series
Product Specification
xi
Figure 27. Typical RC Oscillator Frequency as a Function of External Capacitance
with a 45 kΩ Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 28. Op Code Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 29. First Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 30. Second Op Code Map after 1FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 31. ICC Versus System Clock Frequency (HALT Mode) . . . . . . . . . . . . . . . . 187
Figure 32. ICC Versus System Clock Frequency (NORMAL Mode) . . . . . . . . . . . . . 188
Figure 33. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 34. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 35. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 36. Flash Current Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
PS025113-1212
List of Figures
Z8 Encore!® F0830 Series
Product Specification
xii
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Z8 Encore! F0830 Series Family Part Selection Guide . . . . . . . . . . . . . . . . . 2
Acronyms and Expansions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Z8 Encore! F0830 Series Package Options . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Characteristics (20- and 28-pin Devices) . . . . . . . . . . . . . . . . . . . . . . . 13
Z8 Encore! F0830 Series Program Memory Maps . . . . . . . . . . . . . . . . . . . 15
Z8 Encore! F0830 Series Flash Memory Information Area Map . . . . . . . . 16
Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reset and Stop Mode Recovery Characteristics and Latency . . . . . . . . . . . 22
Table 10. Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Stop Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . . . 27
Table 12. POR Indicator Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. Reset Status Register (RSTSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. Power Control Register 0 (PWRCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 15. Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. Port Alternate Function Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17. GPIO Port Registers and Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 18. Port A–D GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . . 40
Table 19. Port Control Subregister Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 20. Port A–D Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 21. Port A–D Data Direction Subregisters (PxDD) . . . . . . . . . . . . . . . . . . . . . . 41
Table 22. Port A–D Alternate Function Subregisters (PxAF) . . . . . . . . . . . . . . . . . . . 42
Table 23. Port A–D Output Control Subregisters (PxOC) . . . . . . . . . . . . . . . . . . . . . 43
Table 24. Port A–D High Drive Enable Subregisters (PxHDE) . . . . . . . . . . . . . . . . . 44
Table 25. Port A–D Stop Mode Recovery Source Enable Subregisters (PxSMRE) . . 45
Table 26. Port A–D Pull-Up Enable Subregisters (PxPUE) . . . . . . . . . . . . . . . . . . . . 46
Table 27. Port A–D Alternate Function Set 1 Subregisters (PxAFS1) . . . . . . . . . . . . 47
Table 28. Port A–D Alternate Function Set 2 Subregisters (PxAFS2) . . . . . . . . . . . . 48
PS025113-1212
List of Tables
Z8 Encore!® F0830 Series
Product Specification
xiii
Table 29. Port A–C Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 30. Port A–D Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 31. LED Drive Enable (LEDEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 32. LED Drive Level High Register (LEDLVLH) . . . . . . . . . . . . . . . . . . . . . . 51
Table 33. LED Drive Level Low Register (LEDLVLL) . . . . . . . . . . . . . . . . . . . . . . . 52
Table 34. Trap and Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . . . . . 54
Table 35. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 36. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 37. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 38. IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 39. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 40. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . . 61
Table 41. IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 42. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . . 62
Table 43. IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 44. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 45. IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 46. IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . . . . 64
Table 47. Interrupt Edge Select Register (IRQES) . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 48. Shared Interrupt Select Register (IRQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 49. Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 50. Timer 0–1 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 51. Timer 0–1 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 52. Timer 0–1 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . . . . . 85
Table 53. Timer 0–1 Reload Low Byte Register (TxRL) . . . . . . . . . . . . . . . . . . . . . . 85
Table 54. Timer 0–1 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . . . . 86
Table 55. Timer 0–1 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . . . . 86
Table 56. Timer 0–1 Control Register 0 (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 57. Timer 0–1 Control Register 1 (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 58. Watchdog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . . . . . . 92
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List of Tables
Z8 Encore!® F0830 Series
Product Specification
xiv
Table 59. Watchdog Timer Control Register (WDTCTL) . . . . . . . . . . . . . . . . . . . . . 95
Table 60. Watchdog Timer Reload Upper Byte Register (WDTU) . . . . . . . . . . . . . . 96
Table 61. Watchdog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . . . . . 96
Table 62. Watchdog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . . . 97
Table 63. ADC Control Register 0 (ADCCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 64. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 65. ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 66. Sample Settling Time (ADCSST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 67. Sample Time (ADCST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 68. Comparator Control Register (CMP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 69. Z8 Encore! F0830 Series Flash Memory Configuration . . . . . . . . . . . . . . 108
Table 70. Z8F083 Flash Memory Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 71. Flash Code Protection using the Flash Option Bits . . . . . . . . . . . . . . . . . . 115
Table 72. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 73. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 74. Flash Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 75. Flash Sector Protect Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 76. Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . . . . . 123
Table 77. Flash Frequency Low Byte Register (FFREQL) . . . . . . . . . . . . . . . . . . . . 123
Table 78. Trim Bit Address Register (TRMADR) . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 79. Trim Bit Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 80. Trim Bit Data Register (TRMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 81. Flash Option Bits at Program Memory Address 0000H . . . . . . . . . . . . . . 127
Table 82. Flash Options Bits at Program Memory Address 0001H . . . . . . . . . . . . . 128
Table 83. Trim Option Bits at 0000H (ADCREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 84. Trim Option Bits at 0001H (TADC_COMP) . . . . . . . . . . . . . . . . . . . . . . 130
Table 85. Trim Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 86. Trim Option Bits at 0002H (TIPO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 87. Trim Option Bits at 0003H (TVBO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 88. VBO Trim Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
PS025113-1212
List of Tables
Z8 Encore!® F0830 Series
Product Specification
xv
Table 89. Trim Option Bits at 0006H (TCLKFLT) . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 90. ClkFlt Delay Control Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 91. Write Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 92. Read Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 93. NVDS Read Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 94. OCD Baud-Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 95. On-Chip Debugger Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 96. OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 97. OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 98. Oscillator Configuration and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 99. Oscillator Control Register (OSCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 100. Recommended Crystal Oscillator Specifications . . . . . . . . . . . . . . . . . . . 158
Table 101. Assembly Language Syntax Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 102. Assembly Language Syntax Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 103. Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 104. Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 105. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 106. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 107. Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 108. CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 109. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 110. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 111. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 112. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 113. eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 114. Op Code Map Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 115. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 116. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 117. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 118. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Tim-
ing 190
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List of Tables
Z8 Encore!® F0830 Series
Product Specification
xvi
Table 119. Flash Memory Electrical Characteristics and Timing . . . . . . . . . . . . . . . . 192
Table 120. Watchdog Timer Electrical Characteristics and Timing . . . . . . . . . . . . . . 192
Table 121. Nonvolatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 122. Analog-to-Digital Converter Electrical Characteristics and Timing . . . . . 193
Table 123. Comparator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 124. GPIO Port Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 125. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 126. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 127. Power Consumption Reference Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 128. Z8 Encore! XP F0830 Series Ordering Matrix . . . . . . . . . . . . . . . . . . . . . 200
Table 129. Package and Pin Count Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 130. Timer 0 High Byte Register (T0H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 131. Timer 0 Low Byte Register (T0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 132. Timer 0 Reload High Byte Register (T0RH) . . . . . . . . . . . . . . . . . . . . . . . 209
Table 133. Timer 0 Reload Low Byte Register (T0RL) . . . . . . . . . . . . . . . . . . . . . . . 209
Table 134. Timer 0 PWM High Byte Register (T0PWMH) . . . . . . . . . . . . . . . . . . . . 209
Table 135. Timer 0 PWM Low Byte Register (T0PWML) . . . . . . . . . . . . . . . . . . . . . 210
Table 136. Timer 0 Control Register 0 (T0CTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 137. Timer 0 Control Register 1 (T0CTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 138. Timer 1 High Byte Register (T1H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 139. Timer 1 Low Byte Register (T1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 140. Timer 1 Reload High Byte Register (T1RH) . . . . . . . . . . . . . . . . . . . . . . . 211
Table 141. Timer 1 Reload Low Byte Register (T1RL) . . . . . . . . . . . . . . . . . . . . . . . 211
Table 142. Timer 1 PWM High Byte Register (T1PWMH) . . . . . . . . . . . . . . . . . . . . 211
Table 143. Timer 1 PWM Low Byte Register (T1PWML) . . . . . . . . . . . . . . . . . . . . . 212
Table 144. Timer 1 Control Register 0 (T1CTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 145. Timer 1 Control Register 1 (T1CTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 146. ADC Control Register 0 (ADCCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 147. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 148. ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . . . . . . . . . . . . . . 214
PS025113-1212
List of Tables
Z8 Encore!® F0830 Series
Product Specification
xvii
Table 149. ADC Sample Settling Time (ADCSST) . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 150. ADC Sample Time (ADCST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 151. Power Control Register 0 (PWRCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 152. LED Drive Enable (LEDEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 153. LED Drive Level High Register (LEDLVLH) . . . . . . . . . . . . . . . . . . . . . 217
Table 154. LED Drive Level Low Register (LEDLVLL) . . . . . . . . . . . . . . . . . . . . . . 217
Table 155. Oscillator Control Register (OSCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 156. Comparator Control Register (CMP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 157. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 158. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . 219
Table 159. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . 219
Table 160. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 161. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . 219
Table 162. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . 220
Table 163. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 164. IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . . . 220
Table 165. IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . . . . . . . . . . . . . 220
Table 166. Interrupt Edge Select Register (IRQES) . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 167. Shared Interrupt Select Register (IRQSS) . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 168. Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 169. Port A GPIO Address Register (PAADDR) . . . . . . . . . . . . . . . . . . . . . . . 222
Table 170. Port A Control Registers (PACTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 171. Port A Input Data Registers (PAIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 172. Port A Output Data Register (PAOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 173. Port B GPIO Address Register (PBADDR) . . . . . . . . . . . . . . . . . . . . . . . 223
Table 174. Port B Control Registers (PBCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 175. Port B Input Data Registers (PBIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 176. Port B Output Data Register (PBOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 177. Port C GPIO Address Register (PCADDR) . . . . . . . . . . . . . . . . . . . . . . . 224
Table 178. Port C Control Registers (PCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
PS025113-1212
List of Tables
Z8 Encore!® F0830 Series
Product Specification
xviii
Table 179. Port C Input Data Registers (PCIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 180. Port C Output Data Register (PCOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 181. Port D GPIO Address Register (PDADDR) . . . . . . . . . . . . . . . . . . . . . . . 225
Table 182. Port D Control Registers (PDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 183. Port D Output Data Register (PDOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 184. Watchdog Timer Control Register (WDTCTL) . . . . . . . . . . . . . . . . . . . . 226
Table 185. Reset Status Register (RSTSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 186. Watchdog Timer Reload Upper Byte Register (WDTU) . . . . . . . . . . . . . 227
Table 187. Watchdog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . . . . 227
Table 188. Watchdog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . . 227
Table 189. Trim Bit Address Register (TRMADR) . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 190. Trim Bit Data Register (TRMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 191. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 192. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 193. Flash Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 194. Flash Sector Protect Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 195. Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . . . . . 229
Table 196. Flash Frequency Low Byte Register (FFREQL) . . . . . . . . . . . . . . . . . . . . 230
PS025113-1212
List of Tables
Z8 Encore!® F0830 Series
Product Specification
1
Overview
Zilog’s Z8 Encore! MCU family of products are the first in a line of Zilog microcontroller
products based on the 8-bit eZ8 CPU. The Z8 Encore! F0830 Series products expand on
Zilog’s extensive line of 8-bit microcontrollers. The Flash in-circuit programming capabil-
ity allows for faster development time and program changes in the field. The new eZ8
CPU is upward-compatible with existing Z8 CPU instructions. The rich peripheral set of
Z8 Encore! F0830 Series makes it suitable for a variety of applications including motor
control, security systems, home appliances, personal electronic devices and sensors.
Features
The key features of Z8 Encore! F0830 Series MCU include:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
20MHz eZ8 CPU
Up to 12KB Flash memory with in-circuit programming capability
Up to 256B register RAM
64B Nonvolatile Data Storage (NVDS)
Up to 25 I/O pins depending upon package
Internal Precision Oscillator (IPO)
External crystal oscillator
Two enhanced 16-bit timers with capture, compare and PWM capability
Watchdog Timer (WDT) with dedicated internal RC oscillator
Single-pin, On-Chip Debugger (OCD)
Optional 8-channel, 10-bit Analog-to-Digital Converter (ADC)
On-chip analog comparator
Up to 17 interrupt sources
Voltage Brown-Out (VBO) protection
Power-On Reset (POR)
2.7V to 3.6V operating voltage
Up to thirteen 5V-tolerant input pins
20- and 28-pin packages
0°C to +70°C standard temperature range and –40°C to +105°C extended temperature
operating ranges
PS025113-1212
Overview
Z8 Encore!® F0830 Series
Product Specification
2
Part Selection Guide
Table 1 lists the basic features available for each device within the Z8 Encore! F0830
Series product line. See the Ordering Information chapter on page 200 for details.
Table 1. Z8 Encore! F0830 Series Family Part Selection Guide
Part
Number
Flash
(KB)
RAM
(B)
NVDS
(64B)
ADC
Yes
No
Z8F1232
Z8F1233
Z8F0830
Z8F0831
Z8F0430
Z8F0431
Z8F0230
Z8F0231
Z8F0130
Z8F0131
12
12
8
256
256
256
256
256
256
256
256
256
256
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
8
4
Yes
No
4
2
Yes
No
2
1
Yes
No
1
PS025113-1212
Part Selection Guide
Z8 Encore!® F0830 Series
Product Specification
3
Block Diagram
Figure 1 displays a block diagram of the Z8 Encore! F0830 Series architecture.
System
Clock
Oscillator
Control
XTAL/RC
Oscillator
Internal
Precision
Oscillator
Low Power
RC Oscillator
On-Chip
Debugger
POR/VBO
eZ8
CPU
& Reset
Interrupt
Controller
WDT
Controller
Memory Bus
Register Bus
NVDS
Controller
Flash
Controller
RAM
Controller
Timers
ADC
Comparator
Flash Memory
RAM
GPIO
Figure 1. Z8 Encore! F0830 Series Block Diagram
PS025113-1212
Block Diagram
Z8 Encore!® F0830 Series
Product Specification
4
CPU and Peripheral Overview
The eZ8 CPU, Zilog’s latest 8-bit CPU, meets the continuing demand for faster and more
code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8
instruction set. The eZ8 CPU features include:
•
Direct register-to-register architecture allows each register to function as an accumula-
tor, improving execution time and decreasing the required program memory
•
Software stack allows much greater depth in subroutine calls and interrupts than hard-
ware stacks
•
•
•
Compatible with existing Z8 CPU code
Expanded internal register file allows access up to 4KB
New instructions improve execution efficiency for code developed using high-level
programming languages, including C
•
•
Pipelined instruction fetch and execution
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT and SRL
•
•
•
•
New instructions support 12-bit linear addressing of the register file
Up to 10 MIPS operation
C Compiler-friendly
2 to 9 clock cycles per instruction
For more information about the eZ8 CPU, refer to the eZ8 CPU Core User Manual
(UM0128), which is available for download on www.zilog.com.
General Purpose Input/Output
The Z8 Encore! F0830 Series features up to 25 port pins (Ports A–D) for general-purpose
input/output (GPIO). The number of GPIO pins available is a function of package. Each
pin is individually programmable.
Flash Controller
The Flash Controller programs and erases the Flash memory. It also supports protection
against accidental programming and erasure.
PS025113-1212
CPU and Peripheral Overview
Z8 Encore!® F0830 Series
Product Specification
5
Nonvolatile Data Storage
The Nonvolatile Data Storage (NVDS) function uses a hybrid hardware/software scheme
to implement a byte-programmable data memory and is capable of storing about 100,000
write cycles.
Internal Precision Oscillator
The Internal Precision Oscillator (IPO) function, with an accuracy of ±4% full voltage/
temperature range, is a trimmable clock source that requires no external components.
External Crystal Oscillator
The crystal oscillator circuit provides highly accurate clock frequencies using an external
crystal, ceramic resonator or RC network.
10-Bit Analog-to-Digital Converter
The optional Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-
bit binary number. The ADC accepts inputs from eight different analog input pins.
Analog Comparator
The analog comparator compares the signal at an input pin with either an internal pro-
grammable reference voltage or with a signal at the second input pin. The comparator out-
put is used either to drive a logic output pin or to generate an interrupt.
Timers
Two enhanced 16-bit reloadable timers can be used for timing/counting events or for
motor control operations. These timers provide a 16-bit programmable reload counter and
operate in ONE-SHOT, CONTINUOUS, GATED, CAPTURE, CAPTURE RESTART,
COMPARE, CAPTURE and COMPARE, PWM SINGLE OUTPUT and PWM DUAL
OUTPUT Modes.
Interrupt Controller
The Z8 Encore! F0830 Series products support seventeen interrupt sources with sixteen
interrupt vectors: up to five internal peripheral interrupts and up to twelve GPIO inter-
rupts. These interrupts have three levels of programmable interrupt priority.
PS025113-1212
CPU and Peripheral Overview
Z8 Encore!® F0830 Series
Product Specification
6
Reset Controller
The Z8 Encore! F0830 Series products are reset using any one of the following: the
RESET pin, Power-On Reset, Watchdog Timer (WDT) time-out, STOP Mode exit or Volt-
age Brown-Out (VBO) warning signal. The RESET pin is bidirectional; i.e., it functions as
a reset source as well as a reset indicator.
On-Chip Debugger
The Z8 Encore! F0830 Series products feature an integrated On-Chip Debugger (OCD).
The OCD provides a rich set of debugging capabilities, such as reading and writing regis-
ters, programming Flash memory, setting breakpoints and executing code. The OCD uses
one single-pin interface for communication with an external host.
Acronyms and Expansions
This document references a number of acronyms; each is expanded in Table 2 for the
reader’s understanding.
Table 2. Acronyms and Expansions
Acronyms
ADC
Expansions
Analog-to-Digital Converter
Nonvolatile Data Storage
Watchdog Timer
NVDS
WDT
GPIO
OCD
POR
VBO
General-Purpose Input/Output
On-Chip Debugger
Power-On Reset
Voltage Brown-Out
IPO
Internal Precision Oscillator
Plastic Dual Inline Package
Small Outline Integrated Circuit
Small Shrink Outline Package
Quad Flat No Lead
PDIP
SOIC
SSOP
QFN
IRQ
Interrupt request
ISR
Interrupt service routine
Most significant byte
MSB
LSB
Least significant byte
Pulse Width Modulation
Successive Approximation Regis-
PWM
SAR
PS025113-1212
Acronyms and Expansions
Z8 Encore!® F0830 Series
Product Specification
7
Pin Description
The Z8 Encore! F0830 Series products are available in a variety of package styles and pin
configurations. This chapter describes the signals and the pin configurations for each of
the package styles. For information about the physical package specifications, see the
Packaging chapter on page 199.
Available Packages
Table 3 lists the package styles that are available for each device in the Z8 Encore! F0830
Series product line.
Table 3. Z8 Encore! F0830 Series Package Options
Part
Number
20-pin
QFN
20-pin
SOIC
20-pin
SSOP
20-pin
PDIP
28-pin
QFN
28-pin
SOIC
28-pin
SSOP
28-pin
PDIP
ADC
Yes
No
Z8F1232
Z8F1233
Z8F0830
Z8F0831
Z8F0430
Z8F0431
Z8F0230
Z8F0231
Z8F0130
Z8F0131
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Yes
No
Yes
No
Yes
No
Yes
No
Pin Configurations
Figures 2 and 3 display the pin configurations of all of the packages available in the Z8
Encore! F0830 Series. See Table 4 on page 11 for a description of the signals. Analog
input alternate functions (ANAx) are not available on the following devices:
•
•
•
•
•
Z8F0831
Z8F0431
Z8F0131
Z8F0231
Z8F1233
PS025113-1212
Pin Description
Z8 Encore!® F0830 Series
Product Specification
8
The analog supply pins (AVDD and AVSS) are also not available on these parts and are
replaced by PB6 and PB7.
At reset, by default, all pins of Port A, B and C are in Input state. The alternate functional-
ity is also disabled, so the pins function as general purpose input ports until programmed
otherwise. At power-up, the Port D0 pin defaults to the RESET Alternate function.
The pin configurations listed are preliminary and subject to change based on manufactur-
ing limitations.
PB1/ANA1
PB2/ANA2
PB0/ANA0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PC3/COUT/LED
PC2/ANA6/LED
PC1/ANA5/CINN/LED
PC0/ANA4/CINP/LED
PB3/CLKIN/ANA3
V
DD
PA0/T0IN/T0OUT/X
IN
DBG
PA1/T0OUT/XOUT
RESET/PD0
PA7/T1OUT
PA6/T1IN/T1OUT
PA5
V
SS
PA2
PA3
PA4
Figure 2. Z8F0830 Series in 20-Pin SOIC, SSOP, PDIP Package
PB2/ANA2
PB1/ANA1
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PB0/ANA0
2
PB4/ANA7
PB5/VREF
3
PC3/COUT/LED
PC2/ANA6/LED
PC1/ANA5/CINN/LED
PB3/CLKIN/ANA3
(PB6) AVDD
4
5
6
PC0/ANA4/CINP/LED
DBG
VDD
PA0/T0IN/T0OUT/XIN
7
8
RESET/PD0
PC7/LED
PA1/T0OUT/XOUT
9
VSS
(PB7) AVSS
PA2
10
11
12
13
14
PC6/LED
PA7/T1OUT
PC5/LED
PA3
PA4
PC4/LED
PA5
PA6/T1IN/T1OUT
Figure 3. Z8F0830 Series in 28-Pin SOIC, SSOP, PDIP Package
PS025113-1212
Pin Configurations
Z8 Encore!® F0830 Series
Product Specification
9
PC3/COUT/LED
PB0/ANA0
16
17
18
19
20
PA7/T1OUT
PA6/T1IN/T1OUT
10
9
PB1/ANA1
PA5
8
20-Pin QFN
PB2/ANA2
PA4
7
PB3/CLKIN/ANA3
PA3
6
Figure 4. Z8F0830 Series in 20-Pin QFN Package
PS025113-1212
Pin Configurations
Z8 Encore!® F0830 Series
Product Specification
10
21 20 19 18 17 16 15
14
22
23
24
25
26
27
PC3/COUT/LED
PB0/ANA0
PA7/T1OUT
PC5/LED
PC4/LED
PA6/T1IN/T1OUT
PA5
13
12
11
10
9
PB1/ANA1
PB2/ANA2
PB4/ANA7
28-Pin QFN
PB5/V
PA4
REF
PB3/CLKIN/ANA3
PA3
1
2
3
4
5
6
7
Figure 5. Z8F0830 Series in 28-Pin QFN Package
PS025113-1212
Pin Configurations
Z8 Encore!® F0830 Series
Product Specification
11
Signal Descriptions
Table 4 describes the Z8 Encore! F0830 Series signals. See the Pin Configurations section
on page 7 to determine the signals available for each specific package style.
Table 4. Signal Descriptions
Signal
Mnemonic
I/O
Description
General-Purpose I/O Ports A–D
PA[7:0]
PB[7:0]
I/O
I/O
Port A. These pins are used for general purpose I/O.
Port B. These pins are used for general purpose I/O. PB6 and PB7 are
available only in those devices without an ADC.
PC[7:0]
PD[0]
I/O
I/O
Port C. These pins are used for general purpose I/O.
Port D. This pin is used for general purpose output only.
Note: PB6 and PB7 are only available in 28-pin packages without ADC. In 28-pin packages with ADC, they are re-
placed by AVDD and AVSS
.
Timers
T0OUT/T1OUT
T0OUT/T1OUT
O
O
Timer output 0–1. These signals are the output from the timers.
Timer complement output 0–1. These signals are output from the timers in
PWM DUAL OUTPUT Mode.
T0IN/T1IN
I
Timer Input 0–1. These signals are used as the capture, gating and counter
inputs. The T0IN signal is multiplexed T0OUT signals.
Comparator
CINP/CINN
I
Comparator inputs. These signals are the positive and negative inputs to
the comparator.
COUT
O
Comparator output. This is the output of the comparator.
Analog
ANA[7:0]
I
Analog port. These signals are used as inputs to the analog-to-digital con-
verter (ADC).
V
I/O
Analog-to-digital converter reference voltage input.
REF
Note: When configuring ADC using external V
, PB5 is used as V
in
REF
REF
28-pin package.
Note: The AVDD and AVSS signals are available only in the 28-pin packages with ADC. They are replaced by PB6
and PB7 on 28-pin packages without ADC.
PS025113-1212
Signal Descriptions
Z8 Encore!® F0830 Series
Product Specification
12
Table 4. Signal Descriptions (Continued)
Description
Signal
Mnemonic
I/O
Oscillators
X
I
External crystal input. This is the input pin to the crystal oscillator. A crystal
can be connected between it and the XOUT pin to form the oscillator. In
addition, this pin is used with external RC networks or external clock drivers
to provide the system clock.
IN
X
O
I
External crystal output. This pin is the output of the crystal oscillator. A crys-
tal can be connected between it and the XIN pin to form the oscillator.
OUT
Clock Input
CLK
Clock input signal. This pin may be used to input a TTL-level signal to be
used as the system clock.
IN
LED Drivers
LED
O
Direct LED drive capability. All Port C pins have the capability to drive an
LED without any other external components. These pins have programma-
ble drive strengths set by the GPIO block.
On-Chip Debugger
DBG
I/O
I/O
Debug. This signal is the control and data input and output to and from the
On-Chip Debugger.
Caution: The DBG pin is open-drain and requires an external pull-up resis-
tor to ensure proper operation.
Reset
RESET
RESET. Generates a reset when asserted (driven Low). Also serves as a
reset indicator; the Z8 Encore! forces this pin low when in reset. This pin is
open-drain and features an enabled internal pull-up resistor.
Power Supply
V
I
I
I
I
Digital power supply.
Analog power supply.
Digital ground.
DD
AV
DD
V
SS
AV
Analog ground.
SS
Note: The AVDD and AVSS signals are available only in the 28-pin packages with ADC. They are replaced by PB6
and PB7 on 28-pin packages without ADC.
PS025113-1212
Signal Descriptions
Z8 Encore!® F0830 Series
Product Specification
13
Pin Characteristics
Table 5 provides detailed characteristics of each pin available on the Z8 Encore! F0830
Series 20- and 28-pin devices. Data in Table 5 are sorted alphabetically by the pin symbol
mnemonic.
Table 5. Pin Characteristics (20- and 28-pin Devices)
Active
Low or
Internal
Schmitt-
Symbol
Mnemonic Direction Direction
Reset
Active Tristate Pull-Up or Trigger Open Drain
5V
Tolerance
High
N/A
N/A
N/A
N/A
Output Pull-Down
Input
N/A
N/A
Yes
Yes
Output
N/A
AV
AV
N/A
N/A
I/O
N/A
N/A
N/A
Yes
Yes
N/A
N/A
No
N/A
NA
DD
SS
N/A
N/A
DBG
I
I
Yes
Yes
PA[7:0]
I/O
Programma-
ble pull-up
Yes,
Programma-
ble
PA[7:2]
only
PB[7:0]
I/O
I/O
I/O
I
I
N/A
N/A
Yes
Yes
Yes
Programma-
ble pull-up
Yes
Yes
Yes
Yes,
Programma-
ble
PB[7:6]
only
PC[7:0]
Programma-
ble pull-up
Yes,
Programma-
ble
PC[7:3]
only
RESET/PD0
I/O
Low (in
Programma-
Programma-
ble for PD0;
always on
Yes
(defaults RESET
(PD0 ble for PD0;
only)
to
mode)
always on
for RESET
RESET)
for RESET
V
V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
DD
SS
PB6 and PB7 are available only in devices without an ADC function.
Note:
PS025113-1212
Pin Characteristics
Z8 Encore!® F0830 Series
Product Specification
14
Address Space
The eZ8 CPU can access the following three distinct address spaces:
•
•
•
The register file addresses access for the general purpose registers and the eZ8 CPU,
peripheral and general purpose I/O port control registers
The program memory addresses access for all of the memory locations having execut-
able code and/or data
The data memory addresses access for all of the memory locations containing only the
data
The following sections describe these three address spaces. For more information about
the eZ8 CPU and its address space, refer to the eZ8 CPU Core User Manual (UM0128),
which is available for download at www.zilog.com.
Register File
The register file address space in the Z8 Encore! MCU is 4KB (4096 bytes). The register
file consists of two sections: control registers and general-purpose registers. When instruc-
tions are executed, registers defined as source are read and registers defined as destina-
tions are written. The architecture of the eZ8 CPU allows all general purpose registers to
function as accumulators, address pointers, index registers, stack areas or scratch pad
memory.
The upper 256 bytes of the 4KB register file address space are reserved for controlling the
eZ8 CPU, on-chip peripherals and the I/O ports. These registers are located at addresses
from F00Hto FFFH. Some of the addresses within the 256B Control Register section are
reserved (unavailable). Reading from a reserved register file address returns an undefined
value. Writing to reserved register file addresses is not recommended and can produce
unpredictable results.
The on-chip RAM always begins at address 000Hin the register file address space. The Z8
Encore! F0830 Series devices contain up to 256B of on-chip RAM. Reading from register
file addresses outside the available RAM addresses (and not within the Control Register
address space), returns an undefined value. Writing to these register file addresses has no
effect.
PS025113-1212
Address Space
Z8 Encore!® F0830 Series
Product Specification
15
Program Memory
The eZ8 CPU supports 64KB of program memory address space. The Z8 Encore! F0830
Series devices contain 1KB to 12KB of on-chip Flash memory in the program memory
address space, depending on the device. Reading from program memory addresses outside
the available Flash memory address range returns FFH. Writing to these unimplemented
program memory addresses produces no effect. Table 6 shows a program memory map for
the Z8 Encore! F0830 Series products.
Table 6. Z8 Encore! F0830 Series Program Memory Maps
Program Memory Address (Hex) Function
Z8F0830 and Z8F0831 Products
0000–0001
0002–0003
0004–003D
003E–1FFF
Flash Option Bits
Reset Vector
Interrupt Vectors*
Program Memory
Z8F0430 and Z8F0431 Products
0000–0001
Flash Option Bits
Reset Vector
0002–0003
0004–003D
Interrupt Vectors*
Program Memory
003E–0FFF
Z8F0130 and Z8F0131 Products
0000–0001
Flash Option Bits
Reset Vector
0002–0003
0004–003D
Interrupt Vectors*
Program Memory
003E–03FF
Z8F0230 and Z8F0231 Products
0000–0001
Flash Option Bits
Reset Vector
0002–0003
0004–003D
Interrupt Vectors*
Program Memory
003E–07FF
Note: *See Table 34 on page 54 for a list of interrupt vectors.
PS025113-1212
Program Memory
Z8 Encore!® F0830 Series
Product Specification
16
Data Memory
The Z8 Encore! F0830 Series does not use the eZ8 CPU’s 64KB data memory address
space.
Flash Information Area
Table 7 maps the Z8 Encore! F0830 Series Flash information area. The 128-byte informa-
tion area is accessed, by setting bit 7 of the Flash Page Select Register to 1. When access is
enabled, the Flash information area is mapped into program memory and overlays these
128 bytes at addresses FE00Hto FE7FH. When information area access is enabled, all
reads from these program memory addresses return information area data rather than pro-
gram memory data. Access to the Flash information area is read-only.
Table 7. Z8 Encore! F0830 Series Flash Memory Information Area Map
Program
Memory
Address (Hex)
FE00–FE3F
FE40–FE53
Function
Zilog option bits
Part Number
20-character ASCII alphanumeric code
Left-justified and filled with FH
FE54–FE5F
FE60–FE7F
FE80–FFFF
Reserved
Reserved
Reserved
PS025113-1212
Data Memory
Z8 Encore!® F0830 Series
Product Specification
17
Register Map
Table 8 provides an address map of the Z8 Encore! F0830 Series register file. Not all
devices and package styles in the Z8 Encore! F0830 Series support the ADC or all of the
GPIO ports. Consider registers for unimplemented peripherals as reserved.
Table 8. Register File Address Map
Address (Hex)
Register Description
Mnemonic
Reset (Hex)
Page No.
General Purpose RAM
000–0FF
100–EFF
General purpose register file RAM
—
—
XX
XX
Reserved
Timer 0
F00
Timer 0 high byte
T0H
T0L
00
01
FF
FF
00
00
00
00
83
83
85
85
86
86
87
88
F01
Timer 0 low byte
F02
Timer 0 reload high byte
Timer 0 reload low byte
Timer 0 PWM high byte
Timer 0 PWM low byte
Timer 0 control 0
T0RH
F03
T0RL
F04
T0PWMH
T0PWML
T0CTL0
T0CTL1
F05
F06
F07
Timer 0 control 1
Timer 1
F08
Timer 1 high byte
Timer 1 low byte
T1H
T1L
00
01
FF
FF
00
00
00
00
XX
83
83
85
85
86
86
87
83
F09
F0A
Timer 1 reload high byte
Timer 1 reload low byte
Timer 1 PWM high byte
Timer 1 PWM low byte
Timer 1 control 0
T1RH
F0B
T1RL
F0C
T1PWMH
T1PWML
T1CTL0
T1CTL1
—
F0D
F0E
F0F
Timer 1 control 1
F10–F6F
Reserved
Analog-to-Digital Converter (ADC)
F70
F71
F72
ADC control 0
Reserved
ADCCTL0
—
00
XX
XX
102
103
ADC data high byte
ADCD_H
Note: XX = Undefined.
PS025113-1212
Register Map
Z8 Encore!® F0830 Series
Product Specification
18
Table 8. Register File Address Map (Continued)
Address (Hex)
Register Description
Mnemonic
Reset (Hex)
Page No.
Analog-to-Digital Converter (ADC, cont’d)
F73
ADC data low bits
ADC sample settling time
ADC sample time
Reserved
ADCD_L
ADCSST
ADCST
—
XX
0F
3F
XX
XX
103
104
105
F74
F75
F76
F77–F7F
Reserved
—
Low Power Control
F80
F81
Power control 0
PWRCTL0
—
88
32
Reserved
XX
LED Controller
F82
F83
F84
F85
LED drive enable
LED drive level high
LED drive level low
Reserved
LEDEN
LEDLVLH
LEDLVLL
—
00
00
00
XX
51
51
52
Oscillator Control
F86
Oscillator control
Reserved
OSCCTL
—
A0
XX
154
107
F87–F8F
Comparator 0
F90
Comparator 0 control
Reserved
CMP0
—
14
F91–FBF
XX
Interrupt Controller
FC0
Interrupt request 0
IRQ0
IRQ0ENH
IRQ0ENL
IRQ1
00
00
00
00
00
00
00
00
00
XX
00
58
61
61
59
62
63
60
64
64
FC1
IRQ0 enable high bit
IRQ0 enable low Bit
Interrupt request 1
IRQ1 enable high bit
IRQ1 enable low bit
Interrupt request 2
IRQ2 enable high bit
IRQ2 enable low bit
Reserved
FC2
FC3
FC4
IRQ1ENH
IRQ1ENL
IRQ2
FC5
FC6
FC7
IRQ2ENH
IRQ2ENL
—
FC8
FC9–FCC
FCD
Interrupt edge select
IRQES
66
Note: XX = Undefined.
PS025113-1212
Register Map
Z8 Encore!® F0830 Series
Product Specification
19
Table 8. Register File Address Map (Continued)
Address (Hex)
Register Description
Mnemonic
Reset (Hex)
Page No.
Interrupt Controller (cont’d)
FCE
FCF
Shared interrupt select
IRQSS
00
00
66
67
Interrupt control
IRQCTL
GPIO Port A
FD0
Port A address
Port A control
PAADDR
PACTL
PAIN
00
00
XX
00
39
41
41
41
FD1
FD2
Port A input data
Port A output data
FD3
PAOUT
GPIO Port B
FD4
Port B address
Port B control
PBADDR
PBCTL
PBIN
00
00
XX
00
39
41
41
41
FD5
FD6
Port B input data
Port B output data
FD7
PBOUT
GPIO Port C
FD8
Port C address
Port C control
PCADDR
PCCTL
PCIN
00
00
XX
00
39
41
41
41
FD9
FDA
Port C input data
Port C output data
FDB
PCOUT
GPIO Port D
FDC
Port D address
Port D control
Reserved
PDADDR
PDCTL
—
00
00
XX
00
XX
39
41
FDD
FDE
FDF
Port D output data
Reserved
PDOUT
—
41
FE0–FEF
Watchdog Timer (WDT)
FF0
Reset status
RSTSTAT
WDTCTL
WDTU
WDTH
WDTL
—
XX
XX
FF
FF
FF
XX
95
95
96
96
97
Watchdog Timer control
FF1
Watchdog Timer reload upper byte
Watchdog Timer reload high byte
Watchdog Timer reload low byte
Reserved
FF2
FF3
FF4–FF5
Note: XX = Undefined.
PS025113-1212
Register Map
Z8 Encore!® F0830 Series
Product Specification
20
Table 8. Register File Address Map (Continued)
Address (Hex)
Register Description
Mnemonic
Reset (Hex)
Page No.
Trim Bit Control
FF6
FF7
Trim bit address
Trim data
TRMADR
TRMDR
00
126
127
XX
Flash Memory Controller
FF8
FF8
FF9
Flash control
FCTL
FSTAT
FPS
00
00
00
00
00
00
119
120
121
122
123
123
Flash status
Flash page select
Flash sector protect
FPROT
FFREQH
FFREQL
FFA
FFB
Flash programming frequency high byte
Flash programming frequency low byte
eZ8 CPU
FFC
Flags
—
XX
XX
XX
XX
Refer to the
eZ8 CPU
Core User
Manual
FFD
Register pointer
Stack pointer high byte
Stack pointer low byte
RP
FFE
SPH
SPL
FFF
(UM0128)
Note: XX = Undefined.
PS025113-1212
Register Map
Z8 Encore!® F0830 Series
Product Specification
21
Reset and Stop Mode Recovery
The reset controller in the Z8 Encore! F0830 Series controls RESET and Stop Mode
Recovery operations. In a typical operation, the following events can cause a reset:
•
•
•
Power-On Reset (POR)
Voltage Brown-Out (VBO)
Watchdog Timer time-out (when configured by the WDT_RES Flash option bit to
initiate a reset)
•
•
External RESET pin assertion (when the alternate RESET function is enabled by the
GPIO register)
On-Chip Debugger initiated reset (OCDCTL[0] set to 1)
When the device is in STOP Mode, a Stop Mode Recovery event is initiated by either of
the following occurrences:
•
•
A Watchdog Timer time-out
A GPIO port input pin transition on an enabled Stop Mode Recovery source
The VBO circuitry on the device generates a VBO reset when the supply voltage drops
below a minimum safe level.
Reset Types
The Z8 Encore! F0830 Series provides different types of Reset operations. Stop Mode
Recovery is considered a form of reset. Table 9 lists the types of resets and their operating
characteristics. The duration of a system reset is longer if the external crystal oscillator is
enabled by the Flash option bits; the result is additional time for oscillator startup.
PS025113-1212
Reset and Stop Mode Recovery
Z8 Encore!® F0830 Series
Product Specification
22
Table 9. Reset and Stop Mode Recovery Characteristics and Latency
Reset Characteristics and Latency
Reset Type
Control Registers
eZ8 CPU
Reset Latency (Delay)
System Reset
Reset (as applicable) Reset
About 66 Internal Precision Oscillator
Cycles
System Reset with Crystal Reset (as applicable) Reset
Oscillator Enabled
About 5000 Internal Precision Oscillator
Cycles
Stop Mode Recovery
Unaffected, except
WDT_CTL and
Reset
About 66 Internal Precision Oscillator
cycles
OSC_CTL registers
Stop Mode Recovery with Unaffected, except
crystal oscillator enabled WDT_CTL and
OSC_CTL registers
Reset
About 5000 Internal Precision Oscillator
cycles
During a system RESET or Stop Mode Recovery, the Z8 Encore! F0830 Series device is
held in reset for about 66 cycles of the Internal Precision Oscillator. If the crystal oscillator
is enabled in the Flash option bits, the reset period is increased to about 5000 IPO cycles.
When a reset occurs because of a low voltage condition or Power-On Reset, the reset delay
is measured from the time that the supply voltage first exceeds the POR level (discussed
later in this chapter). If the external pin reset remains asserted at the end of the reset
period, the device remains in reset until the pin is deasserted.
At the beginning of reset, all GPIO pins are configured as inputs with pull-up resistor dis-
abled, except PD0 which is shared with the reset pin. On reset, the Port D0 pin is config-
ured as a bidirectional open-drain reset. This pin is internally driven low during port reset,
after which the user code may reconfigure this pin as a general purpose output.
During reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer Oscillator continues to run.
On reset, control registers within the register file that have a defined reset value are loaded
with their reset values. Other control registers (including the Stack Pointer, Register
Pointer and Flags) and general purpose RAM are undefined following the reset. The eZ8
CPU fetches the reset vector at program memory addresses 0002Hand 0003Hand loads
that value into the program counter. Program execution begins at the reset vector address.
Because the control registers are reinitialized by a system reset, the system clock after
reset is always the IPO. User software must reconfigure the oscillator control block, to
enable and select the correct system clock source.
PS025113-1212
Reset Types
Z8 Encore!® F0830 Series
Product Specification
23
Reset Sources
Table 10 lists the possible sources of a system reset.
Table 10. Reset Sources and Resulting Reset Type
Operating Mode
Reset Source
Special Conditions
NORMAL or HALT Power-On Reset/Voltage Brown-Out Reset delay begins after supply voltage
modes
exceeds POR level.
Watchdog Timer time-out when con- None.
figured for reset
RESET pin assertion
All reset pulses less than four system clocks
in width are ignored.
On-Chip Debugger initiated reset
(OCDCTL[0] set to 1)
System, except the On-Chip Debugger is
unaffected by the reset.
STOP Mode
Power-On Reset/Voltage Brown-Out Reset delay begins after supply voltage
exceeds POR level.
RESET pin assertion
DBG pin driven Low
All reset pulses less than 12 ns are ignored.
None.
Power-On Reset
Each device in the Z8 Encore! F0830 Series contains an internal Power-On Reset circuit.
The POR circuit monitors the digital supply voltage and holds the device in the Reset state
until the digital supply voltage reaches a safe operating level. After the supply voltage
exceeds the POR voltage threshold (VPOR), the device is held in the Reset state until the
POR counter has timed out. If the crystal oscillator is enabled by the option bits, the time-
out is longer.
After the Z8 Encore! F0830 Series device exits the Power-On Reset state, the eZ8 CPU
fetches the reset vector. Following the Power-On Reset, the POR status bit in the Reset
Status (RSTSTAT) Register is set to 1.
Figure 6 displays the Power-On Reset operation. See the Electrical Characteristics chapter
on page 184 for the POR threshold voltage (VPOR).
PS025113-1212
Reset Sources
Z8 Encore!® F0830 Series
Product Specification
24
VDD = 3.3V
VPOR
VVBO
Program
Execution
VDD = 0.0V
Internal Precision
Oscillator
Crystal
Oscillator
Oscillator
Start-up
Internal RESET
signal
POR
counter delay
optional XTAL
counter delay
Note: Not to Scale
Figure 6. Power-On Reset Operation
Voltage Brown-Out Reset
The devices in the Z8 Encore! F0830 Series provide low Voltage Brown-Out (VBO) pro-
tection. The VBO circuit forces the device to the Reset state, when the supply voltage
drops below the VBO threshold voltage (unsafe level). While the supply voltage remains
below the Power-On Reset threshold voltage (VPOR), the VBO circuit holds the device in
reset.
After the supply voltage exceeds the Power-On Reset threshold voltage, the device pro-
gresses through a full system reset sequence, as described in the POR section. Following
Power-On Reset, the POR status bit in the Reset Status (RSTSTAT) Register is set to 1.
Figure 7 displays the Voltage Brown-Out operation. See the Electrical Characteristics
chapter on page 184 for the VBO and POR threshold voltages (VVBO and VPOR).
The POR level is greater than the VBO level by the specified hysteresis value. This
ensures that the device undergoes a POR after recovering from a VBO condition.
PS025113-1212
Reset Sources
Z8 Encore!® F0830 Series
Product Specification
25
The Voltage Brown-Out circuit can be either enabled or disabled during STOP Mode.
Operations during STOP Mode is set by the VBO_AO Flash option bit. See the Flash
Option Bits chapter on page 124 for information about configuring VBO_AO.
V
= 3.3V
V
= 3.3V
VPOR
VVBO
DD
DD
Program
Voltage
Program
Execution
Brown-Out
Execution
WDT Clock
System Clock
Internal RESET
signal
POR
Note: Not to Scale
counter delay
Figure 7. Voltage Brown-Out Reset Operation
Watchdog Timer Reset
If the device is operating in NORMAL or STOP Mode, the Watchdog Timer can initiate a
system reset at time-out if the WDT_RES Flash option bit is programmed to 1; this state is
the unprogrammed state of the WDT_RES Flash option bit. If the bit is programmed to 0,
it configures the Watchdog Timer to cause an interrupt – not a system reset – at time-out.
The WDT status bit in the Reset Status (RSTSTAT) Register is set to 1 to signify that the
reset was initiated by the Watchdog Timer.
External Reset Input
The RESET pin has a Schmitt-triggered input and an internal pull-up resistor. After the
RESET pin is asserted for a minimum of four system clock cycles, the device progresses
through the system reset sequence. Because of the possible asynchronicity of the system
PS025113-1212
Reset Sources
Z8 Encore!® F0830 Series
Product Specification
26
clock and reset signals, the required reset duration may be three or four clock periods. A
reset pulse of three clock cycles in duration might trigger a reset and a reset pulse of four
cycles in duration always triggers a reset.
While the RESET input pin is asserted low, the Z8 Encore! F0830 Series devices remain
in the Reset state. If the RESET pin is held low beyond the system reset time-out, the
device exits the Reset state on the system clock rising edge following RESET pin deasser-
tion. Following a system reset initiated by the external RESET pin, the EXT status bit in
the Reset Status (RSTSTAT) Register is set to 1.
External Reset Indicator
During system reset or when enabled by the GPIO logic, the RESET pin functions as an
open-drain (active low) RESET mode indicator in addition to the input functionality. This
reset output feature allows an Z8 Encore! F0830 Series device to reset other components
to which it is connected, even if that reset is caused by internal sources such as POR, VBO
or WDT events. See the Port A–D Control Registers section on page 41.
After an internal Reset event occurs, the internal circuitry begins driving the RESET pin
low. The RESET pin is held low by the internal circuitry until the appropriate delay listed
in Table 9 (see page 22) has elapsed.
On-Chip Debugger Initiated Reset
A Power-On Reset can be initiated using the On-Chip Debugger by setting the RSTbit in
the OCD Control Register. The OCD block is not reset, but the remainder of the chip goes
through a normal system reset. The RSTbit automatically clears during the system reset.
Following the system reset, the POR bit in the Reset Status (RSTSTAT) Register is set.
Stop Mode Recovery
The device enters the STOP Mode when the STOP instruction is executed by the eZ8
CPU. See the Low-Power Modes chapter on page 30 for detailed STOP Mode informa-
tion. During Stop Mode Recovery, the CPU is held in reset for about 66 IPO cycles if the
crystal oscillator is disabled or about 5000 cycles if it is enabled.
Stop Mode Recovery does not affect the on-chip registers other than the Reset Status
(RSTSTAT) Register and the Oscillator Control Register (OSCCTL). After any Stop
Mode Recovery, the IPO is enabled and selected as the system clock. If another system
clock source is required or IPO disabling is required, the Stop Mode Recovery code must
reconfigure the oscillator control block such that the correct system clock source is
enabled and selected.
PS025113-1212
Stop Mode Recovery
Z8 Encore!® F0830 Series
Product Specification
27
The eZ8 CPU fetches the reset vector at program memory addresses 0002Hand 0003H
and loads that value into the program counter. Program execution begins at the reset vector
address. Following Stop Mode Recovery, the STOP bit in the Reset Status (RSTSTAT)
Register is set to 1. Table 11 lists the Stop Mode Recovery sources and resulting actions.
The following sections provide more details about each of the Stop Mode Recovery
sources.
Table 11. Stop Mode Recovery Sources and Resulting Action
Operating
Mode
Stop Mode Recovery Source
Action
STOP Mode
Watchdog Timer time-out when configured
for Reset
Stop Mode Recovery
Watchdog Timer time-out when configured
for interrupt
Stop Mode Recovery followed by interrupt
(if interrupts are enabled)
Data transition on any GPIO port pin enabled Stop Mode Recovery
as a Stop Mode Recovery source
Assertion of external RESET Pin
Debug pin driven Low
System reset
System reset
Stop Mode Recovery using WDT Time-Out
If the Watchdog Timer times out during STOP Mode, the device undergoes a Stop Mode
Recovery sequence. In the Reset Status (RSTSTAT) Register, the WDT and STOP bits are
set to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and
the Z8 Encore! F0830 Series device is configured to respond to interrupts, the eZ8 CPU
services the WDT interrupt request following the normal Stop Mode Recovery sequence.
Stop Mode Recovery using GPIO Port Pin Transition
Each of the GPIO port pins may be configured as a Stop Mode Recovery input source. If
any GPIO pin is enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery. In the Reset Sta-
tus (RSTSTAT) Register, the STOP bit is set to 1.
In STOP Mode, the GPIO Port Input Data registers (PxIN) are disabled. These Port Input
Data registers record the port transition only if the signal stays on the port pin through the
end of the Stop Mode Recovery delay. As a result, short pulses on the port pin can initiate
Stop Mode Recovery without being written to the Port Input Data Register or without ini-
tiating an interrupt (if enabled for that pin).
Caution:
PS025113-1212
Stop Mode Recovery
Z8 Encore!® F0830 Series
Product Specification
28
Stop Mode Recovery Using the External RESET Pin
When the Z8 Encore! F0830 Series device is in STOP Mode and the external RESET pin
is driven low, a system reset occurs. Because of a glitch filter operating on the RESET pin,
the low pulse must be greater than the minimum width specified about 12 ns or it is
ignored. The EXT bit in the Reset Status (RSTSTAT) Register is set.
Debug Pin Driven Low
Debug reset is initiated when the On-Chip Debugger detects any of the following error
conditions on the DBG pin:
•
•
•
Serial break (a minimum of nine continuous bits Low)
Framing error (received STOP bit is Low)
Transmit collision (simultaneous OCD and host transmission detected by the OCD)
When the Z8F0830 Series device is operating in STOP Mode, the debug reset will cause a
system reset. The On-Chip Debugger block is not reset, but the remainder of the chip’s
operations go through a normal system reset. The POR bit in the Reset Status (RSTSTAT)
Register is set to 1.
Reset Register Definitions
The following sections define the Reset registers.
Reset Status Register
The Reset Status (RSTSTAT) Register, shown in Table 12, is a read-only register that indi-
cates the source of the most recent Reset event, Stop Mode Recovery event or Watchdog
Timer time-out event. Reading this register resets the upper four bits to 0.
This register shares its address with the Watchdog Timer Control Register, which is write-
only.
PS025113-1212
Debug Pin Driven Low
Z8 Encore!® F0830 Series
Product Specification
29
Table 12. Reset Status Register (RSTSTAT)
Bit
7
6
STOP
5
4
EXT
0
3
2
1
0
Field
POR
WDT
Reserved
RESET
R/W
See Table 13
R
0
0
0
0
R
R
R
R
R
R
R
Address
FF0H
Bit
Description
Power-On Reset Indicator
[7]
POR
This bit is set to 1 if a Power-On Reset event occurs and is reset to 0, if a WDT time-out or Stop
Mode Recovery occurs. Reading this register also reset this bit to 0.
[6]
STOP
Stop Mode Recovery Indicator
This bit is set to 1 if a Stop Mode Recovery occurs. If the STOP and WDT bits are both set to 1,
the Stop Mode Recovery occurs because of a WDT time-out. If the STOP bit is 1 and the WDT
bit is 0, the Stop Mode Recovery is not caused by a WDT time-out. This bit is reset by a Power-
On Reset or a WDT time-out that occurred while not in STOP Mode. Reading this register also
resets this bit.
[5]
WDT
Watchdog Timer Time-Out Indicator
This bit is set to 1 if a WDT time-out occurs. A Power-On Reset resets this pin. A Stop Mode
Recovery from a change in an input pin also resets this bit. Reading this register resets this bit.
This read must occur before clearing the WDT interrupt.
[4]
EXT
External Reset Indicator
If this bit is set to 1, a reset initiated by the external RESET pin occurred. A Power-On Reset or
a Stop Mode Recovery from a change in an input pin resets this bit. Reading this register
resets this bit.
[3:0]
Reserved
These registers are reserved and must be programmed to 0000.
Table 13. POR Indicator Values
Reset or Stop Mode Recovery Event
Power-On Reset
POR
STOP
WDT
EXT
0
1
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
Reset using RESET pin assertion
1
Reset using Watchdog Timer time-out
Reset using the On-Chip Debugger (OCTCTL[1] set to 1)
Reset from STOP Mode using DBG pin driven Low
Stop Mode Recovery using GPIO pin transition
Stop Mode Recovery using WDT time-out
0
0
0
0
0
PS025113-1212
Reset Register Definitions
Z8 Encore!® F0830 Series
Product Specification
30
Low-Power Modes
The Z8 Encore! F0830 Series products contain power saving features. The highest level of
power reduction is provided by the STOP Mode. The next level of power reduction is pro-
vided by the HALT Mode.
Further power savings can be implemented by disabling the individual peripheral blocks
while in NORMAL Mode.
The user must not enable the pull-up register bits for unused GPIO pins, since these ports
are default output to VSS. Unused GPIOs include those missing on 20-pin packages, as
well as those missing on the ADC-enabled 28-pin packages.
STOP Mode
Executing the eZ8 CPU’s STOP instruction places the device into STOP Mode. In STOP
Mode, the operating characteristics are:
•
Primary crystal oscillator and Internal Precision Oscillator are stopped; XIN and
XOUT (if previously enabled) are disabled and PA0/PA1 revert to the states pro-
grammed by the GPIO registers
•
•
•
•
System clock is stopped
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watchdog Timer’s internal RC oscillator continues to operate if enabled by the Oscil-
lator Control Register
•
•
If enabled, the Watchdog Timer logic continues to operate
If enabled for operation in STOP Mode by the associated Flash option bit, the Voltage
Brown-Out protection circuit continues to operate
•
All other on-chip peripherals are idle
To minimize the current in STOP Mode, all GPIO pins that are configured as digital inputs
must be driven to VDD when the pull-up register bit is enabled or to one of power rail
(VDD or GND) when the pull-up register bit is disabled. The device can be brought out of
STOP Mode using Stop Mode Recovery. For more information about Stop Mode Recov-
ery, see the Reset and Stop Mode Recovery chapter on page 21.
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Low-Power Modes
Z8 Encore!® F0830 Series
Product Specification
31
HALT Mode
Executing the eZ8 CPU HALT instruction places the device into HALT Mode. In HALT
Mode, the operating characteristics are:
•
•
•
•
•
•
•
Primary oscillator is enabled and continues to operate
System clock is enabled and continues to operate
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watchdog Timer’s internal RC oscillator continues to operate
If enabled, the Watchdog Timer continues to operate
All other on-chip peripherals continue to operate
The eZ8 CPU can be brought out of HALT Mode by any one of the following operations:
•
•
•
•
•
Interrupt
Watchdog Timer time-out (interrupt or reset)
Power-On Reset
Voltage Brown-Out reset
External RESET pin assertion
To minimize current in HALT Mode, all GPIO pins that are configured as digital inputs
must be driven to VDD when pull-up register bit is enabled or to one of power rail (VDD or
GND) when pull-up register bit is disabled.
Peripheral Level Power Control
In addition to the STOP and HALT modes, it is possible to disable each peripheral on each
of the Z8 Encore! F0830 Series devices. Disabling a given peripheral minimizes its power
consumption.
Power Control Register Definitions
Power Control Register 0
Each bit of the following registers disables a peripheral block, either by gating its system
clock input or by removing power from the block.
PS025113-1212
HALT Mode
Z8 Encore!® F0830 Series
Product Specification
32
This register is only reset during a Power-On Reset sequence. Other system reset events do
not affect it.
Note:
Table 14. Power Control Register 0 (PWRCTL0)
Bit
7
6
Reserved
0
5
4
3
2
1
COMP
0
0
Reserved
0
Field
VBO
0
Reserved Reserved
RESET
R/W
1
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F80H
Bit
Description
Reserved
[7:5]
These registers are reserved and must be programmed to 000.
[4]
VBO
Voltage Brown-Out detector disable
This bit takes only effect when the VBO_AO Flash option bit is disabled. In STOP Mode, VBO
is always disabled when the VBO_AO Flash option bit is disabled. To learn more about the
VBO_AO Flash option bit function, see the Flash Option Bits chapter on page 124.
0 = VBO enabled.
1 = VBO disabled.
[3]
[2]
Reserved
This bit is reserved and must be programmed to 1.
Reserved
This bit is reserved and must be programmed to 0.
[1]
COMP
Comparator Disable
0 = Comparator is enabled.
1 = Comparator is disabled.
[0]
Reserved
This bit is reserved and must be programmed to 0.
PS025113-1212
Power Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
33
General Purpose Input/Output
The Z8 Encore! F0830 Series products support a maximum of 25 port pins (Ports A–D)
for General Purpose Input/Output (GPIO) operations. Each port contains control and data
registers. The GPIO control registers determine data direction, open-drain, output drive
current, programmable pull-ups, Stop Mode Recovery functionality and alternate pin
functions. Each port pin is individually programmable. In addition, the Port C pins are
capable of direct LED drive at programmable drive strengths.
GPIO Port Availability by Device
Table 15 lists the port pins available with each device and package type.
Table 15. Port Availability by Device and Package Type
10-Bit
Devices
Package
ADC
Port A
Port B
Port C
Port D
Total I/O
Z8F1232, Z8F0830,
Z8F0430, Z8F0230,
Z8F0130
20-pin
Yes
[7:0]
[3:0]
[3:0]
[0]
17
Z8F1233, Z8F0831
Z8F0431, Z8F0231
Z8F0131
20-pin
28-pin
28-pin
No
Yes
No
[7:0]
[7:0]
[7:0]
[3:0]
[5:0]
[7:0]
[3:0]
[7:0]
[7:0]
[0]
[0]
[0]
17
23
25
Z8F1232, Z8F0830,
Z8F0430, Z8F0230,
Z8F0130
Z8F1233, Z8F0831
Z8F0431, Z8F0231
Z8F0131
Note: 20-pin and 28-pin and 10-bit ADC Enabled or Disabled can be selected via the option bits.
PS025113-1212
General Purpose Input/Output
Z8 Encore!® F0830 Series
Product Specification
34
Architecture
Figure 8 displays a simplified block diagram of a GPIO port pin. In this figure, the ability
to accommodate alternate functions and variable port current drive strength is not dis-
played.
Port Input
Data Register
Schmitt Trigger
Q
D
Q
D
System
Clock
VDD
Port Output Control
Port Output
Data Register
DATA
Bus
D
Q
Port
Pin
System
Clock
Port Data Direction
GND
Figure 8. GPIO Port Pin Block Diagram
GPIO Alternate Functions
Many of the GPIO port pins can be used for general purpose input/output and access to on-
chip peripheral functions such as the timers and serial communication devices. The Port
A–D Alternate Function subregisters configure these pins for either GPIO or Alternate
function operation. When a pin is configured for Alternate function, control of the port pin
direction (input/output) is passed from the Port A–D data direction registers to the Alter-
nate function assigned to this pin. Table 16 on page 36 lists the alternate functions possible
with each port pin. The alternate function associated at a pin is defined through Alternate
Function subregisters AFS1 and AFS2.
The crystal oscillator functionality is not controlled by the GPIO block. When the crystal
oscillator is enabled in the oscillator control block, the GPIO functionality of PA0 and PA1
is overridden. In that case, pins PA0 and PA1 functions as input and output for the crystal
oscillator.
PS025113-1212
Architecture
Z8 Encore!® F0830 Series
Product Specification
35
PA0 and PA6 contain two different Timer functions, a timer input and a complementary
timer output. Both of these functions require the same GPIO configuration, the selection
between the two is based on the TIMER mode. For more details, see the Timers chapter on
page 68.
Direct LED Drive
The Port C pins provide a sinked current output, capable of driving an LED without
requiring an external resistor. The output sinks current at programmable levels, 3mA,
7mA, 13mA and 20mA. This mode is enabled through the LED Control registers.
For proper function, the LED anode must be connected to VDD and the cathode to the
GPIO pin.
Using all Port C pins in LED drive mode with maximum current may result in excessive
total current. See the Electrical Characteristics chapter on page 184 for the maximum total
current for the applicable package.
Shared Reset Pin
On the 20- and 28-pin devices, the Port D0 pin shares function with a bidirectional reset
pin. Unlike all other I/O pins, this pin does not default to GPIO function on power-up.
This pin acts as a bidirectional input/output open-drain reset with an internal pull-up until
the user software reconfigures it as a GPIO PD0. When in GPIO mode, the Port D0 pin
functions as output only, and must be configured as an output. PD0 supports the high drive
feature, but not the stop-mode recovery feature.
Crystal Oscillator Override
For systems using a crystal oscillator, the pins PA0 and PA1 are connected to the crystal.
When the crystal oscillator is enabled, the GPIO settings are overridden and PA0 and PA1
are disabled. See the Oscillator Control Register Definitions section on page 154.
5V Tolerance
In the 20- and 28-pin versions of this device, any pin, which shares functionality with an
ADC, crystal or comparator port is not 5V-tolerant, including PA[1:0], PB[5:0] and
PC[2:0]. All other signal pins are 5V-tolerant and can safely handle inputs higher than
VDD even with the pull-ups enabled, but with excess power consumption on pull-up resis-
tor.
PS025113-1212
Direct LED Drive
Z8 Encore!® F0830 Series
Product Specification
36
External Clock Setup
For systems using an external TTL drive, PB3 is the clock source for 20- and 28-pin
devices. In this case, configure PB3 for Alternate function CLKIN. Write to the Oscillator
Control Register (see the Oscillator Control Register Definitions section on page 154) to
select the PB3 as the system clock.
Table 16. Port Alternate Function Mapping
Alternate Function
Port
Pin
Mnemonic
T0IN/T0OUT
Reserved
T0OUT
Alternate Function Description
Set Register AFS1
1
Port A
PA0
Timer 0 input/Timer 0 output complement
N/A
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Timer 0 output
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
T1IN/T1OUT
Reserved
T1OUT
Reserved
Reserved
Reserved
Reserved
Timer 1 input/Timer 1 output complement
Timer 1 output
Reserved
Notes:
1. Because there is only a single alternate function for each Port A and Port D (PD0) pin, the Alternate Function
Set registers are not implemented for Port A and Port D (PD0). Enabling alternate function selections (as
described in the Port A–D Alternate Function Subregisters section on page 42) automatically enables the asso-
ciated alternate function.
2. Because there are at most two choices of alternate functions for any Port B pin, the AFS2 Alternate Function Set
Register is implemented but is not used to select the function. Additionally, alternate function selection (as
described in the Port A–D Alternate Function Subregisters section on page 42) must also be enabled.
3. Because there are at most two choices of alternate functions for any Port C pin, the AFS2 Alternate Function Set
Register is implemented but is not used to select the function. Additionally, alternate function selection (as
described in the Port A–D Alternate Function Subregisters section on page 42) must also be enabled.
PS025113-1212
External Clock Setup
Z8 Encore!® F0830 Series
Product Specification
37
Table 16. Port Alternate Function Mapping (Continued)
Alternate Function
Set Register AFS1
Port
Pin
Mnemonic
Reserved
ANA0
Alternate Function Description
ADC analog input
2
Port B
PB0
AFS1[0]: 0
AFS1[0]: 1
AFS1[1]: 0
AFS1[1]: 1
AFS1[2]: 0
AFS1[2]: 1
AFS1[3]: 0
AFS1[3]: 1
AFS1[4]: 0
AFS1[4]: 1
AFS1[5]: 0
AFS1[5]: 1
AFS1[6]: 0
AFS1[6]: 1
AFS1[7]: 0
AFS1[7]: 1
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Reserved
ANA1
ADC analog input
Reserved
ANA2
ADC analog input
External input clock
ADC analog input
CLKIN
ANA3
Reserved
ANA7
ADC analog input
Reserved
V
ADC reference voltage
REF
Reserved
Reserved
Reserved
Reserved
Notes:
1. Because there is only a single alternate function for each Port A and Port D (PD0) pin, the Alternate Function
Set registers are not implemented for Port A and Port D (PD0). Enabling alternate function selections (as
described in the Port A–D Alternate Function Subregisters section on page 42) automatically enables the asso-
ciated alternate function.
2. Because there are at most two choices of alternate functions for any Port B pin, the AFS2 Alternate Function Set
Register is implemented but is not used to select the function. Additionally, alternate function selection (as
described in the Port A–D Alternate Function Subregisters section on page 42) must also be enabled.
3. Because there are at most two choices of alternate functions for any Port C pin, the AFS2 Alternate Function Set
Register is implemented but is not used to select the function. Additionally, alternate function selection (as
described in the Port A–D Alternate Function Subregisters section on page 42) must also be enabled.
PS025113-1212
External Clock Setup
Z8 Encore!® F0830 Series
Product Specification
38
Table 16. Port Alternate Function Mapping (Continued)
Alternate Function
Set Register AFS1
Port
Pin
Mnemonic
Reserved
ANA4/CINP
Reserved
ANA5/CINN
Reserved
ANA6
Alternate Function Description
ADC or comparator input
3
Port C
PC0
AFS1[0]: 0
AFS1[0]: 1
AFS1[1]: 0
AFS1[1]: 1
AFS1[2]: 0
AFS1[2]: 1
AFS1[3]: 0
AFS1[3]: 1
AFS1[4]: 0
AFS1[4]: 1
AFS1[5]: 0
AFS1[5]: 1
AFS1[6]: 0
AFS1[6]: 1
AFS1[7]: 0
AFS1[7]: 1
N/A
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
ADC or comparator input
ADC analog input
Comparator output
COUT
Reserved
Reserved
Reserved
Reserved
Reserved
RESET
1
Port D
Default to be Reset function
Notes:
1. Because there is only a single alternate function for each Port A and Port D (PD0) pin, the Alternate Function
Set registers are not implemented for Port A and Port D (PD0). Enabling alternate function selections (as
described in the Port A–D Alternate Function Subregisters section on page 42) automatically enables the asso-
ciated alternate function.
2. Because there are at most two choices of alternate functions for any Port B pin, the AFS2 Alternate Function Set
Register is implemented but is not used to select the function. Additionally, alternate function selection (as
described in the Port A–D Alternate Function Subregisters section on page 42) must also be enabled.
3. Because there are at most two choices of alternate functions for any Port C pin, the AFS2 Alternate Function Set
Register is implemented but is not used to select the function. Additionally, alternate function selection (as
described in the Port A–D Alternate Function Subregisters section on page 42) must also be enabled.
PS025113-1212
External Clock Setup
Z8 Encore!® F0830 Series
Product Specification
39
GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. Some port pins can be con-
figured to generate an interrupt request on either the rising edge or falling edge of the input
pin signal. Other port pin interrupt sources, generate an interrupt when any edge occurs
(both rising and falling). See the Interrupt Controller chapter on page 53 for more informa-
tion about interrupts using the GPIO pins.
GPIO Control Register Definitions
Four registers for each port provide access to GPIO control, input data and output data;
Table 17 lists these port registers. Use the Port A–D Address and Control registers
together to provide access to subregisters for port configuration and control.
Table 17. GPIO Port Registers and Subregisters
Port Register Mnemonic
Port Register Name
PxADDR
PxCTL
PxIN
Port A–D Address Register (selects subregisters)
Port A–D Control Register (provides access to subregisters)
Port A–D Input Data Register
PxOUT
Port A–D Output Data Register
Port Subregister Mnemonic Port Register Name
PxDD
Data Direction
PxAF
Alternate Function
PxOC
Output Control (open-drain)
High Drive Enable
PxHDE
PxSMRE
PxPUE
PxAFS1
PxAFS2
Stop Mode Recovery Source Enable
Pull-Up Enable
Alternate Function Set 1
Alternate Function Set 2
PS025113-1212
GPIO Interrupts
Z8 Encore!® F0830 Series
Product Specification
40
Port A–D Address Registers
The Port A–D Address registers select the GPIO port functionality accessible through the
Port A–D Control registers. The Port A–D Address and Control registers combine to pro-
vide access to all GPIO port controls; see Tables 18 and 19.
Table 18. Port A–D GPIO Address Registers (PxADDR)
Bit
7
6
5
4
3
2
1
0
Field
PADDR[7:0]
00H
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FD0H, FD4H, FD8H, FDCH
Bit
Description
[7:0]
Port Address
PADDR The port address selects one of the subregisters accessible through the Port Control Register.
Table 19. Port Control Subregister Access
PADDR[7:0] Port Control Subregister accessible using the Port A–D Control registers
00H
01H
No function. Provides some protection against accidental port reconfiguration.
Data Direction
02H
Alternate Function
03H
Output Control (open-drain)
High Drive Enable
04H
05H
Stop Mode Recovery Source Enable
Pull-Up Enable
06H
07H
Alternate Function Set 1
Alternate Function Set 2
No function
08H
09H–FFH
PS025113-1212
GPIO Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
41
Port A–D Control Registers
The Port A–D Control registers, shown in Table 20, set the GPIO port operation. The
value in the corresponding Port A–D Address Register determines which subregister is
read from or written to by a Port A–D Control Register transaction.
Table 20. Port A–D Control Registers (PxCTL)
Bit
7
6
5
4
3
2
1
0
Field
PCTL
00H
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FD1H, FD5H, FD9H, FDDH
Bit
Description
Port Control
[7:0]
PCTL
The Port Control Register provides access to all subregisters that configure the GPIO port
operation.
Port A–D Data Direction Subregisters
The Port A–D Data Direction Subregister, shown in Table 21, is accessed through the Port
A–D Control Register by writing 01Hto the Port A–D Address Register.
Table 21. Port A–D Data Direction Subregisters (PxDD)
Bit
7
6
5
4
3
2
1
0
Field
DD7
1
DD6
1
DD5
1
DD4
1
DD3
1
DD2
1
DD1
1
DD0
1
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
If 01H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit
Description
[7:0]
DDx
Data Direction
These bits control the direction of the associated port pin. Port Alternate Function operation
overrides the Data Direction Register setting.
0 = Output. Data in the Port A–D Output Data Register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–D Input Data Register.
The output driver is tristated.
Note: x indicates the specific GPIO port pin number (7–0).
PS025113-1212
GPIO Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
42
Port A–D Alternate Function Subregisters
The Port A–D Alternate Function Subregister is accessed through the Port A–D Control
Register by writing 02Hto the Port A–D Address Register. See Table 22 on page 42. The
Port A–D Alternate Function subregisters enable the alternate function selection on pins.
If disabled, the pins function as GPIOs. If enabled, select one of four alternate functions
using Alternate Function Set subregisters 1 and 2, as described in the the Port A–D Alter-
nate Function Set 1 Subregisters section on page 47 and the Port A–D Alternate Function
Set 2 Subregisters section on page 48. See the GPIO Alternate Functions section on
page 34 to determine the alternate functions associated with each port pin.
Do not enable alternate functions for GPIO port pins for which there is no associated Al-
ternate function. Failure to follow this guideline can result in unpredictable operation.
Caution:
Table 22. Port A–D Alternate Function Subregisters (PxAF)
Bit
7
AF7
6
5
4
3
2
1
0
Field
RESET
R/W
AF6
AF5
AF4
AF3
AF2
AF1
AF0
00H (Ports A–C); 01H (Port D)
R/W
Address If 02H in Port A–D Address Register, then accessible through the Port A–D Control Register
Bit
Description
[7:0]
AFx
Port Alternate Function Enable
0 = The port pin is in NORMAL Mode and the DDxbit in the Port A–D Data Direction Subregis-
ter determines the direction of the pin.
1 = The alternate function selected through Alternate function set subregisters is enabled. Port
pin operation is controlled by the Alternate function.
Note: x indicates the specific GPIO port pin number (7–0).
PS025113-1212
GPIO Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
43
Port A–D Output Control Subregisters
The Port A–D Output Control Subregister, shown in Table 23, is accessed through the Port
A–D Control Register by writing 03Hto the Port A–D Address Register. Setting the bits in
the Port A–D Output Control subregisters to 1 configures the specified port pins for open-
drain operation. These subregisters affect the pins directly and, as a result, alternate func-
tions are also affected.
Table 23. Port A–D Output Control Subregisters (PxOC)
Bit
7
POC7
0
6
POC6
0
5
POC5
0
4
POC4
0
3
POC3
0
2
POC2
0
1
POC1
0
0
POC0
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
If 03H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit
Description
[7:0]
POCx
Port Output Control
These bits function independently of the Alternate function bit and always disable the drains, if
set to 1.
0 = The drains are enabled for any OUTPUT Mode (unless overridden by the Alternate func-
tion).
1 = The drain of the associated pin is disabled (OPEN-DRAIN mode).
Note: x indicates the specific GPIO port pin number (7–0).
PS025113-1212
GPIO Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
44
Port A–D High Drive Enable Subregisters
The Port A–D High Drive Enable Subregister, shown in Table 24, is accessed through the
Port A–D Control Register by writing 04Hto the Port A–D Address Register. Setting the
bits in the Port A–D High Drive Enable subregisters to 1 configures the specified port pins
for high-output current drive operation. The Port A–D High Drive Enable Subregister
affects the pins directly and, as a result, alternate functions are also affected.
Table 24. Port A–D High Drive Enable Subregisters (PxHDE)
Bit
7
PHDE7
0
6
PHDE6
0
5
PHDE5
0
4
PHDE4
0
3
PHDE3
0
2
PHDE2
0
1
PHDE1
0
0
PHDE0
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
If 04H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit
Description
[7:0]
PHDEx
Port High Drive Enable
0 = The port pin is configured for standard output current drive.
1 = The port pin is configured for high output current drive.
Note: x indicates the specific GPIO port pin number (7–0).
PS025113-1212
GPIO Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
45
Port A–D Stop Mode Recovery Source Enable Subregisters
The Port A–D Stop Mode Recovery Source Enable Subregister, shown in Table 25, is
accessed through the Port A–D Control Register by writing 05Hto the Port A–D Address
Register. Setting the bits in the Port A–D Stop Mode Recovery Source Enable subregisters
to 1 configures the specified port pins as a Stop Mode Recovery source. During STOP
Mode, any logic transition on a port pin enabled as a Stop Mode Recovery source initiates
a Stop Mode Recovery event.
Table 25. Port A–D Stop Mode Recovery Source Enable Subregisters (PxSMRE)
Bit
7
6
5
4
3
2
1
0
Field
PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMRE0
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
If 05H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit
Description
Port Stop Mode Recovery Source Enable
[7:0]
PSMREx 0 = The port pin is not configured as a Stop Mode Recovery source. Transitions on this pin dur-
ing STOP Mode do not initiate Stop Mode Recovery.
1 = The port pin is configured as a Stop Mode Recovery source. Any logic transition on this pin
during STOP Mode initiates Stop Mode Recovery.
Note: x indicates the specific GPIO port pin number (7–0).
PS025113-1212
GPIO Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
46
Port A–D Pull-up Enable Subregisters
The Port A–D Pull-Up Enable Subregister is accessed through the Port A–D Control Reg-
ister by writing 06Hto the Port A–D Address Register. See Table 26. Setting the bits in the
Port A–D Pull-Up Enable subregisters enables a weak internal resistive pull-up on the
specified port pins.
Table 26. Port A–D Pull-Up Enable Subregisters (PxPUE)
Bit
7
PPUE7
0
6
PPUE6
0
5
PPUE5
0
4
PPUE4
0
3
PPUE3
0
2
PPUE2
0
1
PPUE1
0
0
PPUE0
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
If 06H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit
Description
[7:0]
PxPUE
Port Pull-Up Enable
0 = The weak pull-up on the port pin is disabled.
1 = The weak pull-up on the port pin is enabled.
Note: x indicates the specific GPIO port pin number (7–0).
PS025113-1212
GPIO Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
47
Port A–D Alternate Function Set 1 Subregisters
The Port A–D Alternate Function Set 1 Subregister, shown in Table 27, is accessed
through the Port A–D Control Register by writing 07Hto the Port A–D Address Register.
The Alternate Function Set 1 subregisters select the alternate function available at a port
pin. Alternate functions selected by setting or clearing bits in this register are defined in
the GPIO Alternate Functions section on page 34.
Alternate function selection on the port pins must also be enabled, as described in the Port
A–D Alternate Function Subregisters section on page 42.
Note:
Table 27. Port A–D Alternate Function Set 1 Subregisters (PxAFS1)
Bit
7
PAFS17
0
6
PAFS16
0
5
PAFS15
0
4
PAFS14
0
3
PAFS13
0
2
PAFS12
0
1
PAFS11
0
0
PAFS10
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
If 07H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit
Description
Port Alternate Function Set 1
[7:0]
PAFS1x 0 = Port Alternate function selected as defined in Table 16 in GPIO Alternate Functions sec-
tion.
1 = Port Alternate function selected as defined in Table 16 in GPIO Alternate Functions sec-
tion.
Note: x indicates the specific GPIO port pin number (7–0).
PS025113-1212
GPIO Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
48
Port A–D Alternate Function Set 2 Subregisters
The Port A–D Alternate Function Set 2 Subregister, shown in Table 28, is accessed
through the Port A–D Control Register by writing 08Hto the Port A–D Address Register.
The Alternate Function Set 2 subregisters select the alternate function available at a port
pin. Alternate functions selected by setting or clearing bits in this register are defined in
Table 16 in the GPIO Alternate Functions section on page 34.
Alternate function selection on the port pins must also be enabled, as described in the Port
A–D Alternate Function Subregisters section on page 42.
Note:
Table 28. Port A–D Alternate Function Set 2 Subregisters (PxAFS2)
Bit
7
PAFS27
0
6
PAFS26
0
5
PAFS25
0
4
PAFS24
0
3
PAFS23
0
2
PAFS22
0
1
PAFS21
0
0
PAFS20
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
If 08H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit
Description
Port Alternate Function Set 2
[7:0]
PAFS2x 0 = The Port Alternate function is selected, as defined in Table 16 in the GPIO Alternate Func-
tions section on page 34.
1 = The Port Alternate function is selected, as defined in Table 16 in the GPIO Alternate Func-
tions section on page 34.
Note: x indicates the specific GPIO port pin number (7–0).
PS025113-1212
GPIO Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
49
Port A–C Input Data Registers
Reading from the Port A–C Input Data registers, shown in Table 29, return the sampled
values from the corresponding port pins. The Port A–C Input Data registers are read-only.
The value returned for any unused ports is 0. Unused ports include those not included in
the 8- and 28-pin packages, as well as those not included in the ADC-enabled 28-pin pack-
ages.
Table 29. Port A–C Input Data Registers (PxIN)
Bit
7
PIN7
X
6
PIN6
X
5
PIN5
X
4
PIN4
X
3
PIN3
X
2
PIN2
X
1
PIN1
X
0
PIN0
X
Field
RESET
R/W
R
R
R
R
R
R
R
R
Address
FD2H, FD6H, FDAH
Bit
Description
[7:0]
PxIN
Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
Note: x indicates the specific GPIO port pin number (7–0).
PS025113-1212
GPIO Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
50
Port A–D Output Data Register
The Port A–D Output Data Register, shown in Table 30, controls the output data to the
pins.
Table 30. Port A–D Output Data Register (PxOUT)
Bit
7
POUT7
0
6
POUT6
0
5
POUT5
0
4
POUT4
0
3
POUT3
0
2
POUT2
0
1
POUT1
0
0
POUT0
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FD3H, FD7H, FDBH, FDFH
Bit
Description
[7:0]
PxOUT
Port Output Data
These bits contain the data to be driven to the port pins. The values are only driven if the corre-
sponding pin is configured as an output and the pin is not configured for Alternate function
operation.
0 = Drive a logical 0 (Low).
1= Drive a logical 1 (High). High value is not driven if the drain has been disabled by setting the
corresponding port output Control Register bit to 1.
Note: x indicates the specific GPIO port pin number (7–0).
PS025113-1212
GPIO Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
51
LED Drive Enable Register
The LED Drive Enable Register, shown in Table 31, activates the controlled current drive.
The Alternate Function Register has no control over the LED function; therefore, setting
the Alternate Function Register to select the LED function is not required. LEDEN bits
[7:0] correspond to Port C bits [7:0], respectively.
Table 31. LED Drive Enable (LEDEN)
Bit
7
6
5
4
3
2
1
0
Field
LEDEN[7:0]
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F82H
Bit
Description
[7:0]
LEDEN
LED Drive Enable
These bits determine which Port C pins are connected to an internal current sink.
0 = Tristate the Port C pin.
1= Connect controlled current sink to the Port C pin.
LED Drive Level High Register
The LED Drive Level High Register, shown in Table 32, contains two control bits for each
Port C pin. These two bits select one of four programmable current drive levels for each
Port C pin. Each pin is individually programmable.
Table 32. LED Drive Level High Register (LEDLVLH)
Bit
7
6
5
4
3
2
1
0
Field
LEDLVLH[7:0]
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F83H
Bit
Description
[7:0]
LED Level High Bits
LEDLVLH {LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each Port C pin.
00 = 3mA.
01= 7mA.
10= 13mA.
11= 20mA.
PS025113-1212
GPIO Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
52
LED Drive Level Low Register
The LED Drive Level Low Register, shown in Table 33, contains two control bits for each
Port C pin. These two bits select one of four programmable current drive levels for each
Port C pin. Each pin is individually programmable.
Table 33. LED Drive Level Low Register (LEDLVLL)
Bit
7
6
5
4
3
2
1
0
Field
LEDLVLL[7:0]
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F84H
Bit
Description
[7:0]
LED Level Low Bits
LEDLVLL {LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each Port C pin.
00 = 3mA.
01 = 7mA.
10 = 13mA.
11 = 20mA.
PS025113-1212
GPIO Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
53
Interrupt Controller
The Interrupt Controller on the Z8 Encore!® F0830 Series products prioritize the interrupt
requests from the on-chip peripherals and the GPIO port pins. The features of the Interrupt
Controller include:
•
Seventeen interrupt sources using sixteen unique interrupt vectors:
–
–
Twelve GPIO port pin interrupt sources
Five on-chip peripheral interrupt sources (Comparator Output interrupt shares one
interrupt vector with PA6)
•
Flexible GPIO interrupts
–
–
Eight selectable rising and falling edge GPIO interrupts
Four dual-edge interrupts
•
•
Three levels of individually programmable interrupt priority
Watchdog Timer can be configured to generate an interrupt
m
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information or control infor-
mation between the CPU and the interrupting peripheral. When the service routine is com-
pleted, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the Interrupt Controller has no effect on operation. For more information about interrupt
servicing by the eZ8 CPU, refer to the eZ8 CPU User Manual (UM0128), which is avail-
able for download at www.zilog.com.
Interrupt Vector Listing
Table 34 lists the interrupts available in order of priority. The interrupt vector is stored
with the most significant byte (MSB) at the even program memory address and the least
significant byte (LSB) at the odd program memory address.
Some port interrupts are not available on the 20-pin and 28-pin packages. The ADC inter-
rupt is unavailable on devices not containing an ADC.
Note:
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Interrupt Controller
Z8 Encore!® F0830 Series
Product Specification
54
Table 34. Trap and Interrupt Vectors in Order of Priority
Program
Memory
Priority Vector Address Interrupt or Trap Source
Highest 0002H
0004H
003AH
003CH
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
001AH
001CH
001EH
0020H
0022H
0024H
0026H
0028H
002AH
002CH
002EH
0030H
0032H
0034H
0036H
Reset (not an interrupt)
Watchdog Timer (see Watchdog Timer chapter)
Primary oscillator fail trap (not an interrupt)
Watchdog Oscillator fail trap (not an interrupt)
Illegal instruction trap (not an interrupt)
Reserved
Timer 1
Timer 0
Reserved
Reserved
Reserved
Reserved
ADC
Port A7, selectable rising or falling input edge
Port A6, selectable rising or falling input edge or Comparator Output
Port A5, selectable rising or falling input edge
Port A4, selectable rising or falling input edge
Port A3, selectable rising or falling input edge
Port A2, selectable rising or falling input edge
Port A1, selectable rising or falling input edge
Port A0, selectable rising or falling input edge
Reserved
Reserved
Reserved
Reserved
Port C3, both input edges
Port C2, both input edges
Port C1, both input edges
Port C0, both input edges
Reserved
Lowest
0038H
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Interrupt Vector Listing
Z8 Encore!® F0830 Series
Product Specification
55
Architecture
Figure 9 displays the Interrupt Controller block diagram.
High
Priority
Port Interrupts
Vector
Priority
Mux
IRQ Request
Medium
Priority
Internal Interrupts
Low
Priority
Figure 9. Interrupt Controller Block Diagram
Operation
This section describes the operational aspects of the following functions.
Master Interrupt Enable: see page 55
Interrupt Vectors and Priority: see page 56
Interrupt Assertion: see page 56
Software Interrupt Assertion: see page 57
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables
and disables the interrupts.
Interrupts are globally enabled by any of the following actions:
•
•
Execution of an EI (enable interrupt) instruction
Execution of an IRET (return from interrupt) instruction
PS025113-1212
Architecture
Z8 Encore!® F0830 Series
Product Specification
56
•
Writing 1 to the IRQE bit in the Interrupt Control Register
Interrupts are globally disabled by any of the following actions:
•
•
Execution of a DI(disable interrupt) instruction
eZ8 CPU acknowledgement of an interrupt service request from the Interrupt Control-
ler
•
•
•
•
•
•
Writing a 0 to the IRQE bit in the Interrupt Control Register
Reset
Execution of a trap instruction
Illegal instruction Trap
Primary oscillator fail trap
Watchdog Oscillator fail trap
Interrupt Vectors and Priority
The Interrupt Controller supports three levels of interrupt priority. Level 3 is the highest
priority, level 2 is the second highest priority and level 1 is the lowest priority. If all of the
interrupts are enabled with identical interrupt priority (all as level 2 interrupts, for exam-
ple), the interrupt priority is assigned from highest to lowest as specified in Table 34 on
page 54. Level 3 interrupts are always assigned higher priority than level 2 interrupts and
level 2 interrupts are assigned higher priority than level 1 interrupts. Within each interrupt
priority level (level 1, level 2 or level 3), priority is assigned as specified in Table 34,
above. Reset, Watchdog Timer interrupt (if enabled), primary oscillator fail trap, Watch-
dog Oscillator fail trap and illegal instruction trap always have highest (level 3) priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period (sin-
gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond-
ing bit in the interrupt request register is cleared. Writing 0 to the corresponding bit in the
interrupt request register clears the interrupt request.
Zilog recommends not using a coding style that clears bits in the Interrupt Request reg-
isters. All incoming interrupts received between execution of the first LDX command
and the final LDX command are lost. See Example 1, which follows.
Caution:
Example 1. A poor coding style that can result in lost interrupt requests:
PS025113-1212
Operation
Z8 Encore!® F0830 Series
Product Specification
57
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, use the coding style in Example 2 to clear bits in the Interrupt
Request 0 Register:
Example 2. A good coding style that avoids lost interrupt requests:
ANDX IRQ0, MASK
Software Interrupt Assertion
Program code can generate interrupts directly. Writing 1 to the correct bit in the interrupt
request register triggers an interrupt (assuming that interrupt is enabled). When the inter-
rupt request is acknowledged by the eZ8 CPU, the bit in the interrupt request register is
automatically cleared to 0.
Zilog recommends not using a coding style to generate software interrupts by setting bits
in the Interrupt Request registers. All incoming interrupts received between execution of
the first LDX command and the final LDX command are lost. See Example 3, which fol-
lows.
Caution:
Example 3. A poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, use the coding style in Example 4 to set bits in the Interrupt
Request registers:
Example 4. A good coding style that avoids lost interrupt requests:
ORX IRQ0, MASK
Interrupt Control Register Definitions
The Interrupt Control registers enable individual interrupts, set interrupt priorities and
indicate interrupt requests for all of the interrupts other than the Watchdog Timer interrupt,
the primary oscillator fail trap and the Watchdog Oscillator fail trap interrupts.
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Interrupt Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
58
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) Register, shown in Table 35 stores the interrupt requests
for both vectored and polled interrupts. When a request is sent to the Interrupt Controller,
the corresponding bit in the IRQ0 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the Interrupt Controller passes an interrupt request to the eZ8 CPU.
If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 0 Register to determine if any interrupt requests are pending.
Table 35. Interrupt Request 0 Register (IRQ0)
Bit
7
Reserved
0
6
T1I
0
5
T0I
0
4
3
2
1
0
ADCI
0
Field
Reserved
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC0H
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6]
T1I
Timer 1 Interrupt Request
0 = No interrupt request is pending for timer 1.
1 = An interrupt request from timer 1 is awaiting service.
[5]
T0I
Timer 0 Interrupt Request
0 = No interrupt request is pending for timer 0.
1 = An interrupt request from timer 0 is awaiting service.
[4:1]
Reserved
These registers are reserved and must be programmed to 0000.
[0]
ADCI
ADC Interrupt Request
0 = No interrupt request is pending for the analog-to-digital converter.
1 = An interrupt request from the analog-to-digital converter is awaiting service.
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Interrupt Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
59
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) Register, shown in Table 36, stores interrupt requests for
both vectored and polled interrupts. When a request is sent to the Interrupt Controller, the
corresponding bit in the IRQ1 Register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the Interrupt Controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 1 Register to determine if any interrupt requests are pending.
Table 36. Interrupt Request 1 Register (IRQ1)
Bit
7
6
PA6CI
0
5
4
3
2
1
0
Field
PA7I
0
PA5I
0
PA4I
0
PA3I
0
PA2I
0
PA1I
0
PA0I
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC3H
Bit
Description
Port A7
[7]
PA7I
0 = No interrupt request is pending for GPIO Port A.
1 = An interrupt request from GPIO Port A.
[6]
PA6CI
Port A6 or Comparator Interrupt Request
0 = No interrupt request is pending for GPIO Port A or comparator.
1 = An interrupt request from GPIO Port A or comparator.
[5]
PAxI
Port A Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port A pin x.
1 = An interrupt request from GPIO Port A pin x is awaiting service.
Note: x indicates the specific GPIO port pin number (5–0).
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Interrupt Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
60
Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) Register, shown in Table 37, stores interrupt requests for
both vectored and polled interrupts. When a request is sent to the Interrupt Controller, the
corresponding bit in the IRQ2 Register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the Interrupt Controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 2 Register to determine if any interrupt requests are pending.
Table 37. Interrupt Request 2 Register (IRQ2)
Bit
7
6
5
4
3
PC3I
0
2
PC2I
0
1
PC1I
0
0
PC0I
0
Field
Reserved
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC6H
Bit
Description
Reserved
[7:4]
These registers are reserved and must be programmed to 0000.
[3]
PCxI
Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
Note: x indicates the specific GPIO port pin number (3–0).
IRQ0 Enable High and Low Bit Registers
Table 38 lists the priority control values for IRQ0. The IRQ0 Enable High and Low Bit
registers, shown in Tables 39 and 40, form a priority-encoded enabling service for inter-
rupts in the Interrupt Request 0 Register. Priority is generated by setting the bits in each
register.
Table 38. IRQ0 Enable and Priority Encoding
IRQ0ENH[x]
IRQ0ENL[x]
Priority
Disabled
Level 1
Level 2
Level 3
Description
Disabled
Low
0
0
1
1
0
1
0
1
Nominal
High
Note: x indicates the register bits in the range 7–0.
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Z8 Encore!® F0830 Series
Product Specification
61
Table 39. IRQ0 Enable High Bit Register (IRQ0ENH)
Bit
7
6
5
T0ENH
0
4
3
2
1
0
ADCENH
0
Field
Reserved T1ENH
Reserved
RESET
R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC1H
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6]
Timer 1 Interrupt Request Enable High Bit
T1ENH
[5]
T0ENH
Timer 0 Interrupt Request Enable High Bit
Reserved
[4:1]
These registers are reserved and must be programmed to 0000.
[0]
ADC Interrupt Request Enable High Bit
ADCENH
Table 40. IRQ0 Enable Low Bit Register (IRQ0ENL)
Bit
7
6
T1ENL
0
5
T0ENL
0
4
3
2
1
0
ADCENL
0
Field
Reserved
Reserved
RESET
R/W
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R
R
R/W
Address
FC2H
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6]
Timer 1 Interrupt Request Enable Low Bit
T1ENL
[5]
T0ENL
Timer 0 Interrupt Request Enable Low Bit
Reserved
[4:1]
These registers are reserved and must be programmed to 0000.
[0]
ADC Interrupt Request Enable Low Bit
ADCENL
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Interrupt Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
62
IRQ1 Enable High and Low Bit Registers
Table 41 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit reg-
isters, shown in Tables 42 and 43, form a priority-encoded enabling service for interrupts
in the Interrupt Request 1 Register. Priority is generated by setting the bits in each register.
Table 41. IRQ1 Enable and Priority Encoding
IRQ1ENH[x]
IRQ1ENL[x]
Priority
Disabled
Level 1
Level 2
Level 3
Description
Disabled
Low
0
0
1
1
0
1
0
1
Nominal
High
Note: x indicates register bits in the address range 7–0.
Table 42. IRQ1 Enable High Bit Register (IRQ1ENH)
Bit
7
6
5
4
3
2
1
0
Field
PA7ENH PA6CENH PA5ENH PA4ENH PA3ENH PA2ENH PA1ENH PA0ENH
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC4H
Bit
Description
[7]
Port A Bit[7] Interrupt Request Enable High Bit
PA7ENH
[6]
Port A Bit[7] or Comparator Interrupt Request Enable High Bit
PA6CENH
[5:0]
PAxENH
Port A Bit[x] Interrupt Request Enable High Bit
See the interrupt port select register for selection of either Port A or Port D as the interrupt
source.
Note: x indicates register bits in the address range 5–0.
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Interrupt Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
63
Table 43. IRQ1 Enable Low Bit Register (IRQ1ENL)
Bit
7
6
5
4
3
2
1
0
Field
PA7ENL PA6CENL PA5ENL PA4ENL PA3ENL PA2ENL PA1ENL PA0ENL
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC5H
Bit
Description
[7]
Port A Bit[7] Interrupt Request Enable Low Bit
PA7ENL
[6]
Port A Bit[7] or Comparator Interrupt Request Enable Low Bit
PA6CENL
[5:0]
PAxENL
Port A Bit[x] Interrupt Request Enable Low Bit
See the interrupt port select register for selection of either Port A or Port D as the interrupt
source.
Note: x indicates register bits in the address range 5–0.
IRQ2 Enable High and Low Bit Registers
Table 44 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-
isters, shown in Tables 45 and 46, form a priority-encoded enabling service for interrupts
in the Interrupt Request 2 Register. Priority is generated by setting the bits in each register.
Table 44. IRQ2 Enable and Priority Encoding
IRQ2ENH[x]
IRQ2ENL[x]
Priority
Disabled
Level 1
Level 2
Level 3
Description
Disabled
Low
0
0
1
1
0
1
0
1
Nominal
High
Note: x indicates register bits in the address range 7–0.
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Interrupt Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
64
Table 45. IRQ2 Enable High Bit Register (IRQ2ENH)
Bit
7
6
5
4
3
C3ENH
0
2
C2ENH
0
1
C1ENH
0
0
C0ENH
0
Field
Reserved
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC7H
Bit
Description
Reserved
[7:4]
These registers are reserved and must be programmed to 0000.
[3]
Port C3 Interrupt Request Enable High Bit
C3ENH
[2]
C2ENH
Port C2 Interrupt Request Enable High Bit
Port C1 Interrupt Request Enable High Bit
Port C0 Interrupt Request Enable High Bit
[1]
C1ENH
[0]
C0ENH
Table 46. IRQ2 Enable Low Bit Register (IRQ2ENL)
Bit
7
6
5
4
3
C3ENL
0
2
C2ENL
0
1
C1ENL
0
0
C0ENL
0
Field
Reserved
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC8H
Bit
Description
Reserved
[7:4]
These registers are reserved and must be programmed to 0000.
[3]
Port C3 Interrupt Request Enable Low Bit
C3ENL
[2]
C2ENL
Port C2 Interrupt Request Enable Low Bit
Port C1 Interrupt Request Enable Low Bit
Port C0 Interrupt Request Enable Low Bit
[1]
C1ENL
[0]
C0ENL
PS025113-1212
Interrupt Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
65
Interrupt Edge Select Register
The interrupt edge select (IRQES) register determines whether an interrupt is generated
for the rising edge or falling edge on the selected GPIO Port A or Port D input pin. See
Table 47.
Table 47. Interrupt Edge Select Register (IRQES)
Bit
7
6
5
4
3
2
1
0
Field
IES7
0
IES6
0
IES5
0
IES4
0
IES3
0
IES2
0
IES1
0
IES0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FCDH
Bit
Description
[7]
IESx
Interrupt Edge Select x
0 = An interrupt request is generated on the falling edge of the PAx input or PDx.
1 = An interrupt request is generated on the rising edge of the PAx input or PDx.
Note: x indicates register bits in the address range 7–0.
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Interrupt Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
66
Shared Interrupt Select Register
The shared interrupt select (IRQSS) register determines the source of the PADxS inter-
rupts. See Table 48. The shared interrupt select register selects between Port A and alter-
nate sources for the individual interrupts.
Because these shared interrupts are edge-triggered, it is possible to generate an interrupt
just by switching from one shared source to another. For this reason, an interrupt must be
disabled before switching between sources.
Table 48. Shared Interrupt Select Register (IRQSS)
Bit
7
Reserved
0
6
PA6CS
0
5
4
3
2
1
0
Field
Reserved
RESET
R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FCEH
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6]
PA6CS
PA6/Comparator Selection
0 = PA6 is used for the interrupt caused by PA6CS interrupt request.
1 = The comparator is used for the interrupt caused by PA6CS interrupt request.
[5:0]
Reserved
These registers are reserved and must be programmed to 000000.
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Interrupt Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
67
Interrupt Control Register
The Interrupt Control (IRQCTL) Register, shown in Table 49, contains the master enable
bit for all interrupts.
Table 49. Interrupt Control Register (IRQCTL)
Bit
7
IRQE
0
6
5
4
3
2
1
0
Field
Reserved
RESET
R/W
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
Address
FCFH
Bit
Description
[7]
IRQE
Interrupt Request Enable
This bit is set to 1 by executing an Enable Interrupts (EI) or Interrupt Return (IRET) instruction
or by a direct register write of 1 to this bit. It is reset to 0 by executing a DIinstruction, eZ8
CPU acknowledgement of an interrupt request, reset, or by a direct register write of a 0 to this
bit.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
[6:0]
Reserved
These registers are reserved and must be programmed to 0000000.
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Interrupt Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
68
Timers
The Z8 Encore! F0830 Series products contain up to two 16-bit reloadable timers that can
be used for timing, event counting or generation of pulse width modulated (PWM) signals.
The timers feature include:
•
•
•
•
•
16-bit reload counter
Programmable prescaler with prescale values ranging from 1 to 128
PWM output generation
Capture and compare capability
External input pin for timer input, clock gating or capture signal. External input pin sig-
nal frequency is limited to a maximum of one-fourth the system clock frequency
•
•
Timer output pin
Timer interrupt
Architecture
Figure 10 displays the architecture of the timers.
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Timers
Z8 Encore!® F0830 Series
Product Specification
69
Timer Block
Timer
Control
Data
Bus
Block
Control
Timer
Interrupt
16-Bit
Reload Register
Interrupt,
PWM,
and
Timer Output
Control
Timer
Output
System
Clock
Timer
Output
16-Bit Counter
with Prescaler
Timer
Input
Complement
Gate
Input
16-Bit
PWM/Compare
Capture
Input
Figure 10. Timer Block Diagram
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001Hinto the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000Hinto the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFH, the timer resets back to 0000Hand continues counting.
Timer Operating Modes
The timers can be configured to operate in the following modes:
ONE-SHOT Mode
In ONE-SHOT Mode, the timer counts up to the 16-bit reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the reload value, the timer generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to 0001H. The timer is automatically disabled and stops
counting.
Additionally, if the timer output alternate function is enabled, the timer output pin changes
state for one system clock cycle (from Low to High or from High to Low) upon timer
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Z8 Encore!® F0830 Series
Product Specification
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reload. For the timer output to make a state change at a ONE-SHOT time-out (rather than
a single cycle pulse), first set the TPOL bit in the Timer Control Register to the start value
before enabling ONE-SHOT Mode. After starting the timer, set TPOLto the opposite bit
value.
Observe the following steps for configuring a timer for ONE-SHOT Mode and for initiat-
ing the count:
1. Write to the Timer Control Register to:
–
–
–
–
Disable the timer
Configure the timer for ONE-SHOT Mode
Set the prescale value
Set the initial output level (High or Low) if using the timer output Alternate func-
tion
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the timer output function, configure the associated GPIO port pin for the timer
output alternate function.
6. Write to the Timer Control Register to enable the timer and initiate counting.
In ONE-SHOT Mode, the system clock always provides the timer input. The timer period
is calculated with the following equation:
Reload Value – Start Value Prescale
One-Shot Mode Time-Out Period (s) = ------------------------------------------------------------------------------------------------
System Clock Frequency (Hz)
CONTINUOUS Mode
In CONTINUOUS Mode, the timer counts up to the 16-bit reload value stored in the
Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the reload value, the timer generates an interrupt, the count value in the Timer
High and Low Byte registers is reset to 0001Hand the counting resumes. Additionally, if
the timer output alternate function is enabled, the timer output pin changes state (from
Low to High or from High to Low) at timer reload.
Observe the following steps for configuring a timer for CONTINUOUS Mode and for ini-
tiating the count:
1. Write to the Timer Control Register to:
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Z8 Encore!® F0830 Series
Product Specification
71
–
–
–
–
Disable the timer
Configure the timer for CONTINUOUS Mode
Set the prescale value
If using the timer output Alternate function, set the initial output level (High or
Low)
2. Write to the Timer High and Low Byte registers to set the starting count value (usually
0001H). This action only affects the first pass in CONTINUOUS Mode. After the first
timer reload in CONTINUOUS Mode, counting always begins at the reset value of
0001H.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. Enable the timer interrupt (if appropriate) and set the timer interrupt priority by writ-
ing to the relevant interrupt registers.
5. Configure the associated GPIO port pin (if using the timer output function) for the
timer output alternate function.
6. Write to the Timer Control Register to enable the timer and initiate counting.
In CONTINUOUS Mode, the system clock always provides the timer input. The timer
period is calculated with the following equation:
Reload Value Prescale
Continuous Mode Time-Out Period (s) = ------------------------------------------------------------------------
System Clock Frequency (Hz)
If an initial starting value other than 0001His loaded into the Timer High and Low Byte
registers, use the ONE-SHOT Mode equation to determine the first time-out period.
COUNTER Mode
In COUNTER Mode, the timer counts input transitions from a GPIO port pin. The timer
input is taken from the GPIO port pin: timer input alternate function. The TPOL bit in the
Timer Control Register determines whether the count occurs on the rising edge or the fall-
ing edge of the timer input signal. In COUNTER Mode, the prescaler is disabled.
The input frequency of the timer input signal must not exceed one-fourth the system
clock frequency.
Caution:
Upon reaching the reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001Hand counting resumes. Additionally, if the timer output alternate function
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is enabled, the timer output pin changes state (from Low to High or from High to Low) at
timer reload.
Observe the following steps for configuring a timer for COUNTER Mode and for initiat-
ing the count:
1. Write to the Timer Control Register to:
–
–
–
Disable the timer
Configure the timer for COUNTER Mode
Select either the rising edge or falling edge of the timer input signal for the count.
This selection also sets the initial logic level (High or Low) for the timer output
alternate function. However, the timer output function is not required to be
enabled.
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in COUNTER Mode. After the first timer reload in COUN-
TER Mode, counting always begins at the reset value 0001H. In COUNTER Mode,
the Timer High and Low Byte registers must be written with the value 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the associated GPIO port pin for the timer input alternate function.
6. If using the timer output function, configure the associated GPIO port pin for the timer
output alternate function.
7. Write to the Timer Control Register to enable the timer.
In COUNTER Mode, the number of timer input transitions is calculated with the follow-
ing equation:
Counter Mode Timer Input Transitions = Current Count Value – Start Value
COMPARATOR COUNTER Mode
In COMPARATOR COUNTER Mode, the timer counts the input transitions from the ana-
log comparator output. The TPOL bit in the Timer Control Register determines whether
the count occurs on the rising edge or the falling edge of the comparator output signal. In
COMPARATOR COUNTER Mode, the prescaler is disabled.
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The frequency of the comparator output signal must not exceed one-fourth the system
clock frequency.
Caution:
After reaching the reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001Hand counting resumes. Additionally, if the timer output alternate function
is enabled, the timer output pin changes state (from Low to High or from High to Low) at
timer reload.
Observe the following steps for configuring a timer for COMPARATOR COUNTER
Mode and for initiating the count:
1. Write to the Timer Control Register to:
–
–
–
Disable the timer
Configure the timer for COMPARATOR COUNTER Mode.
Select either the rising edge or falling edge of the comparator output signal for the
count. This also sets the initial logic level (High or Low) for the timer output alter-
nate function. However, the timer output function is not required to be enabled.
2. Write to the Timer High and Low Byte registers to set the starting count value. This
action only affects the first pass in COMPARATOR COUNTER Mode. After the first
timer reload in COMPARATOR COUNTER Mode, counting always begins at the
reset value 0001H. Generally, in COMPARATOR COUNTER Mode, the Timer High
and Low Byte registers must be written with the value 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the timer output function, configure the associated GPIO port pin for the timer
output alternate function.
6. Write to the Timer Control Register to enable the timer.
In COMPARATOR COUNTER Mode, the number of comparator output transitions is cal-
culated with the following equation:
Comparator Output Transitions = Current Count Value – Start Value
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PWM SINGLE OUTPUT Mode
In PWM SINGLE OUTPUT Mode, the timer outputs a pulse width modulated (PWM)
output signal through a GPIO port pin. The timer input is the system clock. The timer first
counts up to 16-bit PWM match value stored in the timer PWM High and Low Byte regis-
ters. When the timer count value matches the PWM value, the timer output toggles. The
timer continues counting until it reaches the reload value stored in the Timer Reload High
and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt,
the count value in the Timer High and Low Byte registers is reset to 0001Hand counting
resumes.
If the TPOL bit in the Timer Control Register is set to 1, the timer output signal begins as
a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The
timer output signal returns to a High (1) after the timer reaches the reload value and is
reset to 0001H.
If the TPOL bit in the Timer Control Register is set to 0, the timer output signal begins as
a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The
timer output signal returns to a Low (0) after the timer reaches the reload value and is reset
to 0001H.
Observe the following steps for configuring a timer for PWM SINGLE OUTPUT Mode
and for initiating PWM operation:
1. Write to the Timer Control Register to:
–
–
–
–
Disable the timer
Configure the timer for PWM Mode
Set the prescale value
Set the initial logic level (High or Low) and PWM High/Low transition for the
timer output alternate function
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001H). This value only affects the first pass in PWM Mode. After the first timer
reset in PWM Mode, counting always begins at the reset value of 0001H.
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM
period). The reload value must be greater than the PWM value.
5. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
6. Configure the associated GPIO port pin for the timer output alternate function.
7. Write to the Timer Control Register to enable the timer and initiate counting.
The PWM period is represented by the following equation:
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Reload Value Prescale
PWM Period (s) = ------------------------------------------------------------------------
System Clock Frequency (Hz)
If an initial starting value other than 0001His loaded into the Timer High and Low Byte
registers, use the ONE-SHOT Mode equation to determine the first PWM time-out period.
If TPOL bit is set to 0, the ratio of the PWM output high time to the total period is repre-
sented by:
Reload Value – PWM Value
--------------------------------------------------------------------
PWM Output High Time Ratio (%) =
100
Reload Value
If TPOL bit is set to 1, the ratio of the PWM output high time to the total period is repre-
sented by:
PWM Value
Reload Value
--------------------------------
PWM Output High Time Ratio (%) =
100
PWM DUAL OUTPUT Mode
In PWM DUAL OUTPUT Mode, the timer outputs a PWM output signal pair (basic
PWM signal and its complement) through two GPIO port pins. The timer input is the sys-
tem clock. The timer first counts up to 16-bit PWM match value stored in the timer PWM
High and Low Byte registers. When the timer count value matches the PWM value, the
timer output toggles. The timer continues counting until it reaches the reload value stored
in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001Hand counting resumes.
If the TPOL bit in the Timer Control Register is set to 1, the timer output signal begins as
a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The
timer output signal returns to a High (1) after the timer reaches the reload value and is
reset to 0001H.
If the TPOL bit in the Timer Control Register is set to 0, the timer output signal begins as
a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The
timer output signal returns to a Low (0) after the timer reaches the reload value and is reset
to 0001H.
The timer also generates a second PWM output signal: the timer output complement. The
timer output complement is the complement of the timer output PWM signal. A program-
mable deadband delay can be configured to time delay (0 to 128 system clock cycles)
PWM output transitions on these two pins from a Low to a High (inactive to active) to
ensure a time gap between the deassertion of one PWM output to the assertion of its com-
plement.
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Observe the following steps for configuring a timer for PWM DUAL OUTPUT Mode and
for initiating the PWM operation:
1. Write to the Timer Control Register to:
–
–
Disable the timer
Configure the timer for PWM DUAL OUTPUT Mode; setting the mode also
involves writing to TMODEHI bit in the TxCTL1 Register
–
–
Set the prescale value
Set the initial logic level (High or Low) and PWM High/Low transition for the
timer output alternate function
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001H). This write only affects the first pass in PWM Mode. After the first timer
reset in PWM Mode, counting always begins at the reset value of 0001H.
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the PWM Control Register to set the PWM deadband delay value. The dead-
band delay must be less than the duration of the positive phase of the PWM signal (as
defined by the PWM High and Low Byte registers). It must also be less than the dura-
tion of the negative phase of the PWM signal (as defined by the difference between
the PWM registers and the Timer Reload registers).
5. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM
period). The reload value must be greater than the PWM value.
6. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
7. Configure the associated GPIO port pin for the timer output and timer output comple-
ment alternate functions. The timer output complement function is shared with the
timer input function for both timers. Setting the timer mode to DUAL PWM will auto-
matically switch the function from timer-in to timer-out complement.
8. Write to the Timer Control Register to enable the timer and initiate counting.
The PWM period is represented by the following equation:
Reload Value Prescale
PWM Period (s) = ------------------------------------------------------------------------
System Clock Frequency (Hz)
If an initial starting value other than 0001His loaded into the Timer High and Low Byte
registers, the ONE-SHOT Mode equation determines the first PWM time-out period.
If TPOLis set to 0, the ratio of the PWM output high time to the total period is represented
by:
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Reload Value – PWM Value
--------------------------------------------------------------------
PWM Output High Time Ratio (%) =
100
Reload Value
If TPOLis set to 1, the ratio of the PWM output high time to the total period is represented
by:
PWM Value
Reload Value
--------------------------------
PWM Output High Time Ratio (%) =
100
CAPTURE Mode
In CAPTURE Mode, the current timer count value is recorded when the appropriate exter-
nal timer input transition occurs. The capture count value is written to the timer PWM
High and Low Byte registers. The timer input is the system clock. The TPOL bit in the
Timer Control Register determines if the capture occurs on a rising edge or a falling edge
of the timer input signal.
When the capture event occurs, an interrupt is generated and the timer continues counting.
The INPCAP bit in the TxCTL1 Register is set to indicate the timer interrupt because of an
input capture event.
The timer continues counting up to the 16-bit reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the reload value, the timer generates an inter-
rupt and continues counting. The INPCAP bit in the TxCTL1 Register clears, indicating
that the timer interrupt has not occurred because of an input capture event.
Observe the following steps for configuring a timer for CAPTURE Mode and initiating
the count:
1. Write to the Timer Control Register to:
–
–
–
–
Disable the timer
Configure the timer for CAPTURE Mode
Set the prescale value
Set the capture edge (rising or falling) for the timer input
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001H).
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. Clear the timer PWM High and Low Byte registers to 0000H. Clearing these registers
allows user software to determine if interrupts were generated either by a capture
event or by a reload. If the PWM High and Low Byte registers still contain 0000H
after the interrupt, the interrupt were generated by a reload.
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5. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input capture and Reload events. If appropriate, configure the timer interrupt to be
generated only at the input capture event or the reload event by setting the TICONFIG
field of the TxCTL1 Register.
6. Configure the associated GPIO port pin for the timer input alternate function.
7. Write to the Timer Control Register to enable the timer and initiate counting.
In CAPTURE Mode, the elapsed time between the timer start and the capture event can be
calculated using the following equation:
Capture Value – Start Value Prescale
Capture Elapsed Time (s) = --------------------------------------------------------------------------------------------------
System Clock Frequency (Hz)
CAPTURE RESTART Mode
In CAPTURE RESTART Mode, the current timer count value is recorded when the
acceptable external timer input transition occurs. The capture count value is written to the
timer PWM High and Low Byte registers. The timer input is the system clock. The TPOL
bit in the Timer Control Register determines whether the capture occurs on a rising edge
or a falling edge of the timer input signal. When the capture event occurs, an interrupt is
generated and the count value in the Timer High and Low Byte registers is reset to 0001H
and counting resumes. The INPCAP bit in the TxCTL1 Register is set to indicate that the
timer interrupt has been caused by an input capture event.
If no capture event occurs, the timer counts up to 16-bit compare value stored in the Timer
Reload High and Low Byte registers. Upon reaching the reload value, the timer generates
an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H
and counting resumes. The INPCAP bit in the TxCTL1 Register is cleared to indicate that
the timer interrupt has not been caused by an input capture event.
Observe the following steps for configuring a timer for CAPTURE RESTART Mode and
for initiating the count:
1. Write to the Timer Control Register to:
–
–
Disable the timer
Configure the timer for CAPTURE RESTART Mode; setting the mode also
involves writing to TMODEHI bit in the TxCTL1 Register
–
–
Set the prescale value
Set the capture edge (rising or falling) for the timer input
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001H).
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3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. Clear the timer PWM High and Low Byte registers to 0000H. This allows user soft-
ware to determine if interrupts are generated by either a capture event or a reload. If
the PWM High and Low Byte registers still contain 0000Hafter the interrupt, the
interrupt were generated by a reload.
5. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input capture and Reload events. The user can configure the timer interrupt to be gen-
erated only at the input capture event or the reload event by setting the TICONFIG
field of the TxCTL1 Register.
6. Configure the associated GPIO port pin for the timer input alternate function.
7. Write to the Timer Control Register to enable the timer and initiate counting.
In CAPTURE Mode, the elapsed time between the timer start and the capture event can be
calculated using the following equation:
Capture Value – Start Value Prescale
Capture Elapsed Time (s) = --------------------------------------------------------------------------------------------------
System Clock Frequency (Hz)
COMPARE Mode
In COMPARE Mode, the timer counts up to 16-bit maximum compare value stored in the
Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the compare value, the timer generates an interrupt and counting continues (the
timer value is not reset to 0001H). Additionally, if the timer output alternate function is
enabled, the timer output pin changes state (from Low to High or from High to Low) upon
compare.
If the timer reaches FFFFH, the timer resets to 0000Hand continues counting.
Observe the following steps for configuring a timer for COMPARE Mode and for initiat-
ing the count:
1. Write to the Timer Control Register to:
–
–
–
–
Disable the timer
Configure the timer for COMPARE Mode
Set the prescale value
Set the initial logic level (High or Low) for the timer output alternate function
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the compare value.
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4. Enable the timer interrupt and set the timer interrupt priority by writing to the relevant
interrupt registers.
5. If using the timer output function, configure the associated GPIO port pin for the timer
output alternate function.
6. Write to the Timer Control Register to enable the timer and initiate counting.
In COMPARE Mode, the system clock always provides the timer input. The compare time
can be calculated by the following equation:
Compare Value – Start Value Prescale
Compare Mode Time (s) = -----------------------------------------------------------------------------------------------------
System Clock Frequency (Hz)
GATED Mode
In GATED Mode, the timer counts only when the timer input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control Register. When the timer
input signal is asserted, counting begins. A timer interrupt is generated when the timer
input signal is deasserted or a timer reload occurs. To determine whether the timer input
signal deassertion generated the interrupt, read the associated GPIO input value and com-
pare to the value stored in the TPOL bit.
The timer counts up to the 16-bit reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. Upon reaching the reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001Hand counting resumes (assuming the timer input signal remains asserted).
Additionally, if the timer output alternate function is enabled, the timer output pin changes
state (from Low to High or from High to Low) at timer reset.
Observe the following steps for configuring a timer for GATED Mode and for initiating
the count:
1. Write to the Timer Control Register to:
–
–
–
Disable the timer
Configure the timer for GATED Mode
Set the prescale value
2. Write to the Timer High and Low Byte registers to set the starting count value. Writing
these registers only affects the first pass in GATED Mode. After the first timer reset in
GATED Mode, counting always begins at the reset value of 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. Enable the timer interrupt and set the timer interrupt priority by writing to the relevant
interrupt registers. By default, the timer interrupt is generated for both input deasser-
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tion and reload events. The user can configure the timer interrupt to be generated only
at the input deassertion event or the reload event by setting the TICONFIG field of the
TxCTL1 Register.
5. Configure the associated GPIO port pin for the timer input alternate function.
6. Write to the Timer Control Register to enable the timer.
7. Assert the timer input signal to initiate the counting.
CAPTURE/COMPARE Mode
In CAPTURE/COMPARE Mode, the timer begins counting on the first external timer
input transition. The acceptable transition (rising edge or falling edge) is set by the TPOL
bit in the Timer Control Register. The timer input is the system clock.
Every subsequent acceptable transition (after the first) of the timer input signal, captures
the current count value. The capture value is written to the timer PWM High and Low
Byte registers. When the capture event occurs, an interrupt is generated, the count value in
the Timer High and Low Byte registers is reset to 0001Hand the counting resumes. The
INPCAP bit in the TxCTL1 Register is set to indicate that the timer interrupt is caused by
an input capture event.
If no capture event occurs, the timer counts up to the 16-bit compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the compare value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001Hand counting resumes. The INPCAP bit in the TxCTL1 Register is cleared to indi-
cate that the timer interrupt has not been caused by an input capture event.
Observe the following steps for configuring a timer for CAPTURE/COMPARE Mode and
for initiating the count:
1. Write to the Timer Control Register to:
–
–
–
–
Disable the timer
Configure the timer for CAPTURE/COMPARE Mode.
Set the prescale value.
Set the capture edge (rising or falling) for the timer input.
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001H).
3. Write to the Timer Reload High and Low Byte registers to set the compare value.
4. Enable the timer interrupt and set the timer interrupt priority by writing to the relevant
interrupt registers.By default, the timer interrupt are generated for both input capture
and Reload events. The user can configure the timer interrupt to be generated only at
the input capture event or the reload event by setting TICONFIG field of the TxCTL1
Register.
5. Configure the associated GPIO port pin for the timer input alternate function.
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6. Write to the Timer Control Register to enable the timer.
7. Counting begins on the first appropriate transition of the timer input signal. No inter-
rupt is generated by the first edge.
In CAPTURE/COMPARE Mode, the elapsed time from timer start to capture event can be
calculated using the following equation:
Capture Value – Start Value Prescale
--------------------------------------------------------------------------------------------------
Capture Elapsed Time (s) =
System Clock Frequency (Hz)
Reading the Timer Count Values
The current count value in the timers can be read while counting (enabled). This capability
has no effect on Timer operation. When the timer is enabled and the Timer High Byte Reg-
ister is read, the contents of the timer low byte register are placed in a holding register. A
subsequent read from the timer low byte register returns the value in the holding register.
This operation allows accurate reads of the full 16-bit timer count value when enabled.
When the timers are not enabled, a read from the timer low byte register returns the actual
value in the counter.
Timer Pin Signal Operation
Timer output is a GPIO port pin alternate function. The timer output is toggled every time
the counter is reloaded.
The timer input can be used as a selectable counting source. It shares the same pin as the
complementary timer output. When selected by the GPIO alternate function registers, this
pin functions as a timer input in all modes except for the DUAL PWM OUTPUT Mode.
For this mode, no timer input is available.
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Timer Control Register Definitions
This section defines the features of the following Timer Control registers.
Timer 0–1 High and Low Byte Registers: see page 83
Timer Reload High and Low Byte Registers: see page 85
Timer 0–1 PWM High and Low Byte Registers: see page 86
Timer 0–1 Control Registers: see page 87
Timer 0–1 High and Low Byte Registers
The Timer 0–1 High and Low Byte (TxH and TxL) registers, shown in Tables 50 and 51,
contain the current 16-bit timer count value. When the timer is enabled, a read from TxH
causes the value in TxL to be stored in a temporary holding register. A read from TxL
always returns this temporary register content when the timer is enabled; however, when
the timer is disabled, a read from the TxL reads the TxL Register content directly.
Writing to the Timer High and Low Byte registers while the timer is enabled is not recom-
mended. There are no temporary holding registers available for write operations; there-
fore, simultaneous 16-bit writes are not possible. If either the timer High or Low Byte
registers are written during counting, the 8-bit written value is placed in the counter (High
or Low byte) at the next clock edge. The counter continues counting from the new value.
Table 50. Timer 0–1 High Byte Register (TxH)
Bit
7
6
5
4
3
2
1
0
Field
TH
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F00H, F08H
Table 51. Timer 0–1 Low Byte Register (TxL)
Bit
7
6
5
4
3
2
1
0
Field
TL
RESET
R/W
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F01H, F09H
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Bit
Description
[7:0]
TH, TL
Timer High and Low Bytes
These 2 bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value.
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Timer Reload High and Low Byte Registers
The Timer 0–1 Reload High and Low Byte (TxRH and TxRL) registers, shown in
Tables 52 and 53, store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the
Timer Reload High Byte Register are stored in a temporary holding register. When a write
to the Timer Reload Low Byte Register occurs, the temporary holding register value is
written to the Timer High Byte Register. This operation allows simultaneous updates of
the 16-bit timer reload value. In COMPARE Mode, the Timer Reload High and Low Byte
registers store the 16-bit compare value.
Table 52. Timer 0–1 Reload High Byte Register (TxRH)
Bit
7
6
5
4
3
2
1
0
Field
TRH
RESET
R/W
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F02H, F0AH
Table 53. Timer 0–1 Reload Low Byte Register (TxRL)
Bit
7
6
5
4
3
2
1
0
Field
TRL
RESET
R/W
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F03H, F0BH
Bit
Description
[7:0]
TRH, TRL
Timer Reload Register High and Low
These two bytes form the 16-bit reload value, {TRH[7:0], TRL[7:0]}. This value sets the max-
imum count value, which initiates a timer reload to 0001H. In COMPARE Mode, these two
bytes form the 16-bit compare value.
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Timer 0–1 PWM High and Low Byte Registers
The Timer 0–1 PWM High and Low Byte (TxPWMH and TxPWML) registers, shown in
Tables 54 and 55, control PWM operations. These registers also store the capture values
for the CAPTURE and CAPTURE/COMPARE modes.
Table 54. Timer 0–1 PWM High Byte Register (TxPWMH)
Bit
7
6
5
4
3
2
1
0
Field
PWMH
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F04H, F0CH
Table 55. Timer 0–1 PWM Low Byte Register (TxPWML)
Bit
7
6
5
4
3
2
1
0
Field
PWML
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F05H, F0DH
Bit
Description
[7:0]
Pulse Width Modulator High and Low Bytes
PWMH, These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the current
PWML
16-bit timer count. When a match occurs, the PWM output changes state. The PWM output
value is set by the TPOL bit in the Timer Control Register (TxCTL1).
The TxPWMH and TxPWML registers also store the 16-bit captured timer value when operat-
ing in capture or CAPTURE/COMPARE modes.
PS025113-1212
Timer Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
87
Timer 0–1 Control Registers
The Timer Control registers are 8-bit read/write registers that control the operation of their
associated counter/timers.
Time 0–1 Control Register 0
The Timer Control 0 (TxCTL0) and Timer Control 1 (TxCTL1) registers determine the
timer operating mode. These registers also include a programmable PWM deadband delay,
two bits to configure the timer interrupt definition, and a status bit to identify if the most
recent timer interrupt is caused by an input capture event.
Table 56. Timer 0–1 Control Register 0 (TxCTL0)
Bit
7
TMODEHI
0
6
5
4
Reserved
0
3
2
PWMD
0
1
0
INPCAP
0
Field
TICONFIG
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F06H, F0EH
Bit
Description
[7]
Timer Mode High Bit
TMODEHI This bit along with the TMODE field in the TxCTL1 Register determines the operating mode
of the timer. This is the most significant bit of the timer mode selection value. See the
TxCTL1 Register description on the next page for additional details.
[6:5]
Timer Interrupt Configuration
TICONFIG This field configures timer interrupt definition.
0x = Timer interrupt occurs on all of the defined reload, compare and input events.
10 = Timer interrupt occurs only on defined input capture/deassertion events.
11 = Timer interrupt occurs only on defined reload/compare events.
[4]
Reserved
This bit is reserved and must be programmed to 0.
[3:1]
PWMD
PWM Delay Value
This field is a programmable delay to control the number of system clock cycles delay
before the timer output and the timer output complement are forced to their Active state.
000 = No delay.
001 = 2 cycles delay.
010 = 4 cycles delay.
011 = 8 cycles delay.
100 = 16 cycles delay.
101 = 32 cycles delay.
110 = 64 cycles delay.
111 = 128 cycles delay.
PS025113-1212
Timer Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
88
Bit
Description (Continued)
Input Capture Event
[0]
INPCAP
This bit indicates whether the most recent timer interrupt is caused by a timer input capture
event.
0 = Previous timer interrupt is not caused by timer input capture event.
1 = Previous timer interrupt is caused by timer input capture event.
Timer 0–1 Control Register 1
The Timer 0–1 Control (TxCTL1) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
Table 57. Timer 0–1 Control Register 1 (TxCTL1)
Bit
7
6
TPOL
0
5
4
PRES
0
3
2
1
TMODE
0
0
Field
TEN
0
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F07H, F0FH
Bit
Description
[7]
TEN
Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
PS025113-1212
Timer Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
89
Bit
Description (Continued)
[6]
TPOL
Timer Input/Output Polarity
Operation of this bit is a function of the current operating mode of the timer.
ONE-SHOT Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented on timer reload.
CONTINUOUS Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled and reloaded, the timer output signal is complemented.
COUNTER Mode
If the timer is disabled, the timer output signal is set to the value of this bit. If the timer is
enabled the timer output signal is complemented after timer reload.
0 = Count occurs on the rising edge of the timer input signal.
1 = Count occurs on the falling edge of the timer input signal.
PWM SINGLE OUTPUT Mode
0 = Timer output is forced Low (0), when the timer is disabled. The timer output is forced High
(1) when the timer is enabled and the PWM count matches and the timer output is forced
Low (0) when the timer is enabled and reloaded.
1 = Timer output is forced High (1), when the timer is disabled. The timer output is forced
low(0), when the timer is enabled and the PWM count matches and forced High (1) when
the timer is enabled and reloaded.
CAPTURE Mode
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
COMPARE Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled and reloaded, the timer output signal is complemented.
GATED Mode
0 = Timer counts when the timer input signal is High (1) and interrupts are generated on the
falling edge of the timer input.
1 = Timer counts when the timer input signal is Low (0) and interrupts are generated on the ris-
ing edge of the timer input.
CAPTURE/COMPARE Mode
0 = Counting is started on the first rising edge of the timer input signal. The current count is
captured on subsequent rising edges of the timer input signal.
1 = Counting is started on the first falling edge of the timer input signal. The current count is
captured on subsequent falling edges of the timer input signal.
PS025113-1212
Timer Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
90
Bit
Description (Continued)
[6]
TPOL
(cont’d)
PWM DUAL OUTPUT Mode
0 = Timer output is forced Low (0) and timer output complement is forced High (1), when the
timer is disabled. When enabled and the PWM count matches, the timer output is forced
High (1) and forced Low (0) when enabled and reloaded. When enabled and the PWM
count matches, the timer output complement is forced Low (0) and forced High (1) when
enabled and reloaded.
1 = Timer output is forced High (1) and timer output complement is forced Low (0) when the
timer is disabled. When enabled and the PWM count matches, the timer output is forced
Low (0) and forced High (1) when enabled and reloaded.When enabled and the PWM
count matches, the timer output complement is forced High (1) and forced Low (0) when
enabled and reloaded. The PWMD field in the TxCTL0 register determines an optional
added delay on the assertion (Low to High) transition of both timer output and timer output
complement for deadband generation.
CAPTURE RESTART Mode
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
COMPARATOR COUNTER Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented on timer reload.
Caution: When the timer output alternate function TxOUT on a GPIO port pin is enabled,
TxOUT will change to whatever state the TPOL bit is in. The timer does not need to be enabled
for that to happen. Additionally, the port data direction sub register is not needed to be set to
output on TxOUT. Changing the TPOL bit when the timer is enabled and running does not
immediately change the polarity TxOUT.
[5:3]
PRES
Prescale Value
The timer input clock is divided by 2
PRES
, where PRES can be set from 0 to 7. The prescaler is
reset each time the timer is disabled. This reset ensures proper clock division each time the
timer is restarted.
000 = Divide by 1.
001 = Divide by 2.
010 = Divide by 4.
011 = Divide by 8.
100 = Divide by 16.
101 = Divide by 32.
110 = Divide by 64.
111 = Divide by 128.
PS025113-1212
Timer Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
91
Bit
Description (Continued)
Timer Mode
[2:0]
TMODE This field along with the TMODEHI bit in TxCTL0 register determines the operating mode of
the timer. TMODEHI is the most significant bit of the timer mode selection value.
0000 = ONE-SHOT Mode.
0001 = CONTINUOUS Mode.
0010 = COUNTER Mode.
0011 = PWM SINGLE OUTPUT Mode.
0100 = CAPTURE Mode.
0101 = COMPARE Mode.
0110 = GATED Mode.
0111 = CAPTURE/COMPARE Mode.
1000 = PWM DUAL OUTPUT Mode.
1001 = CAPTURE RESTART Mode.
1010 = COMPARATOR COUNTER Mode.
PS025113-1212
Timer Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
92
Watchdog Timer
The Watchdog Timer (WDT) protects from corrupted or unreliable software, power faults
and other system-level problems which can place the Z8 Encore! F0830 Series devices
into unsuitable operating states. The features of the Watchdog Timer include:
•
•
•
On-chip RC oscillator
A selectable time-out response: reset or interrupt
24-bit programmable time-out value
Operation
The Watchdog Timer is a retriggerable one-shot timer that resets or interrupts the Z8
Encore! F0830 Series devices when the WDT reaches its terminal count. The WDT uses a
dedicated on-chip RC oscillator as its clock source. The WDT operates only in two modes:
ON and OFF. Once enabled, it always counts and must be refreshed to prevent a time-out.
Perform an enable by executing the WDT instruction or by setting the WDT_AO Flash
option bit. The WDT_AO bit forces the WDT to operate immediately on reset, even if a
WDT instruction has not been executed.
The Watchdog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in
the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is
calculated using the following equation:
WDT Reload Value
-----------------------------------------------
WDT Time-out Period (ms) =
10
where the WDT reload value is the 24-bit decimal value provided by {WDTU[7:0],
WDTH[7:0], WDTL[7:0]} and the typical Watchdog Timer RC oscillator frequency is
10KHz. The Watchdog Timer cannot be refreshed after it reaches 000002H. The WDT
reload value must not be set to values below 000004H. Table 58 provides information
about approximate time-out delays for the minimum and maximum WDT reload values.
Table 58. Watchdog Timer Approximate Time-Out Delays
Approximate Time-Out Delay
(with 10KHz Typical WDT Oscillator Frequency)
WDT Reload Value WDT Reload Value
(Hex)
000004
000400
FFFFFF
(Decimal)
Typical
400µs
Description
4
Minimum time-out delay
Default time-out delay
Maximum time-out delay
1024
102ms
16,777,215
28 minutes
PS025113-1212
Watchdog Timer
Z8 Encore!® F0830 Series
Product Specification
93
Watchdog Timer Refresh
Upon first enable, the Watchdog Timer is loaded with the value in the Watchdog Timer
Reload registers. The Watchdog Timer counts down to 000000Hunless a WDT instruc-
tion is executed by the eZ8 CPU. Execution of the WDT instruction causes the downcoun-
ter to be reloaded with the WDT reload value stored in the Watchdog Timer Reload
registers. Counting resumes following the Reload operation.
When the Z8 Encore! F0830 Series devices are operating in DEBUG Mode (using the On-
Chip Debugger), the Watchdog Timer must be continuously refreshed to prevent any
WDT time-outs.
Watchdog Timer Time-Out Response
The Watchdog Timer times out when the counter reaches 000000H. A time-out of the
Watchdog Timer generates either an interrupt or a system reset. The WDT_RES Flash
option bit determines the time-out response of the Watchdog Timer. See the Flash Option
Bits chapter on page 124 for information about programming the WDT_RES Flash option
bit.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues
an interrupt request to the Interrupt Controller and sets the WDT status bit in the Reset
Status Register. If interrupts are enabled, the eZ8 CPU responds to the interrupt request by
fetching the Watchdog Timer interrupt vector and executing code from the vector address.
After time-out and interrupt generation, the Watchdog Timer counter resets to its maxi-
mum value of FFFFFHand continues counting. The Watchdog Timer counter will not
automatically return to its reload value.
The Reset Status Register (see Table 12 on page 29) must be read before clearing the
WDT interrupt. This read clears the WDT time-out flag and prevents further WDT inter-
rupts occurring immediately.
WDT Interrupt in STOP Mode
If configured to generate an interrupt when a time-out occurs and the Z8 Encore! F0830
Series devices are in STOP Mode, the Watchdog Timer automatically initiates a Stop
Mode Recovery and generates an interrupt request. Both the WDT status bit and the STOP
bit in the Watchdog Timer Control Register are set to 1 following a WDT time-out in
STOP Mode. See the Reset and Stop Mode Recovery chapter on page 21 for more infor-
mation about Stop Mode Recovery operations.
If interrupts are enabled, following completion of the Stop Mode Recovery, the eZ8 CPU
responds to the interrupt request by fetching the Watchdog Timer interrupt vector and exe-
cutes the code from the vector address.
PS025113-1212
Operation
Z8 Encore!® F0830 Series
Product Specification
94
WDT Reset in Normal Operation
If configured to generate a reset when a time-out occurs, the Watchdog Timer forces the
device into the System Reset state. The WDT status bit in the Watchdog Timer Control
Register is set to 1. See the Reset and Stop Mode Recovery chapter on page 21 for more
information about system reset operations.
WDT Reset in STOP Mode
If configured to generate a reset when a time-out occurs and the device is in STOP Mode,
the Watchdog Timer initiates a Stop Mode Recovery. Both the WDT status bit and the
STOP bit in the Watchdog Timer Control Register are set to 1 following WDT time-out in
STOP Mode. See the Reset and Stop Mode Recovery chapter on page 21 for more infor-
mation about Stop Mode Recovery operations.
Watchdog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watchdog Timer (WDTCTL) Control Register
address, unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH and
WDTL) to allow changes to the time-out period. These write operations to the WDTCTL
Register address produce no effect on the bits in the WDTCTL Register. The locking
mechanism prevents spurious writes to the reload registers.
The following sequence is required to unlock the Watchdog Timer Reload Byte registers
(WDTU, WDTH and WDTL) for write access:
1. Write 55Hto the Watchdog Timer Control Register (WDTCTL).
2. Write AAHto the Watchdog Timer Control Register (WDTCTL).
3. Write the Watchdog Timer Reload Upper Byte Register (WDTU).
4. Write the Watchdog Timer Reload High Byte Register (WDTH).
5. Write the Watchdog Timer Reload Low Byte Register (WDTL).
All three Watchdog Timer Reload registers must be written in the order listed above.
There must be no other register writes between each of these operations. If a register write
occurs, the lock state machine resets and no further writes can occur unless the sequence is
restarted. The value in the Watchdog Timer Reload registers is loaded into the counter
when the Watchdog Timer is first enabled and every time a WDT instruction is executed.
PS025113-1212
Operation
Z8 Encore!® F0830 Series
Product Specification
95
Watchdog Timer Control Register Definitions
This section defines the features of the following Watchdog Timer Control registers.
Watchdog Timer Control Register (WDTCTL): see page 95
Watchdog Timer Reload Low Byte Register (WDTL): see page 97
Watchdog Timer Reload Upper Byte Register (WDTU): see page 96
Watchdog Timer Reload High Byte Register (WDTH): see page 96
Watchdog Timer Control Register
The Watchdog Timer Control (WDTCTL) Register is a write-only control register. Writ-
ing the unlock sequence: 55H, AAHto the WDTCTL Register address unlocks the three
Watchdog Timer Reload Byte registers (WDTU, WDTH and WDTL) to allow changes to
the time-out period. These write operations to the WDTCTL Register address have no
effect on the bits in the WDTCTL Register. The locking mechanism prevents spurious
writes to the reload registers.
This register address is shared with the read-only Reset Status Register.
Table 59. Watchdog Timer Control Register (WDTCTL)
Bit
7
6
5
4
3
2
1
0
Field
WDTUNLK
RESET
R/W
X
X
X
X
X
X
X
X
W
W
W
W
W
W
W
W
Address
FF0H
Bit
Description
[7:0]
Watchdog Timer Unlock
WDTUNLK The user software must write the correct unlocking sequence to this register before it is
allowed to modify the contents of the Watchdog Timer Reload registers.
PS025113-1212
Watchdog Timer Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
96
Watchdog Timer Reload Upper, High and Low Byte Registers
The Watchdog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) regis-
ters, shown in Tables 60 through 62, form the 24-bit reload value that is loaded into the
Watchdog Timer when a WDT instruction executes. This 24-bit value ranges across bits
[23:0] to encompass the three bytes {WDTU[7:0], WDTH[7:0], WDTL[7:0]}. Writing to
these registers sets the appropriate reload value; reading from these registers returns the
current Watchdog Timer count value.
The 24-bit WDT reload value must not be set to a value less than 000004H.
Caution:
Table 60. Watchdog Timer Reload Upper Byte Register (WDTU)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
WDTU
FF1H
0
0
0
0
0
0
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
Note: *A read returns the current WDT count value; a write sets the appropriate reload value.
Bit
Description
[7:0]
WDTU
WDT Reload Upper Byte
Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value.
Table 61. Watchdog Timer Reload High Byte Register (WDTH)
Bit
7
6
5
4
3
2
1
0
Field
WDTH
FF2H
RESET
R/W
0
0
0
0
0
1
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
Note: *A read returns the current WDT count value; a write sets the appropriate reload value.
Bit
Description
[7:0]
WDTH
WDT Reload High Byte
Middle byte, bits[15:8] of the 24-bit WDT reload value.
PS025113-1212
Watchdog Timer Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
97
Table 62. Watchdog Timer Reload Low Byte Register (WDTL)
Bit
7
6
5
4
3
2
1
0
Field
WDTL
RESET
R/W
0
0
0
0
0
0
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
FF3H
Note: *A read returns the current WDT count value; a write sets the appropriate reload value.
Bit
Description
[7:0]
WDTL
WDT Reload Low
Least significant byte (LSB), bits[7:0] of the 24-bit WDT reload value.
PS025113-1212
Watchdog Timer Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
98
Analog-to-Digital Converter
The Z8 Encore! MCU includes an eight-channel Successive Approximation Register
(SAR) Analog-to-Digital Converter (ADC). The ADC converts an analog input signal to a
10-bit binary number. The features of the SAR ADC include:
•
•
•
•
•
•
•
Eight analog input sources multiplexed with general purpose I/O ports
Fast conversion time, less than 11.9µs
Programmable timing controls
Interrupt on conversion complete
Internal voltage reference generator
Ability to select external reference voltage
When configuring an ADC using external VREF, PB5 is used as VREF in the 28-pin
package
Architecture
The ADC architecture, displayed in Figure 11, consists of an 8-input multiplexer, sample-
and-hold amplifier and 10-bit SAR ADC. The ADC digitizes the signal on a selected
channel and stores the digitized data in the ADC data registers. In an environment with
high electrical noise, an external RC filter must be added at the input pins to reduce high-
frequency noise.
TCONV = TS/H + TCON
TCONV = TS + TH + 13 * SCLK * 16
where:
SCLK = System Clock
TCONV = Total conversion time
TS = Sample time (SCLK * ADCST)
TCON = Conversion time (13 * SCLK * 16)
TH = Hold time (SCLK * ADCSST)
DIV = 16 (fixed to divide by 16 for F0830 Series products)
Example: For an F0830 Series MCU running @ 20MHz:
TCONV = 1µs + 0.5µs + 13 * SCLK * DIV
TCONV = 1µs + 0.5µs + 13 * (1/20MHz) * 16 = 11.9µs
PS025113-1212
Analog-to-Digital Converter
Z8 Encore!® F0830 Series
Product Specification
99
REFEN
Sel 28 Package
Internal Voltage
Reference Generator
V
RBUF
REF
VR2
Analog Input
Multiplexer
Analog-to-Digital
Converter
ANA0
ANA1
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
Reference Input
10
Data
Output
Sample-and-Hold
Amplifier
Analog Input
BUSY
ADCLK
ANAIN[2:0]
ADCEN
START
SAMPLE/HOLD
Figure 11. Analog-to-Digital Converter Block Diagram
Operation
The ADC converts the analog input, ANAX, to a 10-bit digital representation. The equa-
tion for calculating the digital value is represented by:
ADCOutput = 1024 ANA V
REF
x
Assuming zero gain and offset errors, any voltage outside the ADC input limits of AVSS
and VREF returns all 0s or 1s, respectively. A new conversion can be initiated by a soft-
ware to the ADC Control Register’s start bit.
Initiating a new conversion, stops any conversion currently in progress and begins a new
conversion. To avoid disrupting a conversion already in progress, the START bit can be
read to determine ADC operation status (busy or available).
PS025113-1212
Operation
Z8 Encore!® F0830 Series
Product Specification
100
ADC Timing
Each ADC measurement consists of three phases:
1. Input sampling (programmable, minimum of 1.0µs)
2. Sample-and-hold amplifier settling (programmable, minimum of 0.5µs)
3. Conversion is 13 ADCLK cycles
Figures 12 and 13 display the timing of an ADC conversion.
conversion period
START
1.0µs min
sample period
Programable
settling period
SAMPLE/HOLD
BUSY
13 clocks
convert period
Figure 12. ADC Timing Diagram
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
ADC Clock
BUSY
13 clocks
convert period
Figure 13. ADC Convert Timing
PS025113-1212
Operation
Z8 Encore!® F0830 Series
Product Specification
101
ADC Interrupt
The ADC can generate an interrupt request when a conversion has been completed. An
interrupt request that is pending when the ADC is disabled is not cleared automatically.
Reference Buffer
The reference buffer, RBUF, supplies the reference voltage for the ADC. When enabled,
the internal voltage reference generator supplies the ADC. When RBUF is disabled, the
ADC must have the reference voltage supplied externally through the VREF pin in 28-pin
package. RBUF is controlled by the REFENbit in the ADC Control Register.
Internal Voltage Reference Generator
The internal voltage reference generator provides the voltage VR2, for the RBUF. VR2 is 2V.
Calibration and Compensation
A user can perform calibration and store the values into Flash or the user code can perform
a manual offset calibration. There is no provision for manual gain calibration.
ADC Control Register Definitions
The ADC Control registers are defined in this section.
PS025113-1212
ADC Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
102
ADC Control Register 0
The ADC Control 0 Register, shown in Table 63, initiates an A/D conversion and provides
ADC status information.
Table 63. ADC Control Register 0 (ADCCTL0)
Bit
7
START
0
6
5
4
3
2
1
ANAIN[2:0]
0
0
Field
Reserved REFEN
ADCEN Reserved
RESET
R/W
0
0
0
0
0
0
R/W1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F70h
Bit
Description
[7]
START
ADC Start/Busy
0 = Writing to 0 has no effect; reading a 0 indicates that the ADC is available to begin a conver-
sion.
1 = Writing to 1 starts a conversion; reading a 1 indicates that a conversion is currently in prog-
ress.
[6]
Reserved
This bit is reserved and must be programmed to 0.
[5]
Reference Enable
REFEN 0 = Internal reference voltage is disabled allowing an external reference voltage to be used by
the ADC.
1 = Internal reference voltage for the ADC is enabled. The internal reference voltage can be
measured on the V
pin.
REF
[4]
ADC Enable
ADCEN 0 = ADC is disabled for low power operation.
1 = ADC is enabled for normal use.
[3]
Reserved
This bit is reserved and must be programmed to 0.
[2:0]
ANAIN
Analog Input Select
000 = ANA0 input is selected for analog to digital conversion.
001 = ANA1 input is selected for analog to digital conversion.
010 = ANA2 input is selected for analog to digital conversion.
011 = ANA3 input is selected for analog to digital conversion.
100 = ANA4 input is selected for analog to digital conversion.
101 = ANA5 input is selected for analog to digital conversion.
110 = ANA6 input is selected for analog to digital conversion.
111 = ANA7 input is selected for analog to digital conversion.
PS025113-1212
ADC Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
103
ADC Data High Byte Register
The ADC Data High Byte Register, listed in Table 64, contains the upper eight bits of the
ADC output. Access to the ADC Data High Byte Register is read-only. Reading the ADC
Data High Byte Register latches data in the ADC Low Bits Register.
Table 64. ADC Data High Byte Register (ADCD_H)
Bit
7
6
5
4
3
2
1
0
Field
ADCDH
RESET
R/W
X
R
Address
F72H
Bit
Description
[7:0]
ADC High Byte
ADCDH 00h–FFh = The last conversion output is held in the data registers until the next ADC conver-
sion is completed.
ADC Data Low Bits Register
The ADC Data Low Bits Register, shown in Table 65, contains the lower bits of the ADC
output. Access to the ADC Data Low Bits Register is read-only. Reading the ADC Data
High Byte Register latches lower bits of the ADC in the ADC Data Low Bits Register.
Table 65. ADC Data Low Bits Register (ADCD_L)
Bit
7
6
5
4
3
2
1
0
Field
ADCDL
Reserved
RESET
R/W
X
R
X
R
Address
F73H
Bit
Description
[7:6]
ADC Low Bits
ADCDL 00–11b = These bits are the two least-significant bits of the 10-bit ADC output. These bits are
undefined after a reset. The low bits are latched into this register whenever the ADC Data High
Byte Register is read.
[5:0]
Reserved
These bits are reserved and must be programmed to 000000.
PS025113-1212
ADC Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
104
Sample Settling Time Register
The Sample Settling Time Register, shown in Table 66, is used to program a delay after
the SAMPLE/HOLD signal is asserted and before the START signal is asserted; an ADC
conversion then begins. The number of clock cycles required for settling will vary from
system to system depending on the system clock period used. The system designer should
program this register to contain the number of clocks required to meet a 0.5µs minimum
settling time.
Table 66. Sample Settling Time (ADCSST)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
SST
R/W
RESET
R/W
0
1
1
1
1
R
Address
F74H
Bit
Description
Reserved
[7:4]
These bits are reserved and must be programmed to 0000.
[3:0]
0h–Fh = Sample settling time in number of system clock periods to meet 0.5 µs minimum.
SST
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ADC Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
105
Sample Time Register
The Sample Time Register, shown in Table 67, is used to program the length of active time
for a sample after a conversion has begun by setting the START bit in the ADC Control
Register. The number of system clock cycles required for the sample time varies from sys-
tem to system, depending on the clock period used. The system designer should program
this register to contain the number of system clocks required to meet a 1µs minimum sam-
ple time.
Table 67. Sample Time (ADCST)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
ST
RESET
R/W
0
1
1
1
1
1
1
R/W
R/W
Address
F75H
Bit
Description
Reserved
[7:6]
These bits are reserved and must be programmed to 00.
[5:0]
0h–Fh = Sample-hold time in number of system clock periods to meet 1 µs minimum.
ST
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ADC Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
106
Comparator
The Z8 Encore! F0830 Series devices feature a general purpose comparator that compares
two analog input signals. A GPIO (CINP) pin provides the positive comparator input. The
negative input (CINN) can be taken from either an external GPIO pin or from an internal
reference. The output is available as an interrupt source or can be routed to an external pin
using the GPIO multiplex. The comparator includes the following features:
•
•
Positive input is connected to a GPIO pin
Negative input can be connected to either a GPIO pin or a programmable internal ref-
erence
•
Output can be either an interrupt source or an output to an external pin
Operation
One of the comparator inputs can be connected to an internal reference that is a user-
selectable reference and is user-programmable with 200mV resolution.
The comparator can be powered down to save supply current. For details, see the Power
Control Register 0 section on page 31.
As a result of the propagation delay of the comparator, Zilog does not recommend en-
abling the comparator without first disabling interrupts and waiting for the comparator
output to settle. This delay prevents spurious interrupts after comparator enabling.
Caution:
The following example shows how to safely enable the comparator:
di
ld cmp0,r0; load some new configuration
nop
nop
; wait for output to settle
clr irq0 ; clear any spurious interrupts pending
ei
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Product Specification
107
Comparator Control Register Definitions
The Comparator Control Register (CMP0) configures the comparator inputs and sets the
value of the internal voltage reference. The GPIO pin is always used as positive compara-
tor input.
Table 68. Comparator Control Register (CMP0)
Bit
7
6
5
4
3
2
1
0
Field
Reserved INNSEL
REFLVL
Reserved
RESET
R/W
0
0
0
1
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F90H
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6]
Signal Select for Negative Input
INNSEL 0 = internal reference disabled, GPIO pin used as negative comparator input.
1 = internal reference enabled as negative comparator input.
[5:2]
Internal Reference Voltage Level
REFLVL This reference is independent of the ADC voltage reference.
0000 = 0.0V.
0001 = 0.2V.
0010 = 0.4V.
0011 = 0.6V.
0100 = 0.8V.
0101 = 1.0V (Default).
0110 = 1.2V.
0111 = 1.4V.
1000 = 1.6V.
1001 = 1.8V.
1010–1111 = Reserved.
[1:0]
Reserved
These bits are reserved and must be programmed to 00.
PS025113-1212
Comparator Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
108
Flash Memory
The products in the Z8 Encore! F0830 Series features either 1KB (1024 bytes with
NVDS), 2KB (2048 bytes with NVDS), 4KB (4096 bytes with NVDS), 8KB (8192 bytes
with NVDS) or 12KB (12288 bytes with no NVDS) of nonvolatile Flash memory with
read/write/erase capability. Flash memory can be programmed and erased in-circuit by
either user code or through the On-Chip Debugger.
The Flash memory array is arranged in pages with 512 bytes per page. The 512-byte page
is the minimum Flash block size that can be erased. Each page is divided into eight rows
of 64 bytes.
For program/data protection, Flash memory is also divided into sectors. In the Z8 Encore!
F0830 Series, each sector maps to one page (for 1KB, 2KB and 4KB devices), two pages
(8KB device) or three pages (12KB device).
The first two bytes of Flash program memory is used as Flash option bits. For more infor-
mation, see the Flash Option Bits chapter on page 124.
Table 69 lists the Flash memory configuration for each device in the Z8 Encore! F0830
Series. Figures 14 through 18 display the memory arrangements for each Flash memory
size.
Table 69. Z8 Encore! F0830 Series Flash Memory Configuration
Program
Flash Size
KB (Bytes)
Memory
Addresses
Flash Sector
Size (bytes)
Part Number
Z8F123x
Z8F083x
Z8F043x
Z8F023x
Z8F013x
Flash Pages
12 (12,288)
8 (8196)
4 (4096)
2 (2048)
1 (1024)
24
16
8
0000H–2FFFH
0000H–1FFFH
0000H–0FFFH
0000H–07FFH
0000H–03FFH
1536
1024
512
4
512
2
512
03FFH
03FFH
Sector 1
Sector 0
Page 1
Page 0
0200H
01FFH
0200H
01FFh
0000H
0000H
Figure 14. 1K Flash with NVDS
PS025113-1212
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Z8 Encore!® F0830 Series
Product Specification
109
07FFH
07FFH
Sector 3
Sector 2
Page 3
0600H
05FFH
0600H
05FFH
Page 2
Page 1
Page 0
0400H
03FFH
0400H
03FFH
Sector 1
Sector 0
0200H
01FFH
0200H
01FFH
0000H
0000H
Figure 15. 2K Flash with NVDS
0FFFH
0FFFH
Page 7
Sector 7
0E00H
0DFFH
0E00H
0DFFH
Page 6
Page 5
Sector 6
Sector 5
0C00H
0BFFH
0C00H
0BFFH
0A00H
09FFH
0A00H
09FFH
Page 4
Page 3
Sector 4
Sector 3
0800H
07FFH
0800H
07FFH
0600H
05FFH
0600H
05FFH
Page 2
Sector 2
0400H
03FFH
0400H
03FFH
Page 1
Page 0
Sector 1
Sector 0
0200H
01FFH
0200H
01FFH
0000H
0000H
Figure 16. 4K Flash with NVDS
PS025113-1212
Flash Memory
Z8 Encore!® F0830 Series
Product Specification
110
1FFFH
1E00H
Page 15
1FFFH
1DFFH
1C00H
Page 14
Sector 7
1C00H
18FFH
1BFFH
1A00H
Page 13
19FFH
Page 12
Sector 6
Sector 5
1800H
17FFH
1800H
17FFH
Page 11
1600H
15FFH
1400H
13FFH
1200H
11FFH
1C00H
0FFFH
0E00H
0DFFH
0C00H
0BFFH
0A00H
09FFH
0800H
07FFH
0600H
05FFH
0400H
03FFH
0200H
0100H
0000H
Page 10
Page 9
Page 8
Page 7
1400H
13FFH
Sector 4
Sector 3
1C00H
0FFFH
Page 6
Page 5
Page 4
0C00H
0BFFH
Sector 2
0800H
07FFH
Page 3
Page 2
Page 1
Sector 1
Sector 0
0400H
03FFH
Page 0
0000H
Figure 17. 8K Flash with NVDS
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Z8 Encore!® F0830 Series
Product Specification
111
2FFFH
2FFFH
2E00H
Page 23
Sector 7
Sector 6
2A00H
29FFH
2DFFH
2C00H
Page 22
Page 21
Page 20
2BFFH
2A00H
1600H
23FFH
Sector 5
Sector 4
Sector 3
Sector 2
1E00H
1DFFH
1800H
17FFH
1200H
11FFH
05FFH
0400H
0C00H
0BFFH
Page 2
Page 1
Page 0
Sector 1
Sector 0
03FFH
0200H
0600H
05FFH
01FFH
0000H
0000H
Figure 18. 12K Flash without NVDS
Data Memory Address Space
The Flash information area, including Zilog Flash option bits, are located in the data mem-
ory address space. The Z8 Encore! MCU is configured by these proprietary Flash option
bits to prevent the user from writing to the eZ8 CPU data memory address space.
Flash Information Area
The Flash information area is physically separate from program memory and is mapped to
the address range FE00Hto FE7FH. Not all of these addresses are user-accessible. Factory
trim values for the VBO, Internal Precision Oscillator and factory calibration data for the
ADC are stored here.
Table 70 describes the Flash information area. This 128-byte information area is accessed
by setting the bit 7 of the Flash Page Select Register to 1. When access is enabled, the
PS025113-1212
Data Memory Address Space
Z8 Encore!® F0830 Series
Product Specification
112
Flash information area is mapped into program memory and overlays the 128 bytes in the
address range FE00Hto FE7FH. When the information area access is enabled, all reads
from these program memory addresses return the information area data rather than the
program memory data. Access to the Flash information area is read-only.
The trim bits are handled differently than the other Zilog Flash option bits. The trim bits
are the hybrid of the user option bits and the standard Zilog option bits. These trim bits
must be user-accessible for reading at all times using external registers regardless of the
state of bit 7 in the Flash Page Select Register. Writes to the trim space change the value of
the Option Bit Holding Register but do not affect the Flash bits, which remain as read-
only.
Table 70. Z8F083 Flash Memory Area Map
Program Memory
Address (Hex)
FE00–FE3F
FE40–FE53
Function
Zilog option bits
Part number
20-character ASCII alphanumeric code
Left justified and filled with FH
FE54–FE5F
FE60–FE7F
Reserved
Reserved
Operation
The Flash Controller programs and erases Flash memory. The Flash Controller provides
the proper Flash controls and timing for byte programming, page erase and mass erase of
Flash memory.
The Flash Controller contains several protection mechanisms to prevent accidental pro-
gramming or erasure. These mechanism operate on the page, sector and full-memory lev-
els.
The flowchart in Figure 19 display basic Flash Controller operation. The following sub-
sections provide details about the various operations (Lock, Unlock, Byte Programming,
Page Protect, Page Unprotect, Page Select Page Erase and Mass Erase) displayed in
Figure 19.
PS025113-1212
Operation
Z8 Encore!® F0830 Series
Product Specification
113
Reset
Lock State 0
Write Page
Select Register
Write FCTL
No
73H
Yes
Lock State 1
Write FCTL
Writes to Page Select
Register in Lock State 1
result in a return to
Lock State 0
No
8CH
Yes
Write Page
Select Register
No
Page Select
values match?
Yes
Yes
Page in
Protected Sector?
Byte Program
Write FCTL
No
Page
Yes
Unlocked
95H
No
Page Erase
Program/Erase
Enabled
Figure 19. Flash Controller Operation Flow Chart
PS025113-1212
Operation
Z8 Encore!® F0830 Series
Product Specification
114
Flash Operation Timing Using the Flash Frequency Registers
Before performing either a Program or Erase operation on Flash memory, the user must
first configure the Flash Frequency High and Low Byte registers. The Flash frequency
registers allow programming and erasing of the Flash with system clock frequencies rang-
ing from 10kHz to 20MHz.
The Flash Frequency High and Low Byte registers combine to form a 16-bit value, FFREQ,
to control the timing for Flash Program and Erase operations. The 16-bit binary Flash fre-
quency value must contain the system clock frequency (in kHz). This value is calculated
using the following equation:
System Clock Frequency (Hz)
------------------------------------------------------------------------
FFREQ[15:0] =
1000
Flash programming and erasure are not supported for system clock frequencies below
10kHz or above 20MHz. The Flash Frequency High and Low Byte registers must be
loaded with the correct value to ensure operation of the Z8 Encore! F0830 Series devices.
Caution:
Flash Code Protection Against External Access
The user code contained within Flash memory can be protected against external access by
using the On-Chip Debugger. Programming the FRP Flash option bit prevents reading of
the user code using the On-Chip Debugger. For more information, see the Flash Option
Bits chapter on page 124 and the On-Chip Debugger chapter on page 139.
Flash Code Protection Against Accidental Program and
Erasure
The Z8 Encore! F0830 Series provides several levels of protection against accidental pro-
gram and erasure of the Flash memory contents. This protection is provided by a combina-
tion of the Flash option bits, the register locking mechanism, the page select redundancy
and the sector level protection control of the Flash Controller.
Flash Code Protection Using the Flash Option Bits
The FHSWP and FWP Flash option bits combine to provide three levels of Flash program
memory protection, as listed in Table 71. See the Flash Option Bits chapter on page 124
for more information.
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Operation
Z8 Encore!® F0830 Series
Product Specification
115
Table 71. Flash Code Protection using the Flash Option Bits
FWP Flash Code Protection Description
FHSWP
0
0
Programming and erasing disabled for all Flash program memory. In user code pro-
gramming, page erase and mass erase are all disabled. Mass erase is available
through the On-Chip Debugger.
0 or 1
1
Programming, page erase and mass erase are enabled for all of the Flash program
memory.
At reset, the Flash Controller is locked to prevent accidental program or erasure of Flash
memory. To program or erase Flash memory, first write the target page to the page select
register. Unlock the Flash Controller by making two consecutive writes to the Flash Con-
trol Register with the values 73Hand 8CH, sequentially. The page select register must be
rewritten with the same page previously stored there. If the two page select writes do not
match, the controller reverts to a Locked state. If the two writes match, the selected page
becomes active. See Figure 19 for details.
After unlocking a specific page, you can enable either page program or erase. Writing the
value 95Hcauses a page erase only if the active page resides in a sector that is not pro-
tected. Any other value written to the Flash Control Register locks the Flash Controller.
Mass erase is not allowed in the user code, but is allowed through the debug port.
After unlocking a specific page, the user can also write to any byte on that page. After a
byte is written, the page remains unlocked, allowing for subsequent writes to other bytes
on the same page. Further writes to the Flash Control Register causes the active page to
revert to a Locked state.
Sector Based Flash Protection
The final protection mechanism is implemented on a per-sector basis. The Flash memories
of Z8 Encore! devices are divided into maximum number of eight sectors. A sector is one-
eighth of the total size of Flash memory, unless this value is smaller than the page size, in
which case the sector and page sizes are equal. On Z8 Encore! F0830 Series devices, the
sector size is varied according to the Z8 Encore! F0830 Series Flash Memory Configura-
tion shown in Table 69 on page 108 and in Figures 14 through 18, which follow the table
The Flash Sector Protect Register can be configured to prevent sectors from being pro-
grammed or erased. After a sector is protected, it cannot be unprotected by user code. The
Flash Sector Protect Register is cleared after reset and any previously written protection
values is lost. User code must write this register in their initialization routine if they want
to enable sector protection.
The Flash Sector Protect Register shares its Register File address with the Page Select
Register. The Flash Sector Protect Register is accessed by writing the Flash Control Regis-
ter with 5EH. After the Flash Sector Protect Register is selected, it can be accessed at the
Page Select Register address. When user code writes the Flash Sector Protect Register,
PS025113-1212
Operation
Z8 Encore!® F0830 Series
Product Specification
116
bits can only be set to 1. Thus, sectors can be protected, but not unprotected, via register
write operations. Writing a value other than 5EHto the Flash Control Register deselects
the Flash Sector Protect Register and reenables access to the Page Select Register.
Observe the following procedure to setup the Flash Sector Protect Register from user
code:
1. Write 00Hto the Flash Control Register to reset the Flash Controller.
2. Write 5EHto the Flash Control Register to select the Flash Sector Protect Register.
3. Read and/or write the Flash Sector Protect Register which is now at Register File
address FF9H.
4. Write 00Hto the Flash Control Register to return the Flash Controller to its reset state.
The Sector Protect Register is initialized to 0 on reset, putting each sector into an unpro-
tected state. When a bit in the Sector Protect Register is written to 1, the corresponding
sector can no longer be written or erased. After setting a bit in the Sector Protect Register,
the bit cannot be cleared by the user.
Byte Programming
Flash memory is enabled for byte programming after unlocking the Flash Controller and
successfully enabling either mass erase or page erase. When the Flash Controller is
unlocked and mass erase is successfully enabled, all of the program memory locations are
available for byte programming. In contrast, when the Flash Controller is unlocked and
page erase is successfully enabled, only the locations of the selected page are available for
byte programming. An erased Flash byte contains all 1’s (FFH). The programming opera-
tion can only be used to change bits from 1 to 0. To change a Flash bit (or multiple bits)
from 0 to 1 requires execution of either the page erase or mass erase commands.
Byte programming can be accomplished using the On-Chip Debugger’s write memory
command or eZ8 CPU execution of the LDC or LDCI instructions. Refer to the eZ8 CPU
Core User Manual (UM0128), which is available for download on www.zilog.com, for the
description of the LDCand LDCIinstructions. While the Flash Controller programs the
Flash memory, the eZ8 CPU idles, but the system clock and on-chip peripherals continue
to operate. To exit programming mode and lock the Flash, write any value to the Flash
Control Register, except the mass erase or page erase commands.
The byte at each address within Flash memory cannot be programmed (any bits written
to 0) more than twice before an erase cycle occurs.
Caution:
PS025113-1212
Operation
Z8 Encore!® F0830 Series
Product Specification
117
Page Erase
Flash memory can be erased one page (512 bytes) at a time. Page erasing Flash memory
sets all bytes in that page to the value FFH. The Flash Page Select Register identifies the
page to be erased. Only a page residing in an unprotected sector can be erased. With the
Flash Controller unlocked and the active page set, writing the value 95hto the Flash Con-
trol Register initiates the Page Erase operation. While the Flash Controller executes the
Page Erase operation, the eZ8 CPU idles, but the system clock and on-chip peripherals
continue to operate. The eZ8 CPU resumes operation after the page erase operation com-
pletes. If the Page Erase operation is performed using the On-Chip Debugger, poll the
Flash Status Register to determine when the Page Erase operation is complete. When the
page erase is complete, the Flash Controller returns to its Locked state.
Mass Erase
Flash memory can also be mass erased using the Flash Controller, but only by using the
On-Chip Debugger. Mass erasing Flash memory sets all bytes to the value FFH. With the
Flash Controller unlocked and the mass erase successfully enabled, writing the value 63H
to the Flash Control Register initiates the Mass Erase operation. While the Flash Control-
ler executes the Mass Erase operation, the eZ8 CPU idles, but the system clock and on-
chip peripherals continue to operate. Using the On-Chip Debugger, poll the Flash Status
Register to determine when the Mass Erase operation is complete. When the mass erase is
complete, the Flash Controller returns to its Locked state.
Flash Controller Bypass
The Flash Controller can be bypassed; instead, the control signals for Flash memory can
be brought out to the GPIO pins. Bypassing the Flash Controller allows faster row pro-
gramming algorithms by controlling the Flash programming signals directly.
Row programing is recommended for gang programming applications and large volume
customers who do not require in-circuit initial programming of Flash memory. Mass Erase
and Page Erase operations are also supported, when the Flash Controller is bypassed.
For more information about bypassing the Flash Controller, refer to Third-Party Flash
Programming Support for Z8 Encore!. This document is available for download at
www.zilog.com.
Flash Controller Behavior in Debug Mode
The following behavioral changes can be observed in the Flash Controller when the Flash
Controller is accessed using the On-Chip Debugger:
•
The Flash write protect option bit is ignored.
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Operation
Z8 Encore!® F0830 Series
Product Specification
118
•
•
•
•
The Flash Sector Protect Register is ignored for programming and Erase operations.
Programming operations are not limited to the page selected in the page select register.
Bits in the Flash Sector Protect Register can be written to one or zero.
The second write of the page select register to unlock the Flash Controller is not
necessary.
•
•
The page select register can be written when the Flash Controller is unlocked.
The mass erase command is enabled through the Flash Control Register
For security reasons, Flash Controller allows only a single page to be opened for write/
erase. When writing multiple Flash pages, the Flash Controller must go through the un-
lock sequence again to select another page.
Caution:
NVDS Operational Requirements
The device uses a 12KB Flash memory space, despite the maximum specified Flash size
of 8KB (with the exception of 12KB mode with non-NVDS). User code accesses the
lower 8KB of Flash, leaving the upper 4KB for proprietary (for Zilog-only) memory. The
NVDS is implemented by using this proprietary memory space for special-purpose rou-
tines and for the data required by these routines, which are factory-programmed and can-
not be altered by the user. The NVDS operation is described in detail in the Nonvolatile
Data Storage chapter on page 134.
The NVDS routines are triggered by a user code: CALL into proprietary memory. Code
executing from this proprietary memory must be able to read and write other locations
within proprietary memory. User code must not be able to read or write proprietary mem-
ory.
Flash Control Register Definitions
This section defines the features of the following Flash Control registers.
Flash Control Register: see page 119
Flash Status Register: see page 120
Flash Page Select Register: see page 121
Flash Sector Protect Register: see page 122
Flash Frequency High and Low Byte Registers: see page 123
PS025113-1212
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Z8 Encore!® F0830 Series
Product Specification
119
Flash Control Register
The Flash Controller must be unlocked using the Flash Control Register before program-
ming or erasing Flash memory. Writing the sequence 73H8CH, sequentially, to the Flash
Control Register unlocks the Flash Controller. When the Flash Controller is unlocked,
Flash memory can be enabled for mass erase or page erase by writing the appropriate
enable command to the FCTL. Page erase applies only to the active page selected in Flash
Page Select Register. Mass erase is enabled only through the On-Chip Debugger. Writing
an invalid value or an invalid sequence returns the Flash Controller to its Locked state.
The write-only Flash Control Register shares its register file address with the read-only
Flash Status Register.
Table 72. Flash Control Register (FCTL)
Bit
7
6
5
4
3
2
1
0
Field
FCMD
FF8H
RESET
R/W
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Address
Bit
Description
[7:0]
FCMD
Flash Command
73H = First unlock command.
8CH = Second unlock command.
95H = Page erase command (must be third command in sequence to initiate page erase).
63H = Mass erase command (must be third command in sequence to initiate mass erase).
5EH = Enable Flash Sector Protect Register access.
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Z8 Encore!® F0830 Series
Product Specification
120
Flash Status Register
The Flash Status Register indicates the current state of the Flash Controller. This register
can be read at any time. The read-only Flash Status Register shares its register file address
with the write-only Flash Control Register.
Table 73. Flash Status Register (FSTAT)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
FSTAT
RESET
R/W
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Address
FF8H
Bit
Description
Reserved
[7:6]
These bits are reserved and must be programmed to 00.
[5:0]
FSTAT
Flash Controller Status
000000 = Flash Controller locked.
000001 = First unlock command received (73H written).
000010 = Second unlock command received (8CH written).
000011 = Flash Controller unlocked.
000100 = Sector protect register selected.
001xxx = Program operation in progress.
010xxx = Page Erase operation in progress.
100xxx = Mass Erase operation in progress.
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Z8 Encore!® F0830 Series
Product Specification
121
Flash Page Select Register
The Flash Page Select Register shares address space with the Flash Sector Protect Regis-
ter. Unless the Flash Controller is locked and written with 5EH, any writes to this address
will target the Flash Page Select Register.
The register selects one of the eight available Flash memory pages to be programmed or
erased. Each Flash page contains 512-bytes of Flash memory. During a page erase opera-
tion, all Flash memory containing addresses with the most significant 7-bits within
FPS[6:0] are chosen for program/erase operations.
Table 74. Flash Page Select Register (FPS)
Bit
7
INFO_EN
0
6
5
4
3
PAGE
0
2
1
0
Field
RESET
R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FF9H
Bit
Description
[7]
Information Area Enable
INFO_EN 0 = Information area is not selected.
1 = Information area is selected. The information area is mapped into the program memory
address space at addresses FE00Hthrough FFFFH.
[6:0]
PAGE
Page Select
This 7-bit field identifies the Flash memory page for page erase and page unlocking. Program
memory address[15:9] = PAGE[6:0]. For Z8F04xx and Z8F02xx devices, the upper four bits
must always be 0. For Z8F01xx devices, the upper five bits must always be 0.
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Z8 Encore!® F0830 Series
Product Specification
122
Flash Sector Protect Register
The Flash Sector Protect Register is shared with the Flash Page Select Register. When the
Flash Control Register is locked and written with 5EH, the next write to this address tar-
gets the Flash Sector Protect Register. In all other cases, it targets the Flash Page Select
Register.
This register selects one of the eight available Flash memory sectors to be protected. The
Reset state of each sector protect bit is the zero (unprotected) state. After a sector is pro-
tected by setting its corresponding register bit, the register bit cannot be cleared by the
user.
To determine the appropriate Flash memory sector address range and sector number for
your F0830 Series product, please refer to Table 70 on page 112.
Table 75. Flash Sector Protect Register (FPROT)
Bit
7
6
5
4
3
2
1
0
Field
SPROT7 SPROT6 SPROT5 SPROT4 SPROT3 SPROT2 SPROT1 SPROT0
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FF9H
Bit
Description
[7:0]
Sector Protection
SPROTx For Z8F12xx, Z8F08xx and Z8F04xx devices, all bits are used. For Z8F02xx devices, the
upper four bits remain unused. For Z8F01xx devices, the upper six bits remain unused. To
determine the appropriate Flash memory sector address range and sector number for your
F0830 Series product, please refer to Table 69 and to Figures 14 through 18.
Note: x indicates bits in the range 7–0.
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Z8 Encore!® F0830 Series
Product Specification
123
Flash Frequency High and Low Byte Registers
The Flash Frequency High and Low Byte registers, shown in Tables 76 and 77, combine
to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations.
The 16-bit binary Flash frequency value must contain the system clock frequency (in kHz)
and is calculated using the following equation:
System Clock Frequency
-----------------------------------------------------------
FFREQ[15:0] = FFREQH[7:0],FFREQL[7:0] =
1000
Flash programming and erasure is not supported for system clock frequencies below
10kHz or above 20MHz. The Flash Frequency High and Low Byte registers must be
loaded with the correct value to ensure proper operation of the device.
Caution:
Table 76. Flash Frequency High Byte Register (FFREQH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
FFREQH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FFAH
Bit
Description
[7:0]
Flash Frequency High Byte
FFREQH High byte of the 16-bit Flash frequency value.
Table 77. Flash Frequency Low Byte Register (FFREQL)
Bit
7
6
5
4
3
2
1
0
Field
FFREQL
0
RESET
R/W
R/W
Address
FFBH
Bit
Description
[7:0]
Flash Frequency High Byte
FFREQL Low byte of the 16-bit Flash frequency value.
PS025113-1212
Flash Control Register Definitions
Z8 Encore!® F0830 Series
Product Specification
124
Flash Option Bits
Programmable Flash option bits allow user configuration of certain aspects of Z8 Encore!
F0830 Series operation. The feature configuration data is stored in the Flash program
memory and read during reset. The features available for control through the Flash option
bits are:
•
•
•
•
Watchdog Timer time-out response selection–interrupt or system reset
Watchdog Timer enabled at reset
The ability to prevent unwanted read access to user code in program memory
The ability to prevent accidental programming and erasure of all or a portion of the user
code in program memory
•
•
•
Voltage Brown-Out configuration always enabled or disabled during STOP Mode to re-
duce STOP Mode power consumption
OSCILLATOR Mode selection for high, medium and low power crystal oscillators or
external RC oscillator
Factory trimming information for the Internal Precision Oscillator and VBO voltage
Operation
This section describes the type and configuration of the programmable Flash option bits.
Option Bit Configuration by Reset
Each time the Flash option bits are programmed or erased, the device must be reset for the
change to be effective. During any Reset operation (system reset or Stop Mode Recovery),
the Flash option bits are automatically read from Flash program memory and written to the
Option Configuration registers, which control Z8 Encore! F0830 Series device operation.
Option bit control is established before the device exits reset and the eZ8 CPU begins code
execution. The Option Configuration registers are not part of the register file and are not
accessible for read or write access.
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Flash Option Bits
Z8 Encore!® F0830 Series
Product Specification
125
Option Bit Types
This section describes the two types of Flash option bits offered in the F0830 Series.
User Option Bits
The user option bits are contained in the first two bytes of program memory. User access
to these bits is provided because these locations contain application specific device config-
urations. The information contained here is lost when page 0 of program memory is
erased.
Trim Option Bits
The trim option bits are contained in the information page of the Flash memory. These bits
are factory programmed values required to optimize the operation of onboard analog cir-
cuitry and cannot be permanently altered by the user. Program memory can be erased
without endangering these values. It is possible to alter working values of these bits by
accessing the trim bit address and data registers, but these working values are lost after a
power loss.
There are 32 bytes of trim data. To modify one of these values, the user code must first
write a value between 00Hand 1FHinto the Trim Bit Address Register. The next write to
the Trim Bit Data Register changes the working value of the target trim data byte.
Reading the trim data requires the user code to write a value between 00Hand 1FHinto the
Trim Bit Address Register. The next read from the Trim Bit Data Register returns the
working value of the target trim data byte.
The trim address range is from information address 20–3Fonly. The remaining informa-
Note:
tion page is not accessible via the Trim Bit Address and Data registers.
During reset, the first 43 system clock cycles perform 43 Flash accesses. The six bits of
the counter provide the lower six bits of the Flash memory address. All other address bits
are set to 0. The option bit registers use the 6-bit address from the counter as an address
and latch the data from the Flash on the positive edge of the IPO clock, allowing for a
maximum of 344-bits (43 bytes) of option information to be read from Flash.
Because option information is stored in both the first two bytes of program memory and in
the information area of Flash memory, the data must be placed in specific locations to be
read correctly. In this case, the first two bytes at addresses 0 and 1 in program memory are
read out and the remainder of the bytes are read out of the Flash information area.
PS025113-1212
Operation
Z8 Encore!® F0830 Series
Product Specification
126
Flash Option Bit Control Register Definitions
This section briefly describes the features of the Trim Bit Address and Data registers.
Trim Bit Address Register
The Trim Bit Address Register, shown in Table 78, contains the target address to access
the trim option bits. Trim bit addresses in the range 00h–1Fhmap to the information area
at addresses 20h–3Fh, as shown in Table 79.
Table 78. Trim Bit Address Register (TRMADR)
Bit
7
6
5
4
3
2
1
0
Field
TRMADR: Trim Bit Address (00H to 1FH)
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FF6H
Table 79. Trim Bit Address Map
Information Area
Trim Bit Address
Address
20h
21h
22h
23h
:
00h
01h
02h
03h
:
1Fh
3Fh
Trim Bit Data Register
The Trim Bit Data Register, shown in Table 80, contains the read or write data to access
the trim option bits.
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Z8 Encore!® F0830 Series
Product Specification
127
Table 80. Trim Bit Data Register (TRMDR)
Bit
7
6
5
4
3
2
1
0
Field
TRMDR: Trim Bit Data
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FF7H
Flash Option Bit Address Space
The first two bytes of Flash program memory at addresses 0000Hand 0001Hare reserved
for the user-programmable Flash option bits. See Tables 81 and 82.
Table 81. Flash Option Bits at Program Memory Address 0000H
Bit
7
6
5
4
3
VBO_AO
U
2
1
Reserved
U
0
Field
WDT_RES WDT_AO
OSC_SEL[1:0]
FRP
U
FWP
U
RESET
R/W
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Program Memory 0000H
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
[7]
Watchdog Timer Reset
WDT_RES 0 = Watchdog Timer time-out generates an interrupt request. Interrupts must be globally
enabled for the eZ8 CPU to acknowledge the interrupt request.
1 = Watchdog Timer time-out causes a system reset. This is the default setting for unpro-
grammed (erased) Flash.
[6]
WDT_AO
Watchdog Timer Always On
0 = On application of system power, Watchdog Timer is automatically enabled. Watchdog
Timer cannot be disabled.
1 = Watchdog Timer is enabled on execution of the WDT instruction. Once enabled, the
Watchdog Timer can only be disabled by a reset. This is the default setting for unpro-
grammed (erased) Flash.
[5:4]
OSCILLATOR Mode Selection
OSC_SEL 00 = On-chip oscillator configured for use with external RC networks (<4MHz).
01 = Minimum power for use with very low frequency crystals (32 kHz to 1.0MHz).
10 = Medium power for use with medium frequency crystals or ceramic resonators (0.5MHz
to 5.0MHz).
11 = Maximum power for use with high frequency crystals (5.0MHz to 20.0MHz). This is the
default setting for unprogrammed (erased) Flash.
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Flash Option Bit Address Space
Z8 Encore!® F0830 Series
Product Specification
128
Bit
Description (Continued)
[3]
VBO_AO
Voltage Brown-Out Protection Always On
0 = Voltage Brown-Out protection is disabled in STOP Mode to reduce total power con-
sumption.
1 = Voltage Brown-Out protection is always enabled, even during STOP Mode. This setting
is the default setting for unprogrammed (erased) Flash.
[2]
FRP
Flash Read Protect
0 = User program code is inaccessible. Limited control features are available through the
On-Chip Debugger.
1 = User program code is accessible. All On-Chip Debugger commands are enabled. This is
the default setting for unprogrammed (erased) Flash.
[1]
Reserved
This bit is reserved and must be programmed to 1.
[0]
FWP
Flash Write Protect
This option bit provides Flash program memory protection.
0 = Programming and erasure disabled for all Flash program memory. Programming, page
erase and mass erase through user code is disabled. Mass erase is available using the
On-Chip Debugger.
1 = Programming, page erase and mass erase are enabled for all Flash program memory.
Table 82. Flash Options Bits at Program Memory Address 0001H
Bit
7
VBO_RES
U
6
5
4
XTLDIS
U
3
2
1
0
Field
Reserved
Reserved
RESET
R/W
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Program Memory 0001H
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
[7]
Voltage Brown-Out reset
VBO_RES 1 = VBO detection causes a system reset. This setting is the default setting for unpro-
grammed (erased) Flash.
[6:5]
Reserved
These bits are reserved and must be programmed to 11.
PS025113-1212
Flash Option Bit Address Space
Z8 Encore!® F0830 Series
Product Specification
129
Bit
Description (Continued)
[4]
XTLDIS
State of the Crystal Oscillator at Reset
This bit enables only the crystal oscillator. Selecting the crystal oscillator as the system
clock must be performed manually.
0 = The crystal oscillator is enabled during reset, resulting in longer reset timing.
1 = The crystal oscillator is disabled during reset, resulting in shorter reset timing.
[3:0]
Reserved
These bits are reserved and must be programmed to 1111.
Trim Bit Address Space
All available trim bit addresses and their functions are listed in Tables 83 through 90.
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Z8 Encore!® F0830 Series
Product Specification
130
Table 83. Trim Bit Address Space
Address
Function
00h
01h
02h
03h
06h
ADC reference voltage
ADC and comparator
Internal Precision Oscillator
Oscillator and VBO
ClkFltr
Table 84. Trim Option Bits at 0000H (ADCREF)
Bit
7
6
5
4
3
2
1
Reserved
U
0
Field
ADCREF_TRIM
RESET
R/W
U
R/W
R/W
Address
Information Page Memory 0020H
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
[7:3]
ADC Reference Voltage Trim Byte
ADCREF_TRIM Contains trimming bits for ADC reference voltage.
[2:0]
Reserved
These bits are reserved and must be programmed to 111.
The bit values used in Table 84 are set at the factory; no calibration is required.
Note:
Table 85. Trim Option Bits at 0001H (TADC_COMP)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
RESET
R/W
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Information Page Memory 0021H
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
[7:0]
Reserved
Altering this register may result in incorrect device operation.
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Z8 Encore!® F0830 Series
Product Specification
131
The bit values used in Table 85 are set at the factory; no calibration is required.
Note:
Table 86. Trim Option Bits at 0002H (TIPO)
Bit
7
6
5
4
3
2
1
0
Field
IPO_TRIM
RESET
R/W
U
R/W
Address
Information Page Memory 0022H
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
[7:0]
Internal Precision Oscillator Trim Byte
IPO_TRIM Contains trimming bits for the Internal Precision Oscillator.
The bit values used in Table 86 are set at the factory; no calibration is required.
Note:
Table 87. Trim Option Bits at 0003H (TVBO)
Bit
7
6
5
4
3
Reserved
U
2
1
VBO_TRIM
0
0
Field
Reserved
U
RESET
R/W
1
0
R/W
R/W
R/W
Address
Information Page Memory 0023H
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
[7:3]
Reserved
These bits are reserved and must be programmed to 11111.
[2]
VBO Trim Values
VBO_TRIM Contains factory-trimmed values for the oscillator and the VBO.
PS025113-1212
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Z8 Encore!® F0830 Series
Product Specification
132
The bit values used in Table 87 are set at the factory; no calibration is required.
Note:
Table 88. VBO Trim Definition
Trigger Voltage
VBO_TRIM
Level
000
1.7
001
1.6
101
2.2
110
2.0
100
2.4
111
1.8
On-chip Flash memory is only guaranteed to perform write operations when voltage sup-
plies exceed 2.7V. Write operations at voltages below 2.7V will yield unpredictable
results.
Table 89. Trim Option Bits at 0006H (TCLKFLT)
Bit
7
DivBy4
0
6
Reserved
1
5
DlyCtl1
0
4
DlyCtl2
0
3
DlyCtl3
0
2
1
0
Field
Reserved FilterSel1 FilterSel0
RESET
R/W
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Information Page Memory 0026H
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
[7]
DivBy4
Output Frequency Selection
0 = Output frequency is input frequency.
1 = Output frequency is 1/4 of the input frequency.
[6]
Reserved
This bit is reserved and must be programmed to 1.
[5:3]
DlyCtlx
Delay Control
3-bit selection for the pulse width that can be filtered. See Table 90 for Delay Control values at
3.3V operation voltage.
[2]
Reserved
This bit is reserved and must be programmed to 1.
Notes: x indicates bit values 3–1; y indicates bit values 1–0.
PS025113-1212
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Z8 Encore!® F0830 Series
Product Specification
133
Bit
Description (Continued)
Filter Select
[1:0]
FilterSely 2-bit selection for the clock filter mode.
00 = No filter.
01 = Filter low level noise on high level signal.
10 = Filter high level noise on low level signal.
11 = Filter both.
Notes: x indicates bit values 3–1; y indicates bit values 1–0.
The bit values used in Table 89 are set at factory and no calibration is required.
Note:
Table 90. ClkFlt Delay Control Definition
DlyCtl3, DlyCtl2,
Low Noise Pulse
High Noise Pulse
DlyCtl1
000
001
010
011
on High Signal (ns) on Low Signal (ns)
5
5
7
7
9
9
11
13
17
20
25
11
13
17
20
25
100
101
110
111
Note: The variation is about 30%.
PS025113-1212
Trim Bit Address Space
Z8 Encore!® F0830 Series
Product Specification
134
Nonvolatile Data Storage
Z8 Encore! F0830 Series devices contain a Nonvolatile Data Storage (NVDS) element of
up to 64 bytes (except when in Flash 12KB mode). This type of memory can perform over
100,000 write cycles.
Operation
NVDS is implemented by special-purpose Zilog software stored in areas of program mem-
ory that are not user-accessible. These special-purpose routines use Flash memory to store
the data, and incorporate a dynamic addressing scheme to maximize the write/erase endur-
ance of the Flash.
The products in the Z8 Encore! F0830 Series feature multiple NVDS array sizes. See the
Z8 Encore! F0830 Series Family Part Selection Guide section on page 2 for details.
Note:
NVDS Code Interface
Two routines are required to access the NVDS: a write routine and a read routine. Both of
these routines are accessed with a CALLinstruction to a predefined address outside of pro-
gram memory that is accessible to the user. Both the NVDS address and data are single-
byte values. In order to not disturb the user code, these routines save the working register
set before using it so that 16 bytes of stack space are required to preserve the site. After
finishing the call to these routines, the working register set of the user code is recovered.
During both read and write accesses to the NVDS, interrupt service is not disabled. Any
interrupts that occur during NVDS execution must not disturb the working register and
existing stack contents; otherwise, the array can become corrupted. Zilog recommends the
user disable interrupts before executing NVDS operations.
Use of the NVDS requires 16 bytes of available stack space. The contents of the working
register set are saved before calling NVDS read or write routines.
For correct NVDS operation, the Flash Frequency registers must be programmed based on
the system clock frequency. See the Flash Operation Timing Using the Flash Frequency
Registers section on page 114.
PS025113-1212
Nonvolatile Data Storage
Z8 Encore!® F0830 Series
Product Specification
135
Byte Write
To write a byte to the NVDS array, the user code must first push the address, then the data
byte onto the stack. The user code issues a CALLinstruction to the address of the Byte
Write routine (0x20B3). At the return from the subroutine, the write status byte resides in
working register R0. The bit fields of this status byte are defined in Table 91. Additionally,
user code should pop the address and data bytes off the stack.
The write routine uses 16 bytes of stack space in addition to the two bytes of address and
data pushed by the user code. Sufficient memory must be available for this stack usage.
Because of the Flash memory architecture, NVDS writes exhibit a nonuniform execution
time. In general, a write takes 136µs (assuming a 20MHz system clock). For every 200
writes, however, a maintenance operation is necessary. In this rare occurrence, the write
takes up to 58ms to complete. Slower system clock speeds result in proportionally higher
execution times.
NVDS byte writes to invalid addresses (those exceeding the NVDS array size) have no
effect. Illegal write operations have a 7µs execution time.
Table 91. Write Status Byte
Bit
7
6
5
4
3
2
1
0
Field
Reserved
FE
IGADDR
WE
Default
Value
0
0
0
0
0
0
0
0
Bit
Description
Reserved
[7:3]
These bits are reserved and must be programmed to 00000.
[2]
FE
Flash Error
If a Flash error is detected, this bit is set to 1.
[1]
Illegal Address
IGADDR When an NVDS byte writes to invalid addresses occur (those exceeding the NVDS array size),
this bit is set to 1.
[0]
WE
Write Error
A failure occurs during data writes to Flash. When writing data into a certain address, a read-
back operation is performed. If the read-back value is not the same as the value written, this bit
is set to 1.
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NVDS Code Interface
Z8 Encore!® F0830 Series
Product Specification
136
Byte Read
To read a byte from the NVDS array, user code must first push the address onto the stack.
User code issues a CALLinstruction to the address of the byte-read routine (0x2000). At
the return from the subroutine, the read byte resides in working register R0 and the read
status byte resides in working register R1. The bit fields of this status byte are defined in
Table 92. Additionally, the user code should pop the address byte off the stack.
The read routine uses 16 bytes of stack space in addition to the one byte of address pushed
by the user code. Sufficient memory must be available for this stack usage.
Due to the Flash memory architecture, NVDS reads exhibit a nonuniform execution time.
A read operation takes between 71µs and 258µs (assuming a 20MHz system clock).
Slower system clock speeds result in proportionally higher execution times.
NVDS byte reads from invalid addresses (those exceeding the NVDS array size) return
0xff. Illegal read operations have a 6µs execution time.
The status byte returned by the NVDS read routine is zero for a successful read. If the sta-
tus byte is nonzero, there is a corrupted value in the NVDS array at the location being
read. In this case, the value returned in R0 is the byte most recently written to the array
that does not have an error.
Table 92. Read Status Byte
Bit
7
6
5
4
3
2
1
0
Field
Reserved
DE
Reserved
FE
IGADDR Reserved
Default
Value
0
0
0
0
0
0
0
0
Bit
Description
Reserved
[7:5]
These bits are reserved and must be programmed to 000.
[4]
DE
Data Error
When reading an NVDS address, if an error is found in the latest data corresponding to this NVDS
address, this bit is set to 1. NVDS source code steps forward until it finds valid data at this address.
[3]
Reserved
This bit is reserved and must be programmed to 0.
[2]
FE
Flash Error
If a Flash error is detected, this bit is set to 1.
[1]
Illegal Address
IGADDR When NVDS byte reads from invalid addresses (those exceeding the NVDS array size) occur,
this bit is set to 1.
[0]
Reserved
This bit is reserved and must be programmed to 0.
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Product Specification
137
Power Failure Protection
NVDS routines employ error-checking mechanisms to ensure that any power failure will
only endanger the most recently written byte. Bytes previously written to the array are not
perturbed. For this protection to function, the VBO must be enabled (see the Low-Power
Modes chapter on page 30) and configured for a threshold voltage of 2.4V or greater (see
the Trim Bit Address Space section on page 129).
A system reset (such as a pin reset or Watchdog Timer reset) that occurs during a write
operation also perturbs the byte currently being written. All other bytes in the array are
unperturbed.
Optimizing NVDS Memory Usage for Execution Speed
As indicated in Table 93, the NVDS read time varies drastically; this discrepancy being a
trade-off for minimizing the frequency of writes that require post-write page erases. The
NVDS read time of address N is a function of the number of writes to addresses other than
N since the most recent write to address N as well as the number of writes since the most
recent page erase. Neglecting the effects caused by page erases and results caused by the
initial condition in which the NVDS is blank, a rule of thumb to consider is that every
write since the most recent page erase causes read times of unwritten addresses to increase
by 0.8µs up to a maximum of 258µs.
Table 93. NVDS Read Time
Minimum
Maximum
Operation
Read
Latency (µs) Latency (µs)
71
126
6
258
136
6
Write
Illegal Read
Illegal Write
7
7
For every 200 writes, a maintenance operation is necessary. In this rare occurrence, the
write takes up to 58ms to complete.
Note:
If NVDS read performance is critical to your software architecture, you can optimize your
code for speed by using either of the two methods listed below.
1. Periodically refresh all addresses that are used; this is the more useful method. The
optimal use of NVDS, in terms of speed, is to rotate the writes evenly among all
addresses planned for use, thereby bringing all reads closer to the minimum read time.
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Product Specification
138
Because the minimum read time is much less than the write time, however, actual
speed benefits are not always realized.
2. Use as few unique addresses as possible to optimize the impact of refreshing.
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Product Specification
139
On-Chip Debugger
The Z8 Encore! devices contain an integrated On-Chip Debugger (OCD) that provides the
following advanced debugging features:
•
•
•
•
Reading and writing of the register file
Reading and writing of program and data memory
Setting of breakpoints and watchpoints
Executing eZ8 CPU instructions
Architecture
The On-Chip Debugger consists of four primary functional blocks: transmitter, receiver,
autobaud detector/generator and debug controller. Figure 20 displays the architecture of
the On-Chip Debugger.
System Clock
Autobaud
Detector/Generator
Transmitter
Receiver
Debug Controller
DBG Pin
Figure 20. On-Chip Debugger Block Diagram
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Product Specification
140
Operation
The following section describes the operation of the On-Chip Debugging function.
OCD Interface
The On-Chip Debugger uses the DBG pin for communication with an external host. This
one-pin interface is a bidirectional open-drain interface that transmits and receives data.
Data transmission is half-duplex, which means that transmission and data retrieval cannot
occur simultaneously. The serial data on the DBG pin is sent using the standard asynchro-
nous data format defined in RS-232.This pin creates an interface between the Z8 Encore!
F0830 Series products and the serial port of a host PC using minimal external hardware.
Two different methods for connecting the DBG pin to an RS-232 interface are displayed in
Figures 21 and 22. The recommended method is the buffered implementation depicted in
Figure 22. The DBG pin must always be connected to VDD through an external pull-up
resistor.
For proper operation of the On-Chip Debugger, all power pins (VDD and AVDD) must be
supplied with power and all ground pins (VSS and AVSS) must be properly grounded. The
DBG pin is open-drain and must always be connected to VDD through an external pull-
up resistor to ensure proper operation.
Caution:
VDD
RS-232
Transceiver
10KΩ
Schottky
Diode
RS-232 TX
RS-232 RX
DBG Pin
Figure 21. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, #1 of 2
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141
VDD
RS-232
Transceiver
10KΩ
Open-Drain
Buffer
RS-232 TX
RS-232 RX
DBG Pin
Figure 22. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, #2 of 2
DEBUG Mode
The operating characteristics of the devices in DEBUG Mode are:
•
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to ex-
ecute specific instructions
•
•
•
•
The system clock operates, unless the device is in STOP Mode
All enabled on-chip peripherals operate, unless the device is in STOP Mode
Automatically exits HALT Mode
Constantly refreshes the Watchdog Timer, if enabled
Entering DEBUG Mode
•
The device enters DEBUG Mode after the eZ8 CPU executes a Breakpoint (BRK) in-
struction
•
If the DBG pin is held low during the most recent clock cycle of system reset, the de-
vice enters DEBUG Mode on exiting system reset
Exiting DEBUG Mode
The device exits DEBUG Mode following any of these operations:
•
•
•
Clearing the DBGMODE bit in the OCD Control Register to 0
Power-On Reset
Voltage Brown-Out reset
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•
•
•
Watchdog Timer reset
Asserting the RESET pin Low to initiate a reset
Driving the DBG pin Low while the device is in STOP Mode initiates a system reset
OCD Data Format
The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 start bit, 8 data bits (least-significant bit first) and 1 stop bit. See
Figure 23.
START
D0
D1
D2
D3
D4
D5
D6
D7
STOP
Figure 23. OCD Data Format
OCD Autobaud Detector/Generator
To run over a range of baud rates (data bits per second) with various system clock frequen-
cies, the On-Chip Debugger contains an autobaud detector/generator. After a reset, the
OCD is idle until it receives data. The OCD requires that the first character sent from the
host is the character 80H. The character 80Hhas eight continuous bits low (one Start bit
plus 7 data bits), framed between high bits. The autobaud detector measures this period
and sets the OCD baud rate generator accordingly.
The autobaud detector/generator is clocked by the system clock. The minimum baud rate
is the system clock frequency divided by 512. For optimal operation with asynchronous
datastreams, the maximum recommended baud rate is the system clock frequency divided
by 8. The maximum possible baud rate for asynchronous datastreams is the system clock
frequency divided by 4, but this theoretical maximum is possible only for low noise
designs with clean signals. Table 94 lists minimum and recommended maximum baud
rates for sample crystal frequencies.
Table 94. OCD Baud-Rate Limits
System Clock
Frequency
(MHz)
Recommended
Recommended
Maximum Baud Rate Standard PC Baud Rate Minimum Baud Rate
(kbps)
2500.0
125.0
(bps)
1,843,200
115,200
2400
(kbps)
39
20.0
1.0
1.95
0.064
0.032768 (32 KHz)
4.096
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If the OCD receives a serial break (nine or more continuous bits low), the autobaud detec-
tor/generator resets. Reconfigure the autobaud detector/generator by sending 80H.
OCD Serial Errors
The OCD can detect any of the following error conditions on the DBG pin:
•
•
•
Serial break (a minimum of nine continuous bits Low)
Framing error (received Stop bit is Low)
Transmit collision (simultaneous transmission by OCD and host detected by the OCD)
When the OCD detects one of these errors, it aborts any command currently in progress,
transmits a four character long serial break back to the host and resets the autobaud detec-
tor/generator. A framing error or transmit collision may be caused by the host sending a
serial break to the OCD. As a result of the open-drain nature of the interface, returning a
serial break back to the host only extends the length of the serial break if the host releases
the serial break early.
The host transmits a serial break on the DBGpin when first connecting to the Z8 Encore!
F0830 Series devices or when recovering from an error. A serial break from the host resets
the autobaud generator/detector, but does not reset the OCD Control Register. A serial
break leaves the device in DEBUG Mode, if that is the current mode. The OCD is held in
reset until the end of the serial break when the DBG pin returns high. Because of the open-
drain nature of the DBG pin, the host can send a serial break to the OCD even if the OCD
is transmitting a character.
Breakpoints
Execution breakpoints are generated using the BRKinstruction (opcode 00H). When the
eZ8 CPU decodes a BRK instruction, it signals the OCD. If breakpoints are enabled, the
OCD enters DEBUG Mode and idles the eZ8 CPU. If breakpoints are not enabled, the
OCD ignores the BRK signal and the BRKinstruction operates as an NOP instruction.
Breakpoints in Flash Memory
The BRKinstruction is opcode 00H, which corresponds to the fully programmed state of a
byte in Flash memory. To implement a breakpoint, write 00Hto the required break address
overwriting the current instruction. To remove a breakpoint, the corresponding page of
Flash memory must be erased and reprogrammed with the original data.
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Runtime Counter
The OCD contains a 16-bit runtime counter. It counts system clock cycles between break-
points. The counter starts counting when the OCD leaves DEBUG Mode and stops count-
ing when it enters DEBUG Mode again or when it reaches the maximum count of FFFFH.
On-Chip Debugger Commands
The host communicates to the On-Chip Debugger by sending OCD commands using the
DBG interface. During normal operation, only a subset of the OCD commands are avail-
able. In DEBUG Mode, all OCD commands become available unless the user code and
control registers are protected by programming the Flash read protect option bit (FRP).
The FRP prevents the code in memory from being read out of the Z8 Encore! F0830 Series
products. When this option is enabled, several of the OCD commands are disabled.
Table 95 summarizes the On-Chip Debugger commands. This table indicates the com-
mands that operate when the device is not in DEBUG Mode (normal operation) and the
commands that are disabled by programming the FRP.
Table 95. On-Chip Debugger Command Summary
Command Enabled when not
Disabled by
Debug Command
Byte
00H
01H
02H
03H
04H
05H
06H
07H
08H
in DEBUG Mode?
Flash Read Protect Option Bit
Read OCD Revision
Reserved
Yes
–
–
–
Read OCD Status Register
Read Runtime Counter
Write OCD Control Register
Read OCD Control Register
Write Program Counter
Read Program Counter
Write Register
Yes
–
–
–
Yes
Yes
–
Cannot clear DBGMODE bit
–
Disabled
Disabled
–
–
Only writes of the Flash Memory Con-
trol registers are allowed. Additionally,
only the Mass Erase command is
allowed to be written to the Flash Con-
trol register.
Read Register
09H
0AH
0BH
0CH
0DH
–
–
–
–
–
Disabled
Disabled
Disabled
Yes
Write Program Memory
Read Program Memory
Write Data Memory
Read Data Memory
–
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Table 95. On-Chip Debugger Command Summary (Continued)
Command Enabled when not
Disabled by
Debug Command
Read Program Memory CRC
Reserved
Byte
in DEBUG Mode?
Flash Read Protect Option Bit
0EH
–
–
–
–
–
–
–
0FH
–
Step Instruction
Stuff Instruction
Execute Instruction
Reserved
10H
Disabled
Disabled
Disabled
–
11H
12H
13H–FFH
In the following bulleted list of OCD commands, data and commands sent from the host to
the OCD are identified by DBG← Command/Data. Data sent from the OCD back to the
host is identified by DBGData.
Read OCD Revision (00H). The read OCD revision command determines the version of
the On-Chip Debugger. If OCD commands are added, removed or changed this revision
number changes.
DBG ← 00H
DBG → OCDRev[15:8] (Major revision number)
DBG → OCDRev[7:0] (Minor revision number)
Read OCD Status Register (02H). The read OCD Status Register command reads the
OCDSTAT register.
DBG ← 02H
DBG → OCDSTAT[7:0]
Read Runtime Counter (03H). The runtime counter counts system clock cycles in
between breakpoints. The 16-bit runtime counter counts from 0000Hand stops at the max-
imum count of FFFFH. The runtime counter is overwritten during the write memory, read
memory, write register, read register, read memory CRC, step instruction, stuff instruction
and execute instruction commands.
DBG ← 03H
DBG → RuntimeCounter[15:8]
DBG → RuntimeCounter[7:0]
Write OCD Control Register (04H). The write OCD Control Register command writes
the data that follows to the OCDCTL register. When the Flash read protect option bit is
enabled, the DBGMODE bit (OCDCTL[7]) can only be set to 1, it cannot be cleared to 0. To
return the device to normal operating mode, the device must be reset.
DBG ← 04H
DBG ← OCDCTL[7:0]
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Read OCD Control Register (05H). The read OCD Control Register command reads the
value of the OCDCTL register.
DBG ← 05H
DBG → OCDCTL[7:0]
Write Program Counter (06H). The write program counter command, writes the data that
follows to the eZ8 CPU’s program counter (PC). If the device is not in DEBUG Mode or if
the Flash read protect option bit is enabled, the program counter (PC) values are discarded.
DBG ← 06H
DBG ← ProgramCounter[15:8]
DBG ← ProgramCounter[7:0]
Read Program Counter (07H). The read program counter command, reads the value in
the eZ8 CPUs program counter (PC). If the device is not in DEBUG Mode or if the Flash
read protect option bit is enabled, this command returns FFFFH.
DBG ← 07H
DBG → ProgramCounter[15:8]
DBG → ProgramCounter[7:0]
Write Register (08H). The write register command, writes data to the register file. Data
can be written 1–256 bytes at a time (256 bytes can be written by setting size to 0). If the
device is not in DEBUG Mode, the address and data values are discarded. If the Flash read
protect option bit is enabled, only writes to the Flash control registers are allowed and all
other register write data values are discarded.
DBG ← 08H
DBG ← {4’h0,Register Address[11:8]}
DBG ← Register Address[7:0]
DBG ← Size[7:0]
DBG ← 1–256 data bytes
Read Register (09H). The read register command, reads data from the register file. Data
can be read 1–256 bytes at a time (256 bytes can be read by setting size to 0). If the device
is not in DEBUG Mode or if the Flash read protect option bit is enabled, this command
returns FFHfor all of the data values.
DBG ← 09H
DBG ← {4’h0,Register Address[11:8]
DBG ← Register Address[7:0]
DBG ← Size[7:0]
DBG → 1–256 data bytes
Write Program Memory (0AH). The write program memory command, writes data to
program memory. This command is equivalent to the LDC and LDCI instructions.
Data can be written 1–65536 bytes at a time (65536 bytes can be written by setting size to
0). The on-chip Flash Controller must be written to and unlocked for the programming
operation to occur. If the Flash Controller is not unlocked, the data is discarded. If the
device is not in DEBUG Mode or if the Flash read protect option bit is enabled, the data is
discarded.
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DBG ← 0AH
DBG ← Program Memory Address[15:8]
DBG ← Program Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG ← 1–65536 data bytes
Read Program Memory (0BH). The read program memory command, reads data from
program memory. This command is equivalent to the LDC and LDCI instructions. Data
can be read 1–65536 bytes at a time (65536 bytes can be read by setting size to 0). If the
device is not in DEBUG Mode or if the Flash read protect option bit is enabled, this com-
mand returns FFHfor the data.
DBG ← 0BH
DBG ← Program Memory Address[15:8]
DBG ← Program Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG → 1–65536 data bytes
Write Data Memory (0CH). The write data memory command, writes data to data mem-
ory. This command is equivalent to the LDE and LDEI instructions. Data can be written
1–65536 bytes at a time (65536 bytes can be written by setting size to 0). If the device is
not in DEBUG Mode or if the flash read protect option bit is enabled, the data is discarded.
DBG ← 0CH
DBG ← Data Memory Address[15:8]
DBG ← Data Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG ← 1–65536 data bytes
Read Data Memory (0DH). The read data memory command, reads from data memory.
This command is equivalent to the LDE and LDEI instructions. Data can be read from 1 to
65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in
DEBUG Mode, this command returns FFHfor the data.
DBG ← 0DH
DBG ← Data Memory Address[15:8]
DBG ← Data Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG → 1–65536 data bytes
Read Program Memory CRC (0EH). The read program memory CRC command, com-
putes and returns the cyclic redundancy check (CRC) of program memory using the 16-bit
CRC-CCITT polynomial. If the device is not in DEBUG Mode, this command returns
FFFFHfor the CRC value. Unlike the other OCD read commands, there is a delay from
issuing of the command until the OCD returns the data. The OCD reads program memory,
calculates the CRC value and returns the result. The delay is a function of program mem-
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ory size and is approximately equal to the system clock period multiplied by the number of
bytes in program memory.
DBG ← 0EH
DBG → CRC[15:8]
DBG → CRC[7:0]
Step Instruction (10H). The step instruction command, steps one assembly instruction at
the current program counter (PC) location. If the device is not in DEBUG Mode or the
Flash read protect option bit is enabled, the OCD ignores this command.
DBG ← 10H
Stuff Instruction (11H). The stuff instruction command, steps one assembly instruction
and allows specification of the first byte of the instruction. The remaining 0–4 bytes of the
instruction are read from program memory. This command is useful for stepping over
instructions where the first byte of the instruction has been overwritten by a breakpoint. If
the device is not in DEBUG Mode or the Flash read protect option bit is enabled, the OCD
ignores this command.
DBG ← 11H
DBG ← opcode[7:0]
Execute Instruction (12H). The execute instruction command allows sending an entire
instruction to be executed to the eZ8 CPU. This command can also step over breakpoints.
The number of bytes to send for the instruction depends on the opcode. If the device is not
in DEBUG Mode or the Flash read protect option bit is enabled, this command reads and
discards one byte.
DBG ← 12H
DBG ← 1–5 byte opcode
On-Chip Debugger Control Register Definitions
This section describes the features of the On-Chip Debugger Control and Status registers.
OCD Control Register
The OCD Control Register controls the state of the On-Chip Debugger. This register is
used to enter or exit DEBUG Mode and to enable the BRKinstruction. It can also reset the
Z8 Encore! F0830 Series device.
A reset and stop function can be achieved by writing 81Hto this register. A reset and go
function can be achieved by writing 41Hto this register. If the device is in DEBUG Mode,
a run function can be implemented by writing 40H to this register.
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Table 96. OCD Control Register (OCDCTL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DBGMODE BRKEN DBGACK
Reserved
RST
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R
R
R/W
Bit
Description
[7]
DEBUG Mode
DBGMODE The device enters DEBUG Mode when this bit is 1. When in DEBUG Mode, the eZ8 CPU
stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is
automatically set when a BRKinstruction is decoded and breakpoints are enabled. If the
Flash read protect option bit is enabled, this bit can only be cleared by resetting the device. It
cannot be written to 0.
0 = The Z8 Encore! F0830 Series device is operating in NORMAL Mode.
1 = The Z8 Encore! F0830 Series device is in DEBUG Mode.
[6]
BRKEN
Breakpoint Enable
This bit controls the behavior of the BRKinstruction (opcode 00H). By default, breakpoints
are disabled and the BRKinstruction behaves similar to an NOP instruction. If this bit is 1
when a BRKinstruction is decoded, the DBGMODEbit of the OCDCTL register is automati-
cally set to 1.
0 = Breakpoints are disabled.
1 = Breakpoints are enabled.
[5]
DBGACK
Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a
Debug acknowledge character (FFH) to the host when a breakpoint occurs.
0 = Debug acknowledge is disabled.
1 = Debug acknowledge is enabled.
[4:1]
Reserved
These bits are reserved and must be programmed to 0000.
[0]
RST
Reset
Setting this bit to 1 resets the Z8F04xA family device. The device goes through a normal
Power-On Reset sequence with the exception that the On-Chip Debugger is not reset. This
bit is automatically cleared to 0 at the end of the reset sequence.
0 = No effect.
1 = Reset the Flash read protect option bit device.
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OCD Status Register
The OCD Status Register reports status information about the current state of the debugger
and the system.
Table 97. OCD Status Register (OCDSTAT)
Bit
7
DBG
0
6
HALT
0
5
4
3
2
1
0
Field
RESET
R/W
FRPENB
Reserved
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Description
[7]
DBG
Debug Status
0 = NORMAL Mode.
1 = DEBUG Mode.
[6]
HALT
HALT Mode
0 = Not in HALT Mode.
1 = In HALT Mode.
[5]
Flash Read Protect Option Bit Enable
FRPENB 0 = FRP bit enabled, that allows disabling of many OCD commands.
1 = FRP bit has no effect.
[4:0]
Reserved
These bits are reserved and must be programmed to 00000.
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Oscillator Control
The Z8 Encore! F0830 Series device uses five possible clocking schemes. Each one of
these is user-selectable.
•
•
•
•
•
On-chip precision trimmed RC oscillator
On-chip oscillator using off-chip crystal or resonator
On-chip oscillator using external RC network
External clock drive
On-chip low precision Watchdog Timer Oscillator
In addition, Z8 Encore! F0830 Series devices contain clock failure detection and recovery
circuitry, allowing continued operation despite a failure of the primary oscillator.
Operation
This chapter discusses the logic used to select the system clock and handle primary oscil-
lator failures. A description of the specific operation of each oscillator is outlined further
in this document.
System Clock Selection
The oscillator control block selects from the available clocks. Table 98 describes each
clock source and its usage.
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Table 98. Oscillator Configuration and Selection
Clock Source
Characteristics
Required Setup
Internal precision
RC oscillator
• 32.8 kHz or 5.53MHz
• ± 4% accuracy when trimmed
• No external components required
• Unlock and write to the Oscillator Con-
trol Register (OSCCTL) to enable and
select oscillator at either 5.53MHz or
32.8 kHz
External crystal/res- • 32 kHz to 20MHz
onator • Very high accuracy (dependent on
• Configure Flash option bits for correct
external OSCILLATOR Mode
crystal or resonator used)
• Requires external components
• Unlock and write OSCCTL to enable
crystal oscillator, wait for it to stabilize
and select as system clock (if the
XTLDIS option bit has been
de-asserted, no waiting is required)
External RC oscilla- • 32 kHz to 4MHz
tor • Accuracy dependent on
nal components
• Configure Flash option bits for correct
external OSCILLATOR Mode
• Unlock and write OSCCTL to enable
crystal oscillator and select as system
clock
exter-
exter-
External clock drive • 0 to 20MHz
• Accuracy dependent on
• Write GPIO registers to configure PB3
pin for external clock function
nal clock source
• Unlock and write OSCCTL to select
external system clock
• Apply external clock signal to GPIO
Internal Watchdog • 10 kHz nominal
• Enable WDT if not enabled and wait
until WDT oscillator is operating.
• Unlock and write to the Oscillator Con-
trol Register (OSCCTL) to enable and
select oscillator
Timer Oscillator
• ± 40% accuracy; no external compo-
nents required
• Low power consumption
Unintentional accesses to the Oscillator Control Register can actually stop the chip by
switching to a nonfunctioning oscillator. To prevent this condition, the oscillator control
block employs a register unlocking/locking scheme.
Caution:
OSC Control Register Unlocking/Locking
To write the Oscillator Control Register, unlock it by making two writes to the OSCCTL
Register with the values E7Hfollowed by 18H. A third write to the OSCCTL Register
changes the value of the actual register and returns the register to a Locked state. Any
other sequence of Oscillator Control Register writes have no effect. The values written to
unlock the register must be ordered correctly, but are not necessarily consecutive. It is pos-
sible to write to or read from other registers within the unlocking/locking operation.
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When selecting a new clock source, the primary oscillator failure detection circuitry and
the Watchdog Timer Oscillator failure circuitry must be disabled. If POFEN and WOFEN
are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a
failure of either oscillator. The failure detection circuitry can be enabled anytime after a
successful write of OSCSEL in the Oscillator Control Register.
The Internal Precision Oscillator is enabled by default. If the user code changes to a differ-
ent oscillator, it may be appropriate to disable the IPO for power savings. Disabling the
IPO does not occur automatically.
Clock Failure Detection and Recovery
Primary Oscillator Failure
The Z8F04xA family devices can generate nonmaskable interrupt-like events when the
primary oscillator fails. To maintain system function in this situation, the clock failure
recovery circuitry automatically forces the Watchdog Timer Oscillator to drive the system
clock. The Watchdog Timer Oscillator must be enabled to allow the recovery. Although
this oscillator runs at a much slower speed than the original system clock, the CPU contin-
ues to operate, allowing execution of a clock failure vector and software routines that
either remedy the oscillator failure or issue a failure alert. This automatic switch-over is
not available if the Watchdog Timer is the primary oscillator. It is also unavailable if the
Watchdog Timer Oscillator is disabled, though it is not necessary to enable the Watchdog
Timer reset function outlined in the Watchdog Timer chapter of this document.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1 KHz ±50%. If an external signal is selected as the system oscillator, it is
possible that a very slow but nonfailing clock can generate a failure condition. Under these
conditions, do not enable the clock failure circuitry (POFEN must be deasserted in the
OSCCTL Register).
Watchdog Timer Failure
In the event of failure of a Watchdog Timer Oscillator, a similar nonmaskable interrupt-
like event is issued. This event does not trigger an attendant clock switch-over, but alerts
the CPU of the failure. After a Watchdog Timer failure, it is no longer possible to detect a
primary oscillator failure. The failure detection circuitry does not function if the Watchdog
Timer is used as the primary oscillator or if the Watchdog Timer Oscillator has been dis-
abled. For either of these cases, it is necessary to disable the detection circuitry by deas-
serting the WDFEN bit of the OSCCTL Register.
The Watchdog Timer Oscillator failure detection circuit counts system clocks while look-
ing for a Watchdog Timer clock. The logic counts 8004 system clock cycles before deter-
mining that a failure has occurred. The system clock rate determines the speed at which
the Watchdog Timer failure is detected. A very slow system clock results in very slow
detection times.
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It is possible to disable the clock failure detection circuitry as well as all functioning
clock sources. In this case, the Z8 Encore! F0830 Series device ceases functioning and
can only be recovered by power-on-reset.
Caution:
Oscillator Control Register Definitions
The following section provides the bit definitions for the Oscillator Control Register.
Oscillator Control Register
The Oscillator Control Register (OSCCTL) enables/disables the various oscillator circuits,
enables/disables the failure detection/recovery circuitry and selects the primary oscillator,
which becomes the system clock.
The Oscillator Control Register must be unlocked before writing. Writing the two step
sequence E7Hfollowed by 18Hto the Oscillator Control Register unlocks it. The register
is locked at successful completion of a register write to the OSCCTL.
Figure 24 displays the oscillator control clock switching flow. See Table 117 on page 189
to review the waiting times of various oscillator circuits.
Table 99. Oscillator Control Register (OSCCTL)
Bit
7
INTEN
1
6
XTLEN
0
5
WDTEN
1
4
POFEN
0
3
WDFEN
0
2
1
SCKSEL
0
0
Field
RESET
R/W
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F86H
Bit
Description
[7]
INTEN
Internal Precision Oscillator Enable
1 = Internal Precision Oscillator is enabled.
0 = Internal Precision Oscillator is disabled.
[6]
XTLEN
Crystal Oscillator Enable
This setting overrides the GPIO register control for PA0 and PA1.
1 = Crystal oscillator is enabled.
0 = Crystal oscillator is disabled.
[5]
Watchdog Timer Oscillator Enable
WDTEN 1 = Watchdog Timer Oscillator is enabled.
0 = Watchdog Timer Oscillator is disabled.
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Bit
Description (Continued)
[4]
Primary Oscillator Failure Detection Enable
POFEN 1 = Failure detection and recovery of primary oscillator is enabled.
0 = Failure detection and recovery of primary oscillator is disabled.
[3]
Watchdog Timer Oscillator Failure Detection Enable
WDFEN 1 = Failure detection of Watchdog Timer Oscillator is enabled.
0 = Failure detection of Watchdog Timer Oscillator is disabled.
[2:0]
System Clock Oscillator Select
SCKSEL 000 = Internal Precision Oscillator functions as system clock at 5.53MHz.
001 = Internal Precision Oscillator functions as system clock at 32 kHz.
010 = Crystal oscillator or external RC oscillator functions as system clock.
011 = Watchdog Timer Oscillator functions as system clock.
100 = External clock signal on PB3 functions as system clock.
101 = Reserved.
110 = Reserved.
111 = Reserved.
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Normal Running
NO
NO
NO
Switch to OSC?
YES
Switch to IPO?
Switch to WDT?
YES
YES
NO
NO
NO
WDT OSC is
enabled?
OSC is enabled?
IPO is enabled?
Set bit7 in OSCCTL
register and wait
one NOP
instruction(wait
25 us if IPO
Set bit6 in
OSCCTL register
and wait
Set bit5 in OSCCTL
register and wait
50us
YES
YES
YES
1.5ms@20MHz
bandgap is closed)
Write to OSCCTL
Write to OSCCTL register:
Write to OSCCTL register:
register:
E7
18
E7
18
E7
18
to unlock OSCCTL
register
to unlock OSCCTL
register
to unlock OSCCTL
register
Write to OSCCTL
register:
010 to bits [2:0]
Write to OSCCTL register:
000 to bits [2:0]
Write to OSCCTL register:
011 to bits [2:0]
Figure 24. Oscillator Control Clock Switching Flow Chart
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Oscillator Control Register Definitions
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Product Specification
157
Crystal Oscillator
The products in the Z8 Encore! F0830 Series contain an on-chip crystal oscillator for use
with external crystals with 32kHz to 20MHz frequencies. In addition, the oscillator sup-
ports external RC networks with oscillation frequencies up to 4MHz or ceramic resonators
with frequencies up to 8MHz. The on-chip crystal oscillator can be used to generate the
primary system clock for the internal eZ8 CPU and the majority of its on-chip peripherals.
Alternatively, the XIN input pin can also accept a CMOS-level clock input signal (32kHz–
20MHz). If an external clock generator is used, the XOUT pin must remain unconnected.
The on-chip crystal oscillator also contains a clock filter function. To see the settings for
this clock filter, see Table 90 on page 133. By default, however, this clock filter is dis-
abled; therefore, no divide to the input clock (namely, the frequency of the signal on the
XIN input pin) can determine the frequency of the system clock when using the default set-
tings.
Although the XIN pin can be used as an input for an external clock generator, the CLKIN
pin is better suited for such use. See the System Clock Selection section on page 151 for
more information.
Note:
Operating Modes
The Z8 Encore! F0830 Series products support the following four OSCILLATOR Modes:
•
•
Minimum power for use with very low frequency crystals (32kHz to 1MHz)
Medium power for use with medium frequency crystals or ceramic resonators (0.5MHz
to 8MHz)
•
•
Maximum power for use with high frequency crystals (8MHz to 20MHz)
On-chip oscillator configured for use with external RC networks (<4MHz)
The OSCILLATOR Mode is selected using user-programmable Flash option bits. See the
Flash Option Bits chapter on page 124 for more information.
Crystal Oscillator Operation
The XTLDIS Flash option bit controls whether the crystal oscillator is enabled during
reset. The crystal may later be disabled after reset if a new oscillator has been selected as
the system clock. If the crystal is manually enabled after reset through the OSCCTL Reg-
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Product Specification
158
ister, the user code must wait at least 5000 IPO cycles for the crystal to stabilize. After this
period, the crystal oscillator may be selected as the system clock.
Figure 25 displays a recommended configuration for connection with an external funda-
mental-mode, parallel-resonant crystal operating at 20MHz. Recommended 20MHz crys-
tal specifications are provided in Table 100. Resistor R1 is optional and limits total power
dissipation by the crystal. Printed circuit board layout must add no more than 4pF of stray
capacitance to either the XIN or XOUT pins. If oscillation does not occur, reduce the values
of capacitors C1 and C2 to decrease loading.
On-Chip Oscillator
XIN
XOUT
R1 = 220
Crystal
C1 = 22pF
C2 = 22pF
Figure 25. Recommended 20MHz Crystal Oscillator Configuration
Table 100. Recommended Crystal Oscillator Specifications
Parameter
Frequency
Resonance
Mode
Value
Units
Comments
20
MHz
Parallel
Fundamental
Series Resistance (R )
60
30
7
pF
Maximum
Maximum
Maximum
Maximum
S
Load Capacitance (C )
L
Shunt Capacitance (C )
pF
0
Drive Level
1
mW
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159
Oscillator Operation with an External RC Network
Figure 26 displays a recommended configuration for connection with an external resistor-
capacitor (RC) network.
VDD
R
XIN
C
Figure 26. Connecting the On-Chip Oscillator to an External RC Network
An external resistance value of 45kΩ is recommended for oscillator operation with an
external RC network. The minimum resistance value to ensure operation is 40kΩThe
typical oscillator frequency can be estimated from the values of the resistor (R in kΩ) and
capacitor (C in pF) elements using the following equation:
6
110
--------------------------------------------------------
Oscillator Frequency (kHz) =
0.4 R C + 4 C
Figure 27 displays the typical (3.3V and 25°C) oscillator frequency as a function of the
capacitor (C in pF) employed in the RC network assuming a 45 kΩ external resistor. For
very small values of C, the parasitic capacitance of the oscillator XIN pin and the printed
circuit board should be included in the estimation of the oscillator frequency.
It is possible to operate the RC oscillator using only the parasitic capacitance of the pack-
age and printed circuit board. To minimize sensitivity to external parasitics, external
capacitance values in excess of 20pF are recommended.
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Oscillator Operation with an External RC Network
Z8 Encore!® F0830 Series
Product Specification
160
4000
3750
3500
3250
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
500
250
0
0
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500
C (pF)
Figure 27. Typical RC Oscillator Frequency as a Function of External Capacitance
with a 45 kΩ Resistor
When using the external RC OSCILLATOR Mode, the oscillator can stop oscillating if
the power supply drops below 2.7V but before it drops to the Voltage Brown-Out thresh-
old. The oscillator resumes oscillation when the supply voltage exceeds 2.7V.
Caution:
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Oscillator Operation with an External RC Network
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Product Specification
161
Internal Precision Oscillator
The Internal Precision Oscillator (IPO) is designed for use without external components.
The user can either manually trim the oscillator for a nonstandard frequency or use the
automatic factory-trimmed version to achieve a 5.53MHz frequency with ±4% accuracy
and 45%~55% duty cycle over the operating temperature and supply voltage of the device.
The maximum start-up time of the IPO is 25µs. IPO features include:
•
•
On-chip RC oscillator that does not require external components
Output frequency of either 5.53MHz or 32.8kHz (contains both a FAST and a SLOW
mode)
•
•
Trimming possible through Flash option bits, with user override
Elimination of crystals or ceramic resonators in applications where high timing accu-
racy is not required
Operation
The internal oscillator is an RC relaxation oscillator with a minimized sensitivity to power
supply variations. By using ratio-tracking thresholds, the effect of power supply voltage is
cancelled out. The dominant source of oscillator error is the absolute variance of chip-
level fabricated components, such as capacitors. An 8-bit trimming register, incorporated
into the design, compensates for absolute variation of oscillator frequency. Once trimmed,
the oscillator frequency is stable and does not require subsequent calibration. Trimming
was performed during manufacturing and is not necessary for the user to repeat unless a
frequency other than 5.53MHz (FAST mode) or 32.8kHz (SLOW mode) is required.
The user can power down the IPO block for minimum system power.
Note:
By default, the oscillator is configured through the Flash option bits. However, the user
code can override these trim values, as described in the Trim Bit Address Space section on
page 129.
Select one of two frequencies for the oscillator: 5.53MHz or 32.8 kHz, using the OSCSEL
bits described in the Oscillator Control chapter on page 151.
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Product Specification
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eZ8 CPU Instruction Set
This chapter describes the following features of the eZ8 CPU instruction set:
Assembly Language Programming Introduction: see page 162
Assembly Language Syntax: see page 163
eZ8 CPU Instruction Notation: see page 164
eZ8 CPU Instruction Classes: see page 166
eZ8 CPU Instruction Summary: see page 171
Assembly Language Programming Introduction
The eZ8 CPU assembly language provides a means for writing an application program
without concern for actual memory addresses or machine instruction formats. A program
written in assembly language is called a source program. Assembly language allows the
use of symbolic addresses to identify memory locations. It also allows mnemonic codes
(op codes and operands) to represent the instructions themselves. The op codes identify
the instruction while the operands represent memory locations, registers or immediate data
values.
Each assembly language program consists of a series of symbolic commands called state-
ments. Each statement contains labels, operations, operands and comments.
Labels can be assigned to a particular instruction step in a source program. The label iden-
tifies that step in the program as an entry point for use by other instructions.
The assembly language also includes assembler directives that supplement the machine
instruction. The assembler directives, or pseudo-ops, are not translated into a machine
instruction. Rather, these pseudo-ops are interpreted as directives that control or assist the
assembly process.
The source program is processed (assembled) by the assembler to obtain a machine lan-
guage program called the object code. The object code is executed by the eZ8 CPU. An
example segment of an assembly language program is provided in the following example.
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Product Specification
163
Assembly Language Source Program Example
JP START
START:
; Everything after the semicolon is a comment.
; A label called “START”. The first instruction (JP START) in this
; example causes program execution to jump to the point within the
; program where the START label occurs.
LD R4, R7
; A Load (LD) instruction with two operands. The first operand,
; Working register R4, is the destination. The second operand,
; Working register R7, is the source. The contents of R7 is
; written into R4.
LD 234H, #%01
; Another Load (LD) instruction with two operands.
; The first operand, extended mode register Address 234H,
; identifies the destination. The second operand, immediate data
; value 01H, is the source. The value 01H is written into the
; register at address 234H.
Assembly Language Syntax
For proper instruction execution, eZ8 CPU assembly language syntax requires that the
operands be written as destination, source. After assembly, the object code usually reflects
the operands in the order source, destination, but ordering is op code-dependent.
The following examples illustrate the format of some basic assembly instructions and the
resulting object code produced by the assembler. This binary format must be followed by
users that prefer manual program coding or intend to implement their own assembler.
Example 1
If the contents of registers 43Hand 08Hare added and the result is stored in 43H, the
assembly syntax and resulting object code is:
Table 101. Assembly Language Syntax Example 1
Assembly Language Code
Object Code
ADD
04
43H,
08
08H (ADD dst, src)
43 (OPC src, dst)
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Product Specification
164
Example 2
In general, when an instruction format requires an 8-bit register address, the address can
specify any register location in the range 0–255 or, using escaped mode addressing, a
working register R0–R15. If the contents of register 43Hand working register R8 are
added and the result is stored in 43H, the assembly syntax and resulting object code is:
Table 102. Assembly Language Syntax Example 2
Assembly Language Code
Object Code
ADD
04
43H,
E8
R8 (ADD dst, src)
43 (OPC src, dst)
See the device specific product specification to determine the exact register file range
available. The register file size varies, depending on the device type.
eZ8 CPU Instruction Notation
In the eZ8 CPU instruction summary and description sections, the operands, condition
codes, status flags and address modes are represented by the notational shorthand listed in
Table 103.
Table 103. Notational Shorthand
Notation Description
Operand Range
b
Bit
b
b represents a value from 0 to 7 (000B to 111B).
cc
Condition Code
—
See condition codes overview in the eZ8 CPU
User Manual.
DA
ER
Direct Address
Addrs
Reg
Addrs. represents a number in the range of
0000H to FFFFH
Extended Addressing Register
Reg. represents a number in the range of 000H
to FFFH
IM
Ir
Immediate Data
#Data
@Rn
Data is a number between 00H to FFH
n = 0 –15
Indirect Working Register
Indirect Register
IR
@Reg
Reg. represents a number in the range of 00H
to FFH
Irr
Indirect Working Register Pair
Indirect Register Pair
@RRp
@Reg
p = 0, 2, 4, 6, 8, 10, 12 or 14
IRR
Reg. represents an even number in the range
00H to FEH
p
r
Polarity
p
Polarity is a single bit binary value of either 0B
or 1B.
Working Register
Rn
n = 0 – 15
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Table 103. Notational Shorthand (Continued)
Operand Range
Notation Description
R
Register
Reg
Reg. represents a number in the range of 00H
to FFH
RA
Relative Address
X
X represents an index in the range of +127 to –
128 which is an offset relative to the address of
the next instruction
rr
Working Register Pair
Register Pair
RRp
Reg
p = 0, 2, 4, 6, 8, 10, 12 or 14
RR
Reg. represents an even number in the range of
00H to FEH
Vector
X
Vector Address
Indexed
Vector
#Index
Vector represents a number in the range of 00H
to FFH
The register or register pair to be indexed is off-
set by the signed Index value (#Index) in a +127
to
–128 range.
Table 104 contains additional symbols that are used throughout the instruction summary
and instruction set description sections.
Table 104. Additional Symbols
Symbol
dst
src
@
Definition
Destination Operand
Source Operand
Indirect Address Prefix
Stack Pointer
SP
PC
FLAGS
RP
#
Program Counter
Flags Register
Register Pointer
Immediate Operand Prefix
Binary Number Suffix
Hexadecimal Number Prefix
Hexadecimal Number Suffix
B
%
H
Assignment of a value is indicated by an arrow, as shown in the following example.
dst ← dst + src
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This example indicates that the source data is added to the destination data; the result is
stored in the destination location.
eZ8 CPU Instruction Classes
eZ8 CPU instructions can be divided functionally into the following groups:
•
•
•
•
•
•
•
•
Arithmetic
Bit manipulation
Block transfer
CPU control
Load
Logical
Program control
Rotate and shift
Tables 105 through 112 contain the instructions belonging to each group and the number
of operands required for each instruction. Some instructions appear in more than one table
as these instructions can be considered as a subset of more than one category. Within these
tables, the source operand is identified as src, the destination operand is dst and a condi-
tion code is cc.
Table 105. Arithmetic Instructions
Mnemonic
ADC
Operands
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst
Instruction
Add with Carry
ADCX
ADD
Add with Carry using Extended Addressing
Add
ADDX
CP
Add using Extended Addressing
Compare
CPC
Compare with Carry
Compare with Carry using Extended Addressing
Compare using Extended Addressing
Decimal Adjust
CPCX
CPX
DA
DEC
dst
Decrement
DECW
INC
dst
Decrement Word
dst
Increment
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Table 105. Arithmetic Instructions (Continued)
Mnemonic
INCW
MULT
SBC
Operands
dst
Instruction
Increment Word
Multiply
dst
dst, src
dst, src
dst, src
dst, src
Subtract with Carry
SBCX
SUB
Subtract with Carry using Extended Addressing
Subtract
SUBX
Subtract using Extended Addressing
Table 106. Bit Manipulation Instructions
Mnemonic
BCLR
BIT
Operands
bit, dst
p, bit, dst
bit, dst
dst
Instruction
Bit Clear
Bit Set or Clear
Bit Set
BSET
BSWAP
CCF
Bit Swap
—
Complement Carry Flag
Reset Carry Flag
Set Carry Flag
Test Complement Under Mask
RCF
—
SCF
—
TCM
dst, src
dst, src
TCMX
Test Complement Under Mask using Extended
Addressing
TM
dst, src
dst, src
Test Under Mask
TMX
Test Under Mask using Extended Addressing
Table 107. Block Transfer Instructions
Mnemonic
Operands
Instruction
LDCI
dst, src
Load Constant to/from Program Memory and Auto-
Increment Addresses
LDEI
dst, src
Load External Data to/from Data Memory and Auto-
Increment Addresses
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Table 108. CPU Control Instructions
Mnemonic
ATM
CCF
DI
Operands
Instruction
—
—
—
—
—
—
—
—
src
—
—
Atomic Execution
Complement Carry Flag
Disable Interrupts
Enable Interrupts
HALT Mode
EI
HALT
NOP
RCF
SCF
No Operation
Reset Carry Flag
Set Carry Flag
SRP
STOP
WDT
Set Register Pointer
STOP Mode
Watchdog Timer Refresh
Table 109. Load Instructions
Mnemonic
CLR
Operands
Instruction
dst
Clear
LD
dst, src
dst, src
dst, src
Load
LDC
Load Constant to/from Program Memory
LDCI
Load Constant to/from Program Memory and Auto-
Increment Addresses
LDE
dst, src
dst, src
Load External Data to/from Data Memory
LDEI
Load External Data to/from Data Memory and Auto-
Increment Addresses
LDWX
LDX
dst, src
dst, src
dst, X(src)
dst
Load Word using Extended Addressing
Load using Extended Addressing
Load Effective Address
Pop
LEA
POP
POPX
PUSH
PUSHX
dst
Pop using Extended Addressing
Push
src
src
Push using Extended Addressing
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Table 110. Logical Instructions
Mnemonic
AND
Operands
dst, src
dst, src
dst
Instruction
Logical AND
ANDX
COM
Logical AND using Extended Addressing
Complement
OR
dst, src
dst, src
dst, src
dst, src
Logical OR
ORX
Logical OR using Extended Addressing
Logical Exclusive OR
XOR
XORX
Logical Exclusive OR using Extended Addressing
Table 111. Program Control Instructions
Mnemonic
BRK
Operands
Instruction
—
On-chip Debugger Break
BTJ
p, bit, src, DA Bit Test and Jump
BTJNZ
BTJZ
CALL
DJNZ
IRET
JP
bit, src, DA
Bit Test and Jump if Non-Zero
bit, src, DA
Bit Test and Jump if Zero
Call Procedure
dst
dst, src, RA
Decrement and Jump Non-Zero
Interrupt Return
Jump
—
dst
dst
DA
DA
—
JP cc
JR
Jump Conditional
Jump Relative
JR cc
RET
Jump Relative Conditional
Return
TRAP
vector
Software Trap
Table 112. Rotate and Shift Instructions
Mnemonic
BSWAP
RL
Operands
Instruction
dst
dst
dst
Bit Swap
Rotate Left
RLC
Rotate Left through Carry
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Table 112. Rotate and Shift Instructions (Continued)
Mnemonic
RR
Operands
Instruction
dst
dst
dst
dst
dst
Rotate Right
RRC
Rotate Right through Carry
Shift Right Arithmetic
Shift Right Logical
SRA
SRL
SWAP
Swap Nibbles
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eZ8 CPU Instruction Summary
Table 113 summarizes the eZ8 CPU instructions. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags register, the number of CPU
clock cycles required for the instruction fetch and the number of CPU clock cycles
required for the instruction execution.
Table 113. eZ8 CPU Instruction Summary
Address
Op
Mode
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Code(s)
(Hex)
Fetch Instr.
Symbolic Operation
dst
src
r
ADC dst, src
dst ← dst + src + C
r
r
12
13
14
15
16
17
18
19
02
03
04
05
06
07
08
09
*
*
*
*
0
*
2
2
3
3
3
3
4
4
2
2
3
3
3
3
4
4
3
4
3
4
3
4
3
3
3
4
3
4
3
4
3
3
Ir
R
R
R
IR
IM
IM
ER
IM
r
R
IR
ER
ER
r
ADCX dst, src dst ← dst + src + C
*
*
*
*
*
*
*
*
0
0
*
*
ADD dst, src
dst ← dst + src
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
ADDX dst, src dst ← dst + src
*
*
*
*
0
*
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
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Table 113. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Code(s)
(Hex)
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Fetch Instr.
Symbolic Operation
dst
r
src
r
AND dst, src
dst ← dst AND src
52
53
54
55
56
57
58
59
2F
–
*
*
0
–
–
2
2
3
3
3
3
4
4
1
3
4
3
4
3
4
3
3
2
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
ANDX dst, src dst ← dst AND src
–
–
*
*
0
–
–
–
–
–
ATM
Block all interrupt and
DMA requests during
execution of the next 3
instructions
–
–
BCLR bit, dst dst[bit] ← 0
BIT p, bit, dst dst[bit] ← p
r
r
E2
E2
00
E2
D5
F6
F7
F6
F7
F6
F7
D4
D6
–
–
–
–
X
–
*
*
*
*
0
0
–
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
1
2
2
3
3
3
3
3
3
2
3
2
2
1
2
2
3
4
3
4
3
4
6
3
BRK
Debugger Break
–
*
–
*
BSET bit, dst dst[bit] ← 1
r
BSWAP dst
dst[7:0] ← dst[0:7]
R
*
*
BTJ p, bit, src, if src[bit] = p
r
Ir
r
–
–
dst
PC ← PC + X
BTJNZ bit, src, if src[bit] = 1
dst PC ← PC + X
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Ir
r
BTJZ bit, src, if src[bit] = 0
dst
PC ← PC + X
Ir
CALL dst
SP ← SP –2
@SP ← PC
PC ← dst
IRR
DA
CCF
C ← ~C
EF
*
–
–
–
– –-
1
2
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
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Table 113. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Code(s)
(Hex)
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Fetch Instr.
Symbolic Operation
dst
R
src
CLR dst
dst ← 00H
B0
B1
–
–
*
–
–
–
0
*
–
–
–
–
–
–
2
2
2
2
2
2
3
3
3
3
3
3
4
4
4
4
5
5
4
4
2
2
2
2
2
2
1
2
3
2
3
3
4
3
4
3
4
3
4
3
4
3
4
3
3
3
3
2
3
2
3
5
6
2
IR
R
COM dst
CP dst, src
dst ← ~dst
60
*
*
IR
r
61
dst - src
r
A2
*
*
r
Ir
A3
R
R
A4
R
IR
IM
IM
r
A5
R
A6
IR
r
A7
CPC dst, src
dst - src - C
1F A2
1F A3
1F A4
1F A5
1F A6
1F A7
1F A8
1F A9
A8
*
*
*
*
–
–
r
Ir
R
R
R
IR
IM
IM
ER
IM
ER
IM
R
IR
ER
ER
ER
ER
R
CPCX dst, src dst - src - C
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
CPX dst, src
DA dst
dst - src
A9
dst ← DA(dst)
dst ← dst - 1
dst ← dst - 1
IRQCTL[7] ← 0
40
*
*
*
X
*
IR
R
41
DEC dst
DECW dst
DI
30
–
–
–
*
*
IR
RR
IRR
31
80
*
*
*
81
8F
–
–
–
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS025113-1212
eZ8 CPU Instruction Summary
Z8 Encore!® F0830 Series
Product Specification
174
Table 113. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Code(s)
(Hex)
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Fetch Instr.
Symbolic Operation
dst
src
DJNZ dst, RA dst ← dst – 1
if dst 0
r
0A–FA
–
–
–
–
–
–
2
3
PC ← PC + X
EI
IRQCTL[7] ← 1
HALT Mode
9F
7F
–
–
–
–
–
*
–
–
*
–
–
–
–
–
–
–
–
–
1
1
2
2
1
2
2
1
2
2
2
3
2
5
6
5
HALT
INC dst
dst ← dst + 1
R
IR
20
21
r
0E–FE
A0
INCW dst
IRET
dst ← dst + 1
RR
IRR
–
*
*
*
*
*
*
*
–
*
–
*
A1
FLAGS ← @SP
SP ← SP + 1
PC ← @SP
BF
SP ← SP + 2
IRQCTL[7] ← 1
JP dst
PC ← dst
DA
IRR
DA
8D
C4
–
–
–
–
–
–
–
–
–
–
–
–
3
2
3
2
3
2
JP cc, dst
if cc is true
PC ← dst
0D–FD
JR dst
PC ← PC + X
DA
DA
8B
–
–
–
–
–
–
–
–
–
–
–
–
2
2
2
2
JR cc, dst
if cc is true
0B–FB
PC ← PC + X
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS025113-1212
eZ8 CPU Instruction Summary
Z8 Encore!® F0830 Series
Product Specification
175
Table 113. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Code(s)
(Hex)
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Fetch Instr.
Symbolic Operation
dst
r
src
IM
X(r)
r
LD dst, rc
dst ← src
0C–FC
C7
D7
E3
–
–
–
–
–
–
2
3
3
2
3
3
3
3
2
3
2
2
2
2
2
2
3
4
3
2
4
2
3
3
3
5
9
5
9
9
r
X(r)
r
Ir
R
R
R
IR
Ir
R
E4
IR
IM
IM
r
E5
E6
E7
F3
IR
r
R
F5
LDC dst, src
dst ← src
Irr
Irr
r
C2
C5
D2
C3
D3
–
–
–
–
–
–
–
–
–
–
–
–
Ir
Irr
Ir
LDCI dst, src dst ← src
r ← r + 1
Irr
Ir
Irr
rr ← rr + 1
LDE dst, src
dst ← src
r
Irr
r
82
92
83
93
–
–
–
–
–
–
–
–
–
–
–
–
2
2
2
2
5
5
9
9
Irr
Ir
LDEI dst, src dst ← src
r ← r + 1
Irr
Ir
Irr
rr ← rr + 1
LDWX dst, src dst ← src
ER
ER
1FE8
–
–
–
–
–
–
5
4
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS025113-1212
eZ8 CPU Instruction Summary
Z8 Encore!® F0830 Series
Product Specification
176
Table 113. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Code(s)
(Hex)
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Fetch Instr.
Symbolic Operation
dst
r
src
ER
ER
IRR
IRR
X(rr)
r
LDX dst, src
dst ← src
84
85
86
87
88
89
94
95
96
97
E8
E9
98
99
F4
–
–
–
–
–
–
3
3
3
3
3
3
3
3
3
3
4
4
3
3
2
2
3
4
5
4
4
2
3
4
5
2
2
3
5
8
Ir
R
IR
r
X(rr)
ER
ER
IRR
IRR
ER
ER
r
r
Ir
R
IR
ER
IM
LEA dst, X(src) dst ← src + X
X(r)
X(rr)
–
–
–
–
–
–
–
–
–
–
–
–
rr
MULT dst
dst[15:0] ←
RR
dst[15:8] * dst[7:0]
NOP
No operation
0F
42
43
44
45
46
47
48
49
50
51
–
–
–
*
–
*
–
0
–
–
–
–
1
2
2
3
3
3
3
4
4
2
2
2
3
4
3
4
3
4
3
3
2
3
OR dst, src
dst ← dst OR src
r
r
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
R
ORX dst, src
POP dst
dst ← dst OR src
–
–
*
*
0
–
–
–
–
–
dst ← @SP
SP ← SP + 1
–
–
IR
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS025113-1212
eZ8 CPU Instruction Summary
Z8 Encore!® F0830 Series
Product Specification
177
Table 113. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Code(s)
(Hex)
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Fetch Instr.
Symbolic Operation
dst
src
POPX dst
dst ← @SP
ER
D8
–
–
–
–
–
–
3
2
SP ← SP + 1
PUSH src
SP ← SP – 1
@SP ← src
R
IR
70
71
–
–
–
–
–
–
2
2
3
3
2
3
2
2
IM
ER
IF70
C8
PUSHX src
SP ← SP – 1
@SP ← src
–
–
–
–
–
–
RCF
RET
C ← 0
CF
AF
0
–
–
–
–
–
–
–
–
–
–
–
1
1
2
4
PC ← @SP
SP ← SP + 2
RL dst
R
IR
R
90
91
10
11
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
1
–
–
–
–
*
2
2
2
2
2
2
2
2
2
2
3
3
3
3
4
4
1
2
3
2
3
2
3
2
3
3
4
3
4
3
4
3
3
2
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
RLC dst
RR dst
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
R
E0
E1
C0
C1
32
33
34
35
36
37
38
39
DF
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
IR
R
RRC dst
SBC dst, src
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
IR
r
dst ← dst – src - C
r
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
SBCX dst, src dst ← dst – src - C
*
*
*
*
1
–
*
SCF
C ← 1
1
–
–
–
–
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS025113-1212
eZ8 CPU Instruction Summary
Z8 Encore!® F0830 Series
Product Specification
178
Table 113. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Code(s)
(Hex)
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Fetch Instr.
Symbolic Operation
dst
R
src
SRA dst
D0
D1
1F C0
1F C1
01
*
*
*
0
–
–
2
2
3
3
2
1
2
2
3
3
3
3
4
4
2
2
2
2
3
3
3
3
4
4
2
3
2
3
2
2
3
4
3
4
3
4
3
3
2
3
3
4
3
4
3
4
3
3
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
C
IR
R
SRL dst
*
*
0
*
–
–
0
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
SRP src
STOP
RP ← src
IM
–
–
*
–
–
*
–
–
*
–
–
*
–
–
1
–
–
*
STOP Mode
dst ← dst – src
6F
SUB dst, src
r
r
r
22
Ir
23
R
R
24
R
IR
IM
IM
ER
IM
25
R
26
IR
ER
ER
R
27
SUBX dst, src dst ← dst – src
28
*
*
*
*
*
*
*
*
1
–
–
*
29
SWAP dst
dst[7:4] dst[3:0]
F0
X
–
X
0
–
–
IR
r
F1
TCM dst, src
(NOT dst) AND src
r
62
r
Ir
63
R
R
64
R
IR
IM
IM
ER
IM
65
R
66
IR
ER
ER
67
TCMX dst, src (NOT dst) AND src
Note: Flags Notation:
68
–
*
*
0
–
–
69
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS025113-1212
eZ8 CPU Instruction Summary
Z8 Encore!® F0830 Series
Product Specification
179
Table 113. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Code(s)
(Hex)
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Fetch Instr.
Symbolic Operation
dst
r
src
r
TM dst, src
dst AND src
72
73
74
75
76
77
78
79
F2
–
*
*
0
–
–
2
2
3
3
3
3
4
4
2
3
4
3
4
3
4
3
3
6
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
TMX dst, src
dst AND src
–
–
*
*
0
–
–
–
–
–
TRAP Vector SP ← SP – 2
@SP ← PC
Vec-
tor
–
–
SP ← SP – 1
@SP ← FLAGS
PC ← @Vector
WDT
5F
B2
B3
B4
B5
B6
B7
B8
B9
–
–
–
*
–
*
–
0
–
–
–
–
1
2
2
3
3
3
3
4
4
2
3
4
3
4
3
4
3
3
XOR dst, src
dst ← dst XOR src
r
r
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
XORX dst, src dst ← dst XOR src
–
*
*
0
–
–
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS025113-1212
eZ8 CPU Instruction Summary
Z8 Encore!® F0830 Series
Product Specification
180
Op Code Maps
A description of the opcode map data and the abbreviations are provided in Figure 28.
Table 114 on page 181 lists opcode map abbreviations.
Op Code
Lower Nibble
Fetch Cycles
Instruction Cycles
4
3.3
CP
Op Code
Upper Nibble
A
R2,R1
First Operand
After Assembly
Second Operand
After Assembly
Figure 28. Op Code Map Cell Description
PS025113-1212
Op Code Maps
Z8 Encore!® F0830 Series
Product Specification
181
Table 114. Op Code Map Abbreviations
Abbreviation
Description
Abbreviation
Description
b
Bit position
IRR
Indirect Register Pair
Polarity (0 or 1)
cc
X
Condition code
p
r
8-bit signed index or displace-
ment
4-bit Working Register
DA
ER
Destination address
R
8-bit register
Extended Addressing Register r1, R1, Ir1, Irr1,
Destination address
IR1, rr1, RR1,
IRR1, ER1
IM
Immediate data value
r2, R2, Ir2, Irr2,
IR2, rr2, RR2,
IRR2, ER2
Source address
Ir
Indirect Working Register
Indirect Register
RA
rr
Relative
IR
Irr
Working Register Pair
Register Pair
Indirect Working Register Pair
RR
PS025113-1212
Op Code Maps
Z8 Encore!® F0830 Series
Product Specification
182
Figures 29 and 30 provide information about each of the eZ8 CPU instructions.
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1.1
2.2
2.3
2.4
3.3
3.4
3.3
3.4
4.3
4.3
2.3
2.2
JR
cc,X
2.2
LD
r1,IM
3.2
JP
cc,DA
1.2
INC
r1
1.2
NOP
BRK SRP ADD ADD ADD ADD ADD ADD ADDX ADDX DJNZ
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IM
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
r1,X
2.2
RLC
R1
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
See 2nd
Op Code
Map
RLC ADC ADC ADC ADC ADC ADC ADCX ADCX
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
INC
R1
2.3
INC
IR1
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
SUB SUB SUB SUB SUB SUB SUBX SUBX
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
DEC DEC SBC SBC SBC SBC SBC SBC SBCX SBCX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
DA
R1
2.3
DA
IR1
2.3
OR
r1,r2
2.4
OR
r1,Ir2
3.3
OR
R2,R1
3.4
OR
IR2,R1
3.3
OR
R1,IM
3.4
4.3
4.3
OR
ORX ORX
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
1.2
WDT
POP POP AND AND AND AND AND AND ANDX ANDX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
1.2
STOP
COM COM TCM TCM TCM TCM TCM TCM TCMX TCMX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
TM
r1,Ir2
3.3
TM
R2,R1
3.4
TM
IR2,R1
3.3
TM
R1,IM
3.4
4.3
4.3
1.2
HALT
PUSH PUSH TM
R2
TM
TMX TMX
IR2
r1,r2
IR1,IM ER2,ER1 IM,ER1
2.5
2.6
2.5
2.9
3.2
3.3
LDX
3.4
LDX
3.5
3.4
3.4
1.2
DI
DECW DECW LDE LDEI LDX
RR1
LDX
LDX
LDX
IRR1
r1,Irr2
Ir1,Irr2 r1,ER2 Ir1,ER2 IRR2,R1 IRR2,IR1 r1,rr2,X rr1,r2,X
2.2
RL
R1
2.3
RL
IR1
2.5
2.9
3.2
3.3
LDX
3.4
LDX
3.5
3.3
3.5
1.2
EI
LDE LDEI LDX
r2,Irr1
LDX
LEA
LEA
Ir2,Irr1 r2,ER1 Ir2,ER1 R2,IRR1 IR2,IRR1 r1,r2,X rr1,rr2,X
2.5
2.6
2.3
CP
r1,r2
2.4
CP
r1,Ir2
3.3
CP
R2,R1
3.4
CP
IR2,R1
3.3
CP
R1,IM
3.4
4.3
4.3
1.4
RET
INCW INCW
RR1
CP
CPX
CPX
IRR1
IR1,IM ER2,ER1 IM,ER1
2.2
CLR
R1
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
1.5
IRET
CLR XOR XOR XOR XOR XOR XOR XORX XORX
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
3.4 3.2
LD PUSHX
2.2
2.3
2.5
2.9
2.3
JP
IRR1
2.9
LDC
Ir1,Irr2
1.2
RCF
RRC RRC LDC LDCI
R1
IR1
r1,Irr2
Ir1,Irr2
r1,r2,X
ER2
2.2
2.3
2.5
2.9
2.6
2.2
3.3
3.4
LD
r2,r1,X
3.2
POPX
ER1
1.2
SCF
SRA SRA LDC LDCI CALL BSWAP CALL
R1
IR1
r2,Irr1
Ir2,Irr1
IRR1
R1
DA
2.2
RR
R1
2.3
RR
IR1
2.2
BIT
p,b,r1
2.3
LD
r1,Ir2
3.2
LD
R2,R1
3.3
LD
IR2,R1
3.2
LD
R1,IM
3.3
4.2
4.2
1.2
CCF
LD
LDX
LDX
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.6
2.3
LD
Ir1,r2
2.8
MULT
RR1
3.3
LD
3.3
BTJ
3.4
BTJ
SWAP SWAP TRAP
R1
IR1
Vector
R2,IR1 p,b,r1,X p,b,Ir1,X
Figure 29. First Op Code Map
PS025113-1212
Op Code Maps
Z8 Encore!® F0830 Series
Product Specification
183
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
3.2
PUS
3.3
3.4
4.3
4.4
4.3
4.4
5.3
5.3
CPC CPC
r1,r2
CPC CPC
R2,R1
CPC CPC CPCX CPCX
R1,IM
r1,Ir2
IR2,R1
IR1,IM ER2,ER1 IM,ER1
3.2
SRL
R1
3.3
SRL
IR1
5, 4
LDWX
ER2,ER1
Figure 30. Second Op Code Map after 1FH
PS025113-1212
Op Code Maps
Z8 Encore!® F0830 Series
Product Specification
184
Electrical Characteristics
The data in this chapter represents all known data prior to qualification and characteriza-
tion of the F0830 Series of products, and is therefore subject to change. Additional electri-
cal characteristics may be found in the individual chapters of this document.
Absolute Maximum Ratings
Stresses greater than those listed in Table 115 may cause permanent damage to the device.
These ratings are stress ratings only. Operation of the device at any condition outside those
indicated in the operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
For improved reliability, tie unused inputs to one of the supply voltages (VDD or VSS).
Table 115. Absolute Maximum Ratings
Parameter
Minimum Maximum
Units
°C
Notes
Ambient temperature under bias
Storage temperature
0
+105
+150
+5.5
+3.6
+5
–65
–0.3
–0.3
–5
°C
Voltage on any pin with respect to V
V
SS
Voltage on V pin with respect to V
V
DD
SS
Maximum current on input and/or inactive output pin
Maximum output current from active output pin
µA
mA
–25
+25
20-pin Packages Maximum Ratings at 0°C to 70°C
Total power dissipation
430
120
mW
mA
Maximum current into V or out of V
DD
SS
28-pin Packages Maximum Ratings at 0°C to 70°C
Total power dissipation
450
125
mW
mA
Maximum current into V or out of V
DD
SS
PS025113-1212
Electrical Characteristics
Z8 Encore!® F0830 Series
Product Specification
185
DC Characteristics
Table 116 lists the DC characteristics of the Z8 Encore! F0830 Series products. All volt-
ages are referenced to VSS, the primary system ground.
Table 116. DC Characteristics
T = 0°C to +70°C T = –40°C to +105°C
A
A
Symbol Parameter
Min Typ Max
Min
2.7
Typ
Max Units Conditions
V
Supply Voltage
–
3.6
V
Power supply noise not
to exceed 100mV peak
to peak
DD
V
V
V
Low Level Input
Voltage
–0.3
–0.3
2.0
–
–
–
0.3*V
D
V
V
V
For all input pins except
RESET.
IL1
IL2
IH1
D
Low Level Input
Voltage
0.8
For RESET.
High Level Input
Voltage
5.5
For all input pins without
analog or oscillator func-
tion.
V
V
High Level Input
Voltage
2.0
–
–
–
V
+0.
DD
3
V
V
For those pins with ana-
log or oscillator function.
IH2
Low Level
0.4
I
= 2mA; V = 3.0V
OL DD
OL1
Output Voltage
High Output Drive dis-
abled.
V
V
V
High Level
Output Voltage
2.4
–
–
–
–
–
0.6
–
V
V
V
I
= –2mA; V = 3.0V
OH DD
OH1
OL2
OH2
High Output Drive dis-
abled.
Low Level
Output Voltage
I
= 20mA; V = 3.3V
OL DD
High Output Drive
enabled.
High Level
2.4
I
= –20mA;
OH
Output Voltage
V
= 3.3V
DD
High Output Drive
enabled.
I
Input Leakage
Current
–5
–5
–
–
+5
+5
µA
µA
V
V
= 3.6V;
DD
IL
1
= V or V
IN
DD
SS
I
Tristate Leakage
Current
V
= 3.6V
DD
TL
Notes:
1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.
3. See Figure 31 for HALT Mode current.
PS025113-1212
DC Characteristics
Z8 Encore!® F0830 Series
Product Specification
186
Table 116. DC Characteristics (Continued)
T = 0°C to +70°C T = –40°C to +105°C
A
A
Symbol Parameter
Min Typ Max
Min
1.5
2.8
7.8
12
–
Typ
3
Max Units Conditions
I
Controlled
4.5
10.5
19.5
30
mA See GPIO section on
LED
Current Drive
LED description
7
mA
13
20
mA
mA
2
C
C
C
GPIO Port Pad
Capacitance
8.0
–
pF TBD
PAD
2
XIN Pad
Capacitance
–
–
8.0
–
–
pF TBD
pF TBD
XIN
2
XOUT Pad
9.5
XOUT
Capacitance
I
Weak Pull-up
Current
50
120
TBD
220
µA
mA
V
= 2.7 - 3.6V
DD
PU
3
ICCH
ICCS
Supply Current
in HALT Mode
TBD
2
8
Supply Current
in STOP Mode
µA Without Watchdog Timer
running
Notes:
1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.
3. See Figure 31 for HALT Mode current.
PS025113-1212
DC Characteristics
Z8 Encore!® F0830 Series
Product Specification
187
Figure 31 displays the typical current consumption while operating at 25 ºC, 3.3V, versus
the system clock frequency in HALT Mode.
Figure 31. I Versus System Clock Frequency (HALT Mode)
CC
PS025113-1212
DC Characteristics
Z8 Encore!® F0830 Series
Product Specification
188
Figure 32 displays the typical current consumption versus the system clock frequency in
NORMAL Mode.
Figure 32. I Versus System Clock Frequency (NORMAL Mode)
CC
PS025113-1212
DC Characteristics
Z8 Encore!® F0830 Series
Product Specification
189
AC Characteristics
The section provides information about the AC characteristics and timing. All AC timing
information assumes a standard load of 50pF on all outputs.
Table 117. AC Characteristics
V
= 2.7 to 3.6V
DD
V
= 2.7 to 3.6V
T = –40°C to
DD
A
T = 0°C to +70°C
+105°C
A
Symbol Parameter
Min
Max
Min
Max
Units Conditions
FSYSCLK System Clock Fre-
quency
–
20.0
MHz Read-only from Flash
memory
0.03276
8
20.0
20.0
MHz Program or erasure of
the Flash memory
F
F
Crystal Oscillator
Frequency
1.0
MHz System clock frequen-
cies below the crystal
oscillator minimum
XTAL
IPO
require an external
Internal Precision
Oscillator Frequency
0.03276 5.5296
8
MHz Oscillator is not adjust-
able over the entire
range. User may select
Min or Max value only.
F
F
F
F
T
T
T
Internal Precision
Oscillator Frequency
5.31
4.15
30.7
24
5.75
6.91
33.3
40
MHz High speed with trim-
ming
IPO
IPO
IPO
IPO
XIN
XINH
Internal Precision
Oscillator Frequency
MHz High speed without
trimming
Internal Precision
Oscillator Frequency
KHz Low speed with trim-
ming
Internal Precision
Oscillator Frequency
KHz Low speed without
trimming
System Clock
Period
50
–
ns
ns
ns
T
T
T
= 1/F
sysclk
CLK
CLK
CLK
System Clock High
Time
20
30
= 50 ns
= 50 ns
System Clock Low
Time
20
30
XINL
PS025113-1212
AC Characteristics
Z8 Encore!® F0830 Series
Product Specification
190
Table 117. AC Characteristics (Continued)
= 2.7 to 3.6V
V
DD
V
= 2.7 to 3.6V
T = –40°C to
DD
A
T = 0°C to +70°C
+105°C
A
Symbol Parameter
Min
Max
Min
Max
Units Conditions
T
T
T
T
System Clock Rise
Time
–
3
ns
T
= 50 ns
XINR
CLK
System Clock Fall
Time
–
–
–
3
ns
T
= 50 ns
XINF
CLK
Crystal Oscillator
Setup Time
30,000 cycle Crystal oscillator cycles
XTALSET
IPOSET
Internal Precision
Oscillator Startup
Time
25
50
µs Startup time after
enable
T
WDT Startup Time
–
µs Startup time after reset
WDTSET
On-Chip Peripheral AC and DC Electrical Characteristics
Table 118. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing
T = –40°C to
A
T = 0°C to +70°C
+105°C
A
1
Symbol Parameter
Min
Typ
Max
Min Typ
Max Units Conditions
V
Power-On Reset
Voltage Threshold
2.20 2.45 2.70
V
V
= V
DD POR
POR
(default VBO trim)
V
Voltage Brown-Out
Reset Voltage
Threshold
2.15 2.40 2.65
V
V
DD
= V
VBO
VBO
(default VBO trim)
V
to V
50
75
–
mV
V
POR
VBO
hysteresis
Starting V
–
–
V
SS
DD
voltage to ensure
valid Power-On
Reset.
T
Power-On Reset
Analog Delay
50
–
µs
V
> V ; T
POR POR
ANA
DD
Digital Reset delay
follows T
ANA
Note: 1Data in the typical column is from characterization at 3.3V and 0°C. These values are provided for design guid-
ance only and are not tested in production.
PS025113-1212
On-Chip Peripheral AC and DC Electrical
Z8 Encore!® F0830 Series
Product Specification
191
Table 118. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing
T = –40°C to
A
T = 0°C to +70°C
+105°C
A
1
Symbol Parameter
Min
Typ
Max
Min Typ
Max Units Conditions
T
T
T
Power-On Reset
Digital Delay
TBD
TBD
TBD
13
TBD
TBD
TBD
µs 66 Internal Preci-
sion Oscillator
cycles
POR
POR
SMR
Power-On Reset
Digital Delay
8
ms 5000 Internal Pre-
cision Oscillator
cycles
Stop Mode
13
µs 66 Internal Preci-
sion Oscillator
cycles
Recovery with
crystal oscillator
disabled
T
Stop Mode
TBD
8
TBD
ms 5000 Internal Pre-
cision Oscillator
cycles
SMR
Recovery with
crystal oscillator
enabled
T
T
Voltage Brown-Out
Pulse Rejection
Period
µs
V
< V
to gen-
VBO
–
10
–
VBO
DD
erate a Reset.
Time for V to
0.10
–
100
ms
RAMP
DD
transition from V
SS
to V
to ensure
POR
valid Reset
Note: 1Data in the typical column is from characterization at 3.3V and 0°C. These values are provided for design guid-
ance only and are not tested in production.
PS025113-1212
On-Chip Peripheral AC and DC Electrical
Z8 Encore!® F0830 Series
Product Specification
192
Table 119. Flash Memory Electrical Characteristics and Timing
= 2.7 to 3.6V = 2.7 to 3.6V
V
V
DD
DD
T = 0°C to +70°C
T = –40°C to +105°C
A
A
Parameter
Min
Typ
Max
Min
Typ
Max
Units Notes
Flash Byte Read
Time
50
–
–
ns
Flash Byte Program
Time
20
50
50
–
–
–
–
–
–
–
–
2
µs
ms
ms
Flash Page Erase
Time
Flash Mass Erase
Time
Writes to Single
Address Before Next
Erase
Flash Row Program
Time
–
–
8
ms Cumulative pro-
gram time for single
row cannot exceed
limit before next
erase. This parame-
ter is only an issue
when bypassing the
Flash Controller.
Data Retention
Endurance
10
–
–
–
–
years 25°C
10,000
cycles Program/erase
cycles
Table 120. Watchdog Timer Electrical Characteristics and Timing
= 2.7 - 3.6V
V
DD
V
= 2.7 to 3.6V
T = –40°C to
DD
A
T = 0°C to +70°C
+105°C
A
Symbol Parameter
Min
Typ
Max
Min
Typ
Max Units Conditions
Active power
consumption
2
3
µA
F
WDT oscillator
frequency
2.5
5
7.5
kHz
WDT
PS025113-1212
On-Chip Peripheral AC and DC Electrical
Z8 Encore!® F0830 Series
Product Specification
193
Table 121. Nonvolatile Data Storage
= 2.7 to 3.6V = 2.7 to 3.6V
V
V
DD
DD
T = 0°C to +70°C
T = –40°C to +105°C
A
A
Parameter
Min
Typ
Max
Min
Typ
Max
Units Notes
NVDS Byte Read
Time
71
–
258
µs Withsystemclockat
20MHz
NVDS Byte Pro-
gram Time
126
–
136
µs Withsystemclockat
20MHz
Data Retention
Endurance
10
–
–
–
–
years 25°C
100,000
cycles Cumulative write
cycles for entire
memory
For every 200 writes, a maintenance operation is necessary. In this rare occurrence, the
write can take up to 58ms to complete.
Note:
Table 122. Analog-to-Digital Converter Electrical Characteristics and Timing
V
= 2.7 to 3.6V
V
= 2.7 to 3.6V
DD
DD
T = 0°C to +70°C
T = –40°C to +105°C
A
A
Symbol Parameter
Resolution
Min
Typ
Max
Min
–
Typ
10
–
Max Units Conditions
–
bits
Differential
–1
+4
LSB
Nonlinearity (DNL) 1
Integral
–5
–
+5
LSB
LSB
Nonlinearity (INL) 1
Gain Error
15
Offset Error
–15
–9
–
–
15
9
LSB PDIP package
LSB Other packages
V
On chip reference
1.9
2.0
4
2.1
V
REF
Active Power
Consumption
mA
Power Down
Current
1
µA
Note: 1When the input voltage is lower than 20mV, the conversion error is out of spec.
PS025113-1212
On-Chip Peripheral AC and DC Electrical
Z8 Encore!® F0830 Series
Product Specification
194
Table 122. Analog-to-Digital Converter Electrical Characteristics and Timing (Continued)
V
= 2.7 to 3.6V
V
= 2.7 to 3.6V
DD
DD
T = 0°C to +70°C
T = –40°C to +105°C
A
A
Symbol Parameter
Min
Typ
Max
Min
10
0
Typ
Max Units Conditions
Z
Input Impedance
MΩ
IN
V
Input Voltage
Range
2.0
V
Internal refer-
ence
IN
0
0.9*VD
D
External refer-
ence
Conversion Time
11.9
µs 20MHz (ADC
Clock)
Input Bandwidth
Wake Up Time
500
KHz
0.02
ms Internal refer-
ence
10
50
External refer-
ence
Input Clock Duty
45
55
20
Maximum Input
Clock Frequency
MHz
Note: 1When the input voltage is lower than 20mV, the conversion error is out of spec.
Table 123. Comparator Electrical Characteristics
V
= 2.7 to 3.6V
V
= 2.7 to 3.6V
DD
DD
T = 0°C to +70°C
T = –40°C to +105°C
A
A
Symbol Parameter
Min
Typ
Max
Min
Typ
Max Units Conditions
V
V
Input DC Offset
5
mV
OS
Programmable
Internal Reference
Voltage Range
0
1.8
V
User-program-
mable in 200
mV step
CREF
V
Programmable
internal reference
voltage
0.92
1.0
1.08
V
Default
(CMP0[REFLVL]
=5H)
CREF
T
Propagation delay
Input hysteresis
100
8
ns
PROP
V
mV
HYS
PS025113-1212
On-Chip Peripheral AC and DC Electrical
Z8 Encore!® F0830 Series
Product Specification
195
General Purpose I/O Port Input Data Sample Timing
Figure 33 displays timing of the GPIO port input sampling. The input value on a GPIO
port pin is sampled on the rising edge of the system clock. The port value is available to
the eZ8 CPU on the second rising clock edge following the change of the port value.
TCLK
System
Clock
Port Value
Changes to 0
Port Pin
Input Value
Port Input Data
Register Latch
0 Latched
Into Port Input
Data Register
Port Input Data Register
Value 0 Read
by eZ8
Port Input Data
Read on Data Bus
Figure 33. Port Input Sample Timing
Table 124. GPIO Port Input Timing
Delay (ns)
Parameter Abbreviation
Minimum
Maximum
T
T
T
Port Input Transition to X Rise Setup Time (not pictured)
5
0
–
–
S_PORT
H_PORT
SMR
IN
X
Rise to Port Input Transition Hold Time (not pictured)
IN
GPIO port pin pulse width to ensure Stop Mode Recovery (for
GPIO port pins enabled as SMR sources)
1µs
PS025113-1212
On-Chip Peripheral AC and DC Electrical
Z8 Encore!® F0830 Series
Product Specification
196
General Purpose I/O Port Output Timing
Figure 34 and Table 125 provide timing information for the GPIO port pins.
TCLK
XIN
T1
T2
Port Output
Figure 34. GPIO Port Output Timing
Table 125. GPIO Port Output Timing
Delay (ns)
Parameter Abbreviation
GPIO Port Pins
Minimum
Maximum
T
T
XIN Rise to Port Output Valid Delay
XIN Rise to Port Output Hold Time
–
2
15
–
1
2
PS025113-1212
On-Chip Peripheral AC and DC Electrical
Z8 Encore!® F0830 Series
Product Specification
197
On-Chip Debugger Timing
Figure 35 and Table 126 provide timing information for the DBG pin. The DBG pin tim-
ing specifications assume a 4 ns maximum rise and fall time.
TCLK
XIN
T1
T2
T4
DBG
(Output)
Output Data
T3
DBG
(Input)
Input Data
Figure 35. On-Chip Debugger Timing
Table 126. On-Chip Debugger Timing
Delay (ns)
Parameter Abbreviation
DBG
Minimum
Maximum
T
T
T
T
XIN Rise to DBG Valid Delay
–
2
5
5
15
–
1
2
3
4
XIN Rise to DBG Output Hold Time
DBG to XIN Rise Input Setup Time
DBG to XIN Rise Input Hold Time
–
–
PS025113-1212
On-Chip Peripheral AC and DC Electrical
Z8 Encore!® F0830 Series
Product Specification
198
Table 127. Power Consumption Reference Table
Power Consumption
Category
Logic
Block
Typical
Maximum
CPU/Peripherals @20MHz
Flash @20MHz
ADC @20MHz
IPO
5mA
Flash
12mA
4.5mA
400µA
450µA
150µA
3µA
4mA
350µA
330µA
120µA
2µA
Comparator @10MHz
POR & VBO
Analog
WDT Oscillator
OSC @20MHz
Clock Filter
600µA
120µA
900µA
150µA
Note: The values in this table are subject to change after characterization.
Figure 36. Flash Current Diagram
PS025113-1212
On-Chip Peripheral AC and DC Electrical
Z8 Encore!® F0830 Series
Product Specification
199
Packaging
Zilog’s F0830 Series of MCUs includes the Z8F0130, Z8F0131, Z8F0230, Z8F0231,
Z8F1232 and Z8F1233 devices, which are available in the following packages:
•
•
•
•
•
•
•
•
20-Pin Quad Flat No-Lead Package (QFN)
20-pin Small Outline Integrated Circuit Package (SOIC)
20-pin Plastic Dual-Inline Package (PDIP)
20-pin Small Shrink Outline Package (SSOP)
28-Pin Quad Flat No-Lead Package (QFN)
28-pin Small Outline Integrated Circuit Package (SOIC)
28-pin Plastic Dual-Inline Package (PDIP)
28-pin Small Shrink Outline Package (SSOP)
Current diagrams for each of these packages are published in Zilog’s Packaging Product
Specification (PS0072), which is available free for download from the Zilog website.
PS025113-1212
Packaging
Z8 Encore!® F0830 Series
Product Specification
200
Ordering Information
Order your F0830 Series products from Zilog using the part numbers shown in Table 128.
For more information about ordering, please consult your local Zilog sales office. The
Sales Location page on the Zilog website lists all regional offices.
Table 128. Z8 Encore! XP F0830 Series Ordering Matrix
ADC
Part Number
Flash
RAM
NVDS Channels Description
Z8 Encore! F0830 Series MCUs with 12KB Flash
Standard Temperature: 0°C to 70°C
Z8F1232SH020SG
Z8F1232HH020SG
Z8F1232PH020SG
Z8F1232QH020SG
Z8F1233SH020SG
Z8F1233HH020SG
Z8F1233PH020SG
Z8F1233QH020SG
Z8F1232SJ020SG
Z8F1232HJ020SG
Z8F1232PJ020SG
Z8F1232QJ020SG
Z8F1233SJ020SG
Z8F1233HJ020SG
Z8F1233PJ020SG
Z8F1233QJ020SG
12KB
12KB
12KB
12KB
12KB
12KB
12KB
12KB
12KB
12KB
12KB
12KB
12KB
12KB
12KB
12KB
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
7
7
7
7
0
0
0
0
8
8
8
8
0
0
0
0
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
Extended Temperature: –40°C to 105°C
Z8F1232SH020EG
Z8F1232HH020EG
Z8F1232PH020EG
Z8F1232QH020EG
Z8F1233SH020EG
Z8F1233HH020EG
Z8F1233PH020EG
12KB
12KB
12KB
12KB
12KB
12KB
12KB
256
256
256
256
256
256
256
No
No
No
No
No
No
No
7
7
7
7
0
0
0
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
PS025113-1212
Ordering Information
Z8 Encore!® F0830 Series
Product Specification
201
Table 128. Z8 Encore! XP F0830 Series Ordering Matrix
ADC
Part Number
Flash
12KB
12KB
12KB
12KB
12KB
12KB
12KB
12KB
12KB
RAM
256
256
256
256
256
256
256
256
256
NVDS Channels Description
Z8F1233QH020EG
Z8F1232SJ020EG
Z8F1232HJ020EG
Z8F1232PJ020EG
Z8F1232QJ020EG
Z8F1233SJ020EG
Z8F1233HJ020EG
Z8F1233PJ020EG
Z8F1233QJ020EG
No
No
No
No
No
No
No
No
No
0
8
8
8
8
0
0
0
0
QFN 20-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
Z8 Encore! F0830 with 8KB Flash
Standard Temperature: 0°C to 70°C
Z8F0830SH020SG
Z8F0830HH020SG
Z8F0830PH020SG
Z8F0830QH020SG
Z8F0831SH020SG
Z8F0831HH020SG
Z8F0831PH020SG
Z8F0831QH020SG
Z8F0830SJ020SG
Z8F0830HJ020SG
Z8F0830PJ020SG
Z8F0830QJ020SG
Z8F0831SJ020SG
Z8F0831HJ020SG
Z8F0831PJ020SG
Z8F0831QJ020SG
8KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
7
7
7
7
0
0
0
0
8
8
8
8
0
0
0
0
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
Extended Temperature: –40°C to 105°C
Z8F0830SH020EG
Z8F0830HH020EG
Z8F0830PH020EG
Z8F0830QH020EG
Z8F0831SH020EG
8KB
8KB
8KB
8KB
8KB
256
256
256
256
256
Yes
Yes
Yes
Yes
Yes
7
7
7
7
0
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 20-pin
PS025113-1212
Ordering Information
Z8 Encore!® F0830 Series
Product Specification
202
Table 128. Z8 Encore! XP F0830 Series Ordering Matrix
ADC
Part Number
Flash
8KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
RAM
256
256
256
256
256
256
256
256
256
256
256
NVDS Channels Description
Z8F0831HH020EG
Z8F0831PH020EG
Z8F0831QH020EG
Z8F0830SJ020EG
Z8F0830HJ020EG
Z8F0830PJ020EG
Z8F0830QJ020EG
Z8F0831SJ020EG
Z8F0831HJ020EG
Z8F0831PJ020EG
Z8F0831QJ020EG
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0
0
0
8
8
8
8
0
0
0
0
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
Z8 Encore! F0830 with 4KB Flash
Standard Temperature: 0°C to 70°C
Z8F0430SH020SG
Z8F0430HH020SG
Z8F0430PH020SG
Z8F0430QH020SG
Z8F0431SH020SG
Z8F0431HH020SG
Z8F0431PH020SG
Z8F0431QH020SG
Z8F0430SJ020SG
Z8F0430HJ020SG
Z8F0430PJ020SG
Z8F0430QJ020SG
Z8F0431SJ020SG
Z8F0431HJ020SG
Z8F0431PJ020SG
Z8F0431QJ020SG
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
7
7
7
7
0
0
0
0
8
8
8
8
0
0
0
0
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
Extended Temperature: –40°C to 105°C
Z8F0430SH020EG
Z8F0430HH020EG
Z8F0430PH020EG
4KB
4KB
4KB
256
256
256
Yes
Yes
Yes
7
7
7
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
PS025113-1212
Ordering Information
Z8 Encore!® F0830 Series
Product Specification
203
Table 128. Z8 Encore! XP F0830 Series Ordering Matrix
ADC
Part Number
Flash
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
RAM
256
256
256
256
256
256
256
256
256
256
256
256
256
NVDS Channels Description
Z8F0430QH020EG
Z8F0431SH020EG
Z8F0431HH020EG
Z8F0431PH020EG
Z8F0431QH020EG
Z8F0430SJ020EG
Z8F0430HJ020EG
Z8F0430PJ020EG
Z8F0430QJ020EG
Z8F0431SJ020EG
Z8F0431HJ020EG
Z8F0431PJ020EG
Z8F0431QJ020EG
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
7
0
0
0
0
8
8
8
8
0
0
0
0
QFN 20-pin
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
Z8 Encore! F0830 with 2KB Flash
Standard Temperature: 0°C to 70°C
Z8F0230SH020SG
Z8F0230HH020SG
Z8F0230PH020SG
Z8F0230QH020SG
Z8F0231SH020SG
Z8F0231HH020SG
Z8F0231PH020SG
Z8F0231QH020SG
Z8F0230SJ020SG
Z8F0230HJ020SG
Z8F0230PJ020SG
Z8F0230QJ020SG
Z8F0231SJ020SG
Z8F0231HJ020SG
Z8F0231PJ020SG
Z8F0231QJ020SG
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
7
7
7
7
0
0
0
0
8
8
8
8
0
0
0
0
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
PS025113-1212
Ordering Information
Z8 Encore!® F0830 Series
Product Specification
204
Table 128. Z8 Encore! XP F0830 Series Ordering Matrix
ADC
Part Number
Flash
RAM
NVDS Channels Description
Extended Temperature: –40°C to 105°C
Z8F0230SH020EG
Z8F0230HH020EG
Z8F0230PH020EG
Z8F0230QH020EG
Z8F0231SH020EG
Z8F0231HH020EG
Z8F0231PH020EG
Z8F0231QH020EG
Z8F0230SJ020EG
Z8F0230HJ020EG
Z8F0230PJ020EG
Z8F0230QJ020EG
Z8F0231SJ020EG
Z8F0231HJ020EG
Z8F0231PJ020EG
Z8F0231QJ020EG
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
2KB
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
7
7
7
7
0
0
0
0
8
8
8
8
0
0
0
0
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
Z8 Encore! F0830 with 1KB Flash
Standard Temperature: 0°C to 70°C
Z8F0130SH020SG
Z8F0130HH020SG
Z8F0130PH020SG
Z8F0130QH020SG
Z8F0131SH020SG
Z8F0131HH020SG
Z8F0131PH020SG
Z8F0131QH020SG
Z8F0130SJ020SG
Z8F0130HJ020SG
Z8F0130PJ020SG
Z8F0130QJ020SG
Z8F0131SJ020SG
Z8F0131HJ020SG
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
256
256
256
256
256
256
256
256
256
256
256
256
256
256
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
7
7
7
7
0
0
0
0
8
8
8
8
0
0
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
SOIC 28-pin
SSOP 28-pin
PS025113-1212
Ordering Information
Z8 Encore!® F0830 Series
Product Specification
205
Table 128. Z8 Encore! XP F0830 Series Ordering Matrix
ADC
Part Number
Flash
1KB
RAM
256
NVDS Channels Description
Z8F0131PJ020SG
Z8F0131QJ020SG
Yes
Yes
0
0
PDIP 28-pin
QFN 28-pin
1KB
256
Extended Temperature: –40°C to 105°C
Z8F0130SH020EG
Z8F0130HH020EG
Z8F0130PH020EG
Z8F0130QH020EG
Z8F0131SH020EG
Z8F0131HH020EG
Z8F0131PH020EG
Z8F0131QH020EG
Z8F0130SJ020EG
Z8F0130HJ020EG
Z8F0130PJ020EG
Z8F0130QJ020EG
Z8F0131SJ020EG
Z8F0131HJ020EG
Z8F0131PJ020EG
Z8F0131QJ020EG
ZUSBSC00100ZACG
ZUSBOPTSC01ZACG
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
7
7
7
7
0
0
0
0
8
8
8
8
0
0
0
0
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 20-pin
SSOP 20-pin
PDIP 20-pin
QFN 20-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
SOIC 28-pin
SSOP 28-pin
PDIP 28-pin
QFN 28-pin
USB Smart Cable Accessory Kit
Opto-Isolated USB Smart Cable
Accessory Kit
Part Number Suffix Designations
Zilog part numbers consist of a number of components, as indicated in the following
example.
Example. Part number Z8F0830SH020SG is an 8-bit 20MHz Flash MCU with 8KB Pro-
gram Memory and equipped with ADC and NVDS in a 20-pin SOIC package, operating
within a 0ºC to +70ºC temperature range and built using lead-free solder.
PS025113-1212
Part Number Suffix Designations
Z8 Encore!® F0830 Series
Product Specification
206
Z8
F
08 30
S
H
020
S
G
Environmental Flow
G = Green Plastic Packaging Compound
Temperature Range
S = Standard, 0°C to 70°C
E = Extended, –40°C to +105°C
Speed
020 = 20MHz
Pin Count*
H = 20
J = 28
Package*
P = PDIP
Q = QFN
S = SOIC
H = SSOP
Device Type
30 = Equipped with ADC and with NVDS.
31 = Equipped without ADC and with NVDS.
32 = Equipped with ADC and without NVDS (12 K
version only).
33 = Equipped without ADC and without NVDS (12 K
version only).
Memory Size
12 = 12KB Flash
08 = 8KB Flash
04 = 4KB Flash
02 = 2KB Flash
01 = 1KB Flash
Memory Type
F = Flash
Device Family
Z8 = Zilog’s 8-bit microcontroller
PS025113-1212
Part Number Suffix Designations
Z8 Encore!® F0830 Series
Product Specification
207
Table 129 lists the pin count by package.
Table 129. Package and Pin Count Description
Pin Count
Package
PDIP
20
√
28
√
QFN
√
√
SOIC
√
√
SSOP
√
√
PS025113-1212
Part Number Suffix Designations
Z8 Encore!® F0830 Series
Product Specification
208
Appendix A. Register Tables
For the reader’s convenience, this appendix lists all F0830 Series registers numerically by
hexadecimal address.
General Purpose RAM
In the F0830 Series, the 000–EFF hexadecimal address range is partitioned for general-
purpose random access memory, as follows.
Hex Addresses: 000–0FF
This address range is reserved for general-purpose register file RAM. For more details, see
the Register File section on page 14.
Hex Addresses: 100–EFF
This address range is reserved.
Timer 0
For more information about these Timer Control registers, see the Timer Control Register
Definitions section on page 83.
Hex Address: F00
Table 130. Timer 0 High Byte Register (T0H)
Bit
7
6
5
4
3
2
1
0
Field
TH
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F00H
PS025113-1212
General Purpose RAM
Z8 Encore!® F0830 Series
Product Specification
209
Hex Address: F01
Table 131. Timer 0 Low Byte Register (T0L)
Bit
7
6
5
4
3
2
1
0
Field
TL
RESET
R/W
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F01H
Hex Address: F02
Table 132. Timer 0 Reload High Byte Register (T0RH)
Bit
7
6
5
4
3
2
1
0
Field
TRH
RESET
R/W
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F02H
Hex Address: F03
Table 133. Timer 0 Reload Low Byte Register (T0RL)
Bit
7
6
5
4
3
2
1
0
Field
TRL
RESET
R/W
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F03H
Hex Address: F04
Table 134. Timer 0 PWM High Byte Register (T0PWMH)
Bit
7
6
5
4
3
2
1
0
Field
PWMH
F04H
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
PS025113-1212
Timer 0
Z8 Encore!® F0830 Series
Product Specification
210
Hex Address: F05
Table 135. Timer 0 PWM Low Byte Register (T0PWML)
Bit
7
6
5
4
3
2
1
0
Field
PWML
F05H
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Hex Address: F06
Table 136. Timer 0 Control Register 0 (T0CTL0)
Bit
7
TMODEHI
0
6
5
4
Reserved
0
3
2
PWMD
0
1
0
INPCAP
0
Field
TICONFIG
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F06H
Hex Address: F07
Table 137. Timer 0 Control Register 1 (T0CTL1)
Bit
7
6
TPOL
0
5
4
PRES
0
3
2
1
TMODE
0
0
Field
TEN
0
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F07H
Hex Address: F08
Table 138. Timer 1 High Byte Register (T1H)
Bit
7
6
5
4
3
2
1
0
Field
TH
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F08H
PS025113-1212
Timer 0
Z8 Encore!® F0830 Series
Product Specification
211
Hex Address: F09
Table 139. Timer 1 Low Byte Register (T1L)
Bit
7
6
5
4
3
2
1
0
Field
TL
RESET
R/W
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F09H
Hex Address: F0A
Table 140. Timer 1 Reload High Byte Register (T1RH)
Bit
7
6
5
4
3
2
1
0
Field
TRH
RESET
R/W
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F0AH
Hex Address: F0B
Table 141. Timer 1 Reload Low Byte Register (T1RL)
Bit
7
6
5
4
3
2
1
0
Field
TRL
RESET
R/W
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F0BH
Hex Address: F0C
Table 142. Timer 1 PWM High Byte Register (T1PWMH)
Bit
7
6
5
4
3
2
1
0
Field
PWMH
F0CH
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
PS025113-1212
Timer 0
Z8 Encore!® F0830 Series
Product Specification
212
Hex Address: F0D
Table 143. Timer 1 PWM Low Byte Register (T1PWML)
Bit
7
6
5
4
3
2
1
0
Field
PWML
F0DH
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Hex Address: F0E
Table 144. Timer 1 Control Register 0 (T1CTL0)
Bit
7
TMODEHI
0
6
5
4
Reserved
0
3
2
PWMD
0
1
0
INPCAP
0
Field
TICONFIG
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F0EH
Hex Address: F0F
Table 145. Timer 1 Control Register 1 (T1CTL1)
Bit
7
6
TPOL
0
5
4
PRES
0
3
2
1
TMODE
0
0
Field
TEN
0
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F0FH
Hex Addresses: F10–F6F
This address range is reserved.
PS025113-1212
Timer 0
Z8 Encore!® F0830 Series
Product Specification
213
Analog-to-Digital Converter
For more information about these ADC registers, see the ADC Control Register Defini-
tions section on page 101.
Hex Address: F70
Table 146. ADC Control Register 0 (ADCCTL0)
Bit
7
START
0
6
5
4
3
2
1
ANAIN[2:0]
0
0
Field
Reserved REFEN
ADCEN Reserved
RESET
R/W
0
0
0
0
0
0
R/W1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F70h
Bit
Description
[7]
START
ADC Start/Busy
0 = Writing to 0 has no effect; reading a 0 indicates that the ADC is available to begin a conver-
sion.
1 = Writing to 1 starts a conversion; reading a 1 indicates that a conversion is currently in prog-
ress.
[6]
This bit is reserved and must be programmed to 0.
[5]
Reference Enable
REFEN 0 = Internal reference voltage is disabled allowing an external reference voltage to be used by
the ADC.
1 = Internal reference voltage for the ADC is enabled. The internal reference voltage can be
measured on the V
pin.
REF
[4]
ADC Enable
ADCEN 0 = ADC is disabled for low power operation.
1 = ADC is enabled for normal use.
[3]
This bit is reserved and must be programmed to 0.
[2:0]
ANAIN
Analog Input Select
000 = ANA0 input is selected for analog to digital conversion.
001 = ANA1 input is selected for analog to digital conversion.
010 = ANA2 input is selected for analog to digital conversion.
011 = ANA3 input is selected for analog to digital conversion.
100 = ANA4 input is selected for analog to digital conversion.
101 = ANA5 input is selected for analog to digital conversion.
110 = ANA6 input is selected for analog to digital conversion.
111 = ANA7 input is selected for analog to digital conversion.
PS025113-1212
Analog-to-Digital Converter
Z8 Encore!® F0830 Series
Product Specification
214
Hex Address: F71
This address range is reserved.
Hex Address: F72
Table 147. ADC Data High Byte Register (ADCD_H)
Bit
7
6
5
4
3
2
1
0
Field
ADCDH
RESET
R/W
X
R
Address
F72H
Bit
Description
[7:0]
ADC High Byte
00h–FFh = The last conversion output is held in the data registers until the next ADC conver-
sion is completed.
Hex Address: F73
Table 148. ADC Data Low Bits Register (ADCD_L)
Bit
7
6
5
4
3
2
1
0
Field
ADCDL
Reserved
RESET
R/W
X
R
X
R
Address
F73H
Bit
Position Description
[7:6]
ADC Low Bits
00–11b = These bits are the two least significant bits of the 10-bit ADC output. These bits are
undefined after a reset. The low bits are latched into this register whenever the ADC Data High
Byte Register is read.
[5:0]
Reserved
These bits are reserved and must be programmed to 000000.
PS025113-1212
Analog-to-Digital Converter
Z8 Encore!® F0830 Series
Product Specification
215
Hex Address: F74
Table 149. ADC Sample Settling Time (ADCSST)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
SST
R/W
RESET
R/W
0
1
1
1
1
R
Address
F74H
Bit
Description
Reserved
[7:4]
These bits are reserved and must be programmed to 0000.
[3:0]
SST
Sample Settling Time
0h–Fh = Number of system clock periods to meet 0.5 µs minimum.
Hex Address: F75
Table 150. ADC Sample Time (ADCST)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
ST
RESET
R/W
0
1
1
1
1
1
1
R/W
R/W
Address
F75H
Bit
Description
Reserved
[7:6]
This register is reserved and must be programmed to 0.
[5:0]
ST
Sample/Hold Time
0h–Fh = Number of system clock periods to meet 1 µs minimum.
Hex Addresses: F77–F7F
This address range is reserved.
PS025113-1212
Analog-to-Digital Converter
Z8 Encore!® F0830 Series
Product Specification
216
Low Power Control
For more information about the Power Control Register, see the Power Control Register
Definitions section on page 31.
Hex Address: F80
Table 151. Power Control Register 0 (PWRCTL0)
Bit
7
6
Reserved
0
5
4
3
2
1
COMP
0
0
Reserved
0
Field
VBO
0
Reserved Reserved
RESET
R/W
1
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F80H
Hex Address: F81
This address range is reserved.
LED Controller
For more information about the LED Drive registers, see the GPIO Control Register Defi-
nitions section on page 39.
Hex Address: F82
Table 152. LED Drive Enable (LEDEN)
Bit
7
6
5
4
3
2
1
0
Field
LEDEN[7:0]
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F82H
PS025113-1212
Low Power Control
Z8 Encore!® F0830 Series
Product Specification
217
Hex Address: F83
Table 153. LED Drive Level High Register (LEDLVLH)
Bit
7
6
5
4
3
2
1
0
Field
LEDLVLH[7:0]
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F83H
Hex Address: F84
Table 154. LED Drive Level Low Register (LEDLVLL)
Bit
7
6
5
4
3
2
1
0
Field
LEDLVLL[7:0]
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F84H
Hex Address: F85
This address range is reserved.
Oscillator Control
For more information about the Oscillator Control registers, see the Oscillator Control
Register Definitions section on page 154.
Hex Address: F86
Table 155. Oscillator Control Register (OSCCTL)
Bit
7
INTEN
1
6
XTLEN
0
5
WDTEN
1
4
POFEN
0
3
WDFEN
0
2
1
SCKSEL
0
0
Field
RESET
R/W
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F86H
PS025113-1212
Oscillator Control
Z8 Encore!® F0830 Series
Product Specification
218
Hex Addresses: F87–F8F
This address range is reserved.
Comparator 0
For more information about the Comparator Register, see the Comparator Control Regis-
ter Definitions section on page 107.
Hex Address: F90
Table 156. Comparator Control Register (CMP0)
Bit
7
6
5
4
3
2
1
0
Field
Reserved INNSEL
REFLVL
Reserved
RESET
R/W
0
0
0
1
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F90H
Hex Addresses: F91–FBF
This address range is reserved.
Interrupt Controller
For more information about the Interrupt Control registers, see the Interrupt Control Reg-
ister Definitions section on page 57.
Hex Address: FC0
Table 157. Interrupt Request 0 Register (IRQ0)
Bit
7
Reserved
0
6
T1I
0
5
T0I
0
4
3
2
1
0
ADCI
0
Field
Reserved Reserved Reserved Reserved
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC0H
PS025113-1212
Comparator 0
Z8 Encore!® F0830 Series
Product Specification
219
Hex Address: FC1
Table 158. IRQ0 Enable High Bit Register (IRQ0ENH)
Bit
7
6
5
4
3
2
1
0
Field
Reserved T1ENH
T0ENH Reserved Reserved Reserved Reserved ADCENH
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC1H
Hex Address: FC2
Table 159. IRQ0 Enable Low Bit Register (IRQ0ENL)
Bit
7
6
T1ENL
0
5
T0ENL
0
4
3
2
1
0
Field
Reserved
Reserved Reserved Reserved Reserved ADCENL
RESET
R/W
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R
R
R/W
Address
FC2H
Hex Address: FC3
Table 160. Interrupt Request 1 Register (IRQ1)
Bit
7
6
PA6CI
0
5
4
3
2
1
0
Field
PA7I
0
PA5I
0
PA4I
0
PA3I
0
PA2I
0
PA1I
0
PA0I
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC3H
Hex Address: FC4
Table 161. IRQ1 Enable High Bit Register (IRQ1ENH)
Bit
7
6
5
4
3
2
1
0
Field
PA7ENH PA6CENH PA5ENH PA4ENH PA3ENH PA2ENH PA1ENH PA0ENH
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC4H
PS025113-1212
Interrupt Controller
Z8 Encore!® F0830 Series
Product Specification
220
Hex Address: FC5
Table 162. IRQ1 Enable Low Bit Register (IRQ1ENL)
Bit
7
6
5
4
3
2
1
0
Field
PA7ENL PA6CENL PA5ENL PA4ENL PA3ENL PA2ENL PA1ENL PA0ENL
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC5H
Hex Address: FC6
Table 163. Interrupt Request 2 Register (IRQ2)
Bit
7
6
5
4
3
PC3I
0
2
PC2I
0
1
PC1I
0
0
PC0I
0
Field
Reserved
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC6H
Hex Address: FC7
Table 164. IRQ2 Enable High Bit Register (IRQ2ENH)
Bit
7
6
5
4
3
C3ENH
0
2
C2ENH
0
1
C1ENH
0
0
C0ENH
0
Field
Reserved
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC7H
Hex Address: FC8
Table 165. IRQ2 Enable Low Bit Register (IRQ2ENL)
Bit
7
6
5
4
3
C3ENL
0
2
C2ENL
0
1
C1ENL
0
0
C0ENL
0
Field
Reserved
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC8H
PS025113-1212
Interrupt Controller
Z8 Encore!® F0830 Series
Product Specification
221
Hex Addresses: FC9–FCC
This address range is reserved.
Hex Address: FCD
Table 166. Interrupt Edge Select Register (IRQES)
Bit
7
6
5
4
3
2
1
0
Field
IES7
0
IES6
0
IES5
0
IES4
0
IES3
0
IES2
0
IES1
0
IES0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FCDH
Hex Address: FCE
Table 167. Shared Interrupt Select Register (IRQSS)
Bit
7
Reserved
0
6
PA6CS
0
5
4
3
2
1
0
Field
Reserved
RESET
R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FCEH
Hex Address: FCF
Table 168. Interrupt Control Register (IRQCTL)
Bit
7
IRQE
0
6
5
4
3
2
1
0
Field
Reserved
RESET
R/W
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
Address
FCFH
PS025113-1212
Interrupt Controller
Z8 Encore!® F0830 Series
Product Specification
222
GPIO Port A
For more information about the GPIO registers, see the GPIO Control Register Definitions
section on page 39.
Hex Address: FD0
Table 169. Port A GPIO Address Register (PAADDR)
Bit
7
6
5
4
3
2
1
0
Field
PADDR[7:0]
RESET
R/W
00H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FD0H
Hex Address: FD1
Table 170. Port A Control Registers (PACTL)
Bit
7
6
5
4
3
2
1
0
Field
PCTL
00H
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FD1H
Hex Address: FD2
Table 171. Port A Input Data Registers (PAIN)
Bit
7
PIN7
X
6
PIN6
X
5
PIN5
X
4
PIN4
X
3
PIN3
X
2
PIN2
X
1
PIN1
X
0
PIN0
X
Field
RESET
R/W
R
R
R
R
R
R
R
R
Address
FD2H
PS025113-1212
GPIO Port A
Z8 Encore!® F0830 Series
Product Specification
223
Hex Address: FD3
Table 172. Port A Output Data Register (PAOUT)
Bit
7
POUT7
0
6
POUT6
0
5
POUT5
0
4
POUT4
0
3
POUT3
0
2
POUT2
0
1
POUT1
0
0
POUT0
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FD3H
Hex Address: FD4
Table 173. Port B GPIO Address Register (PBADDR)
Bit
7
6
5
4
3
2
1
0
Field
PADDR[7:0]
RESET
R/W
00H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FD4H
Hex Address: FD5
Table 174. Port B Control Registers (PBCTL)
Bit
7
6
5
4
3
2
1
0
Field
PCTL
00H
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FD5H
Hex Address: FD6
Table 175. Port B Input Data Registers (PBIN)
Bit
7
PIN7
X
6
PIN6
X
5
PIN5
X
4
PIN4
X
3
PIN3
X
2
PIN2
X
1
PIN1
X
0
PIN0
X
Field
RESET
R/W
R
R
R
R
R
R
R
R
Address
FD6H
PS025113-1212
GPIO Port A
Z8 Encore!® F0830 Series
Product Specification
224
Hex Address: FD7
Table 176. Port B Output Data Register (PBOUT)
Bit
7
POUT7
0
6
POUT6
0
5
POUT5
0
4
POUT4
0
3
POUT3
0
2
POUT2
0
1
POUT1
0
0
POUT0
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FD7H
Hex Address: FD8
Table 177. Port C GPIO Address Register (PCADDR)
Bit
7
6
5
4
3
2
1
0
Field
PADDR[7:0]
RESET
R/W
00H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FD8H
Hex Address: FD9
Table 178. Port C Control Registers (PCCTL)
Bit
7
6
5
4
3
2
1
0
Field
PCTL
00H
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FD9H
Hex Address: FDA
Table 179. Port C Input Data Registers (PCIN)
Bit
7
PIN7
X
6
PIN6
X
5
PIN5
X
4
PIN4
X
3
PIN3
X
2
PIN2
X
1
PIN1
X
0
PIN0
X
Field
RESET
R/W
R
R
R
R
R
R
R
R
Address
FDAH
PS025113-1212
GPIO Port A
Z8 Encore!® F0830 Series
Product Specification
225
Hex Address: FDB
Table 180. Port C Output Data Register (PCOUT)
Bit
7
POUT7
0
6
POUT6
0
5
POUT5
0
4
POUT4
0
3
POUT3
0
2
POUT2
0
1
POUT1
0
0
POUT0
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FDBH
Hex Address: FDC
Table 181. Port D GPIO Address Register (PDADDR)
Bit
7
6
5
4
3
2
1
0
Field
PADDR[7:0]
RESET
R/W
00H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FDCH
Hex Address: FDD
Table 182. Port D Control Registers (PDCTL)
Bit
7
6
5
4
3
2
1
0
Field
PCTL
00H
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FDDH
Hex Address: FDE
This address range is reserved.
PS025113-1212
GPIO Port A
Z8 Encore!® F0830 Series
Product Specification
226
Hex Address: FDF
Table 183. Port D Output Data Register (PDOUT)
Bit
7
POUT7
0
6
POUT6
0
5
POUT5
0
4
POUT4
0
3
POUT3
0
2
POUT2
0
1
POUT1
0
0
POUT0
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FDFH
Hex Addresses: FE0–FEF
This address range is reserved.
Watchdog Timer
For more information about the Watchdog Timer registers, see the Watchdog Timer Con-
trol Register Definitions section on page 95.
Hex Address: FF0
The Watchdog Timer Control Register address is shared with the read-only Reset Status
Register.
Table 184. Watchdog Timer Control Register (WDTCTL)
Bit
7
6
5
4
3
2
1
0
Field
WDTUNLK
RESET
R/W
X
X
X
X
X
X
X
X
W
W
W
W
W
W
W
W
Address
FF0H
Table 185. Reset Status Register (RSTSTAT)
Bit
7
6
5
4
EXT
0
3
2
1
0
Field
POR
STOP
WDT
Reserved
RESET
R/W
See Table 12 on page 29
0
0
0
0
R
R
R
R
R
R
R
R
Address
FF0H
PS025113-1212
Watchdog Timer
Z8 Encore!® F0830 Series
Product Specification
227
Hex Address: FF1
Table 186. Watchdog Timer Reload Upper Byte Register (WDTU)
Bit
7
6
5
4
3
2
1
0
Field
WDTU
FF1H
RESET
R/W
0
0
0
0
0
0
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
Note: *Read returns the current WDT count value; write sets the appropriate reload value.
Hex Address: FF2
Table 187. Watchdog Timer Reload High Byte Register (WDTH)
Bit
7
6
5
4
3
2
1
0
Field
WDTH
FF2H
RESET
R/W
0
0
0
0
0
1
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
Note: *Read returns the current WDT count value; write sets the appropriate reload value.
Hex Address: FF3
Table 188. Watchdog Timer Reload Low Byte Register (WDTL)
Bit
7
6
5
4
3
2
1
0
Field
WDTL
RESET
R/W
0
0
0
0
0
0
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
FF3H
Note: *Read returns the current WDT count value; write sets the appropriate reload value.
Hex Addresses: FF4–FF5
This address range is reserved.
PS025113-1212
Watchdog Timer
Z8 Encore!® F0830 Series
Product Specification
228
Trim Bit Control
For more information about the Trim Bit Control registers, see the Flash Option Bit Con-
trol Register Definitions section on page 126.
Hex Address: FF6
Table 189. Trim Bit Address Register (TRMADR)
Bit
7
6
5
4
3
2
1
0
Field
TRMADR - Trim Bit Address (00H to 1FH)
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FF6H
Hex Address: FF7
Table 190. Trim Bit Data Register (TRMDR)
Bit
7
6
5
4
3
2
1
0
Field
TRMDR - Trim Bit Data
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FF7H
Flash Memory Controller
For more information about the Flash Control registers, see the Flash Control Register
Definitions section on page 118.
Hex Address: FF8
Table 191. Flash Control Register (FCTL)
Bit
7
6
5
4
3
2
1
0
Field
FCMD
FF8H
RESET
R/W
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Address
PS025113-1212
Trim Bit Control
Z8 Encore!® F0830 Series
Product Specification
229
Hex Address: FF8
Table 192. Flash Status Register (FSTAT)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
FSTAT
RESET
R/W
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Address
FF8H
Hex Address: FF9
The Flash Page Select Register is shared with the Flash Sector Protect Register.
Table 193. Flash Page Select Register (FPS)
Bit
7
INFO_EN
0
6
5
4
3
PAGE
0
2
1
0
Field
RESET
R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FF9H
Table 194. Flash Sector Protect Register (FPROT)
Bit
7
6
5
4
3
2
1
0
Field
SPROT7 SPROT6 SPROT5 SPROT4 SPROT3 SPROT2 SPROT1 SPROT0
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FF9H
Hex Address: FFA
Table 195. Flash Frequency High Byte Register (FFREQH)
Bit
7
6
5
4
3
2
1
0
Field
FFREQH
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FFAH
PS025113-1212
Flash Memory Controller
Z8 Encore!® F0830 Series
Product Specification
230
Hex Address: FFB
Table 196. Flash Frequency Low Byte Register (FFREQL)
Bit
7
6
5
4
3
2
1
0
Field
FFREQL
0
RESET
R/W
R/W
Address
FFBH
PS025113-1212
Flash Memory Controller
Z8 Encore!® F0830 Series
Product Specification
231
Index
Symbols
@ 165
# 165
B
B 165
b 164
% 165
BCLR 167
binary number suffix 165
BIT 167
Numerics
10-bit ADC 4
bit 164
clear 167
manipulation instructions 167
set 167
set or clear 167
swap 167
A
absolute maximum ratings 184
AC characteristics 189
ADC 166
test and jump 169
test and jump if non-zero 169
test and jump if zero 169
bit jump and test if non-zero 166
bit swap 169
block diagram 3
block transfer instructions 167
BRK 169
BSET 167
BSWAP 167, 169
BTJ 169
BTJNZ 166, 169
BTJZ 169
block diagram 99
overview 98
ADC Channel Register 1 (ADCCTL) 102
ADC Data High Byte Register (ADCDH) 103
ADC Data Low Bit Register (ADCDL) 103, 104,
105
ADCX 166
ADD 166
add - extended addressing 166
add with carry 166
add with carry - extended addressing 166
additional symbols 165
address space 14
C
ADDX 166
calibration and compensation, motor control mea-
analog block/PWM signal synchronization 100
analog block/PWM signal zynchronization 100
analog signals 11
analog-to-digital converter
overview 98
surements 101
CALL procedure 169
capture mode 89, 90
capture/compare mode 89
cc 164
AND 169
ANDX 169
CCF 168
characteristics, electrical 184
clear 168
CLR 168
COM 169
compare 89
architecture
voltage measurements 98
arithmetic instructions 166
assembly language programming 162
assembly language syntax 163
PS025113-1212
P R E L I M I N A R Y
Index
Z8 Encore!® F0830 Series
Product Specification
232
compare - extended addressing 166
compare mode 89
compare with carry 166
compare with carry - extended addressing 166
complement 169
complement carry flag 167, 168
condition code 164
continuous mode 89
Control Registers 14, 17
counter modes 89
CP 166
CPC 166
CPCX 166
CPU and peripheral overview 4
CPU control instructions 168
CPX 166
E
EI 168
electrical characteristics 184
GPIO input data sample timing 195
watch-dog timer 194
electrical noise 98
enable interrupt 168
ER 164
extended addressing register 164
external pin reset 25
eZ8 CPU features 4
eZ8 CPU instruction classes 166
eZ8 CPU instruction notation 164
eZ8 CPU instruction set 162
eZ8 CPU instruction summary 171
current measurement
architecture 98
F
operation 99
FCTL register 119, 126, 127, 228
features, Z8 Encore! 1
first opcode map 182
FLAGS 165
Customer Feedback Form 239
Customer Information 239
flags register 165
flash
D
DA 164, 166
controller 4
data memory 16
DC characteristics 185
debugger, on-chip 139
DEC 166
decimal adjust 166
decrement 166
decrement and jump non-zero 169
decrement word 166
DECW 166
destination operand 165
device, port availability 33
DI 168
option bit address space 127
option bit configuration - reset 124
program memory address 0000H 127
program memory address 0001H 128
flash memory 108
byte programming 116
code protection 114
configurations 108
control register definitions 118, 126
controller bypass 117
flash control register 119, 126, 127, 228
flash option bits 115
flash status register 120
flow chart 113
direct address 164
disable interrupts 168
DJNZ 169
frequency high and low byte registers 123
mass erase 117
dst 165
operation 112
operation timing 114
page erase 117
PS025113-1212
P R E L I M I N A R Y
Index
Z8 Encore!® F0830 Series
Product Specification
233
page select register 121, 122
FPS register 121, 122
FSTAT register 120
indexed 165
indirect address prefix 165
indirect register 164
indirect register pair 164
indirect working register 164
indirect working register pair 164
instruction set, ez8 CPU 162
instructions
G
gated mode 89
general-purpose I/O 33
GPIO 4, 33
ADC 166
ADCX 166
ADD 166
ADDX 166
AND 169
ANDX 169
alternate functions 34
architecture 34
control register definitions 39
input data sample timing 195
interrupts 39
arithmetic 166
BCLR 167
BIT 167
bit manipulation 167
block transfer 167
BRK 169
BSET 167
BSWAP 167, 169
BTJ 169
BTJNZ 166, 169
BTJZ 169
CALL 169
port A-C pull-up enable sub-registers 46, 47, 48
port A-H address registers 40
port A-H alternate function sub-registers 42
port A-H control registers 41
port A-H data direction sub-registers 41
port A-H high drive enable sub-registers 44
port A-H input data registers 49
port A-H output control sub-registers 43
port A-H output data registers 50, 51
port A-H stop mode recovery sub-registers 45
port availability by device 33
port input timing 195
CCF 167, 168
CLR 168
port output timing 196
COM 169
CP 166
CPC 166
CPCX 166
CPU control 168
CPX 166
H
H 165
HALT 168
halt mode 31, 168
hexadecimal number prefix/suffix 165
DA 166
DEC 166
DECW 166
DI 168
DJNZ 169
EI 168
HALT 168
INC 166
INCW 167
IRET 169
I
IM 164
immediate data 164
immediate operand prefix 165
INC 166
increment 166
increment word 167
INCW 167
PS025113-1212
P R E L I M I N A R Y
Index
Z8 Encore!® F0830 Series
Product Specification
234
JP 169
LD 168
LDC 168
interrupt control register 67
interrupt controller 53
architecture 53
LDCI 167, 168
LDE 168
LDEI 167
interrupt assertion types 56
interrupt vectors and priority 56
operation 55
LDX 168
LEA 168
load 168
logical 169
MULT 167
NOP 168
register definitions 57
software interrupt assertion 57
interrupt edge select register 65
interrupt request 0 register 58
interrupt request 1 register 59
interrupt request 2 register 60
interrupt return 169
OR 169
ORX 169
POP 168
interrupt vector listing 53
IR 164
POPX 168
program control 169
PUSH 168
PUSHX 168
RCF 167, 168
RET 169
Ir 164
IRET 169
IRQ0 enable high and low bit registers 60
IRQ1 enable high and low bit registers 62
IRQ2 enable high and low bit registers 63
IRR 164
RL 169
Irr 164
RLC 169
rotate and shift 169
RR 170
RRC 170
SBC 167
SCF 167, 168
SRA 170
J
JP 169
jump, conditional, relative, and relative conditional
169
SRL 170
SRP 168
STOP 168
SUB 167
SUBX 167
SWAP 170
TCM 167
TCMX 167
TM 167
L
LD 168
LDC 168
LDCI 167, 168
LDE 168
LDEI 167, 168
LDX 168
LEA 168
load 168
load constant 167
load constant to/from program memory 168
load constant with auto-increment addresses 168
load effective address 168
load external data 168
TMX 167
TRAP 169
watch-dog timer refresh 168
XOR 169
XORX 169
instructions, eZ8 classes of 166
PS025113-1212
P R E L I M I N A R Y
Index
Z8 Encore!® F0830 Series
Product Specification
235
load external data to/from data memory and auto-
increment addresses 167
load external to/from data memory and auto-incre-
ment addresses 168
load instructions 168
load using extended addressing 168
logical AND 169
cc 164
DA 164
ER 164
IM 164
IR 164
Ir 164
IRR 164
Irr 164
p 164
logical AND/extended addressing 169
logical exclusive OR 169
logical exclusive OR/extended addressing 169
logical instructions 169
R 165
r 164
logical OR 169
logical OR/extended addressing 169
low power modes 30
RA 165
RR 165
rr 165
vector 165
X 165
M
notational shorthand 164
master interrupt enable 55
memory
O
OCD
data 16
program 15
mode
architecture 139
capture 89, 90
capture/compare 89
continuous 89
auto-baud detector/generator 142
baud rate limits 142
block diagram 139
counter 89
breakpoints 143
gated 89
commands 144
one-shot 89
control register 148
PWM 89, 90
data format 142
modes 89
DBG pin to RS-232 Interface 140
debug mode 141
debugger break 169
interface 140
serial errors 143
motor control measurements
ADC Control register definitions 101
calibration and compensation 101
interrupts 101
overview 98
status register 150
MULT 167
timing 197
multiply 167
OCD commands
execute instruction (12H) 148
read data memory (0DH) 147
read OCD control register (05H) 146
read OCD revision (00H) 145
read OCD status register (02H) 145
read program counter (07H) 146
read program memory (0BH) 147
N
noise, electrical 98
NOP (no operation) 168
notation
b 164
PS025113-1212
P R E L I M I N A R Y
Index
Z8 Encore!® F0830 Series
Product Specification
236
read program memory CRC (0EH) 147
read register (09H) 146
port output timing, GPIO 196
power supply signals 12
power-on reset (POR) 23
program control instructions 169
program counter 165
program memory 15
PUSH 168
push using extended addressing 168
PUSHX 168
PWM mode 89, 90
PxADDR register 40, 222, 223, 224, 225
PxCTL register 41, 222, 223, 224, 225
read runtime counter (03H) 145
step instruction (10H) 148
stuff instruction (11H) 148
write data memory (0CH) 147
write OCD control register (04H) 145
write program counter (06H) 146
write program memory (0AH) 146
write register (08H) 146
on-chip debugger (OCD) 139
on-chip debugger signals 12
on-chip oscillator 157
one-shot mode 89
opcode map
R
abbreviations 181
cell description 180
first 182
second after 1FH 183
R 165
r 164
RA
register address 165
operation 100
RCF 167, 168
current measurement 99
voltage measurement timing diagram 100
Operational Description 21, 30, 33, 53, 68, 92, 98,
106, 108, 124, 134, 139, 151, 157, 161
OR 169
ordering information 200
ORX 169
oscillator signals 12
register 165
flash control (FCTL) 119, 126, 127, 228
flash high and low byte (FFREQH and FRE-
EQL) 123
flash page select (FPS) 121, 122
flash status (FSTAT) 120
GPIO port A-H address (PxADDR) 40, 222,
223, 224, 225
GPIO port A-H alternate function sub-registers
42
GPIO port A-H control address (PxCTL) 41,
222, 223, 224, 225
P
p 164
Packaging 199
part selection guide 2
PC 165
GPIO port A-H data direction sub-registers 41
OCD control 148
OCD status 150
peripheral AC and DC electrical characteristics 190
pin characteristics 13
Pin Descriptions 7
polarity 164
POP 168
pop using extended addressing 168
POPX 168
watch-dog timer control (WDTCTL) 95, 107,
154, 217, 218, 226
watchdog timer control (WDTCTL) 29
watch-dog timer reload high byte (WDTH) 227
watchdog timer reload high byte (WDTH) 96
watch-dog timer reload low byte (WDTL) 227
watchdog timer reload low byte (WDTL) 97
watch-dog timer reload upper byte (WDTU)
227
port availability, device 33
port input timing (GPIO) 195
PS025113-1212
P R E L I M I N A R Y
Index
Z8 Encore!® F0830 Series
Product Specification
237
watchdog timer reload upper byte (WDTU) 96
register file 14
stack pointer 165
STOP 168
register pair 165
register pointer 165
registers
stop mode 30, 168
stop mode recovery
sources 26
ADC channel 1 102
ADC data high byte 103
ADC data low bit 103, 104, 105
reset
using a GPIO port pin transition 27, 28
using watch-dog timer time-out 27
SUB 167
subtract 167
and stop mode characteristics 22
and stop mode recovery 21
carry flag 167
subtract - extended addressing 167
subtract with carry 167
subtract with carry - extended addressing 167
SUBX 167
sources 23
RET 169
SWAP 170
return 169
swap nibbles 170
RL 169
symbols, additional 165
RLC 169
rotate and shift instuctions 169
rotate left 169
rotate left through carry 169
rotate right 170
rotate right through carry 170
RP 165
RR 165, 170
rr 165
RRC 170
T
Table 134. Power Consumption Reference Table
197
TCM 167
TCMX 167
test complement under mask 167
test complement under mask - extended addressing
167
test under mask 167
test under mask - extended addressing 167
tiing diagram, voltage measurement 100
timer signals 11
S
SBC 167
SCF 167, 168
timers 68
second opcode map after 1FH 183
set carry flag 167, 168
set register pointer 168
shift right arithmatic 170
shift right logical 170
signal descriptions 11
software trap 169
source operand 165
SP 165
architecture 68
block diagram 69
capture mode 77, 78, 89, 90
capture/compare mode 81, 89
compare mode 79, 89
continuous mode 70, 89
counter mode 71, 72
counter modes 89
gated mode 80, 89
SRA 170
src 165
one-shot mode 69, 89
operating mode 69
SRL 170
SRP 168
PWM mode 74, 75, 89, 90
reading the timer count values 82
PS025113-1212
P R E L I M I N A R Y
Index
Z8 Encore!® F0830 Series
Product Specification
238
reload high and low byte registers 85
timer control register definitions 83
timer output signal operation 82
X
X 165
XOR 169
XORX 169
timers 0-3
control registers 87, 88
high and low byte registers 83, 86
TM 167
TMX 167
TRAP 169
Z
Z8 Encore!
block diagram 3
features 1
part selection guide 2
V
vector 165
voltage brown-out reset (VBR) 24
voltage measurement timing diagram 100
W
watch-dog timer
approximate time-out delay 92
approximate time-out delays 92, 106, 134, 151,
161
CNTL 24
control register 95, 154
electrical characteristics and timing 194
interrupt in noromal operation 93
interrupt in stop mode 93
operation 92, 106, 134, 151, 161
refresh 93
reload unlock sequence 94
reload upper, high and low registers 96
reset 25
reset in normal operation 94
reset in Stop mode 94
time-out response 93
watchdog timer
refresh 168
WDTCTL register 29, 95, 107, 154, 217, 218, 226
WDTH register 96, 227
WDTL register 97, 227
working register 164
working register pair 165
WTDU register 96, 227
PS025113-1212
P R E L I M I N A R Y
Index
Z8 Encore!® F0830 Series
Product Specification
239
Customer Support
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PS025113-1212
Customer Support
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