Z86E0208SEC1903_技术文档

PRELIMINARY PRODUCT SPECIFICATION

1

Z86C02/E02/L02

1

COST EFFECTIVE, 512-BYTE ROM

®

CMOS Z8 MICROCONTROLLERS

FEATURES

■ ROM Mask/OTP Options:

ROM

(KB)

RAM* Speed Auto Permanent

(Bytes) (MHz) Latch WDT

–

Low-Noise (Z86C02/E02 only)

ROM Protect

Device

Z86C02

Z86E02

Z86L02

512

61

8

Optional Optional

Auto Latch

Permanent Watch-Dog Timer (WDT)

RC Oscillator (Z86C02/L02 Only)

32 KHz Operation (Z86C02/L02 Only)

Note: *General-Purpose

■ 18-Pin DIP and SOIC Packages

■ One Programmable 8-Bit Counter/Timer with a 6-Bit

■ 0°C to 70°C Standard Temperature

–40°C to 105°C Extended Temperature

Programmable Prescaler

■ Power-On Reset (POR) Timer

(Z86C02/E02 only)

■ On-Chip Oscillator that Accepts RC, Crystal, Ceramic

■ 3.0V to 5.5V Operating Range (Z86C02)

4.5V to 5.5V Operating Range (Z86E02)

2.0V to 3.9V Operating Range (Z86L02)

Resonator, LC, or External Clock Drive (C02/L02 only)

■ On-Chip Oscillator that Accepts RC or External Clock

Drive (Z86E02 SL1903 only)

■ 14 Input / Output Lines

■ On-Chip Oscillator that Accepts Crystal, Ceramic

■ Five Vectored, Prioritized Interrupts from Five Different

Resonator, LC, or External Clock Drive (Z86E02 only)

Sources

■ Clock-Free WDT Reset

■ Two On-Board Comparators

■ Low-Power Consumption (50mw)

■ Fast Instruction Pointer (1.5µs @ 8 MHz)

■ Software Enabled Watch-Dog Timer (WDT)

■

Programmable Interrupt Polarity

■ Fourteen Digital Inputs at CMOS Levels;

■ Two Standby Modes: STOP and HALT

■ Low-Voltage Protection

Schmitt-Triggered

GENERAL DESCRIPTION

Zilog's Z86C02/E02/L02 microcontrollers (MCUs) are

members of the Z8 single-chip MCU family, which offer

three ports, and are configurable under software control to

provide timing, status signals, or parallel I/O.

®

easy software/hardware system expansion.

One on-chip counter/timer, with a large number of user-se-

lectable modes, off-load the system of administering real-

time tasks such as counting/timing and I/O data communi-

For applications demanding powerful I/O capabilities, the

MCU's dedicated input and output lines are grouped into

DS96DZ80301

P R E L I M I N A R Y

1

Z86C02/E02/L02

®

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Zilog

GENERAL DESCRIPTION (Continued)

cations. Additionally, two on-board comparators process

analog signals with a common reference voltage (Figure

1).

Power connections follow conventional descriptions be-

low:

Connection

Power

Circuit

Device

Note: All Signals with a preceding front slash, "/", are ac-

tive Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is

active Low, only).

V

DD

CC

Ground

GND

V

SS

Input

XTAL

Vcc

GND

Machine

Timing & Inst.

Control

Port 3

Counter/

ALU

Timer

Program

Memory

FLAG

Interrupt

Control

Register

Pointer

Two Analog

Comparators

Program

Counter

General-Purpose

Register File

Port 2

Port 0

I/O

(Bit Programmable)

Figure 1. Z86C02/E02/L02 Functional Block Diagram

2

P R E L I M I N A R Y

DS96DZ80301

Z86C02/E02/L02

®

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Zilog

GENERAL DESCRIPTION (Continued)

D7-D0

Z8 MCU

A10-A0

Address

Counter

EPROM

D7-D0

3 Bits

Option Bits

D7-D0

PGM

Mode Logic

Clear Clock EPM /CE /PGM

VPP

P33

/OE

P31

P00 P01

P32 XT1 P02

Figure 2. EPROM Programming Mode Block Diagram

PIN DESCRIPTIONS

Table 1. 18-Pin Standard Mode Identiﬁcation

P24

P25

1

2

3

4

5

6

7

8

9

P23

P22

P21

P20

GND

P02

P01

P00

P33

18

17

16

15

14

13

12

11

Pin #

Symbol

Function

Direction

1-4

5

P24-P27 Port 2, Pins 4, 5, 6, 7 In/Output

P26

V

Power Supply

CC

P27

6

XTAL2

Crystal Oscillator

Clock

Output

Input

Vcc

XTAL2

XTAL1

P31

7

XTAL1

Crystal Oscillator

Clock

8

9

P31

P32

Port 3, Pin 1, AN1

Port 3, Pin 2, AN2

Port 3, Pin 3, REF

Port 0, Pins 0, 1, 2

Ground

Input

P32

10

P33

Input

Standard Mode

11-13

14

P00-P02

GND

In/Output

15-18

P20-P23 Port 2, Pins 0, 1, 2, 3 In/Output

Figure 3. 18-Pin Standard Mode Conﬁguration

3

P R E L I M I N A R Y

DS96DZ80301

Z86C02/E02/L02

®

Zilog

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

D4

D3

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

1

2

3

4

18

17

16

P23

P22

P21

P24

P25

P26

D5

D6

D2

D1

1

D7

D0

15

14

P20

P27

VCC

Vcc

GND

5

6

/PGM

N/C

/CE

13

12

11

P02

P01

P00

P33

XTAL2

XTAL1

P31

CLOCK

7

8

CLEAR

VPP

/OE

EPM

10

9

P32

EPROM Mode

Figure 5. 18-Pin SOIC Conﬁguration

Table 3. 18-Pin SOIC Pin Identiﬁcation

Standard Mode

Figure 4. 18-Pin EPROM Mode Conﬁguration

Table 2. 18-Pin EPROM Mode Identiﬁcation

Pin #

Symbol

Function

Direction

1-4

5

D4-D7

Vcc

Data 4, 5, 6, 7

Power Supply

No Connection

Chip Enable

In/Output

Pin #

Symbol

Function

Direction

1-4

P24-P27

Port 2, Pins

4,5,6,7

In/Output

6

NC

7

/CE

Input

5

6

Vcc

XTAL2

XTAL1

P31

Power Supply

8

/OE

Output Enable

Crystal Osc. Clock

Port 3, Pin 1, AN1

Port 3, Pin 2, AN2

Port 3, Pin 3, REF

Output

Input

9

EPM

EPROM Program

Mode

7

8

10

11

VPP

Clear

Clock

/PGM

GND

Program Voltage

Clear Clock

Address

Input

9

P32

10

P33

12

11-13

14

P00-P02

GND

Port 0, Pins 0,1,2 In/Output

Ground

13

Program Mode

Ground

14

15-18

P20-P23

Port 2, Pins

0,1,2,3

In/Output

15-18

D0-D3

Data 0, 1, 2, 3

In/Output

DS96DZ80301

P R E L I M I N A R Y

4

Z86C02/E02/L02

®

Zilog

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

ABSOLUTE MAXIMUM RATINGS

Parameter

Min

Max

Units

1

Ambient Temperature under Bias

Storage Temperature

Voltage on any Pin with Respect to V [Note 1]

–40

–65

–0.7

+105

+150

+12

C

V

SS

Voltage on V Pin with Respect to V

–0.3

–0.7

+7

V

DD

SS

Voltage on Pin 7 with Respect to V [Note 2] (Z86C02/L02)

V

+1

SS

DD

Voltage on Pin 7,8,9,10 with Respect to V [Note 2] (Z86E02)

V

+1

SS

Total Power Dissipation

Maximum Allowed Current out of V

462

300

mW

mA

SS

Maximum Allowed Current into V

270

mA

DD

Maximum Allowed Current into an Input Pin [Note 3]

Maximum Allowed Current into an Open-Drain Pin [Note 4]

Maximum Allowed Output Current Sinked by Any I/O Pin

Maximum Allowed Output Current Sourced by Any I/O Pin

Maximum Allowed Output Current Sinked by Port 2, Port 0

Maximum Allowed Output Current Sourced by Port 2, Port 0

–600

+600

20

80

µA

mA

80

Notes:

Stresses greater than those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. This is a stress rating only; functional operation of

the device at any condition above those indicated in the

operational sections of these specifications is not implied.

Exposure to absolute maximum rating conditions for an

extended period may affect device reliability.

1. This applies to all pins except where otherwise noted.

2. Maximum current into pin must be ±600µA.

There is no input protection diode from pin to V

.

DD

3. This excludes Pin 6 and Pin 7.

4. Device pin is not at an output Low state.

Total power dissipation should not exceed 462 mW for the

package. Power dissipation is calculated as follows:

Total Power dissipation = V x [I – (sum of I )] + sum of [(V – V ) x I ] + sum of (V x I )

DD

OH

DD

OH

0L

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test

conditions as noted. All voltages are referenced to

Ground. Positive current flows into the referenced pin (Fig-

ure 6).

From Output

Under Test

150 pF

Figure 6. Test Load Diagram

CAPACITANCE

T = 25°C, V = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.

A

CC

Parameter

Min

Max

Input capacitance

Output capacitance

I/O capacitance

0

15 pF

20 pF

25 pF

DS96DZ80301

P R E L I M I N A R Y

5

Z86C02/E02/L02

®

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Zilog

DC ELECTRICAL CHARACTERISTICS

Z86C02

T = 40°C to +105°C

A

T = 0°C to +70°C

Typical

@ 25°C

1.7

A

V

[4]

Sym. Parameter

Min

Max

Units

Conditions

Notes

CC

V

Clock Input High

Voltage

3.0V

5.5V

3.0V

5.5V

0.8 V

V

+0.3

V

Driven by External

Clock Generator

CH

CC

0.8 V

+0.3

2.8

0.8

1.7

V

Driven by External

Clock Generator

CC

V

Clock Input Low

Voltage

V

–0.3

0.2 V

Driven by External

Clock Generator

CL

SS

CC

Driven by External

Clock Generator

SS

V

Input High Voltage

Input Low Voltage

Output High Voltage

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

0.7 V

V

+0.3

1.8

2.8

0.8

1.5

3.0

4.8

3.0

V

[1]

[5]

IH

CC

V

–0.3

–0.4

0.2 V

IL

SS

CC

V

I

= –2.0 mA

OH

OL1

OL2

OH

Low Noise @

= –0.5 mA

I

OH

5.5V

V

–0.4

4.8

V

Low Noise @

CC

I

= –0.5 mA

= +4.0 mA

OH

OL

V

Output Low Voltage

3.0V

5.5V

3.0V

0.8

0.4

0.8

0.2

0.1

0.2

V

[5]

Low Noise @

= 1.0 mA

I

OL

5.5V

0.4

0.1

V

Low Noise @

I

= 1.0 mA

= +12 mA

OL

3.0V

5.5V

1.0

0.8

0.3

V

[5]

V

Comparator Input

Offset Voltage

3.0V

5.5V

25

10

mV

V

OFFSET

V

Low Voltage

CC

LV

Auto Reset

2.2

2.8

3.0

1.0

2.6

V

[9]

2.0

V

[10]

I

Input Leakage

(Input Bias Current

of Comparator)

3.0V

5.5V

–1.0

µA

V

= 0V, V

IL

IN

CC

–1.0

1.0

µA

CC

I

Output Leakage

3.0V

5.5V

–1.0

1.0

µA

V

= 0V, V

OL

IN

CC

V

Comparator Input

Common Mode

Voltage Range

V

–0.3

V

–1.0

[9]

VICR

SS

CC

–0.3

–1.5

V

[10]

6

P R E L I M I N A R Y

DS96DZ80301

Z86C02/E02/L02

®

Zilog

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

DC CHARACTERISTICS

Z86C02

1

T = 40°C to+105°C

A

T = 0°C to +70°C

Typical

A

V

[4]

Sym. Parameter

Min

Max

@ 25°C Units

Conditions

Notes

CC

I

Supply Current

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

3.5

7.0

8.0

11.0

2.5

4.0

5.0

3.5

7.0

5.8

9.0

8.0

11.0

2.5

4.0

3.0

4.5

4.0

5.0

10

1.5

3.8

3.0

4.4

0.7

2.5

1.0

3.0

1.5

3.8

2.5

4.0

3.0

4.4

0.7

2.5

0.9

2.8

1.0

3.0

1.0

3.0

mA

µA

@ 2 MHz

@ 8 MHz

@ 2 MHz

@ 8 MHz

@ 1 MHz

@ 2 MHz

@ 4 MHz

@ 1 MHz

@ 2 MHz

@ 4 MHz

[5,6,7]

[6,7,8]

[6,7,8,9]

[6,7,8,10]

[6,7,8,9]

[6,7,8,10]

CC

I

Standby Current (Halt Mode)

Supply Current (Low Noise Mode)

CC1

I

CC

I

Standby Current

(Low Noise Halt Mode)

CC1

I

Standby Current (Stop Mode)

CC2

20

µA

10

µA

20

µA

I

Auto Latch Low Current

Auto Latch High Current

12

µA

0V < V < V

IN

ALL

CC

5.5V

3.0V

5.5V

32

–8

16

µA

0V < V < V

IN

-1.5

-8.0

0V < V < V

IN

ALH

–16

0V < V < V

IN

Notes:

1. ort 0, 2, and 3 only.

2. V = 0V = GND.

SS

3. The device operates down to V The minimum operational V is determined on the value of the voltage

LV

CC

V

at the ambient temperature.

LV

4. V = 3.0V to 5.5V, typical values measured at V = 3.3V and V = 5.0V.

CC

5. Standard mode (not Low EMI mode).

6. Inputs at V or V , outputs unloaded.

CC

SS

7. Halt mode and Low EMI mode.

8. WDT not running.

9. T = 0˚C to 70˚C.

A

10. T = 40˚C to 105˚C.

A

DS96DZ80301

P R E L I M I N A R Y

7

Z86C02/E02/L02

®

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Zilog

DC CHARACTERISTICS

Z86L02

T = 0°C to +70°C

Typical

A

V

[4]

Sym. Parameter

Min

Max

@ 25°C Units

Conditions

Driven by External

Clock Generator

Notes

CC

V

Clock Input High

Voltage

2.0V

3.9V

2.0V

3.9V

0.9 V

V

+0.3

V

CH

CC

+0.3

V

Driven by External

Clock Generator

CC

V

Clock Input Low

Voltage

V

–0.3

0.1 V

Driven by External

Clock Generator

CL

SS

CC

Driven by External

Clock Generator

V

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

0.9 V

V

+0.3

V

[1]

[5]

IH

CC

V

–0.3

–0.4

0.1 V

IL

SS

CC

V

3.0

0.2

0.1

0.8

0.3

V

I

= – 500 µA

= –500 µA

= +1.0 mA

= + 3.0 mA

OH

OL1

OL2

OH

OL

V

0.8

0.4

1.0

0.8

V

Comparator Input

Offset Voltage

2.0V

3.9V

25

10

mV

V

OFFSET

V

Low Voltage

CC

1.4

2.15

LV

Auto Reset

I

Input Leakage

(Input Bias Current

of Comparator)

2.0V

3.9V

–1.0

1.0

µA

V

= 0V, V

IL

IN

CC

IN

CC

I

Output Leakage

2.0V

3.9V

–1.0

1.0

µA

OL

V

= 0V, V

IN

µA

IN

CC

V

Comparator Input

Common Mode

Voltage Range

V

–0.3

V –1.0

CC

V

VICR

SS

8

P R E L I M I N A R Y

DS96DZ80301

Z86C02/E02/L02

®

Zilog

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

T = 0°C to +70°C

Typical

A

V

[4]

Sym Parameter

Min

Max

@ 25°C Units

Conditions

Notes

CC

I

Supply Current

2.0V

3.3

6.8

6.0

9.0

2.3

3.8

4.8

10

mA

@ 2 MHz

@ 8 MHz

@ 2 MHz

@ 8 MHz

[5,6]

CC

1

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

[5,6]

I

Standby Current (Halt Mode)

[5,6,7]

[6,7]

CC1

I

Standby Current (Stop Mode)

Auto Latch Low Current

1.0

3.0

µA

CC2

10

[6,7]

I

12

0V < V < V

IN

ALL

CC

3.9V

2.0V

3.9V

32

–8

16

µA

0V < V < V

IN

Auto Latch High Current

-1.5

-8.0

0V < V < V

IN

ALH

–16

Notes:

1. Port 0, 2, and 3 only

2. V = 0V = GND.The device operates down to V . The minimum operational V is determined by the value of the voltage V

SS

LV

CC

LV

at the ambient temperature.

3. V = 2.0V to 3.9V, typical values measured at V = 3.3 V.

CC

4. Standard Mode (not Low EMI mode).

5. Inputs at V or V , outputs are unloaded.

CC

SS

6. WDT is not running.

DS96DZ80301

P R E L I M I N A R Y

9

Z86C02/E02/L02

®

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Zilog

DC CHARACTERISTICS

Z86E02

T = –40°C to +105°C

A

T = 0°C to +70°C

Typical

A

V

[4]

Sym.

Parameter

Min

Max

@ 25°C

Units

Conditions

Notes

CC

V

Clock Input High

Voltage

4.5V

5.5V

4.5V

5.5V

0.8 V

V

+0.3

2.8

1.7

V

Driven by External

Clock Generator

CH

CC

0.8 V

+0.3

V

Driven by External

Clock Generator

CC

V

Clock Input Low

Voltage

V

–0.3

0.2 V

Driven by External

Clock Generator

CL

SS

CC

V

0.3

Driven by External

Clock Generator

SS–

V

Input High Voltage

Input Low Voltage

Output High Voltage

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

0.7 V

V

+0.3

2.8

1.5

4.8

0.1

V

IH

CC

V

–0.3

–0.4

0.2 V

IL

SS

CC

V

I

= –2.0 mA

[5]

OH

Low Noise @

I

= –0.5 mA

OH

V

Output Low Voltage

0.4

I

= +4.0 mA

[5]

OL1

OL

Low Noise @

= 1.0 mA

I

OL

5.5V

0.4

0.1

V

Low Noise @

I

= 1.0 mA

= +12 mA

OL

V

4.5V

5.5V

1.0

0.8

V

[5]

OL2

V

Comparator Input

Offset Voltage

4.5V

5.5V

25

10

mV

V

OFFSET

V

Low Voltage

CC

2.6

3.3

3.6

1.0

3.0

[9]

LV

Auto Reset

2.2

V

[10]

I

Input Leakage (Input

Bias Current of

Comparator)

4.5V

5.5V

–1.0

µA

V

= 0V, V

IL

IN

CC

–1.0

1.0

µA

IN

CC

I

Output Leakage

4.5V

5.5V

–1.0

1.0

µA

V

= 0V, V

OL

IN

CC

IN

CC

V

Comparator Input

Common Mode

Voltage Range

V

–0.3

V

–1.0

[9]

VICR

SS

CC

–0.3

–1.5

V

[10]

SS

CC

10

P R E L I M I N A R Y

DS96DZ80301

Z86C02/E02/L02

®

Zilog

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

T = –40°C to +105°C

A

T = 0°C to +70°C

Typical

A

V

[4]

Sym. Parameter

Min

Max

9.0

@ 25°C

Units

mA

Conditions

@ 2 MHz

Notes

[5,6]

CC

1

I

Supply Current

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

3.8

CC

9.0

15.0

4.0

5.0

9.0

11.0

15.0

4.0

4.5

5.0

10

3.8

4.4

2.5

3.0

3.8

4.0

4.4

2.5

2.7

3.0

1.0

16

mA

µA

@ 2 MHz

@ 8 MHz

@ 1 MHz

@ 2 MHz

@ 4 MHz

[5,6]

I

Standby Current (HALT mode)

[5,6]

CC1

[5,6]

I

Supply Current (Low Noise

Mode)

[6]

CC

[6]

@ 2 MHz

@ 4 MHz

@ 1 MHz

@ 2 MHz

@ 4 MHz

[6]

I

Standby Current (Low Noise

Halt Mode)

[6,7,8]

[6,7,9]

[6,7,10]

[6,7,9]

6,7,10]

CC1

I

Standby Current (Stop Mode)

CC2

20

µA

10

µA

20

µA

I

Auto Latch Low Current

Auto Latch High

32

µA

0V <V <V

IN

ALL

CC

5.5V

4.5V

5.5V

32

16

µA

0V <V <V

IN

ALH

–16

-8.0

–8.0

0V <V <V

IN

0V <V <V

IN

Notes:

1. Port 0, 2, and 3 only.

2. V = 0V = GND.

SS

3. The device operates down to V of the specified frequency for V . The minimum operational V is determined by the value of

LV

CC

the voltage V at the ambient temperature.

LV

4. The V increases as the temperature decreases.

LV

5. V = 4.5V to 5.5V, typical values measured at V = 5.0V.

CC

6. Standard mode (not Low EMI mode).

7. Inputs at V or V , outputs unloaded.

CC

SS

8. WDT not running.

9. Halt mode and Low EMI mode.

10. T = 0˚C to 70˚C.T = –40˚C to 105˚C.

A

DS96DZ80301

P R E L I M I N A R Y

11

Z86C02/E02/L02

®

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Zilog

AC ELECTRICAL CHARACTERISTICS

PostScript error (invalidfont, findfont)

Figure 7. AC Electrical Timing Diagram

12

P R E L I M I N A R Y

DS96DZ80301

Z86C02/E02/L02

®

Zilog

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

AC ELECTRICAL CHARACTERISTICS

Timing Table (Standard Mode for SCLK/TCLK = XTAL/2)

1

T = –40°C to +105°C

A

T = 0°C to +70°C

A

8 MHz

V

No.

Symbol Parameter

Min

Max

Units

Notes

CC

1

TpC

Input Clock Period

2.0V

5.5V

2.0V

5.5V

2.0V

5.5V

2.0V

5.5V

2.0V

5.5V

2.0V

5.5V

2.0V

5.5V

2.0V

5.5V

3.0V

5.5V

2.0V

3.0V

5.5V

2.0V

3.0V

5.5V

2.0V

3.0V

5.5V

125

DC

25

ns

[1]

2

3

TrC,TfC Clock Input Rise and Fall Times

[1]

25

[1]

TwC

Input Clock Width

62

[1]

4

TwTinL Timer Input Low Width

TwTinH Timer Input High Width

70

[1]

70

[1]

5

5TpC

8TpC

[1]

6

TpTin

Timer Input Period

[1]

7

TrTin,

TtTin

Timer Input Rise and Fall Time

Int. Request Input Low Time

Int. Request Input High Time

Watch-Dog Timer Delay Time Before Time-Out

100

ns

[1]

8

TwIL

TwIH

Twdt

70

5TpC

25

10

5

[1,2,3]

9

10

ms

11

Tpor

Power-On Reset Time

70

50

10

8

250

150

70

[4]

[5]

76

4

38

2

18

Notes:

1. Timing Reference uses 0.7 V for a logic 1 and 0.2 V for a logic 0.

CC

2. Interrupt request through Port 3 (P33-P31).

3. IRQ 0,1,2 only.

CC

4. Z86E02 only.

5. Z86C02/L02 only.

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AC ELECTRICAL CHARACTERISTICS

Low Noise Mode (Z86C02/E02 Only)

T = –40°C to +105°C

A

T = 0°C to +70°C

A

1 MHz

4 MHz

Max

V

No. Symbol

Parameter

Input Clock Period

Min

Max

Min

Units

Notes

CC

1

2

3

TPC

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

3.0V

5.5V

2.0V

3.0V

5.5V

3.0V

5.5V

1000

DC

25

250

DC

25

ns

[1]

TrC

TfC

Clock Input Rise and Fall Times

Input Clock Width

[1]

25

[1]

TwC

500

125

[1]

4. TwTinL

Timer Input Low Width

Timer Input High Width

Timer Input Period

70

[1]

70

[1]

5

6

7

8

9

TwTinH

TpTin

2.5TpC

4TpC

2.5TpC

4TpC

[1]

TrTin,

TtTin

Timer Input Rise and Fall Time

Int. Request Input Low Time

Int. Request Input High Time

Power-On Reset Time

100

ns

[1]

TwIL

70

[1,2,3]

[4]

70

TwIH

2.5TpC

10 Tpor

50

10

8

150

70

76

38

18

50

10

8

150

70

76

38

18

ms

[4]

[5]

4

[5]

2

[5]

11 Twdt

Watch-Dog Timer Delay

10

5

10

5

Notes:

1. Timing Reference uses 0.7 V for a logic 1 and 0.2 V for a logic 0.

CC

2. Interrupt request through Port 3 (P33-P31).

3. IRQ 0,1,2 only.

CC

4. Z86E02 only.

5. Z86C02/L02 only.

14

P R E L I M I N A R Y

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®

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Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

LOW NOISE VERSION

Low EMI Emission

1

The Z8 can be programmed to operate in a Low EMI emis-

sion mode by means of a mask ROM bit option (Z86C02)

or OTP bit option (Z86E02). Use of this feature results in:

■ Output drivers have resistances of 200 ohms (typical).

■ Oscillator divide-by-two circuitry eliminated.

The Low EMI mode is mask-programmable to be selected

by the customer at the time the ROM Code is submitted

(for Z86C02 only).

■ All pre-driver slew rates reduced to 10 ns typical.

■ Internal SCLK/TCLK operation limited to a maximum of

4 MHz - 250 ns cycle time.

PRECAUTION

Stack pointer register (SPL) at FFHex and general purpose register at FEHex are set to 00Hex after reset.

PIN FUNCTIONS

OTP Programming Mode

D7-D0 Data Bus. Data can be read from, or written to the

Clock Address Clock. This pin is a clock input. The internal

EPROM through this data bus.

address counter increases by one with one clock cycle.

V

Power Supply. It is 5V during EPROM Read Mode

/PGM Program Mode (active Low). A Low level at this pin

CC

and 6.4V during the other modes (Program, Program Ver-

ify, etc.).

programs the data to the EPROM through the Data Bus.

Application Precaution

/CE Chip Enable (active Low). This pin is active during

EPROM Read Mode, Program Mode, and Program Verify

Mode.

The production test-mode environment may be enabled

accidentally during normal operation if excessive noise

surges above V occur on the XTAL1 pin.

CC

/OE Output Enable (active Low). This pin drives the Data

Bus direction. When this pin is Low, the Data Bus is output.

When High, the Data Bus is input. This pin must toggle for

each data output read.

In addition, processor operation of Z8 OTP devices may be

affected by excessive noise surges on the V , /CE,

PP

/EPM, /OE pins while the microcontroller is in Standard

Mode.

EPM EPROM Program Mode. This pin controls the differ-

ent EPROM Program Modes by applying different

voltages.

Recommendations for dampening voltage surges in both

test and OTP mode include the following:

■

Using a clamping diode to V

CC.

V

age.

Program Voltage. This pin supplies the program volt-

PP

Adding a capacitor to the affected pin.

Clear Clear (active High). This pin resets the internal ad-

dress counter at the High Level.

DS96DZ80301

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PIN FUNCTIONS (Continued)

XTAL1, XTAL2 Crystal In, Crystal Out (time-based input

and output, respectively). These pins connect a parallel-

resonant crystal, LC, RC, or an external single-phase

clock (8 MHz max) to the on-chip clock oscillator and buff-

er.

Auto Latch. The Auto Latch puts valid CMOS levels on all

CMOS inputs (except P33, P32, P31) that are not external-

ly driven. A valid CMOS level, rather than a floating node,

reduces excessive supply current flow in the input buffer.

On Power-up and Reset, the Auto Latch will set the ports

to an undetermined state of 0 or 1. Default condition is

Auto Latches enabled.

Port 0, P02-P00. Port 0 is a 3-bit bi-directional, Schmitt-

triggered CMOS compatible I/O port. These three I/O lines

can be globally configured under software control to be in-

puts or outputs (Figure 8).

Z8

Port 0 (I/O)

Open

PAD

Out

VCC @ 5.0V

2.3 Hysteresis

1.5

In

Auto Latch Option

R

500 kΩ

Figure 8. Port 0 Conﬁguration

16

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Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Port 2, P27-P20. Port 2 is an 8-bit, bit programmable, bi-

directional, Schmitt-triggered CMOS compatible I/O port.

These eight I/O lines can be configured under software

control to be inputs or outputs, independently. Bits pro-

grammed as outputs can be globally programmed as ei-

ther push-pull or open-drain (Figure 9).

1

Z8

Port 2 (I/O)

Port 2

Open-Drain

Open

PAD

Out

1.5

2.3 Hysteresis

VCC @ 5.0V

In

Auto Latch Option

R

500 kΩ

Figure 9. Port 2 Conﬁguration

DS96DZ80301

P R E L I M I N A R Y

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Z86C02/E02/L02

®

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Zilog

PIN FUNCTIONS (Continued)

Port 3, P33-P31. Port 3 is a 3-bit, CMOS compatible port

with three fixed input (P33-P31) lines. These three input

lines can be configured under software control as digital

Schmitt-trigger inputs or analog inputs.

These three input lines are also used as the interrupt

sources IRQ0-IRQ3 and as the timer input signal T (Fig-

IN

ure 10).

Z8

Port 3

0 = Digital

R247 = P3M 1 = Analog

D1

TIN

DIG.

P31 Data Latch

IRQ2

PAD

+

P31 (AN1)

AN.

-

IRQ3

P32 Data Latch

IRQ0

PAD

+

P32 (AN2)

PAD

-

P33 (REF)

P33 Data Latch

IRQ1

V

cc

IRQ 0,1,2 = Falling Edge Detection

IRQ3 = Rising Edge Detection

Figure 10. Port 3 Conﬁguration

Comparator Inputs. Two analog comparators are added

is 5.0 V; the power supply and common mode rejection ra-

tios are 90 dB and 60 dB, respectively.

to input of Port 3, P31 and P32, for interface flexibility. The

comparators reference voltage P33 (REF) is common to

both comparators.

Interrupts are generated on either edge of Comparator 2's

output, or on the falling edge of Comparator 1's output.

The comparator output is used for interrupt generation,

Typical applications for the on-board comparators; Zero

crossing detection, A/D conversion, voltage scaling, and

threshold detection. In analog mode, P33 input functions

serve as a reference voltage to the comparators.

Port 3 data inputs, or T through P31. Alternatively, the

IN

comparators can be disabled, freeing the reference input

(P33) for use as IRQ1 and/or P33 input.

The dual comparator (common inverting terminal) features

a single power supply which discontinues power in STOP

mode. The common voltage range is 0-4 V when the V

CC

18

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®

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Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

FUNCTIONAL DESCRIPTION

The following special functions have been incorporated

into the Z86C02/E02/L02 devices to enhance the standard

Z8 core architecture to provide the user with increased de-

sign flexibility.

RESET. This function is accomplished by means of a Pow-

er-On Reset or a Watch-Dog Timer Reset. Upon power-

1

up, the Power-On Reset circuit waits for T

ms, plus 18

POR

clock cycles, then starts program execution at address

000C (Hex) (Figure 11). The control registers' reset value

is shown in Table 4.

INT OSC

XTAL OSC

POR

(Cold Start)

18 CLK

Reset Filter

Delay Line

T_PORms

Chip

Reset

P27

(Stop Mode)

Figure 11. Internal Reset Conﬁguration

Power-On Reset (POR). A timer circuit clocked by a ded-

icated on-board RC oscillator is used for a POR timer func-

operate in STOP Mode, but it can operate in HALT Mode

by using a WDH instruction.

tion. The POR time allows V and the oscillator circuit to

CC

Table 4. Control Register

stabilize before instruction execution begins. The POR

timer circuit is a one-shot timer triggered by one of the four

following conditions:

Reset Condition

Addr Reg. D7 D6 D5 D4 D3 D2 D1 D0 Comments

■ Power bad to power good status

■ Stop-Mode Recovery

FF SPL

FE GPR

FD RP

0

■ WDT time-out

FC FLAGS U U U U U U U U

FB IMR

FA IRQ

0

U U U U U U U

■ WDH time-out (in Halt Mode)

■ WDT time-out (in Stop Mode)

U U

0

0 IRQ3 is used

for positive

edge

detection

Watch-Dog Timer Reset. The WDT is a retriggerable

one-shot timer that resets the Z8 if it reaches its terminal

count. The WDT is initially enabled by executing the WDT

instruction and is retriggered on subsequent execution of

the WDT instruction. The timer circuit is driven by an on-

board RC oscillator. If the permanent WDT option is select-

ed then the WDT is enabled after reset and operates in

RUN Mode, HALT mode, STOP mode and cannot be dis-

abled. If the permanent WDT option is not selected then

the WDT, when enabled by the user's software, does not

F9 IPR

U U U U U U U U

F8 P01M U U U

0

U U

0

1

F7* P3M

F6* P2M

U U U U U U

0 P2 open-drain

1

1 Inputs after

reset

F3 PRE1 U U U U U U

0

F2 T1

F1 TMR

Note:

U U U U U U U U

0

*Registers are not reset after a STOP-Mode Recovery

using P27 pin. A subsequent reset will cause these control

registers to be reconfigured as shown in Table 4 and the

user must avoid bus contention on the port pins or it may

affect device reliability.

DS96DZ80301

P R E L I M I N A R Y

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Z86C02/E02/L02

®

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Zilog

FUNCTIONAL DESCRIPTION (Continued)

Location

Indentifiers

Program Memory. The Z8 addresses up to 512 bytes of

internal program memory (Figure 12). The first 12 bytes of

program memory are reserved for the interrupt vectors.

These locations contain six 16-bit vectors that correspond

to the six available interrupts. Bytes 0-511 are on-chip one-

time programmable ROM.

SPL

255

254

253

252

251

250

249

248

247

246

245

244

243

242

241

240

Stack Pointer (Bits 7-0)

Reserved

Register Pointer

Program Control Flags

Interrupt Mask Register

Interrupt Request Register

Interrupt Priority Register

Ports 0-1 Mode

RP

Flags

IMR

IRQ

1024

Location of

First Byte of

Instruction

On-Chip

ROM

IPR

Executed

After RESET

P01M

P3M

P2M

PRE0

T0

12

11

10

9

Port 3 Mode

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

IRQ0

Port 2 Mode

To Prescaler

Timer/Counter0

8

T1 Prescaler

PRE1

T1

7

Interrupt

Vector

(Lower Byte)

Timer/Counter1

6

Timer Mode

TMR

5

Not Implemented

4

128

127

Interrupt

Vector

(Upper Byte)

3

General Purpose

Registers

2

4

3

2

1

0

1

Port 3

Port 2

P3

P2

P1

P0

0

Reserved

Port 0

Figure 12. Program Memory Map

Register File. The Register File consists of three I/O port

registers, 61 general-purpose registers, and 12 control

and status registers R0-R3, R4-R127 and R241-R255, re-

spectively (Figure 13). General-purpose registers occupy

the 04H to 7FH address space. I/O ports are mapped as

per the existing CMOS Z8. The instructions can access

registers directly or indirectly through an 8-bit address

field. This allows short 4-bit register addressing using the

Register Pointer. In the 4-bit mode, the register file is divid-

ed into eight working register groups, each occupying 16

continuous locations. The Register Pointer (Figure 14) ad-

dresses the starting location of the active working-register

group.

Figure 13. Register File

20

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General-Purpose Registers (GPR). These registers are

undefined after the device is powered up. The registers

keep their last value after any reset, as long as the reset

occurs in the V voltage-specified operating range. Note:

Register R254 has been designated as a general-purpose

register. But is set to 00Hex after any reset.

1

CC

r7 r6 r5 r4

r3 r2 r1 r0

R253

(Register Pointer)

The upper nibble of the register file address

provided by the register pointer specifies

the active working-register group.

Counter/Timer. There is an 8-bit programmable

counter/timers (T1), each driven by its 6-bit programmable

prescaler. The T1 prescaler is driven by internal or external

clock sources. (Figure 15).

FF

F0

Register Group F

R15 to R0

The 6-bit prescaler divide the input frequency of the clock

source by any integer number from 1 to 64. The prescaler

7F

70

6F

drives its counter, which decrements the value (1 to 256)

that has been loaded into the counter. When both counter

and prescaler reach the end of count, a timer interrupt re-

quest IRQ5 (T1) is generated.

60

5F

50

4F

The lower nibble

of the register

file address

provided by the

instruction points

to the specified

register.

40

3F

The counter can be programmed to start, stop, restart to

continue, or restart from the initial value. The counters are

also programmed to stop upon reaching zero (Single-Pass

mode) or to automatically reload the initial value and con-

tinue counting (Modulo-N Continuous Mode).

Specified Working

Register Group

30

2F

20

1F

Register Group 1

R15 to R0

10

0F

The counter, but not the prescaler, is read at any time with-

out disturbing its value or count mode. The clock source for

T1 is user-definable and is either the internal microproces-

sor clock divided by four, or an external signal input

through Port 3. The Timer Mode register configures the ex-

ternal timer input (P31) as an external clock, a trigger input

that is retriggerable or non-retriggerable, or used as a gate

input for the internal clock.

R15 to R4

R3 to R0

Register Group 0

I/O Ports

00

Figure 14. Register Pointer

Stack Pointer. The Z8 has an 8-bit Stack Pointer (R255)

used for the internal stack that resides within the 60 gen-

eral-purpose registers. It is set to 00Hex after any reset.

DS96DZ80301

P R E L I M I N A R Y

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Z86C02/E02/L02

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Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

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FUNCTIONAL DESCRIPTION (Continued)

OSC

*

÷ 2

Internal

Clock

External Clock

Clock

Logic

6-Bit

Down

Counter

8-Bit

Down

Counter

IRQ5

÷4

Internal Clock

Gated Clock

Triggered Clock

PRE1

Initial Value

Register

T1

Initial Value

Register

Current Value

Register

T

P31

IN

Write

Internal Data Bus

Write

Read

Figure 15. Counter/Timers Block Diagram

Interrupts. The Z8 has five interrupts from four different

sources. These interrupts are maskable and prioritized

(Figure 16). The sources are divided as follows: the falling

edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge

of P32 (AN2), and one counter/timer. The Interrupt Mask

Register globally or individually enables or disables the

five interrupt requests (Table 5).

User must select any Z86E08 mode in Zilog's C12 ICE-

BOX™ emulator. The rising edge interrupt is not directly

supported on the Z86CCP00ZEM emulator.

Table 5. Interrupt Types, Sources, and Vectors

Vector

Name

IRQ0

Source

AN2(P32)

Location

Comments

External (F)Edge

0,1

When more than one interrupt is pending, priorities are re-

solved by a programmable priority encoder that is con-

trolled by the Interrupt Priority register. All Z8 interrupts are

vectored through locations in program memory. When an

Interrupt machine cycle is activated, an Interrupt Request

is granted. This disables all subsequent interrupts, saves

the Program Counter and Status Flags, and then branches

to the program memory vector location reserved for that in-

terrupt. This memory location and the next byte contain the

16-bit starting address of the interrupt service routine for

that particular interrupt request.

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

Notes:

REF(P33)

AN1(P31)

AN2(P32)

Reserved

T1

2,3

4,5

External (F)Edge

External (R)Edge

Reserved

6,7

8,9

10,11

Internal

F = Falling edge triggered

R = Rising edge triggered

To accommodate polled interrupt systems, interrupt inputs

are masked and the interrupt request register is polled to

determine which of the interrupt requests needs service.

22

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IRQ0 - IRQ5

1

IRQ

IMR

5

IPR

Global

Interrupt

Enable

Interrupt

Request

Priority

Logic

Vector Select

Figure 16. Interrupt Block Diagram

Clock. The Z8 on-chip oscillator has a high-gain, parallel-

resonant amplifier for connection to a crystal, ceramic res-

onator, or any suitable external clock source (XTAL1 = IN-

PUT, XTAL2 = OUTPUT). The crystal should be AT cut,

8 MHz max, with a series resistance (RS) of less than or

equal to 100 Ohms.

The crystal or ceramic resonator should be connected

across XTAL1 and XTAL2 using the vendors crystal or ce-

ramic resonator recommended capacitors from each pin

directly to device ground pin 14 (Figure 17). Note that the

crystal capacitor loads should be connected to V , Pin 14

SS

to reduce Ground noise injection.

XTAL1

XTAL2

XTAL1

XTAL2

C1

C

R

L

*

Vss *

XTAL2

C2

Vss *

Ceramic

LC Clock

External Clock

RC Clock

Resonator

or Crystal

=Device Ground Pin

*

Figure 17. Oscillator Conﬁguration

DS96DZ80301

P R E L I M I N A R Y

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Z86C02/E02/L02

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Zilog

FUNCTIONAL DESCRIPTION (Continued)

HALT Mode. This instruction turns off the internal CPU

clock but not the crystal oscillation. The counter/timer and

external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain ac-

tive. The device is recovered by interrupts, either external-

ly or internally generated. An interrupt request must be ex-

ecuted (enabled) to exit HALT mode. After the interrupt

service routine, the program continues from the instruction

after the HALT.

Watch-Dog Timer (WDT). The Watch-Dog Timer is en-

abled by instruction WDT. When the WDT is enabled, it

cannot be stopped by the instruction. With the WDT in-

struction, the WDT is refreshed when it is enabled within

every 1 Twdt period; otherwise, the controller resets itself,

The WDT instruction affects the flags accordingly; Z=1,

S=0, V=0. WDT = 5F (Hex)

Opcode WDT (5FH). The first time opcode 5FH is execut-

STOP Mode. This instruction turns off the internal clock

and external crystal oscillation and reduces the standby

current to 10 µA. The STOP mode is released by a RESET

through a Stop-Mode Recovery (pin P27). A Low input

condition on P27 releases the STOP mode. Program exe-

cution begins at location 000C(Hex). However, when P27

is used to release the STOP mode, the I/O port mode reg-

isters are not reconfigured to their default power-on condi-

tions. This prevents any I/O, configured as output when the

STOP instruction was executed, from glitching to an un-

known state. To use the P27 release approach with STOP

mode, use the following instruction:

ed, the WDT is enabled and subsequent execution clears

the WDT counter. This must be done at least every T

;

WDT

otherwise, the WDT times out and generates a reset. The

generated reset is the same as a power-on reset of T

,

POR

plus 18 XTAL clock cycles.The WDT does not run in stop

mode, unless the permanent WDT enable option is select-

ed. The WDT does not run in halt mode unless WDH in-

struction is executed or permanent WDT enable option is

selected.

Opcode WDH (4FH). When this instruction is executed it

enables the WDT during HALT. If not, the WDT stops

when entering HALT. This instruction does not clear the

counters, it just makes it possible to have the WDT running

during HALT mode. A WDH instruction executed without

executing WDT (5FH) has no effect.

LD

P2M, #1XXX XXXXB

NOP

STOP

Notes:

Note: Opcode WDH and permanently enabled WDT is

X = Dependent on user’s application.

Stop-Mode Recovery pin P27 is not edge triggered.

not directly supported by the Z86CCP00ZEM.

Auto Reset Voltage (V ). The Z8 has an auto-reset built-

LV

in. The auto-reset circuit resets the Z8 when it detects the

In order to enter STOP or HALT mode, it is necessary to

first flush the instruction pipeline to avoid suspending exe-

cution in mid-instruction. To do this, the user executes a

NOP (opcode=FFH) immediately before the appropriate

SLEEP instruction, i.e.:

V

below V . Figure 18 shows the Auto Reset Voltage

CC

LV

versus temperature.

FF

6F

or

NOP

; clear the pipeline

; enter STOP mode

STOP

FF

7F

NOP

; clear the pipeline

; enter HALT mode

HALT

24

P R E L I M I N A R Y

DS96DZ80301

Z86C02/E02/L02

®

Zilog

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Vcc

(Volts)

3.2

3.1

3.0

2.9

1

Z86E02

Z86C02

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

1.9

Z86L02

1.8

1.7

1.6

Temp

40°C 60°C

80°C

100°C

–40°C –20°C

0°C

20°C

Figure 18.Typical Auto Reset Voltage (V ) vs.Temperature

LV

EPROM/TEST MODE Disable. When selected, this bit will

permanently disable EPROM and Factory Test mode.

Options

The Z86C02/E02/L02 offers ROM protect, Low Noise,

Auto Latch Disable, RC Oscillator, and Permanent WDT

enable features as options. The Z86E02 must be power

cycled to fully implement the selected option after pro-

gramming.

Auto Latch Disable. Auto Latch Disable option when Se-

lected will globally disable all Auto Latches.

RC. RC Oscillator option when selected will allow using a

resistor (R) and a capacitor (C) as a clock source.

Low Noise. The Z8 can operate in a low EMI emission

mode by selecting the low noise option. Use of this feature

will result in:

WDT Enable. WDT Enable option bit when selected will

have the WDT permanently enabled in all modes and can

not be stopped in HALT or STOP Mode.

■ All drivers slew rates are reduced to 10 ns (typical).

EPROM Mode Description. In addition to V and GND

DD

■ Internal SCLK/TCLK = XTAL operation is limited to a

(V ), the Z8 changes all its pin functions in the EPROM

SS

maximum of 4 MHz - 250 ns cycle time.

mode. XTAL2 has no function, XTAL1 functions as /CE,

P31 functions as /OE, P32 functions as EPM, P33 func-

■ Output drivers have resistances of 200 ohms (typical).

■ Oscillator divide-by-two circuitry is eliminated.

tions as V , and P02 functions as /PGM.

PP

Please note that when using the device in a noisy environ-

ment, it is suggested that the voltages on the EPM and CE

ROM Protect. ROM Protect fully protects the Z8 ROM

code from being read externally. When ROM Protect is se-

lected, the instructions LDC and LDCI are supported.

(However, instructions LDE and LDEI are not supported.)

pins be clamped to V through a diode to V to prevent

CC

accidentally entering the OTP mode. The V

both a diode and a 100 pF capacitor.

requires

PP

User Modes. Table 6 shows the programming voltage of

each mode of Z86E02.

DS96DZ80301

P R E L I M I N A R Y

25

Z86C02/E02/L02

®

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Zilog

FUNCTIONAL DESCRIPTION (Continued)

Table 6. EPROM Programming Table

Programming

Modes

V

*

CC

EPM

/CE

/OE

/PGM

ADDR

NU

DATA

Out

In

PP

EPROM READ

PROGRAM

NU

V

IH

5.0V

6.4V

H

IL

V

H

IH

IL

PROGRAM VERIFY

ROM PROTECT

V

Out

NU

6.4V

IL

IH

V

5.0-6.4V

H

IL

LOW NOISE

SELECT

V

NU

IH

AUTO LATCH

DISABLE

V

NU

5.0-6.4V

H

IH

H

IL

WDT ENABLE

V

NU

5.0-6.4V

H

IL

H

IH

IL

EPROM/TEST

MODE Disable

V

IL

H

Notes: V =13.0V ±0.25 V

.

H

DC

V =As per specific Z8 DC specification.

IH

V =As per specific Z8 DC specification.

IL

X=Not used, but must be set to V , V , or V level.

H

IH

IL

NU=Not used, but must be set to either V or V level.

IH

IL

I

during programming = 40 mA maximum.

during programming, verify, or read = 40 mA maximum.

PP

CC

* V has a tolerance of ±0.25V.

CC

Internal Address Counter. The address of Z86E02 is

generated internally with a counter clocked through pin

P01 (Clock). Each clock signal increases the address by

one and the "high" level of pin P00 (Clear) will reset the ad-

dress to zero. Figure 19 shows the setup time of the serial

address input.

Programming Waveform. Figures 20, 21, 22, and 23

show the programming waveforms of each mode. Table 7

shows the timing of programming waveforms.

Programming Algorithm. Figure 24 shows the flow chart

of the Z86E02 programming algorithm.

Table 7. Z86E02 Timing of Programming Waveforms

Min

Parameters

Name

Max

Units

1

2

3

Address Setup Time

Data Setup Time

2

µs

V

Setup

PP

CC

4

Setup Time

2

µs

5

6

Chip Enable Setup Time

Program Pulse Width

Data Hold Time

2

0.95

2

µs

ms

µs

ns

ms

µs

ms

ns

7

8

/OE Setup Time

2

9

Data Access Time

188

4000

100

3.2

10

11

12

13

14

15

16

Data Output Float Time

Over-program Pulse Width

EPM Setup Time

2.85

2

/PGM Setup Time

2

Address to /OE Setup Time

Option Program Pulse Width

/OE Low Width

2

150

250

26

P R E L I M I N A R Y

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Z86C02/E02/L02

®

Zilog

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

T2

P01 = Clock

1

T4

T3

T1

P00 = Clear

T5

Internal

Address

0 Min

Vih

Vil

Data

Invalid

Valid

Invalid

Valid

9

Legend:

T1 Reset Clock Width

T2 Input Clock High

T3 Input Clock Period

T4 Input Clock Low

30 ns Min

70 ns Min

30 ns Min

15 ns Max

T5 Clock to Address Counter Out Delay

Figure 19. Z86E02 Address Counter Waveform

DS96DZ80301

P R E L I M I N A R Y

27

Z86C02/E02/L02

®

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Zilog

FUNCTIONAL DESCRIPTION (Continued)

VIH

Address

Address Stable

Valid

VIL

VIH

VIL

0 Min

Data

Invalid

Valid

Invalid

9

VH

VPP

VIH

VH

VIL

EPM

VCC

12

5V

VIH

VIL

VIH

VIL

VIH

VIL

/CE

/OE

0 Min

16

/PGM

3

Figure 20. Z86E02 Programming Waveform (EPROM Read)

28

P R E L I M I N A R Y

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Z86C02/E02/L02

®

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VIH

VIL

Address

1

VIH

VIL

Data

VPP

VH

VIH

3

6.4V

5V

VCC

4

VH

/CE

/OE

VIH

5

VIL

8

VIH

VIL

EPM

12

VIH

VIL

/PGM

15

Auto Latch

ETM

Disable

WDT

Figure 21. Z86E02 Programming Waveform (Program and Verify)

DS96DZ80301

P R E L I M I N A R Y

29

Z86C02/E02/L02

®

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Zilog

FUNCTIONAL DESCRIPTION (Continued)

VIH

Address

VIL

VIH

Data

VIL

VH

VPP

VIH

3

6.4V

5V

VCC

4

V

H

/CE

/OE

VIH

5

VIH

VIL

VH

VIH

EPM

VIL

12

VIH

/PGM

VIL

15

ROM Protect

15

Low Noise

Figure 22. Z86E02 Programming Options Waveform (ROM Protect and Low Noise Program)

30

P R E L I M I N A R Y

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Z86C02/E02/L02

®

Zilog

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

VIH

VIL

Address

1

VIH

VIL

Data

VPP

VH

VIH

3

6.4V

5V

VCC

4

VH

/CE

/OE

VIH

5

VIL

8

VIH

VIL

EPM

12

VIH

VIL

/PGM

15

Auto Latch

ETM

Disable

WDT

Figure 23. Z86E02 Programming Options Waveform (Auto Latch Disable,

Permanent WDT Enable, and EPROM/TEST MODE Disable)

DS96DZ80301

P R E L I M I N A R Y

31

Z86C02/E02/L02

®

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Zilog

FUNCTIONAL DESCRIPTION (Continued)

Start

Addr =

First Location

Vcc = 6.4V

Vpp = 13.0V

N = 0

Program

1 ms Pulse

Increment N

Yes

N = 25 ?

No

Fail

Verify

One Byte

Verify Byte

Pass

Prog. One Pulse

3xN ms Duration

No

Increment

Last Addr ?

Address

Yes

Vcc = Vpp = 5.0V

Fail

Verify All

Bytes

Pass

Device Failed

Device Passed

Figure 24. Z86E02 Programming Algorithm

32

P R E L I M I N A R Y

DS96DZ80301

Z86C02/E02/L02

®

Zilog

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Z8 CONTROL REGISTERS

R241 TMR

R247 P3M

D7 D6 D5 D4 D3 D2 D1 D0

1

D7 D6 D5 D4 D3 D2 D1 D0

Reserved

(Must be 0)

0

1

Port 2 Open-Drain

Port 2 Push-pull

0

1

Disable T Count

0

Enable T Count

0

Port 3 Inputs

0

1

Digital Mode

Analog Mode

0

1

No Function

Reserved (Must be 0)

Load T

1

0

1

Disable T Count

1

Enable T Count

1

Figure 29. Port 3 Mode Register (F7 :Write Only)

H

T

Modes

IN

00 External Clock Input

01 Gate Input

R248 P01M

10 Trigger Input

(Non-retriggerable)

11 Trigger Input

(Retriggerable)

D7 D6 D5 D4 D3 D2 D1 D0

P0 -P0 Mode

3

0

00 = Output

01 = Input

Reserved (Must be 0.)

Reserved (Must be 1.)

Reserved (Must be 0.)

Figure 25. Timer Mode Register (F1 : Read/Write)

H

Figure 30. Port 0 and 1 Mode Register

R242 T1

(F8 :Write Only)

H

D7 D6 D5 D4 D3 D2 D1 D0

R249 IPR

D7 D6 D5 D4 D3 D2 D1 D0

T

Initial Value

1

(When Written)

(Range 1-256 Decimal

01-00 HEX)

Interrupt Group Priority

000 Reserved

001 C > A > B

010 A > B > C

011 A > C > B

100 B > C >A

101 C > B >A

110 B > A > C

111 Reserved

T

Current Value

1

(When READ)

Figure 26. Counter Timer 1 Register (f2 :Read/Write)

H

R243 PRE1

IRQ1, IRQ4 Priority (Group C)

0

1

IRQ1 > IRQ4

IRQ4 > IRQ1

D7 D6 D5 D4 D3 D2 D1 D0

IRQ0, IRQ2 Priority (Group B)

0

1

IRQ2 > IRQ0

IRQ0 > IRQ2

Count Mode

0 = T Single Pass

1

IRQ3, IRQ5 Priority (GroupA)

0

1

1 = T Modulo N

1

IRQ5 > IRQ3

IRQ3 > IRQ5

Clock Source

1 = T Internal

1

Reserved (Must be 0.)

0 = T External Timing Input

1

(T ) Mode

IN

Prescaler Modulo

(Range: 1-64 Decimal

01-00 HEX)

Figure 31. Interrupt Priority Register

(F9 :Write Only)

H

Figure 27. Prescaler! Register (F3 :Write Only)

H

R246 P2M

D7 D6 D5 D4 D3 D2 D1 D0

P2 - P2 I/O Definition

7

0

0 Defines Bit as OUTPUT

1 Defines Bit as INPUT

Figure 28. Port 2 Mode Register (F6 :Write Only)

H

DS96DZ80301

P R E L I M I N A R Y

33

Z86C02/E02/L02

®

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Zilog

Z8 CONTROL REGISTERS (Continued)

R253 RP

R250 IRQ

D7 D6 D5 D4 D3 D2 D1 D0

IRQ0 = P32 Input ↓

IRQ1 = P33 Input ↓

IRQ2 = P31 Input ↓

IRQ3 = P32 Input ↑

IRQ4 = Reserved

IRQ5 = T1

Reserved (Must be 0.)

Register Pointer

Figure 35. Register Pointer FD : Read/Write)

H

Reserved (Must be 0.)

R255 SPL

Figure 32. Interrupt Request Register

D7 D6 D5 D4 D3 D2 D1 D0

(FA : Read/Write)

H

Stack Pointer Lower

Byte (SP - SP

)

7

0

R251 IMR

D7 D6 D5 D4 D3 D2 D1 D0

Figure 36. Stack Pointer (FF : Read/Write)

H

1

Enables IRQ5-IRQ0

(D = IRQ0)

0

Reserved (Must be 0.)

Enables Interrupts

1

Figure 33. Interrupt Mask Register (FB : Read/Write)

H

R252 Flags

D7 D6 D5 D4 D3 D2 D1 D0

User Flag F1

User Flag F2

Half Carry Flag

Decimal Adjust Flag

Overflow Flag

Sign Flag

Zero Flag

Carry Flag

Figure 34. Flag Register (FC : Read/Write)

H

34

P R E L I M I N A R Y

DS96DZ80301

Z86C02/E02/L02

®

Zilog

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

PACKAGE INFORMATION

1

Figure 37. 18-Pin DIP Package Diagram

Figure 38. 18-Pin SOIC Package Diagram

DS96DZ80301

P R E L I M I N A R Y

35

Z86C02/E02/L02

®

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

Zilog

ORDERING INFORMATION

Standard Temperature

18-Pin DIP

18-Pin SOIC

Z86E0208PSC

Z86L0208PSC

Z86C0208PSC

Z86E0208PSC1903

Z86E0208SSC

Z86L0208SSC

Z86C0208SSC

Z86E0208SSC1903

Extended Temperature

18-Pin DIP

18-Pin SOIC

Z86E0208PEC

Z86L0208PEC

Z86C0208PEC

Z86E0208PEC1903

Z86E0208SEC

Z86L0208SEC

Z86C0208SEC

Z86E0208SEC1903

For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired.

CODES

Preferred Package

Speed

P = Plastic DIP

08 = 8 MHz

Longer Lead Time

Environmental

S = SOIC

C = Plastic Standard

Preferred Temperature

S = 0°C to +70°C

E = –40°C to +105°C

Example:

Z 86E08 08 P S C

is a Z86E08, 08 MHz, DIP, 0° to +70°C, Plastic Standard Flow

Environmental Flow

Temperature

Package

Speed

Product Number

Zilog Preﬁx

36

P R E L I M I N A R Y

DS96DZ80301

Z86C02/E02/L02

®

Zilog

Cost Effective, 512-Byte ROM CMOS Z8 Microcontrollers

document may be copied or reproduced in any form or by

any means without the prior written consent of Zilog, Inc.

The information in this document is subject to change

without notice. Devices sold by Zilog, Inc. are covered by

warranty and patent indemnification provisions appearing

in Zilog, Inc. Terms and Conditions of Sale only.

Zilog’s products are not authorized for use as critical

components in life support devices or systems unless a

specific written agreement pertaining to such intended use

is executed between the customer and Zilog prior to use.

Life support devices or systems are those which are

intended for surgical implantation into the body, or which

sustains life whose failure to perform, when properly used

in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in

significant injury to the user.

1

ZILOG, INC. MAKES NO WARRANTY, EXPRESS,

STATUTORY, IMPLIED OR BY DESCRIPTION,

REGARDING THE INFORMATION SET FORTH HEREIN

OR REGARDING THE FREEDOM OF THE DESCRIBED

Zilog, Inc. 210 East Hacienda Ave.

Campbell, CA 95008-6600

Telephone (408) 370-8000

FAX 408 370-8056

DEVICES

FROM

INTELLECTUAL

PROPERTY

INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY

OF MERCHANTABILITY OR FITNESS FOR ANY

PURPOSE.

Internet: http://www.zilog.com

Zilog, Inc. shall not be responsible for any errors that may

appear in this document. Zilog, Inc. makes no commitment

to update or keep current the information contained in this

document.

DS96DZ80301

P R E L I M I N A R Y

37


型号：	Z86E0208SEC1903
厂家：	ZILOG, INC.
描述：	Microcontroller, 8-Bit, OTPROM, Z8 CPU, 8MHz, CMOS, PDSO18, SOIC-18 可编程只读存储器时钟微控制器光电二极管
文件：	总37页 (文件大小：970K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Z86E0208SEC1903 [ZILOG]

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