Z0803008DEA_技术文档

ZiLOG, Inc.

2H - Year 2002

Quality

And

Reliability

Report

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ZiLOG

2002Quality and Reliability Report

Chapter Title and Subsection

TABLE OF CONTENTS

Chapter Title and Subsection

Chapter 1 - ZiLOG’s Quality Culture

Reliability And Quality Assurance Policy Statement………………………………. 1 - 1

ZiLOG Quality Policy Mission Statement…………………………………………. 1 - 2

ZiLOG’s Quality And Reliability Program………………………………………… 1 - 3

ZiLOG’s Environmental, Health and Safety Policy……………………………….. 1 - 8

ISO Certification……………………………………………………………………. 1 - 9

Quality and Reliability Trend Charts………………………………………………. 1 - 10

ZiLOG’s Quality Organization Chart……………………………………………… 1 - 11

Chapter 2 - Customer Quality Support System

Customer Failure Analysis/Correlation Procedure ………………………………… 2 - 1

Summary of QC Test Equipment ………………………………………………….. 2 – 4

List of Outside FA Labs …………………………………………………………… 2 – 9

Customer Notification System……………………………………………………… 2 – 10

Customer Change Notification Letter Z80S183 Die Revision..……………………. 2 - 11

Chapter 3 - Qualification Requirements

Product/Process Qualification Requirements………………………………………. 3 - 1

ZiLOG Product Qualification Summary…………………………………………… 3 - 2

Package Qualification Requirements……………………………………………….. 3 - 3

ZiLOG Package Qualification Summary…………………………………………... 3 - 4

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Chapter Title and Subsection

Chapter 4 - Quality Monitor Systems

Failure Rate Prediction Calculations……………………………………………….. 4 - 1

ESD Testing Methodology…………………………………………………………. 4 – 4

Latchup Testing Methodology………………………………………………….….. 4 – 4

ZiLOG’s Reliability Summary………………………………………………….….. 4 – 5

Early Life…………………………………………………………………………… 4 – 5

Long Term Life…………………………………………………………………….. 4 – 5

Pressure Pot………………………………………………………………………… 4 – 5

Temperature Cycle…………………………………………………………………. 4 – 5

Highly Accelerated Stress Test………………………………………………….…. 4 – 6

Package Integrity Test……………………………………………………………… 4 – 6

Reliability Monitor Testing Requirements Table 1………………………………….. 4 – 7

Reliability Monitor Early Life Test Conditions 168 Hrs, 125°C Burn-In

4 – 8

(CMOS Plastic) Table 2…………..………………………………………………….

Reliability Monitor Early Life Test Conditions 168 Hrs, 125°C Burn-In

(NMOS Plastic) Table 3…………………..…………………………………….……

4 – 9

Reliability Monitor Long-Term Life Test Conditions: 150°C, 5V, 184 Hrs Burn-In

(CMOS) Table 4……………………………………………………………………..

4 – 12

4 – 15

Reliability Monitor Long-Term Life Test Conditions: 125°C, 1000 Hrs Burn-In

(CMOS) Table 5……………………………………………………………………...

Reliability Test Summary Early Life Test Summary Table 6. ...………………….…. 4 – 16

Reliability Test Summary Long-Term Life Test Summary Table7…..…………….. 4 – 16

Reliability Monitor Pressure Pot Test Conditions (CMOS-Plastic) Table 8………... 4 – 17

Reliability Monitor Pressure Pot Test Conditions (NMOS-Plastic) Table 9………... 4 – 19

Reliability Monitor Temperature Cycling Test Conditions (CMOS) Table 10……... 4 – 20

Reliability Monitor Temperature Cycling Test Conditions (NMOS) Table 11……... 4 – 23

Reliability Monitor Highly Accelerated Stress Test (HAST)-(CMOS) Table 12 …... 4 – 24

Reliability Monitor ZiLOG Packaging Integrity Test Results (CMOS) Table 13…... 4 – 25

Reliability Monitor ZiLOG Packaging Integrity Test Results (NMOS) Table 14…... 4 – 28

C-Mode Scanning Acoustic Microscope Monitor 2002 (CMOS) Table 15………… 4 – 29

C-Mode Scanning Acoustic Microscope Monitor 2002 (NMOS) Table 16………… 4 – 37

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2002Quality and Reliability Report

Chapter Title and Subsection

Chapter 5 - Assembly and Test

Package Types……………………………………………………………………... 5 – 1

Technology Data…………………………………………………………………… 5 - 1

Pre/Post Packaging Device Test Procedures………………………………………. 5 - 2

Plastics Process Flow………………………………………………………………. 5 - 3

Plastic-Standard Assembly/Test Process…………………………………….…….. 5 - 4

General Material Specification…………………………………………………….. 5 - 5

Chapter 6 The Handling and Storage of Surface Mount Devices …………

Handling………………………………………………………………..………….. 6- 1

Lead Protection ……………...…………………………………………………….. 6 - 2

ESD Protection ……………...…………………………………………………….. 6 - 2

Storage/Unpacking Cautions ..…………………………………………………….. 6 - 3

Soldering …………………….…………………………………………………….. 6 - 3

Desoldering ………………………………………………………………………... 6 - 3

Chapter 7 - Quality Systems

Quality Systems………………………………………………………….……..….. 7– 1

Subcontracting …………………………………………………………………….. 7 – 1

Lot Traceability …………………………………………………………………… 7 – 1

Availability of Documentation on Monitoring ……………………………………. 7 – 1

Quality Data ……………………………………………………………………….. 7 – 1

Testing …………………………………………………………………………….. 7 – 2

Test Tape Support …………………………………………………………………. 7 – 2

When Manufacturing is Performed Offshore, What Are The Controls? ………….. 7 – 3

Availability of Programming Facilities …………………………………………… 7 – 3

Documentation Control ……………………………………………………………. 7 – 3

QA Audit …………………………………………………………………………... 7 – 3

Material Control …………………………………………………………………… 7 – 3

Vendor of the Year Award ………………………………………………………… 7 - 4

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Chapter Title and Subsection

Chapter 8 - Statistical Process Control

Scope ……………………………………………………………………………..... 8 - 1

Control Charts ……………………………………………………………………... 8 – 1

Design of Experiments …………………………………………………………….. 8 - 1

Chapter 9 - Document Control

Document Control System…………………………………………………………. 9 – 1

ZiLOG Policies, Procedures or Specifications ……………………………………. 9 – 2

Flow Chart ………………………………………………………………………… 9 – 3

SPC Fabrication Typical Process …………………………………………………. 9 – 4

Chapter 10 - Thermal Properties

Thermal Characteristics……………………………………………………………. 10 - 1

Device θ_JA, θ_JCTable 1 Summary Of Thermal Characteristics For ZiLOG Plastic

Packages…………………………………………………………………………….

10 - 2

10 - 3

10 - 4

10 - 10

Device θ_JA, θ_JCTable 2 Summary Of Thermal Resistance For Hermetic

Packages………………...…………………………………………………………..

Device θ_JA, θ_JCTable 3 Summary Of Thermal Resistance For Networking

Technology Devices…………..………………………………..…………………..

Device θ_JA, θ_JCTable 4 Summary Of Thermal Resistance For Connecting

Technology & Home Entertainment……………………………………………….

Chapter 11 - Glossary

ZiLOG Glossary……………………………………………………………………. 11 – 1

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2002Quality and Reliability Report

CHAPTER 1

ZiLOG’s Quality Culture

RELIABILITY AND QUALITY ASSURANCE POLICY STATEMENT

ZiLOG’s philosophy towards quality has been consistently aimed at continuous product

improvement and optimization of processes associated with the design, manufacture, test and

delivery of products that conform to all established requirements for total customer satisfaction.

It has been a ZiLOG tradition that the customer is the main driving force in a company-wide

goal to achieve the highest quality possible. Through excellent management of its personnel,

equipment, materials, and environmental resources, ZiLOG is well positioned for success.

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2002Quality and Reliability Report

ZiLOG QUALITY POLICY MISSION STATEMENT

“ZiLOG designs, builds, tests, and delivers quality through constant product and process

improvements for total customer satisfaction.”

•

ZiLOG designs quality solutions by matching our designs to established process parameters.

Hence, product design will always be guardbanded relative to process capabilities.

ZiLOG builds quality so that the different contributing factors work harmoniously to

achieve and maintain the required level of product quality and reliability.

ZiLOG rigorously tests our products and processes so customers receive the highest quality

and reliability.

ZiLOG delivers quality so customers receive solutions that meet their expectations and

contract requirements.

At ZiLOG, we subscribe to the philosophy that quality is everyone’s responsibility.

The employees of ZiLOG believe that there can be no compromise in the Reliability and

Quality of its products. The information provided in this report reflects their determination to

provide the finest possible products.

ZiLOG is proud of its Reliability and Quality programs and is pleased to share this data with its

customers. For further information, contact ZiLOG’s Director of Reliability and Quality

Assurance.

Mike Burgdorf

Director

Reliability and Quality Assurance

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ZiLOG’S QUALITY AND RELIABILITY PROGRAM

ZiLOG, Inc. has an excellent reputation for the quality and reliability of its products.

ZiLOG’s Quality and Reliability Program is based on careful study of the principles laid down

by such pioneers as W. E. Deming and J. M. Juran. Even more importantly, we have benefited

from the observation and practical implementation of those principles as practiced in Japanese,

European and American manufacturing facilities.

The ZiLOG program begins with employee involvement. Whether the judgment of our

performance is based on perfection with incoming inspection, trouble free service in the field,

or timely and accurate customer service, we recognize that our employees ultimately control

these factors. Hence, our quality program is broadly shared throughout the organization.

Harmony Between Design and Process

High product quality and reliability in VLSI products is possible only if there is structural

harmony between product design and manufacturing. Great care is taken to ensure that the

statistical process control limits observed within the manufacturing plants properly guardband

the design technology used to configure the circuit and layout in ZiLOG’s automated design

methodology.

Through use of a technique which we call Process Templating, the technology file in the

automated design system is periodically updated to ensure that product design parameters fall

within the statistical control limits with which the process is actually operated. In simple terms,

the Process Template is the profile displayed by the process evaluation parameters which are

automatically recorded from the test patterns on wafers as they proceed through the production

line. These parameters are translated into the design technology file attributes so every product

design bears a lock and key relationship to the process.

Training

The integrity of our product design and manufacturing process depends on the skills of our

employees. ZiLOG training emphasizes the fundamentals involved in product design and

processing for quality and reliability.

Customer Service, an important aspect of ZiLOG’s quality performance as a vendor, also

depends upon our people clearly understanding their jobs and our obligations to our customers.

This aspect of training is also a part of the overall curriculum administered by ZiLOG.

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2002Quality and Reliability Report

Order Acknowledgment Policy

One definition of vendor quality performance is that the vendor “does what he promises or

acknowledges.” Acceptable reliability and quality is achieved only if ZiLOG and the customer

are in agreement on product and delivery specifications.

Test Guardbanding

No physical attribute is absolute. Customers’ test methods may differ from ZiLOG’s due to

variations in test equipment, temperature or specification interpretation. To ensure that every

ZiLOG product performs to full customer expectations, ZiLOG uses a “waterfall” methodology

in its testing. The first electrical tests made on the circuit for both AC and DC parameters, at the

wafer probe operation, are guardbanded to the final test specifications. The final test

specifications for both AC and DC parameters, in turn, are guardbanded to the quality control

outgoing sample. The quality control outgoing sample is guardbanded to data sheet

specifications. This technique of “waterfall” guardbanding eliminates circuits which may be

marginal to the customer’s expectations long before they get to the shipping container.

Probe at Temperature

Semiconductor devices tend to exhibit their most limited performance at the highest operating

temperature. Therefore, it is ZiLOG’s policy that all chips are tested at high temperature the

very first time they are electrically screened at the wafer probe station. The circuits are tested

again at their upper operating temperature limit in the 100% final test operation.

Process Characterization

Before release to production, every process is thoroughly characterized by an exhaustive series

of pilot production runs and tests which identify the statistical, electrical, and mechanical limits

of that particular process. This documentation is maintained as the historical record or

“footprint” for that particular regime.

Process recharacterization is done any time there is a major process or manufacturing site

change, and the resulting documentation is then added to the characterization history. Once the

process is fully characterized, test site evaluation and process template data is gathered

frequently to make sure that the process remains in specification.

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Product Characterization

Every ZiLOG product design is evaluated over extremes of operating temperature, supply

voltage, and clock frequency prior to production release. This information permits the proper

guardbanding of the test program waterfall and identification of any marginal “corners” in

design tolerances.

A product characterization summary, which details the more important tolerances identified in

the process of this exhaustive product design evaluation, is available to ZiLOG’s customers.

Process Qualification

ZiLOG also qualifies every process prior to production by an exhaustive stress sequence

performed on test chips and on representative products. Once a process regime is qualified, a

process re-qualification is performed any time there is a major process change, or whenever the

process template statistical quality limits are significantly exceeded or adjusted.

Product Qualification

In addition to characterization, every new ZiLOG product design is fully qualified by a

comprehensive series of life, electrical, and environmental tests before release to production.

Whenever possible, both industry standard environmental and life tests are employed. Again, a

qualification summary is available to our customers which details certain key life and

environmental data taken in the course of these evaluations. Please see Chapter Four

(Qualification Requirements) for an example of the ZiLOG Package Qualification Summary

and Device Qualification Summary.

PPM Measurement, Direct and Indirect

It is frequently said that if you want to improve something, you need to put a measure on it.

Therefore, ZiLOG measures its outgoing quality “parts per million” by the maintenance of

careful records on the statistical sampling of production lots prepared for shipment. This

information is then translated by our statisticians to a statement of our parts per million

outgoing quality performance.

Of course, it is one thing for ZiLOG to think it is doing a good job in outgoing product quality

and it is another for a customer to agree. Therefore, we ask certain key customers to provide us

with their incoming inspection data that helps us calibrate our outgoing performance in terms of

the actual results in the field. The fact that ZiLOG has been awarded “ship to stock” status by

many customers testifies to our success in this area.

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FIT Measurement Direct and Indirect

Just as ZiLOG records its outgoing quality in terms of parts per million, it also measures its

outgoing product reliability in terms of “FITS” or Failures per billion device hours. This

calculation is done by using the results of weekly operating life test measurements on the

circuits performed in accordance with standard specifications.

Field Quality Engineers

ZiLOG maintains a force of skilled Field Application Engineers, who are also trained as Field

Quality Engineers. These engineers are available on immediate call to consult our customers on

any problems they may be experiencing with ZiLOG product performance.

Product Analysis

Product Analysis facilities, staffed by experienced professionals, exist at each ZiLOG site to

provide rapid evaluation of in-process and in-field rejects. ZiLOG is pleased to share product

analysis reports on specific products with the customer upon request.

Oxide Charge to Breakdown (Qbd)

Gate oxide quality for ZiLOG’s major fabrication processes is monitored weekly through

extraction of wafer level Qbd data from the parametric test database. ZiLOG’s Qbd test is based

on the J-ramp test specified in JEDEC Standard JESD35- “Procedure for the Wafer-Level

Testing of Thin Dielectrics.”

Statistical Process Control

ZiLOG employs Statistical Process Control at all critical process steps. Deviations from norms

must be evaluated by a Q/R review board.

Total Quality Program

ZiLOG employees actively participate in meetings where methods are proposed, reviewed, and

adopted. These meetings enable a department to do its job in a more precise and accurate

manner.

ZiLOG Vendor of the Year Award

ZiLOG is proud of the many quality and performance awards it has received from its customers.

In turn, ZiLOG makes an annual award to the vendor who has done the best overall job for

ZiLOG.

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2002Quality and Reliability Report

Environmental Protection Recycling

ZiLOG is committed to an environmental protection-recycling project that is becoming an

international requirement. ZiLOG prefers that materials used to package its finished products be

recyclable and/or manufactured from recycled material. The “Recyclable” symbol can already

be found on shipping boxes, tubes and reels, and on shipping trays for QFP/VQFP products.

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2002Quality and Reliability Report

ZiLOG ENVIRONMENTAL, HEALTH AND SAFETY POLICY

ZiLOG’s mission is to create superior value for our stakeholders. The health and safety of our

employees, and the proper care of our environment, are of paramount importance. ZiLOG’s

concern for them is not only good corporate citizenship, it’s also good business.

ZiLOG is committed to a continuously improving Environmental, Health and Safety

Management System. Strict compliance with applicable EHS regulations is considered a

minimum standard – neither production goals nor financial objectives shall excuse

noncompliance.

The core values of ZiLOG’s EHS Management System are to:

•

Create, maintain and promote a safe and healthful workplace for all employees.

Comply with the intent as well as the letter of all relevant EHS regulations at the Federal,

State and Local levels.

•

Set EHS goals and objectives and measure progress toward them.

Promote a respect for the environment among employees.

Conserve resources and minimize waste by reducing, reusing, and recycling.

Integrate EHS considerations into business planning, decision making, and daily activities.

Provide the resources and training to carry out this policy.

Prevent accidents and minimize environmental impacts.

Communicate our EHS performance.

Respond to the concerns of the communities in which we do business.

Support EHS public policy development.

Encourage our contractors and suppliers to adopt EHS standards similar to our own.

Exchange EHS knowledge and technology.

These core values build on our tradition of quality, innovation, and continuous improvement.

Each employee is personally responsible for making these value a part of everyday worklife at

ZiLOG.

Jim Thorburn

Chief Executive Officer

ZiLOG, Inc.

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2002Quality and Reliability Report

ISO CERTIFICATION

ZiLOG is extremely proud to have received the following ISO 9000 certification awards, which

reflect the stringent quality standards to which all ZiLOG products are manufactured.

FACILITY/LOCATION

CERTIFICATION RECEIVED

ZiLOG Electronics

ISO 9002 – Re-certified 7/98 By

SGS Yarsley International

Certification Services

Philippines, Inc. (ZEPI)

Manila, The Philippines

- Final Test and Shipment of

Semiconductors

Camberley, Surrey, UK

ISO 14001 – Certified 11/99 by SGS

International Certification Services

Zurich, Switzerland

ZiLOG Nampa

Nampa, Idaho

- Wafer Fabrication

ISO 9001 Re-certified 9/98 by the

National Standards Authority of

Ireland.

ISO 14001 – Certified 3/99 by the

National Standards Authority of

Ireland.

(*ISO - International Standards Organization)

ISO 9000 CERTIFICATION FOUNDRIES/SUBCONTRACTORS

FACILITY

Wafer Foundries:

UMC

LOCATION

PROGRAM

Taiwan

ISO 9002

TSMC

Assembly Subcontractors:

Taiwan

AIT

Batam, Indoneasia

ISO 9002

Amkor

ASE

Manila, PI

Manila, PI and Taiwan

Ipoh, Malaysia

Carsem

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QUALITY AND RELIABILITY TREND CHARTS

PPM Electrical

50

40

43

30

35

32

20

10

0

25

20

18

16

14

12

10

9

3

Figure 2-1.– FIT Rate (FIT = Failure in Time: Failures per Billion Hours)

200

150

100

50

200

150

90

80

70

60

50

40

35

25

30

23

22

0

Figure 2-2. PPM Electrical

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2002Quality and Reliability Report

Figure 2-3. R/QA Organizational Chart

Director

Reliability and Quality Assurance

Mike Burgdorf

Principal Engineer

Manager

Quality Assurance

Asia

Director Quality

Assurance

Nampa

Mike Burgdorf

Reliability and

Quality Assurance

Joseph Brajkovich

Malie Fonte

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2002 Quality and Reliability Report

CHAPTER 2

Customer Quality Support

CUSTOMER FAILURE ANALYSIS/CORRELATION PROCEDURE

ZiLOG has a complete Customer Failure Analysis (CFA) system. Using this system, a customer

may return units for failure analysis or test correlation. The sequence of events for the CFA

procedure is as follows:

1. Customer suspects a failure.

2. The Customer and ZiLOG’s Field Applications Engineer (FAE) generate a CFA request. See

Figure 3-1.

3. A CFA request is assigned a number for tracking.

4. ZiLOG’s FAE sends the unit(s) to the factory.

5. Product/Test Engineering performs a go/no-go electrical test.

6. The unit(s) and test results are given to the Failure Analysis Engineer.

7. If the unit(s) fail the test, the Failure Analysis Engineer performs electrical and physical

analysis, and generates a CFA report. See Figure 3-2.

8. If the unit(s) pass the test, the Failure Analysis Engineer generates a CFA report and returns the

unit(s) to the customer.

9. Our goal is to provide a complete CFA report within 10 working days from the time the unit(s)

are received.

ZiLOG and the customer will work together to reduce all types of failures to zero. The CFA

procedure is one of several communication tools that can be used to achieve this goal, proving its

overall effectiveness since its inception in 1985.

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2002 Quality and Reliability Report

Figure 3-1. ZiLOG Guideline Information Needed By The Factory With CFA’s

Purpose: To eliminate time spent researching a failed component/part history in order to concentrate on finding the root cause of

failure or complaint by the customer

OP184

FAILURE ANALYSIS QUESTIONNAIRE

GENERAL INFORMATION:

Initiated By:

Date:

B.U.:

Customer Name:

Customer Address:

Phone No:

Customer priority level:

PART INDENTITY:

Device:

Date/bb Code:

Qty. being returned:

Total # devices in lot:

Qty. of failed devices:

Qty. devices tested/inspected:

Customer Application:

FAILURE DESCRIPTION:

Incoming:

Assembly:

Yes No

Final Test:

Field Return:

Low Noise Option?

How long in service before failure occurred?

Was part removed with any other parts?

Did failure follow part?

Yes

No

Additional processing temperatures which part had seen before failure occurred:

Is this a new application for this device?

Is this a new failure mode?

Yes

No

Is there a Customer board or test program available for use at ZiLOG?

Are there failing and passing samples available for correlation work?

Process steps part had seen up to time of failure:

Yes

No

ADDITIONAL DETAILS:

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2002 Quality and Reliability Report

Figure 3-2. ZiLOG Failure Analysis Report

CUSTOMER FAILURE ANALYSIS

PSI:

Page 1 of 1

Date:

Quantity:

Customer:

Analyst:

REPORT

ZiLOG Confidential

CFA#:

Date:

Approved:

Date:

Problem as reported by customer:

Device Date Code(s):

Analysis:

External Visual:

Bench Test:

Electrical Test, Final Test at 100C, QA test at 25C, Sentry Tester:

Conclusion:

Recommended Action:

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Table 3-1. Summary of QC Test Equipment

Equipment At ZEPI

Wetting Balance Tester

ISOMET Low Speed Saw

Curve Tracer

Brand

Usage

Multicore Must II

Buehler

Solderability Test

Cross-Section Analysis

Bench Check

Tektronix 577

IMCS 700

Oryx 11000

Express Test

Buehler

ESD Tester

VZAP Testing

ESD Tester

VZAP Testing

HAST

Reliability Test

Cross-Section Analysis

Polimet Polisher

High Power Scope

Olympus

External/Internal Visual

Inspection

Low Power Scope

Bausch & Lomb

External/Internal Visual

Inspection

Jet Etch

Novus Technologies

3D Ready-Heat

Electric Steroclave

March Inst Inc

Leica S420

Decapping of Plastic Devices

Solderability-Steam Aging

Reliability Test

Hot Plates

Pressure Cooker

Plasmod Plasma Etcher

SEM & EDX

Topside Etch

Visual & Elemental Analysis

Latchup Test

Digital Multimeter

Power Supply

Timer

Fluke

HP

Latchup Test

Gralab

Timed Operations

Acoustic Microscope

Profile Projector

Sonoscan C-SAM 3100

Mitutoyo

Delamination Inspection

Dimensional Inspection

Temperature/Humidity Test

Chamber

ESPEC

Temperature/Humidity Test

Chamber

Sexton ESPEC

Moisture Resistance Test

Salt Atmospheric Chamber

Mechanical Shock Tester

Associated

Lansmont

Salt Atmosphere Test

Mechanical Shock Test

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Table 3-1. Summary of QC Test Equipment

Equipment At ZEPI

VVF Test

Brand

Usage

Unholtz-Dickie

Tabai

VVF Test

Thermal Shock

Temperature Cycle

Toolmaker Scope

Hardness Tester

Thermal Shock Test

Temp Cycle Test

Dimensional Check

Leadframe IQC

For Plating Thickness

Ransco

Unitron

Ames Precision

Fischerscope

Plating Thickness Measuring

Equipment

Wirepull Tester

Beam Balance

Unitek

Westbond

None

In-Process Wirepull Testing

Weight Measurement

Die Shear Test

Shear Tester

B&G

Particle Counter

Flow Thru Cooler

Digital Linear Gauge

Incubator

Atcor

Airborne Particle Measurement

Viscosity Check

Neslab

---

Wafer Thickness Check

Bacteria Monitor

Millipore

KTC

Ball Shear Tester

High Power Scope

1 Set PH Meter VWR

3 PCS Chatillion Gauge

Coplanarity Tester

Wirebond Check

Olympus

VWR

Inspection

PH Check

Chatillon

RVSI

Die Push Test

Coplanarity Check

MP-4 Land Camera With

Stage And Floodlights

Polaroid

Photo Duplicating,

Macrophotography 8X10

High Power Microscope

w/Video Camera

Leitz, RCA

Wafer Level Inspection

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Table 3-1. Summary of QC Test Equipment

Equipment At Nampa

Brand

Usage

Zoom Stereoscope 5-50X

Nikon

X-Section Mounting, Low-Power

Inspection

High Power Microscope w/Camera,

50-1000X Long-Working Distance

Objectives

Nikon

Package Die Visual

Microphotography

X-Ray System

Faxitron

Film Radiography

Gold Coater

Denton Vacuum

Buehler

Lindberg

SEM Sample Prep (Backup)

Package Cross

High Temp Analysis to 1100C

Low-Speed Diamond Saw

Bench Top Furnace

High Temperature Ovens:

175C

Blue M

Bake Recovering

150C

Blue M

Bake Recovering

125C

Exhaust Hood

Blue M

SEM Sample Storage

Chemical Use Safety

Cross-Section and Lap

Wafer Reliability Analysis

Hot Chemical Etch

Wafer Pressure Pot Test

Chip Unzip

Kewaunee

JST Plastics

Buehler

Corning

Wet Sink w/Exhaust

3-Wheel Polisher

Hot Plate PC100

Hot Plate

Lindberg

Corning

Hot Plate

Arthur H. Thomas Type

2000

Chemical Heating

Ultrasonic Cleaner (2)

Ultrasonic Cleaner

Plasma Etcher

Jet Etch & Jet Rinse

Cerdip Opener

Timmers (2)

Dial-O-Gram (2)

UV Light

Bransonic

Branson 3510

Tegal

B&G Enterprises

Gralab

Sample Cleaning

Topside Etch and Descum

Part Decapsulation

Timed Operations

Chemical Measurement

Dye Penetrant Test

EPROM Erasing

Bench Check

Waveform Photo

Ohaus

Blak-Ray

UV Light EA

Loglcal Devices, Inc.

Tektronix

Temptronic

Wentworth

Curve Tracer 576

Curve Tracer 577

CRT Camera

Temperature Forcing Unit

Microprobe Station

Bench Temperature Testing

Microprobing (Not Complete - no

mcroscope)

Laser Cutter

New Wave EZ LAZE

Trace Cutting

Microprobe Device Socket Cards:

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Table 3-1. Summary of QC Test Equipment

Equipment At Nampa

Brand

Usage

44 LCC/PLCC

48 Lead DIP

64 Lead Narrow Pitch DIP

High Power Microscope 50x - 400x

ZiLOG Designed

Micromanipulator

ZiLOG Designed

Nikon

Bench Microprobe Work

Die Visual Microscope

High Power Microscope 50x - 1000x Nikon

S440 SEM Leica

FIB With SIMS (SIMS not working) FEI

Die Visual Chip Unzip Inspection

High Power Imaging

Micro Cross Sectioning, Device

Modification and Elemental

Analysis and Imaging

Reactive ION Etcher (REI), 8-Inch

Polycon, BF, DF, DIC, Confocal,

Fluorescence,

Trion

Leica-Reichert

Device Deprocessing

Product Visual Examination

W/8x8” Stage

Semprex

Optronics

Sony

HP, Tektronics 7704

HP

Feature Size Measurement

Video Camera

3x4 Inch Color Video Print

Signal and Waveform Monitor

Parametric Tester

W/Micron Stage Readout

W/Sony Color VP Video

Oscilloscopes

4145A (2)

w/LCR Meter

Visionary 2000

W/MP2000 8” Probe

Package Device Thermal

Socket Cards:

20 Lead PLCC

44 Lead PLCC

68 Lead PLCC

84 Lead PLCC

44 Lead PQFP

100 Lead QFP

100 Lead VQFP

124 Lead PGA

HP

Capacitance and CV Measure

Emission Microscope,

Device Microprobe, CV

Emission Microscope,

Microprobe and Liquid

Crystal (Room and Hot)

Hypervision

Carl Suss

Temptronics

IMS

64 Lead DIP

28 Lead DIP (300 Mil)

Blazer 125 Tester

W/8” Probe Station

4156B Precision Semiconductor

Parameter Analyzer

35665A Dynamic Signal Analyzer

Bitmapping, Device Test

Microprobe

Parametric Tester

Wentworth

HP

Tester

4275A Multi-Frequency LCR Meter HP

Tester (Inductance, capacitance,

resistance instrument)

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

Table 3-1. Summary of QC Test Equipment

Equipment At Nampa

Brand

Usage

4274A Multi-Frequency LCR Meter HP

Tester (Inductance, capacitance,

resistance instrument)

Probe Test

Microminipulator Test Station (2)

Micromanipulator

4155B Semiconductor Parameter

Analyzer

Agilent

Parameter Tester

208 PQFP

44 QFP

48 DIP

64 DIP

17x17 PGA

84 PLCC

24 DIP

48 DIP

28 DIP

24 DIP

44 PLCC

124 PGA

HP Display 1340A

Philips XL30

SFEG SEM

Multiprep

Schlumberger

HP

Socket Adapters

Signal Display

Philips

Ultra High Resolution

SEI, BSE (Solid State)

Parallel Polishing

Allied High Tech

Techprep

50x - 4500x High Power Optical

Microscope

Nikon Eclipse L200

Bright field, Dark field, Numarsky,

Confocal inspection, Digital

Camera1280 x 1944

High Temperature Oven 20 C - 550 C Grieve

Hammer Testing, Ink Dot Curing

High Quality Photographic Printer

Photographic Printer

Printer (color)

MP4 Camera

Codonics

Tektronics

Polaroid

Polaroid Photographs

Chip Unzip

Hypevision

Backside Analysis

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

Table 3-1. Summary of QC Test Equipment

Equipment At Campbell

Spectrum Analyzer

Pre-Amplifier

Brand

Usage

HP-8591A

HP8447D

HP-7550A

#CEAB-100

#CEAL-100

Near Field EMI Testing

Plotter

Biconical Antenna

Log Periodic Antenna

USE OF OUTSIDE FMA LABS

RIGA Analytical Lab, Inc.

3375 Scott Blvd., Suite 132

Santa Clara, CA 95051

Charles Evans & Assoc.

301 Chesapeake Drive

Redwood City, CA 94063

BridgePoint Tech. Mfg.

4007 Commercial Drive

Austin, TX 78744

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

CUSTOMER NOTIFICATION SYSTEM

Corporate R/QA notifies the customer with a formal change notification letter on major process and

design changes if the customer requests notification of such.

The following is a list of criteria for which certain customers need to be notified:

1. Process: die size, passivation, metallization, mask changes.

2. Materials and finishes: either internally or externally, including symbolization.

3. Internal Connection Methods: including lead bonding and die attach.

4. Packaging: sealing and encapsulation techniques, including lead bonding and die attach.

5. Test Parameters: which may affect correlation.

6. Anti-Static Handling: procedures or packaging.

Shown on the following pages is an example of a change notification letter that gives the customer

a schedule of the conversion, stating that:

•

The customer will be given 30 days to respond to ZiLOG requesting samples for qualification

by the customer.

New product will be shipped within 60 days from the date of the letter, unless ZiLOG receives

written notice from the customer to continue shipping their current qualified product.

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

June 30, 2000

Subject:

Customer Change Notification -

Z80S183 / Z80L183 Die Revision Change From “B” to “C”

Dear Customer:

Please be advised that ZiLOG is in the process of changing the current Z80S183/Z80L183 die

revision "B" for the Mixed Signal 180. The new Z80S183/Z80L183 die revision “C” is fully

compatible with the existing Z80S183/Z80L183 with the exception of the following improvements.

1. Improved Sleep Mode current of less than 1.7 mA @ 5V less than 700µA @ 3V.

2. All modes of the Watch Dog Timer are functional.

3. The CPU ID Register at location 3Dh is changed from 00h to 02h to reflect the new die.

All Z80S183/Z80L183 have a date code in the lower left corner of the package and follow the

yyww convention, where yy is the year and ww is the week. The improved die will be

stamped date code later than 0025. If you wish to receive qualification samples of the new

product, contact the ZiLOG field sales office serving your area.

Sincerely,

Mike Burgdorf

Director

Reliability and Quality Assurance

ZAC00-0045

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

CHAPTER 3

Qualification Requirements

PRODUCT/PROCESS QUALIFICATION REQUIREMENTS

Per Procedures SOP0940, SOP0903 and SOP0909, ZiLOG performs initial qualification on new

processes, products and packages. Re-qualification is required when material changes occur.

Table 4-1. Product/Process Qualification Requirements

Sample

Size

Acceptance MIL-STD

Test

Test Conditions

Criteria

883C/Procedure

ESD

10

6

HBM

3015.7

2 KV Min.

CMOS Latchup

200 mA Min QR - QCC-1425

EIA/JESD78

3 PTIC, 3 NTIC

Operating Life

Temp Cycle

77

45

1/77

0/45

1005

150°C, 5V

184 Hour/Full Qual

1010, Condition C

–65°C to 150°C

500 Cycles/Qual

1000 Cycles/Test

Pressure Pot

HAST

45

0/45

QCC-1403

PM 25-13

336 Hours

121°C at 2 ATM

96 Hours

140° C, 85% RH,

2 ATM

Package Integrity

10

0/10

240°C, 10 Sec

Note: Process Qual requires three (3) lots, Product Qual requires one (1) lot.

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

ZiLOG Product Qualification Summary

PRODUCT QUALIFICATION

Document Control Nbr.: QR-9392

Page 1 of 1

Rev.: 02

SUMMARY

ZiLOG Authorized Distribution

12-4-01

DATE:

Z86L88

UMC 0.35 um

M. Burgdorf

PRODUCT:

PROCESS:

Joseph Brajkovich

WRITTEN BY:

APPROVED:

•

INTRODUCTION

•

INFORMATION SUMMARY

This report summarizes the qualification results All qualification tests were performed to

of the Z86L88 16K IR Microcontroller.

MIL-STD-883 and/or internal ZiLOG

procedures.

PRODUCT QUALIFICATION

Test Description

ESD

Latch-up

Test Method

Condition

Test Result

PASS

MIL-STD-883/3015

QCC1425

Condition D

Per Test

Burn-in

MIL-STD-883/1005

MIL-STD-883/1010

120° C, 15 PSI

140° C, 85% RH

240° C, 10 seconds

0/77 184 hours

0/50 1000 cycles

0/50 336 hours

0/50 96 hours

0/15

Condition B, 150° C

Condition C

Per Test

Temperature cycle

Pressure pot

HAST

Package integrity

QUALIFICATION

Process

TYPE

DOC. NO.

UMC 0.35 um

Z86L88/G

QR-0656

QR-1098

Device

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

Package Qualification Requirements

Sample

Size

Acceptance

Criteria

MIL-STD

883C/Procedure

Test

Test Conditions

Solderability

4

15

4

0/15

0/4

2003

LTPD 15/Leads

Physical Dimensions

Lead Fatigue

2016

Per Mil-STD

8 Lbs Min

2004

External Visual

Internal Visual

Die Shear

1004

4

0/4

1004

3

0/3

QCC-0105

Bond Strength

Bond Shear

4

0/15

0/3

2011, Condition D 4 gms Min.

QCC-0184

3

Operating Life

77

1/77

1005

150°C, 5V 184

Hour/Full Qual

Temp Cycle

45

0/45

1010, Condition C –65°C to 150°C

500 Cycles/Qual

1000 Cycles/Test

Pressure Pot

HAST

45

0/45

QCC-1403

PM 25-13

336 Hours 121°C

at 2 ATM

96 Hours

140°C, 85% RH,

2 ATM

Package Integrity

X-Ray

5

32

5

0/15

0/32

0/5

240°C, 10 Sec

Per Mil-STD

2012

Solder Dunk

Per Test Method

ZAC03-0004

3- 3

ZiLOG

2002 Quality and Reliability Report

ZiLOG Package Qualification Summary

Document Control Nbr.: QR-3002

Page 1 of 1

Rev.: 01

OP25

PACKAGE QUALIFICATION

SUMMARY

44L QFP

1-27-99

Alice Baluni

PACKAGE TYPE:

WRITTEN BY:

DATE:

APPROVED:

Joseph Brajkovich

•

INTRODUCTION

•

INFORMATION SUMMARY

This report summarizes the qualification results All qualification tests were performed to

of the 44L QFP package.

MIL-STD-883 B, C and/or internal ZiLOG

procedures.

PACKAGE QUALIFICATION

Test Description

Bond Strength

Test Method

Condition

Test Result

6.8/8.2/7.5

min/max/ave

0/3

MIL-STD-883/2011

Condition D

Ball Shear

QCM-0184

Per Spec

Die Shear

QCM-0105

Per Spec

0/3

Physical Dimensions

Resistance to Solvents

Lead Fatigue

Solderability

Pressure Pot

Temperature Cycle

Burn-In

Package Integrity

Solder Dunk

MIL-STD-883/2016

MIL-STD-883/2015

MIL-STD-883/2004

MIL-STD-883/2003

QCC1403

MIL-STD-883/1010

MIL-STD-883/1005

240ºC, 10 seconds 3X

Per Test Method

Per Spec

Condition C

125ºC

Per Test Method

After 1000 Temp

Cycle

0/15

0/1

0/6

0/45 336 hrs

0/45 1000 cycles

0/77 1000 hrs

0/15

0/5

QUALIFICATION

Package

TYPE

DOC. NO.

QR-0308

44L QFP

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

CHAPTER 4

Quality Monitor Systems

FAILURE RATE PREDICTION CALCULATIONS

ZiLOG estimates the operating life of our products through statistical methods. It is not possible to

guarantee the lifetime of an individual part because the tests to determine this are destructive.

Therefore, we can only use statistics to predict the typical behavior of groups of parts. These

predictions, and the methods they are based on, are documented in FIT reports. The FIT report is

based on process specific data and is derated to reflect individual device characteristics. FIT

reports are available for all of ZiLOG’s products.

Other factors that affect device lifetime include actual operating hours, ambient temperature,

stability of the power supply, board assembly and other handling practices. All of these factors are

outside of the control of ZiLOG and may dramatically shorten the lifetime of a device.

The failure rate for each product and process is a function of time, temperature and applied power.

The primary temperature is, of course, the product junction temperature. This is externally

influenced by the ambient temperature and internally influenced by the power dissipated in the die.

The power dissipation, in turn, is a function of the duty cycle and applied VCC. In the case of

CMOS, product power dissipation is also a function of the operating frequency. ZiLOG product

failure rates were derived from accelerated life test results accumulated on an ongoing basis as part

of the ZiLOG reliability monitor. The accelerated life test reliability data includes both infant

mortality (early life results 0-160 hours) and long term life results (168-1000 hours). Various

interim time points and sample sizes are used. Lifetest may be performed at either 125°C for 1000

hours or the Mil-Std-883 equivalent or 150°C for 184 hours.

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

The acceleration obtained when using high temperature life stressing, may be calculated for various

stress and application temperatures using the widely accepted Arrhenius equation as follows:

A = exp(–Ea(T1 – T2)/k(T1)(T2))

Where

A:

Acceleration factor

Ea:

T1:

T2:

k:

Activation energy (eV)

Application junction temperature (°K)

Stress junction temperature (°K)

Boltzmann Constant 8.62 x 10^–5(eV/°K)

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

Z85230VSC FIT Rate Calculation

The acceleration obtained when using high temperature life stressing may be calculated for various stress

and application temperatures using the widely accepted Arrhenius equation as follows:

A = exp (-Ea (T1 - T2) / (k (T1) (T2)))

Where

A:

Acceleration factor

Ea:

T1:

T2:

k:

Activation energy (eV)

Application junction temperature (˚K)

Stress junction temperature (˚K)

Boltzmann Constant 8.62 x 10-5 (eV / ˚K)

Assume Ea = .7, Ta application = 55C, Ta stress = 125˚C and k = 8.62 x 10⁵. Consider now a typical

CMOS product Z85230 operating with a 100% duty cycle at 16 MHz in a 44 pin PLCC package. Then with a

VCC of 5V and an Icc of 7 ma this would give T1 = 330˚K and T2 = 400˚K.

A = exp (-.7(330 - 400) / 8.62 x 10⁵(330) (400) ) = 75

So 1000 hours of life stress at 125˚C is equivalent to 75,000 hours of system application operation at 55˚C.

FIT and Failure Rate Estimation:

Given High Temperature Operating Life stress results:

168 Hours

500 Hours

1000 Hours

Z85230

0/76

Rel Monitor 1994

Rel Monitor 1995

Rel Monitor 1996

Rel Monitor 1997

Rel Monitor 1998

Rel Monitor 1999

Rel Monitor 2000

Rel Monitor 2001

Rel Monitor 1H-2002

0/837

0/760

0/606

0/10,759

1/6,152

0/7,520

0/22,470

0/38,258

0/61,646

0/12,992

0/8,394

077

0/231

0/200

0/77

0/231

0/200

Failure Rate Estimations are made assuming a Poisson distribution using the Chi²density function to assign

confidence values as an estimate for the general population as follows:

60% Confidence

# Fails = 1 then Chi²= 4.05

Given 1 reject from 29,527,680 device hours at 125˚C. Then using Chi²this gives a median failure rate of

4.05/2 rejects per 29,527,680 device hours or 0.0686 rejects per 10⁶device hours.

Failure rate

= 0.0686 rej / 10⁶dev. hrs.

= 68.6 rej / 10⁹dev. hrs.

= 68.6 FIT at 125 C

Failure Rate

MTBF

= 68.6/75 = 1 FIT at 55˚C (A = 75 as above)

= 10⁹/1 = 124,471 years

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

ESD TESTING METHODOLOGY

ZiLOG has an unqualified commitment to quality and reliability and, as part of this commitment,

ZiLOG strives to provide the best possible ESD protection for each of our products.

Since 1983, ZiLOG has had an ongoing electrostatic discharge development program to monitor

and improve its ESD protection circuitry. During an ESD event, the ESD protection circuitry must

absorb the power of the ESD pulse while allowing little or no damage to occur to the internal

circuitry of the chip. A 3000 volt ESD pulse can induce transient currents approaching one amp,

and it is the management of these transient currents that is the key to good ESD protection. At

ZiLOG, ESD protection circuits have been developed to optimize the handling of ESD pulse

currents, by paying close attention to current flow patterns, and minimizing current density and

crowding problems that cause damage to the circuitry. This circuitry has resulted in typical ESD

failure voltages above 2000 volts for NMOS products and above 4000 volts for CMOS products,

with concomitant improvement in product quality and reliability.

All of ZiLOG’s products are tested for their ESD immunity as part of routine internal qualification

procedures. The ESD test hardware is in compliance with MIL-STD-883 and Method 3015.7.

LATCHUP TESTING METHODOLOGY

ZiLOG has an unqualified commitment to quality and reliability and, as part of this commitment,

also strives to provide each of its products with the best possible latchup protection.

ZiLOG has an ongoing program to monitor and improve its latchup protection circuitry. Latchup

may occur as a result of either current injection (positive or negative) or supply pin overvoltage.

The latchup action is that of a parasitic SCR, converting from a high-impedance state, to a low

impedance, regenerative, state. The resulting current flow may exceed the design capabilities of

the device. Damage may occur to interconnections (bond wires and die metallization) as a result of

thermal heating effects and excessive current flow.

During conditions, which may lead to latchup, the device must be able to shunt the triggering event

(the positive or negative injection current) without damage to the device. ZiLOG has targeted a

200 mA minimum latchup requirement for all new designs to minimize the risk of latchup. In

addition, ZiLOG recommends that the customer do a careful analysis of system transients to ensure

that our maximum undershoot and overshoot applied potentials are not violated. Absolute

maximum ratings are: voltage on Vcc with respect to V_SS– 0.3V to +7.0V and voltages on all

inputs with respect to V_SS– 0.3 to V_CC+ 0.3V.

All of ZiLOG’s products are tested for their latchup immunity as part of routine internal

qualification procedures. The latchup test hardware is in compliance with EIA JEDEC Standard

78, and the detailed test procedure is per ZiLOG specification QCC1425, which is available upon

request.

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

ZiLOG’S RELIABILITY SUMMARY

ZiLOG’s reliability program is unique, in that the reliability testing takes place on standard

production material at the point of assembly. Reliability testing has been integrated into the

manufacturing process. This flow creates a “Quick Reaction” reliability monitor, and allows

ZiLOG to ensure the integrity of material prior to shipment, gather trend analysis data for internal

corrective actions, and maintain a meaningful database for customer review.

The tests currently employed under ZiLOG’s quick reaction reliability monitor, include early life

(burn-in), steam pressure pot, and temperature cycle. Testing conditions are included with the

attached test results.

In addition to early life testing, a long-term life test is performed on selected lots to gather FIT data.

Test conditions and FIT calculations are included with the attached data. Following are brief

descriptions of various reliability tests included in this program:

EARLY LIFE

Early Life testing, also called burn-in, is typically performed at 125°C for 168 hours. A dynamic or

static bias is employed, depending on the device that is being tested. Early Life test results expose

process or assembly defects. These results are a valuable measure of a given fabrication or

assembly process.

LONG TERM LIFE

Long Term Life testing is generally performed at 150°C for 184 hours. Either dynamic or static

bias is used to stress the device appropriately. These test results are used to estimate field operation

lifetime for a device. This data can be applied to all products manufactured using the same

fabrication process.

PRESSURE POT

Pressure pot testing is performed at 121°C, 15 PSIG, and 100% relative humidity. This test

evaluates the ability of a plastic device to withstand the long-term effects of a humid environment.

TEMPERATURE CYCLE

Temperature Cycle testing is performed at a –65°C to 150°C temperature. This test uses an air-to-

air environment. The 215°C cold to hot temperature difference determines if proper thermal

expansion matching exists between all materials used in device manufacture. The temperature

cycle simulates the thermal stresses a device undergoes during power-up and power-down events.

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

HIGHLY ACCELERATED STRESS TEST

The Highly Accelerated Stress Test (HAST) is performed at a 141°C temperature and 85% Relative

Humidity (RH) at 2 ATM of pressure with alternate pin bias. This test replaces the traditional

85/85 test and greatly reduces the time taken to evaluate the ability of a plastic encapsulated device

to withstand the long-term effects of a biased humid environment.

PACKAGE INTEGRITY TEST

Package Integrity testing ensures the integrity of surface mount devices in terms of package

cracking, bonding craters, and marked deterioration as a result of heat application during the

soldering operation. This includes testing of 5 units on each 3 legs as follows:

CONTROL

TEST 1

-

10-SECOND SOLDER DUNK AT 240°C

10-HOUR *PPT

10-SECOND SOLDER DUNK AT 240°C

TEST 2

-

10-HOUR *PPT

3-HOUR OVEN BAKE AT 150°C

10-SECOND SOLDER DUNK AT 240°C

(*PPT = Pressure Pot Testing at 121°C, 100% RH, 2 ATM)

End-points are room temperature electrical test, visual inspection, mark permanency and crater test.

ZAC03-0004

4 - 6

ZiLOG

2002 Quality and Reliability Report

Table 5-1. ZiLOG’s Reliability Monitor Testing Requirements

Test

Conditions

Product to be

Tested

Allowable

Rejects

Frequency

SS

Test

Temp cycle

Pressure Pot

Each pkg type

Monthly

45

0

–65° to 150°C

100, 500, 1000

cycles

96, 168, and 336

hrs 121°C, 100%

RH, 2 ATM

Package/Fab

Process

Monthly

Weekly

45

0

Burn-in

Life test

Per assembly and

process flow

Per assembly and

process flow

PLCC or QFP

package

77

15

0

1

0

168 hrs, 125°C

Every 2

Months

Weekly

184 hrs cum, 150°C

Package

Integrity

10-hr Pressure Pot,

10 second solder

dunk

ESD

Each new die

revision or device

Each new die

N/A

10

N/A

Mil Std 883

Latch-up

CMOS

10

or as

needed

45

Per ZiLOG spec

revision or device

HAST

1 pkg/fab process

Monthly

0

NMOS - 48 hours

CMOS - 96 hours

at 140°C, 85% RH

2 ATM

Solderability

Each package

type

Any package type

with solder

Monthly

Weekly

3

0

Mil Std 883

Solder

MAB 1042

thickness

monitor

Lead fatigue

test

Each package

type

Weekly

1

0

Per ZiLOG spec

ZAC03-0004

4 - 7

ZiLOG

2002 Quality and Reliability Report

Table 5-2. ZiLOG Reliability Monitor Early Life Test Conditions: 168 HRS, 125°C Burn-

in

CMOS Plastic Package 2002

Device Type

Lot No.

Rej

S/S

Fail Notes

1H – 2002

Z8018008FSC

Y132AB0Q

0

77

1134

206

397

77

Z88C0020VED1700TR

Z84C9008VED1380TR

Z86E0208PSC1925

Z84C9008VED1380TR

Z8018233FSC

EYH42CC0PBB

EY130NR0PBG

EY130NR0OBG

AYI43HH0BP

EY130NR0PAB

E123AJ0C

110

139

77

AY144LY0P

E125BN0QAA

E125BN0QABA

E125BN0QABB

E125BN0QBA

BX145AS0

Z84C9008VED1380TR

Z8018008VSC

528

795

462

795

77

Z84C9008VED1380TR

Z8622812PSC

E125BN0QBBA

E143GX0T

795

77

Z88C0020VED1700TR

Z86C3316PSCR4124

Z9023406PSCR51X3

Z86C4312PSCR5122

Z86C9012PSC

BY151BH0A

AYH1120AR

EYH1314BG

BYH0988D

1801

77

100

77

EYH1373B

Z86L8708PSCR51R3

Z86C0208PSCR517J

EYHBJ28.01

EHBJ27.0F

77

EZ209HU0E

77

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

Table 5-2. ZiLOG Reliability Monitor Early Life Test Conditions: 168 HRS, 125°C Burn-

in

CMOS Plastic Package 2002

Device Type

Lot No.

Rej

S/S

Fail Notes

Z86C0412PECR4537

Z86L8808PSCR51JW

Z85C3008VSC

EZ208DS0B

NXHCE27.0CT

B038GN0QB

B038GN0QA

A036FY0X1P

A038GG0PQ

B135PT0RBB

EY20SLU0Q

BY206BJ0B

EY145BN8A

BY204FH0AR

BX208DL0P

BYHCE29

0

77

100

77

Z85C3008VSC

Z84C0008PEC1983

Z86C0712PSCR2568

Z84C9010VSC

Z84C0008FEC

Z8S18033VSC

Z86C3312PECR50RX

Z9023406PSCR522X

Z86C9533ASC2041

Z86L8808PSCR51JW

Z9023406PSCR522X

Z9025506PSCR523H

Z9025506PSCR51AP

Z85C3008VSC

A125CF8B

NXHCE27.0CT

BYHCE29

BYN22H6895.00P

BYH1601B

S042AE0R

Z85C3008PSC

K041HJ0S

Z86C0208PSCR4502

Z903561212PSCR50LM

Z8L18020FSC

K207PY0AR

BH1666AC

A214GL0AAP

K207XX0AR

K041HJ0S

Z8S18020VSC

Z85C3008PSC

ZAC03-0004

4 - 9

ZiLOG

2002 Quality and Reliability Report

Table 5-2. ZiLOG Reliability Monitor Early Life Test Conditions: 168 HRS, 125°C Burn-

in

CMOS Plastic Package 2002

Device Type

Lot No.

Rej

S/S

Fail Notes

Z84C9010VSC

K207HR0AP

K207XX0AR

BYH1786D

EY205LU0Q

BYH1490FD

BHBT78.04B

CHBT77

0

77

100

72

75

77

Z8S18020VSC

Z9023406PSCR5140

Z84C9010VSC

Z9025506PSCR51AP

Z8702414SSCR51XK

Z8S18033VSC

BY204FH0AR

2H - 2002

Z8S18020VSC

A222FN0AQ

BZ222HS0B

AZ222JK0AAQ

AZ221TU0PA

KZ219KN0P

BHCWF8.020A

A222FN0AQ

AZ233FP0PB

BYH1509RB

AZ219KP0QR

BZ222HS0B

AZ222JJ0AAB

AZ223FZ0PA

NZ224KR0PB

0

77

Z86L4308FSCR50AF

Z86E3312SSC

77

Z86E0208PSC1925

Z84C0006PEC

77

100

Z9023406PSCR51J1

Z8S18010VSC

Z86K1505PSCR4530

Z9023406PSCR50M5

Z84C0010PEC

Z86L4308FSCR50AF

Z86E0208PSC1925

Z86E0812SSC1866

Z86E3312SSC

AZ222JK0AAQ

AZ223HW0APB

0

100

Z86E0412PSC1866

ZAC03-0004

4 - 10

ZiLOG

2002 Quality and Reliability Report

Table 5-2. ZiLOG Reliability Monitor Early Life Test Conditions: 168 HRS, 125°C Burn-

in

CMOS Plastic Package 2002

Device Type

Lot No.

Rej

S/S

Fail Notes

Z86E0208PSC1925

Z84C2006VEC

AZ221TU0PA

AZ221TU0PC

B219SV0S

0

100

77

Z86E2112PSC

A048LW0X

Z86E3312PSC

B225HN0APB

BZ25HN0APB

AZ227CG0AP

B220CDDAAA

AR60986.1P

BYH16655B

BZ228AL0AQ

AZ221JN0PQA

AZ227LN0AQ

BZ228SY0

Z86E3312PSC

Z86C0812PSCR2422

Z86C3312PSCR2130

Z8F6403FZ030SC

Z864170813SCR3212

Z8674312FSC

77

Z84C0008FEC

100

77

Z86C6116PSCR3360

Z85C3008VSC

Z8S18020VSC1960

Z8702414SSCR52CH

EZ80F92AZ020SC

Z86C0812PSCR50PX

Z86E0212PSC1866

Z86L8808PSCR51JW

Z84C00010PEC

B001LN0P

AZHF11.132A

KR61001.AZ

AZ234HJ0PA

AZ233AY0PPA

BZHF03S.00E

AZ231JP0RR

BHF1W2.03C

BZ233BF0

76

100

77

Z9023306PSCR51J9

Z8018008VSC

Z9025106PSCR52NN

Z86C3312PECR517F

Z8019520FSC

B230EJ0A

NY214GN0P

K232CN0A

77

Z86C6516PSCR3332

Z86C6116PSCR2224

Z84C00008PEC

NZ235DG0B

AZ230PU0KQA

A222KS0ATQ

AZ239KY0BPA

AR61105.A1

77

Z86K1505PSCR4230

Z8F6403FZ030SC

77

83

ZAC03-0004

4 - 11

ZiLOG

2002 Quality and Reliability Report

Table 5-3. ZiLOG Reliability Monitor Early Life Test Conditions: 168 HRS, 125°C Burn-in

NMOS Plastic Package 2002

Device Type

Lot No.

Rej

S/S

Fail Notes

1H - 2002

Z0843004DSA0563

Z0843004DEA0539

Z0843004DSA0563

Z0844004DSA0541

Z0840004DEA0540

Z0843004DSA0563

Z0840004DEA0540

Z0853606DEA

B0315W0RRA

B031SW0RQ

0

381

178

1146

501

1669

275

60

B031SW0RRBA

B031SW0RRBB

B607BDOACAB

B709GJ0AAPB

B031SW0RRBC

B709GJ0AAPC

B031RZ0BA

284

188

285

198

106

Z0840004DEA0540

Z0803008DEA

B709GJ0AAPE

B840KZ0AQA

B031RZ0BB

Z0853606DEA

Z0840004DEA0540

Z0840004DEA0560

Z0847004PSC

B709GJ0AAPG

B709GJ0AAPH

B709GJ0AAPI

B709GJ0AAPJ

B709GJ0AAPG

E1451Z0P

0

285

253

285

100

180

285

200

73

Z0803606PSC

E144NT0P

Z084004DSA0560

Z0803606PSC

B709GJ0AARA

B709GJ0AARB

B709GJ0AARC

B709GJ0AARD

B709GJ0AARE

B709GJ0AAQH

B709GJAAQF

E204FF0AP

77

Z0840004PSC

EY205AN0AP

EY149EX0AR

77

Z0847006PSC

77

ZAC03-0004

4 - 12

ZiLOG

2002 Quality and Reliability Report

Table 5-3. ZiLOG Reliability Monitor Early Life Test Conditions: 168 HRS, 125°C Burn-in

NMOS Plastic Package 2002

Device Type

2H - 2002

Lot No.

Rej

S/S

Fail Notes

Z0847006PSC

Z0853006PSC

Z0853006VSC

Z0844006PSC

Z0853606VSC

Z0853006PSC

A212LN0AZP

A221CG0QP

A217JR0RR

B145WZ0

0

100

77

BZ203AE0AP

A237LZ0AAPA

A237LZ0AAQP

100

77

ZAC03-0004

4 - 13

ZiLOG

2002 Quality and Reliability Report

Table 5-4. ZiLOG Reliability Monitor Long-Term Life Test Conditions: 150°C, 5V,184 HRS Burn-in

CMOS 2002

Device Type

Lot No.

Rej

S/S

Fail Notes

1H - 2002

Z86L990PZ008SCR51ML

Z86L990PZ008SCR51J5

Z86C0612PSCR51RX

Z8932320FSCR51M7

Z86C3316PSCR51F7

Z9023406PSCR51X3

EZ80L92AZ020SC

BYHBHAE

BH0517A

0

77

76

77

72

75

77

0

E146EW8R

AYH2TX8R

AY148BS8

EYH1B032

MB54G

Z9023406PSCR503W

Z9023406PSCR51X3

Z86L8708PSCR51R3

Z0221524VSCRJ0A5

Z9023406PSCR522X

Z8702414SCR51XK

Z86L990PZ008SCR51ML

Z0221524VSCR50A5

EYH134BG

EYHBQ33

EYHBS28.01

EHBJ27.0F

KY209KT0A

BYHCE29

BHBT78.04B

CHBT77

EYHCF08

BY203BJ84

2H - 2002

Z1GS02BA

EY204EE8HSC

EY215BX8

0

77

Z1GS03BA

Z9023406PSCR51J1

Z8702414SSCR52CH

EZ80F92AZ020SC2047

Z86L34PZ008SCR525N

Z0221524VSCR51JA

BCWF8.02DA

KR61001.A2

AZHF11.132A

N2AHF565.01

KA227EU8AB

ZAC03-0004

4 - 14

ZiLOG

2002 Quality and Reliability Report

Table 5-5. ZiLOG Reliability Monitor Long-Term Life Test

Conditions: 125°C 1000 HRS Burn-in CMOS 2002

Device Type

Lot No.

Rej

S/S

Fail Notes

1H - 2002

Z85C3008PSC

Z8S18020VSC

2H - 2002

K041HJ0S

0

77

K207XX0AR

Z86C3312PSCR2130

Z84C0006PEC

B220CD0AAA

KZ219KN0P

0

77

ZAC03-0004

4 - 15

ZiLOG

2002 Quality and Reliability Report

Table 5-6. Reliability Test Summary Early Life Test Summary 2002

Package

Type

Samples

Tested

Rejects

FITS (55°C,60%,0.7eV)

Technology

1H - 2002

NMOS

Plastic

8,873

10,172

19,045

0

8

7

4

CMOS

Plastic

TOTAL 1H - 2002:

2H - 2002

NMOS

Plastic

608

4,245

4,853

0

121

17

CMOS

TOTAL 2H - 2002:

15

TOTAL - 2002

23,898

0

3

Table 5-7. Reliability Test Summary Long-Term Life Test Summary 2002

Technology

Device Hrs @ 125°C

Rejects

FITS (55°C,60%,0.7eV)

1H - 2002

CMOS

1,454,000

0

9

2H - 2002

NMOS

154,000

539,000

693,000

0

80

23

18

CMOS

TOTAL 2H – 2002

TOTAL – 2002

2,147,000

0

6

ZAC03-0004

4 - 16

ZiLOG

2002 Quality and Reliability Report

Table 5-8. ZiLOG Reliability Monitor Pressure Pot Test Conditions: 121°C, 2 ATM.

CMOS Plastic Packages 2002

96 Hrs

168 Hrs

336 Hrs

Device Type

Lot No.

Rej S/S Rej S/S Rej S/S

Fail Notes

1H - 2002

Z86L87088PSCR51R3

Z86L990PZ008SCR51ML

Z86L990PZ008SCR51J5

Z8018008VSC

EYHBJ270F

BYHBHAE

-

0

-

0

-

45

-

0

45

32

45

BH0517A

-

BX145ASO

EYHB032

-

Z9023406PSCR51X3

Z84C0008PEC1983

Z8018008FSC

-

0

-

45

-

A036FY0X1P

Y132AB0Q

-

Z8937320ASC

B810WW8Q2

G1473AFB

-

Z86L87SZ008SCRXXX

Z86C3316PSCR4124

Z86C0408PECR2981

Z86L8808SSCR51PX

Z84C0008FEC

-

AYH1120AR

A204EK0RPPA

BXH1505APB

BY206BJ0B

BYH1786D

-

0

-

45

-

0

-

45

-

Z9023406PSCR5140

Z8673312PSC

-

0EY204JW0B

EY205LU0Q

EYHBHTH.0CP

NYH1736AAT

NYH1736AATA

B038NG0QA

B038GN0QB

K037JX0T

-

Z84C9010VSC

-

Z86L8808SSCR51XF

Z86E136SZ016SC

Z85C3008VSC

-

0

-

45

-

Z85C3008VSC

-

Z0843006PSC

45

-

Z8937320ASC

K813TY8

-

Z16C0110PSC

B9S0JY0

-

ZAC03-0004

4 - 17

ZiLOG

2002 Quality and Reliability Report

Table 5-8. ZiLOG Reliability Monitor Pressure Pot Test Conditions: 121°C, 2 ATM.

CMOS Plastic Packages 2002

96 Hrs

168 Hrs

336 Hrs

Device Type

Lot No.

Rej S/S Rej S/S Rej S/S

Fail Notes

Z8702414SSCR51XK

BHBT78.04B

-

0

-

45

-

0

45

Z8702414SSCR51XK

Z8623316VSCR4591

Z84C9010VSC

CHBT77

KE2080Q

K207HR0AP

K041HJ0S

K930FX0

-

Z85C3008PSC

-

Z16C0110PSC

-

Z86C0208PSCR4502

K207PY0AR

0

45

2H - 2002

Z8F6403FZ020SC

Z86E136SZ016SC

Z80180008VSC00TR

Z8S18020VSC

AR60986

-

0

-

45

-

0

45

AG0797EX

BZ221XX0B

K207XX0AR

A224DL0AP

BHCWF8.02DA

B219FP0

0

1

0

-

45

-

Z8612912SSC

Z9023406PSCR51J1

Z8PE003HZ010SC

Z86C6516PSCR3332

Z84C0006PEC

NY211NS0B

KZ219KN0P

KR61001.02

SY206HH0BAP

A222FN0AQ

R61105.A1

EZ80F92AZ020SC2047

Z86D991SZ008SC2046

Z8S18010VSC

44 B8F -EOS

45

32

45

Z8F6403FT020SC

Z8702414SSCR52CH

Z86C3312PSCR3130

Z8641708BSCR3212

Z86L98HZ008SCR526R

Z8018233ASC1932

Z8019520FSC

AZH11.132A

B220CD0AAA

BYH1665B

SHCNQ5.02RA

AH0657SB

0

-

45

-

K232CN0A

-

Z86C3312PECR5177

NY214GN0P

-

ZAC03-0004

4 - 18

ZiLOG

2002 Quality and Reliability Report

Table 5-9. ZiLOG Reliability Monitor Pressure Pot Test Conditions: 121°C, 2 ATM.

NMOS Plastic Packages 2002

96 Hrs

168 Hrs

336 Hrs

Device Type

Lot No.

Rej S/S Rej S/S Rej S/S

Fail Notes

1H - 2002

No Samples Available

2H - 2002

Z0853606VSC

B205APOA

-

0

45

0

45

ZAC03-0004

4 - 19

ZiLOG

2002 Quality and Reliability Report

Table 5-10. ZiLOG Reliability Monitor For Temperature Cycling Test Conditions: Condition C,

-65°C To 150°C CMOS 2002

100X

S/S

500X

Rej S/S Rej

1000X

Device Type

Lot No.

Rej

S/S Fail Notes

1H - 2002

Z86L8708PSCR51N7

Z86L88708PSCR51R3

Z86L990H2008SCR50XC

Z8623312PSCR4409

Z856L8808PSCR51JW

Z86E136PZ016SC

Z84C3008PEC

EYHBHMA

-

0

-

45

-

0

45

-

EYHBJ270F

H0757

-

EY149EP0RA

EY149EP0RB

EY10004AJ

EYH0765AA

EY144SW0V

EY145DE0Q

EY145DE0R

B810WW8Q2

EYHBQ33

0

-

45

-

Z84C3008PEC

-

Z84C3008PEC

-

Z8937320ASC

0

-

45

-

0

-

45

-

Z9023406PSCR51X3

Z86C0208PSCR517J

Z86C0412PECR4537

Z8673312PSC

-

EZ209HU0E

EZ208DS0B

OEY204JW0B

EYHBHTH.0CP

EY205LU0Q

AY142YY0BBP

AY142RY0RX1

AY142RY0RX2

AYH1120AR

A036FY0X1P

AMB54GC

0

-

45

-

0

45

-

0

45

Z86L8808SCCR51XF

Z84C9010VSC

-

0

-

Z8523008VSC

45

Z8611608SSCR3407

Z86C3316PSCR4124

Z84C0008PEC1983

EZ80L92AZ020SC

Z9035612PSCR3720

-

0

-

45

-

BYH1722A

ZAC03-0004

4 - 20

ZiLOG

2002 Quality and Reliability Report

Table 5-10. ZiLOG Reliability Monitor For Temperature Cycling Test Conditions: Condition C,

-65°C To 150°C CMOS 2002

100X

S/S

500X

Rej S/S Rej

1000X

Device Type

Lot No.

Rej

S/S Fail Notes

Z8018008VSC

BX145AS0

-

0

-

45

-

0

-

45

Z86L8808SSCR51XP

Z8937320ASC

BXH1505APB

B810WW8Q2

BY206BJ0B

BYH1786D

-

45

-

Z84C008FEC

Z9023406PSCR5140

Z86C0408PECR2981

Z853008VSC

-

A204EK0RPPA

B038GN0QA

B038GN0QB

BX145AS0

-

0

45

Z853008VSC

Z8018008VSC

Z8018008FSC

Y132AB0Q

Z86L827SZ008SCRXXX

Z86E136SZ016SC

Z86E0208PSC1925

Z86E126PZ016EC

Z8702414SCR51XK

Z16C0110PSC

G1473AFB

-

0

45

AYH1736AASP

AYB9BN0BBP

AY143HH0BP

AG0797EX

-

CHBT77

-

BHBT78.04B

B9S0JY0

-

Z8018008FSC

Y132AB0Q

-

Z8523008VSC

S042AE0R

Z86E136SZ016SC

Z84C9010VSC

NYH1736AAT

NYH1736AATA

K207HR0AP

Z85C3008PSC

Z16C0110PSC

K041HJ0S

K930FX0

-

0

45

0

45

ZAC03-0004

4 - 21

ZiLOG

2002 Quality and Reliability Report

Table 5-10. ZiLOG Reliability Monitor For Temperature Cycling Test Conditions: Condition C,

-65°C To 150°C CMOS 2002

100X

S/S

500X

Rej S/S Rej

1000X

Device Type

Lot No.

Rej

S/S Fail Notes

Z86C0208PSCR4502

K207PY0AR

-

0

45

0

45

2H - 2002

EZ80L92AZ020SC

Z8018008VSC00TR

Z8623316VSC4591

Z8S18020VSC

AMB54GC

0

-

45

-

0

45

44

45

0

-

45

-

BZ221X0B

KE2080Q

-

K207XX0AR

K813TX8

-

Z8937320ASC

-

Z8623312PSCR51XW

Z86L8808PSCR51JW

Z86L8808PSCR521A

Z86L8808PSCR2607

Z86L8808PSCR51JW

Z8PE003HZ010SC

Z9023406PSCR522F

Z86L8808PSCR51JW

Z9023406PSCR522F

Z86L8808PSCR4455

Z8612912SSC

K151UY0RA

KZHCP26.0MJ

KZHCNYS.0KA

KZH1772BE

KZHCNL2.0B

KZHCNSY.0G

KZHCNSY.00E

B219FP0

0

-

45

-

0

45

KHCRIT.0CRC

OEY204JW0B

KHCYGG.00PI

NZHCPJN.0QS

A224DL0AP

A048LW0X

0

45

B3F Leakage

Z86E2112PSC

1

-

45

-

44

Z86L8808PSCR4455

Z9023406PSCR51J1

Z86L8808PSCR51J1

Z86E136PZ016SC

Z86C6516PSCR3322

Z84C0006PEC

BZHCW79.02E

AYH1120AR

KZHCNL0.00C

KH1577AD

45

-

0

-

45

-

KH1577AG

NY211NS0B

KZ219KN0P

KR61001.A2

-

EZ80F92AZ020SC2047

-

ZAC03-0004

4 - 22

ZiLOG

2002 Quality and Reliability Report

Table 5-10. ZiLOG Reliability Monitor For Temperature Cycling Test Conditions: Condition C,

-65°C To 150°C CMOS 2002

100X

S/S

500X

Rej S/S Rej

1000X

Device Type

Lot No.

Rej

S/S Fail Notes

Z86D991SZ008SC2046

SY206HH0BAP

-

0

-

45

-

0

45

Z8018233ASC1932

Z8F6403FT020SC

Z8018233ASC1932

Z86C3312PSCR2130

Z8641708BSCR3212

Z8019520FSC

AH0657SB

-

45

R61105.A1

AH0657SB

B220CD0AAA

BYH1665B

Y132AB0Q

NY214GN0P

SHCNQ5.01RA

0

45

Z86C3312PECR517F

Z86L98HZ008SCR526R

-

Table 5-11. ZiLOG Reliability Monitor For Temperature Cycling Test Conditions: Condition C,

-65°C To 150°C NMOS 2002

100X

S/S

500X

Rej S/S Rej

1000X

Device Type

Lot No.

Rej

S/S Fail Notes

1H - 2002

Z0844004DSA0541

B607BD0ACAA

-

0

45

0

45

2H - 2002

Z0843006PSC

Z0853606VSC

K037JX0T

B205AP0A

-

0

45

0

45

ZAC03-0004

4 - 23

ZiLOG

2002 Quality and Reliability Report

Table 5-14. ZiLOG Reliability Monitor Highly

Accelerated Stress Test (HAST) Test Conditions:

140°C @ 85% Humidity At 2 ATM Of Pressure CMOS

Plastic 2002

48 Hrs

96

Hrs

Device Type

Lot No.

Rej S/S Rej S/S Fail

Notes

1H - 2002

Z9023406PSCR51X3

Z86L990PZ008SCR51ML

Z86L990PZ00R51J5

EZ80L92AZ020SC

EYHB032

BYHBHAE

BH0517A

MB546

0

45

Z86L990PZ008SCR51ML

Z86L990PZ008SCR51J5

Z8702414SCR51XK

BYHBHAE

BH0517A

BHBT78.04B

2H - 2002

Z8702414SSCR52CH

EZ80F92AZ020SC2047

Z8S18020VEC

AZHF11.132A

KR61001.A2

B222FR0AP

KA227EU8AB

0

45

40

30

Z0221524VSCR51JA

ZAC03-0004

4 - 24

ZiLOG

2002 Quality and Reliability Report

Table 5-13. ZiLOG Reliability Monitor ZiLOG Package Integrity Test Results

CMOS 2002

Device Type

Lot No.

Rej

S/S

Fail Notes

1H - 2002

Z86E0208PSC1925

Z86E3108SSCR50W0

Z8018233FSC

AY139BN0BBP

AY147RS0BPP

AY144LY0P

BYH1722A

0

15

Z9035612PSCR3720

Z8018008VSC

BX145AS0

Z86L8808SSCR51PX

Z8624312FECR51R4

Z8673312VEC

BXH1505APB

BY147KK0R

EY147KP0RB

EYHBJ70F

Z86L8708PSCR51R3

Z8018008FSC

Y132AB0Q

Z86L827SZ008SCRXXX

Z84C0008PEC1983

Z8019520FSC

G1473AFB

A036FY0X1P

AY147NP0RAP

BY150HR0AAD

BY149GU0AAB

BY141JS0R

BY135K0B

Z86E3116PSC

Z8673312VSCR3845

Z86C8316SSCR4564

Z86E0208HSC1925

Z86E0412PSC1866

Z8673312VSCR3845

Z80L183AZ030SCR4567

Z86E0812SSC1866

Z86C3316PSCR4124

Z86E0208SECR516F

Z86L430-8FSCR50AF

Z15M1720ASC1868

Z8624312PECR40945

Z86733VSCR3845

Z8623312SECR4472TR

Z8617216FSCR5053

Z86E0208HSC1925

Z8623312PSCR4409

Z8S18033VSC

EZ150NP0P

EKY149GUOB

KG1164

NZ150NP0A

AYH1120AR

AZ203BP0APP

AX201CW0RPX

A048TY0X10

BY202HS0RAD

BY201EZ0AAQ

B202HR0RA

BY1506Y0RP

BY135KZ0B

EX201DL0R

EY145BN8A

EYHBHTH.0CP

NZ203SU0R

A204EK0RPPA

AY209AG0P

AY204FN0AP

Z86L8808SSCR51XF

Z86L0808SSCR5009

Z86C0408PECR2981

Z8673312VSCR3845

Z8S18010FSC

ZAC03-0004

4 - 25

ZiLOG

2002 Quality and Reliability Report

Device Type

Lot No.

Rej

S/S

Fail Notes

Z86E136SZ016SC

Z9023406PSCR5140

Z8932320VECR519W

Z86L8808SSCR4590TR

Z84C0008FEC

AYH1736AASP

BYH1786D

0

15

BY206BR0RBA

BXHCA91.0QC

BY206BJ0B

OEY204JW0B

EY205LU0Q

NYH1736AAT

NXHCE27.0CT

AZ212CZ0PX

1206FJ8ARP

ABS8859.1XA

BY210GN0AAP

B207XX0AS

BHBT78.04B

BYH1303Q

Z8673312PSC

Z84C9010VSC

Z86E136SZ016SC

Z86L8808PSCR51JW

Z86C8316PSCR264

Z8S18033VSC

Z2209SZ000XC

Z8673312PSC

Z8S18033VSC

Z8702414SCR51XK

Z9023306FSCR51J8

Z86E0812SSC1866

Z8673312VSCR3845

Z8PE002PZ010SCR523K

Z86C0208PSCR4502

Z8937320ASC

EZ209LY0C

E203BT0ABBA

EZ209AR0AB

K207PY0AR

K813TY8

Z8S18020VSC

K207XX0AR

AG0797EX

Z86E126PZ016EC

Z8612912SSC

A217JX0PNP

AR60986

Z8F6403FZ020SC

Z16C0110PSC

B9S0JY0

Z8702414SCR51XK

Z853008PSC

BHBT78.04B

K041HJ0S

Z86L9533ASC

KH006A

Z8623316VSCR4591

Z0221520ASCR50A5

KE2080Q

BY150JP0A

2H - 2002

Z86K1505PSCR4530

Z8S18033VSC00TR

Z8018110FEC

AT221RU0AAC

A222FP0AQ

AY143GZ0AU

AH1575AABAP

BHCT27.00C

BY206BS0A

B224SY0AA

BX208DK0B

B20BL0S

0

15

Z86E132SZ016SC

Z9023406PSCR503W

Z8932320VECR50XPTR

Z86D8608SSCR524

Z86L4308FSCR50AF

Z8E0010HEC

ZAC03-0004

4 - 26

ZiLOG

2002 Quality and Reliability Report

Device Type

Z86E13016PEC

Lot No.

NZ221SU0

Rej

S/S

Fail Notes

0

15

Z86E0812SSC1866

Z86L8808PSCR51JW

Z8L18220ASC

Z86E0412PSC2004

Z8S18010VSC

NZ224KR0PAA

KZHCP26.0N

KY219GU0P

AZ224C00APB

A222FN0AQ

A227PX0APPA

A224DL0AP

BHCWF8.020A

B226GT0P

B224SY0AA

BZ220HS0B

B219FP0

NY211NS0B

NZ224UZ0PB

KZ219KN0P

K816FN0

SZHCPSN.5QB

AZ227CW0RA

BY1506Y0RP

AH0657SB

BZHWY3.1PC

BZ220HS0B

BYH1665B

BZ220BP0AA

NZ224UZ0PB

K816FN0

SY206HH0BAP

AZ229EW0BPA

AZ231PS0APA

AH0657SB

Z8L18020FSC

Z8612912SSC

Z9023406PSCR51J1

Z86C4316VSCR4065

Z86D8608SSCR52L1

Z86L4308FSCR50AF

Z8PE003HZ010SC

Z86C6516PSCR3332

Z86C0208SSCR3358

Z84C0006PEC

Z8937320ASC

Z86L8808SCR50HWTR

Z86E0812PSC1866

Z86C8316SECR52JATR

Z8018233ASC1932

Z86L8808PSCR4455

Z86L4308FSCR50AF

Z8641708BSCR3212

Z8PE003HZ010SC

Z86E0208SSC1925

Z8937320ASC

Z86D991SZ008SC2046

Z86E0812PSC1866

Z86E3412SSC

Z8018233ASC1932

Z8702414SSCR52CH

Z8673312PSC

AZHF11.132A

BZ230AJ0

B226DT0BA

BZ230AN0

Z8932320VECR50XP

Z8674312FSC

Z8641708BSCR3212

Z86D990HZ0082046

Z86C3312PECR517F

Z86C0812SSCR2433

EZ80F92AZ020SC2047

Z8019520FSC

Z86E0412PSC1866

Z8623312SECR4472TR

Z8F6403FT020SC

Z84C3008PEC

BYH1665B

C0142BT0ABA

NY214GN0P

NZ233WZ0BB

KR61001.A2

K232CN0A

AZ237PT0PB

AZ235CY0PA

AR6110.5A

B228AB0AQ

BZ228FW0A

BZ237FG0AB

NE0903D

Z86E3412VSC

Z86L4308FSCR50AF

Z86C6516PSCR3752

ZAC03-0004

4 - 27

ZiLOG

2002 Quality and Reliability Report

Device Type

Lot No.

Rej

S/S

Fail Notes

Z86E0812SSCR5017TR

Z16M1720ASC1868

Z86K1505PSCR5016

Z86C36SSCR5189TR

Z86L4308FSCR50AF

Z09036512PSCR51MR

Z86E7216FSC

NZ235FN0P

KA049B00X1

AH1656APB

AZ24CJP0PA

AZ243CU0PB

BH1670AQB

B242PR0A

0

15

Z86C3316PSCR2913

Z86C0812SECR5129TR

NZ243EH0BP

NZ241EH0AA

Table 5-14. ZiLOG Reliability Monitor ZiLOG

Package Integrity Test Results

NMOS 2002

Device Type

1H - 2002

Lot No.

Rej

S/S

Fail Notes

Z0843006PSC

Z0853008VSC00TR

Z0853008VSC

K037JX0T

A217JR0SP

B217JR0

0

15

2H - 2002

Z0853606VSC

B224CY0AAP

B205AP0A

0

15

ZAC03-0004

4 - 28

ZiLOG

2002 Quality and Reliability Report

Table 5-15. C-Mode Scanning Acoustic Microscope Monitor 2002

CMOS

Device Type

Lot No.

Sample Selection

Results

1H - 2002

Z9035612PSC

Z8673312PSC

Z9035612PSCR3720

Z8673312PSC

Z85C3008VSC00TR

Z9037116PSC

Z8673312PSC

Z86C8316SSCR4564

Z86L990PZ008SCR51J5 BH0517A

Z86L990PZ008SCR51ML BYHBHAE

BE2468

500X TC

0/5

BY146GP0AB

BY143ET0B

BYH1722

BY145CP0

B036DJ0FB

BY146GP0AA

BY145CP0B

BY145JS0R

FRESH SAMPLES

1000X TC

1000XTC

500X

Z9035612PSCR3720

Z8018008VSC

Z8611608SSCR3407

BY1722A

BX145AS0

AY142RY0R1GB

AYK12RY0RIHA

500X

Z86C0812SECR50AHTR AZ150JZ0RAA

FRESH SAMPLES

1000X TC

500X

1000X TC

FRESH SAMPLES

1000X TC

FRESH SAMPLES

500X TC

FRESH SAMPLES

500X TC

FRESH SAMPLES

500X TC

Z86C8316SSCR4564

Z86E0812SSC1866

Z86E0208SSCR2433

Z86C0812SSCR2433

Z8702114SSCR4216TR

Z8611608SSCR3407

Z86E0208PSC1925

Z86L8708PSCR51N7

Z86L0808SSCR5009

Z86L8708PSCR51R3

Z86L827SZ008SCRXXX G1473AFB

Z8018008FSC

Z86C0208SSCR50JH

Z86E0412SSC1866

Z86C0812SECR5129TR NZ150LY0RA

Z86C0812SECR5129TR NZ146EX0RB

AY141JS0R1X

AX144LT0QA

AZ147PZ0RP

AZ146ET0RPA

AZ15V0RAP

AY129FH0R

AY143HH0BP

AY139BN0BBY

EYHBHMA

E151W0RQ

EYHBJ270F

Y132AB0Q

N140CT0RAA

NZ150NP0AP

Z86E0412SSC1866

Z86CE0812SEC

Z86E0208SECR516PTR N149FR0AA

Z86L8808SSCR51PX

Z8937320ASC

Z9037116PSC

NZ145BH0AP

N145BH0AQ

BXH1505APB

B810WW8Q2

BYH101PS

Z9037116PSC

MB546

Z8702114SSCR4216TR

Z86E0812SSC1866

Z86C0812SSCR2433

Z86L0808SSCR5009

Z86C3316PSCR4124

Z84C0008PEC1983

AZ201DG0RAC

AZ151PU0RBP

NZ150NP0A

AZ151RS0RPB

A151AR0RAPC

AYH1120AR

A036FY0X1P

500X TC

ZAC03-0004

4 - 29

ZiLOG

2002 Quality and Reliability Report

Table 5-15. C-Mode Scanning Acoustic Microscope Monitor 2002

CMOS

Device Type

Lot No.

Sample Selection

Results

Z8018008FSC

Z86E0812SSC1866

Z9037116PSC

Z8937320ASC

Z16C3010ASC

Z8937320ASC

Z9037116PSC

Z86L990PZ008SCR51ML BYHBHP1A

Z9023406PSCR5140

Z8937320ASC

Z86C3316PSCR4124

Z86C0408PEC

Z86E136SZ016SC

Z84C9010VSC

Y132AB0Q

500X TC

0/5

NZ150NP0A

BYH1101PWE

BYH1101B

BYH149BPB

B810WW8Q2

B124AT0P

B810WW8Q2

BYH1498QA

BYH1498QB

FRESH SAMPLES

500X TC

FRESH SAMPLES

1000X TC

BYH1786D

B810WW8Q2

AYH1120AR

A204EK0RRPPA

AYH1736AASP

EY205LU0Q

EYHBHTH.0CP

EY204JW0

500X TC

FRESH SAMPLES

500X TC

FRESH SAMPLES

500X TC

Z86L8808SSCR51XF

Z867331PSC

Z86L8808PSCR5101

Z86L8108PSCR5101

Z86E136SZ016SC

Z8937320ASC

Z8E00110HSCR508F

Z85C3008VSC

EH0092A

EH0092B

NYH1736AATA

NYH1736AAT

K810WW8QA

K810WW8Q1

B1091S0S

B038GN0QA

B038GN0QB

BY206BJ0B

B038GN0QA

B038GN0QB

BYH1498SA

BYH1786D

A204EK0RRPPA

AYH1736AASP

A036FY0Y1P

AYH1120AR

EY205LU0Q

EYHBHTH.0CP

NYH1736AAT

NYH1736AATA

KY916JZ0A

KY916JZ0C

BYH1498TG

BYH1498UA

B9S0JY0

Z84C0008FEC

Z85C3008VSC

Z9037116PSC

500X TC

FRESH SAMPLES

1000X TC

500X TC

1000X TC

500X TC

Z9023406PSCR5140

Z86C0408PECR2981

Z86E136SZ016SC

Z84C0008PEC1983

Z86C3316PSCR4124

Z84C9010VSC

Z86L8808SSCR51XF

Z86E136SZ016SC

Z8937320ASC

500X TC

FRESH SAMPLES

Z8937320ASC

Z9037116PSC

Z16C0110PSC

Z85C3008VSC

B0386N00Q

ZAC03-0004

4 - 30

ZiLOG

2002 Quality and Reliability Report

Table 5-15. C-Mode Scanning Acoustic Microscope Monitor 2002

CMOS

Device Type

Lot No.

Sample Selection

Results

Z9023406PSCR5140

Z84C0008FEC

Z9037116PSC

Z9035612PSCR3720

Z85C3008VSC

BYH1786

1000X TC

FRESH SAMPLES

1000X TC

FRESH SAMPLES

500X TC

1000X TC

3X REFLOW

FRESH SAMPLES

500X TC

0/5

BY206BJ0B

BYH1498S0

BYH1498SN

BYH1722A

B0386N0QA

B0386N0QB

B217S0A

B219TU0

BZHCNSW.00U

EYHB032

Z85C3008VSC

Z16C3010VSC00TR

Z86L8808PSCR521A

Z9023406PSCR51X3

Z8673312PSC

Z8937320ASC

Z16C0110PSC

Z84C9010VSC

Z8937320ASC

Z8S18020VSC

Z85C3008PSC

Z9037116PSC

Z16C0110PSC

Z8702414SSCR51XK

Z16C3010VSC00TR

Z86L8808PSCR2607

Z86L8808PSCR5121

Z86E126PZ016EC

Z16C0110PSC

EYHB032

0EY204JW03

KY916JZ0C

K930FX0

K207HR0AP

K813TY8

K207XX0A

K041HJ0S

400X TC

FRESH SAMPLES

500X TC

BYH1498AH

BYH1498PD

BYH1498AC

B9S0JY0

BHBT78.04B

CHBT77

B219TU0

B217S0A

BYHB625.EHA

BZHCNTA.04T

AG0797EX

K930FX0

1000X TC

FRESH SAMPLES

500X TC

1000X TC

300X TC

FRESH SAMPLES

Z85C3008PSC

Z84C9010VSC

K041HJ0S

K207HR0AP

KYMB54GC

KE2080Q

Z86C0208PSCR4502

EZ80L92AZ020SC

Z86C3316VSCR4591

Z84C3006PEC

Z86L8808PSCR521A

Z86L8808PSCR51JW

Z86C9533ASC

Z86L8808PSCR521A

Z86E136PZ016SC

Z84C3010PEC

Z86L1608PSCR2565

Z86E0612PSC

K210GW0CA

KZHCNYS.00G

KZHCNTM.0ZE

KZHCP26.0ML

KZHCP26.0ME

KZHCP26.00P

KYH1769AB

KZHCNYS.0KB

KH1747AABPAC

K213AY0AP

K136BB0A

K117DJ0S

ZAC03-0004

4 - 31

ZiLOG

2002 Quality and Reliability Report

Table 5-15. C-Mode Scanning Acoustic Microscope Monitor 2002

CMOS

Device Type

Lot No.

Sample Selection

Results

Z86L8808PSCR521A

Z8937320ASC

Z86C3312PECR2035

Z86E136PZ016SC

Z86L8808PSCR2607

Z86E3016PSC

Z86C6516PSCR50CH

Z86L8808PSCR51JW

Z86L0808SSCR5009

Z86L8808PSCR51JW

Z85C3008VSC

KZHCNYS.00T

KZHCNYS.00B

K816FP0

FRESH SAMPLES

0/5

K210BX0

KH1736AATA

KZH1772BC

KZH1772BA

KZ210GS0AAB

NG0060A

NZHCNST.0PB

NZ215ABAAA

NZ215ABBAAB

NZ215AB0AB

NZHCNST

S042AE0R

KZHCNSY.00X

Z86L8808PSCR521A

2/15 DIE/MOLD INT

2H - 2002

Z16C0110PSC

B9S0TY0

BZ221XX0B

B019LS0S

1000X TC

300X TC

1000X TC

FRESH

500X TC

FRESH

1000X TC

FRESH

0/5

Z8018008VSC00TR

Z8E0010HSCR508F

Z86K1505PSC4530

Z9010204PSCR3855

Z86C6516PSCR3918

Z86E126PZ016EC

Z86E3016VSC

Z8523016VSC00TR

Z86E126PZ016EC

Z86L8808PSCR51JW

Z86C3312PECR529J

Z86C0208PSCR4448

Z98622812PSC

A220EZ0PAA

A220EZ0PC

A219GG0PB

A2170G0PA

AG0797EX

AZ219JP0AP

AZ215EK0AQ

AG079EX

KXHCP2K.02A

K219JU0A

K219JU0B

KZ218PR0PAA

K220GT0AAB

K220GT0AAA

K219SZ0PB

0/15

0/5

0/15

Z98622812PSC

Z84C3006PEC

K219SZ0PA

FRESH

0/15

Z86C0412PSCR51M6

Z86L0208PSCR4241

Z86C0408PECR2981

Z8623312PEC2035

Z86E136PZ016SC

EZ80L92AZ020SC

Z8623312PECR52F5

KZ219HP0A

K219KY0D

KZ219HL0D

KZ219HL0C

K220CF0A

KH1721AAR

KYMB54GC

KZ220AY0AA3

KZ220AY0AAA

FRESH

100X TC

FRESH

0/15

0/5

0/15

ZAC03-0004

4 - 32

ZiLOG

2002 Quality and Reliability Report

Table 5-15. C-Mode Scanning Acoustic Microscope Monitor 2002

CMOS

Device Type

Lot No.

Sample Selection

Results

Z86K1505PSCR4243

Z8623312PECR52F5

Z86C3312PECR2035

Z86C3312PSCR2130

Z86C3312PSCR2035

Z86C3316VSCR4591

Z86C3012PECR3495

Z16C0110PSC

KZ28FF0A

FRESH

500X TC

FRESH

1000X TC

500X TC

1000X TC

FRESH

FRESH S

1000X TC

FRESH

100X TC

FRESH

0/15

0/5

0/15

0/5

KZ220AY0AB

K220CF0AB

K220CF0AC

K220C00AP

K220CF0AA

KE2080Q

KZ214BZ0BB

K930FX0

K207HP0AP

KYMB54GC

KE2080Q

KZ210GT0AAQ

N219EU0AA

N212CT0

NY211LP0A

NZHCPK0.00P

N214DH0

Z84C9010VSC

EZ80L92AZ020SC

Z8623312VSCR4591

Z86E3116PSC

0/5

0/15

0/5

0/15

0/5

0/15

0/5

Z86C6516PSCR507F

Z86C6516PSCR3918

Z86L8808PSCR51JW

Z86C6516PSCR3918

Z86L8808PSCR51JW

Z86L8808PSCR4455

Z16C3010VSC

Z16C3010VEC00TR

Z8018008VSC00TR

Z16C3010VSC00TR

Z9023106PSC

N211LR0A

NZHCPK0.00A

NZHCPJS.00E

NZHCPJS.00Q

NZHCPJS.00L

NZHCPJS.00N

NZHCPJS.00G

NZHCPJS.00R

B223BB0P

B136CU0P

BZ221XX0B

B223BB0

B213AW0Q

B213AT0B

B213AX0C

Z9023106PSC

B213106PSC

B213AT0A

Z9023406PSCR51J1

Z9023406PSCR522F

Z86L8808PSCR4455

Z16C3010VEC00TR

Z84C1510AEC

BHF0F3.05D

BHF0F3.00PB

BZHCW79.2BC

BZHCW79.28B

BZHCW79.02C

BZHCW79.2BA

A224CX0Q

AZ220FT0P

AR60986

A224CZ0PX

Z8F6403FZ020SC

Z16C3010VSC

0/5

0/15

ZAC03-0004

4 - 33

ZiLOG

2002 Quality and Reliability Report

Table 5-15. C-Mode Scanning Acoustic Microscope Monitor 2002

CMOS

Device Type

Lot No.

Sample Selection

Results

Z16C3010VSC

A224CY0X

A219TT0PAP

KYMB54GC

KZ222ET0

FRESH

1000X TC

FRESH

500X TC

FRESH

PKG INT

FRESH

500X TC

FRESH

100X TC

FRESH

1000X TC

500X TC

FRESH

0/15

0/5

Z8523016VSC00TR

EZ80L92AZ020SC

Z8623312PECR503X

Z88C0020PSC

Z86E136PZ016SC

Z86C3312PECR2035

Z86E136PZ016SC

Z84C3006PEC

0/15

0/5

KZ222EP0

K220EH0A

KH1577AE

K224NZ0A

KH1577AB

K223EK0

Z86E136PZ016SC

Z84C3006FEC

KH1577AF

K208EF0BA

K22ACT0AP

KZ224WY0AP

KH1577AC

KZ221CZ0B

KZ222TT0U

KZHCNL0.0AA

NG0060A

Z86C3108PECR3519

Z86E136PZ016SC

Z86E3016PSC

Z84C0006PEC1527

Z86L8808PSCR51JW

Z86C6516PSCR50CH

Z86L98HZ008SCR526R

SHCNQ5.01RA

Z86L8808SSCR50HWTR SZHCQ47.00B

Z86L8808PSCR51JW

Z86L8808PSCR521A

Z9023306PSCR5159

Z9023406PSCR51J1

Z9023406PSCR522F

Z86L8808PSCR4455

Z8621912SSC

BZHCWY7.02E

BZHCW7C.1PD

BHF0F3.063

BHF0F3.05D

BHF0F3.00PB

BZHCW79.2BC

BZHCW79.28B

A224DL0AP

AR60986.1

AZHF11.132A

A224CZ0PX

A224CY0X

A219TT0PAP

AH0657SB

A224DL0AP

KR61001.A2

NG0060A

SHCNQ5.01RA

SY206HH0BAP

BHF2P0.00AA

BZHF03W.05B

BZHF03W.05A

BHCY0Q.00AA

Z86L8808SSCR4590

Z8702414SSCR52CH

Z16C3010VSC

0/5

0/15

0/5

0/15

Z16C3010VSC

Z8523016VSC00TR

Z8018233ASC1932

Z8621912SSC

EZ80F92AZ020SC

Z86C6516PSCR50CH

Z86L98HZ008SCR526R

Z86D991SZ008SC2046

Z9023406PSCR51KC

Z86L8808PSCR51JW

ZAC03-0004

4 - 34

ZiLOG

2002 Quality and Reliability Report

Table 5-15. C-Mode Scanning Acoustic Microscope Monitor 2002

CMOS

Device Type

Lot No.

Sample Selection

Results

Z86L8808PSCR51JW

Z8641708BSCR3212

Z86L8808PSCR51JW

Z9025106PSC

Z16C3010VSC00TR

Z9023406PSC

Z86L8808PSCR51JW

Z9023406PSCR51KC

Z86L8808PSCR51JW

Z8PE003HZ010SC

Z86L8808SSCR4590

Z8F6403FZ020SC

BZHF03W.05E

BZHF035.0PA

BYH1665B

BZHF035.0PF

BZHF035.0QE

BZHF035.0PB

B230EK0A

BZ233FT0

BZ233FS0A

BZ233FS0AP

BZ233HK0

BZ234AJ0AP

BHF343.00F

BZHF035.00D

BZHF035.00C

BZHF035.00F

BZHF035.0PL

BZHF035.0QJ

BZHF035.0PJ

BZHF035.00E

BHF343.00B

BZHF03R.00B

B219FP0

FRESH

1000X TC

FRESH

500X TC

FRESH

500X TC

FRESH

1000X TC

FRESH

1000X TC

FRESH

0/15

AZHCY3W.00B

AR60986.1

AZHCY3Y.7PB

AZHCY3W.00D

Z86L8808SSCR52M8

Z86L8808SSCR4590

Z86L8808SSCRR5086TR AZHF03W.2PB

Z8018233ASC1932

Z86L8808SSCR52C7

Z8621912SSC

AH0657SB

AZHCY2Y.9PA

A224DL0AP

Z86L8808SSCR50HWTR AZHCY0N.0PI

Z8702414SSCR52CH

Z96L8808SSCR52FN

Z8621912SSC

AZHF11.132A

AZHF096.008

A224DL0AP

BHF42J00PA

BH42J00PG

BHW55.00B

BH42J.00PB

BH42J.00PI

BH42J.00PD

BHCWF8.02DA

BHF42J.00PC

BHFM15.00E

Z90255066PSCR51K9

Z9023406PSCR51J1

Z90255066PSCR51K9

Z9023406PSCR522F

ZAC03-0004

4 - 35

ZiLOG

2002 Quality and Reliability Report

Table 5-15. C-Mode Scanning Acoustic Microscope Monitor 2002

CMOS

Device Type

Lot No.

Sample Selection

Results

Z86L8808PSCR51JW

Z9025506PSCR5288

Z8641708BSCR3212

Z86C3312PSCR2130

Z86L8808PSCR51JW

Z9025506PSCR52LX

Z9023406PSCR51KC

Z86L8808PSCR51JW

Z8621912SSC

Z86L8808SSCR50HWTR AZHCY0N.0PH

Z86L8808SSCR50HWTR AZHCY0N.00C

Z86L8808SSCR50HWTR AZHCY0N.PEB

Z86L8808SSCR50HWTR AZHCY0N.00B

Z86L8808SSCR50HWTR AZHCY0N.00D

Z86L8808SSCR52MC

Z8018233ASC1932

Z8S18010VSC

BZHF29N.01E

BZHF29N.01D

BH0Q3Q.02AB

BHCQ3Q.02A

BYH1665B

B220CD0AAA

BZHF26W.0P1

BZHF26W.0QG

BZHF26W.0PH

BHF3G2.00DB

BHF3QP.02PA

BHF3QP.02PC

BHF343.00AC

BHF3G2.00DC

BZHF26.0PA

A224DL0AP

FRESH

500X TC

FRESH

100X TC

FRESH

500X TC

FRESH

500X TC

FRESH

1000X TC

FRESH

0/15

AZHF29S.01A

AH0G57SB

A222FN0AQ

AH0G57SB

A222FN0AQ

Z8018233ASC1932

Z8S18010VSC

Z86L8808SSCR50HWTR NZHF03T.0BC

Z86L8808SSCR50HWTR NZHF2CF.0AC

Z86L8808SSCR50HWTR NZHF2CF.0AK

Z86L8808SSCR50HWTR NZHF2CF.08K

Z86L8808SSCR50HWTR NZHF2CF.0AL

Z86L8808SSCR50HWTR NZHF2CF.0BI

Z86L8808SSCR50HWTR NZHF2CF.0AM

Z86L8808SSCR50HWTR NZHF2CF.0BH

Z86L8808SSCR519P

Z86L8808SSCR50HWTR NZHF03T.0BE

Z86C3312PECR517F NY214GN0P

Z86L8808SSCR50HWTR NZHF29S.06P

Z86L8808SSCR4470TR

Z86L8808SSCR4590

Z86L8808SSCR52FN

Z86D991SZ008SC2046

Z86L8808SSCR4590

NZHF295.4PA

NZHF29S.06P

NZHF29Q.02

NZHF29Q.1PE

NZHF29Q.1PG

NZHF29S.05

SY206HH0BAP

SZHF29N.02P

ZAC03-0004

4 - 36

ZiLOG

2002 Quality and Reliability Report

Table 5-15. C-Mode Scanning Acoustic Microscope Monitor 2002

CMOS

Device Type

Lot No.

Sample Selection

Results

Z86L8808PSCR51JW

Z84C0006PEC

EZ80F92AZ020SC2047

Z8019520FSC

Z86L8808PSCR51JW

Z9023306PSCR51J9

Z8S18020VEC

KZHCNL0.00C

KZ219KN0P

KR61001.A2

K232CN0A

KZHF29N.01P

BH343.06PC

B222RR0AP

B222FR0BA

BZHFR26W.00D

BZHF2CH.1PB

BZHCN3A.05B

BYH1665B

BZHCN0D.1PB

AH06575B

AZHF29R.0PF

AZHCN3A.05A

AZHCN00.01P

1000X TC

500X TC

1000X TC

500X TC

FRESH

1000X TC

FRESH

1000X TC

FRESH

0/15

Z8S18020VEC

Z86L8808PSCR51JW

Z86L8808PSCR521A

Z86L8108SSCR52HTR

Z8641708BSCR3212

Z86L8108PSCR5101

Z8018233ASC1932

Z86L8808SSCR52FN

Z86L8108SSCR528HTR

Z86L8108PSCR5101

Z86L8808SSCR50HWTR NZHF2CG.01D

Z84C0006PEC

Z8019520FSC

Z86L8808PSCR521A

Z0221524VSCR51JA

Z8019520FSC

KZ219KN0P

K232CN0A

KZHF2CH.01C

KZHF2CH.01B

KA227EU8AB

K232CN0A

1000X TC

500X TC

FRESH

500X TC

1000X TC

Table 5-16. C-Mode Scanning Acoustic Microscope Monitor 2002

NMOS

Device Type

Lot No.

Sample Selection

Results

1H - 2002

Z0843006PSC

Z0220112VSCR4078TR

Z0843004PSC

K037JX0T

K139AX0R

K037JX0T

FRESH SAMPLES

1000X TC

500X TC

0/5

2H - 2002

Z0853606VSC

Z084C3006PSC

B205AP0A

K037JX0T

1000X TC

500X TC

1000X TC

0/15

0/5

ZAC03-0004

4 - 37

ZiLOG

2002 Quality and Reliability Report

CHAPTER 5

Assembly and Test

Package types:

8 / 18 / 20 / 22 / 28 / 40 / 48

Plastic Dual In-line Package (PDIP)

42 / 52 / 64

Shrink Dual In-line Package (SDIP)

Plastic-Leaded Chip Carrier (PLCC)

Quad Flat Pack (QFP)

28 / 44 / 68 / 84

44 / 80 / 100 / 132/ 144 / 208

44 / 64 / 100 / 144 / 160

64

Very Small Quad Flat Pack (VQFP)

Thin Quad Flat Pack (TQFP)

18 / 20 / 28

Small Outline Integrated Circuit (SOIC)

Shrink Small Outline Package (SSOP)

20 / 28 / 48

Technology Data:

Die attach (method/composition) Oven cure/silver filled epoxy

Ball bond, thermosonic/gold to aluminum

Wirebond (type/material)

Crescent bond, thermosonic/gold to silver plated

frame

Bonding wires

Gold 1.0 / 1.3 mil

(material/diameter)

Package seal

Transfer epoxy molding

Solder plate

Lead and lead finish

Copper (A151) / Ag spot plate for PLCC

Copper (A194)/Ag spot plate for PDIP, SDIP, SOIC

and SSOP

Leadframe material/plating

Copper (A7025)/Ag spot plate for QFP and VQFP

Leadframe plating thickness

Moisture Sensitivity Level

for Surface Mount Devices

Ag spot is 150-400 microinches

PLCC, QFP, LQFP & TQFP: MSL = 3, Floor Life

= 168 hrs. @ 30°C/60% RH

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

Pre/Post Packaging Device Test Procedures:

Wafer probe at 70ºC; final test at 70ºC; Wafer probe tests guardband final test

Number/Type of Testers

Sentry 15/20/21, Megatest, ITS9000,

SZ

Provision for Testing at Speed

Provision of high temp testing

Yes

Environmental handlers

Yes

Provisions for tape and reel shipment of

SMT devices

Provisions for tray shipment of QFP

devices

Yes

ZAC03-0004

5- 2

ZiLOG

2002 Quality and Reliability Report

ATTACHMENT 1

Legend:

- Material

- Transport

- Process

- Bank

- QC acceptance

- Inspection/Test

___________________________________________________________________________________________

PLASTICS PROCESS FLOW

Flow

Process/Item

Document

Wafer

Die Bank

SOM-040

SOM-005

Pack/transport to Subcon

Subcon Assembly

Pack/transport ZEPI

SOM-005

QCM-235

Incoming Inspection of Subcontract

ZilOG Products

Electrical Test

TSM-021

Burn-In (48hrs or as specified on PSI)/

100% Electrical Test at Room

TSM-012/

TSM-021

Electrical Test Gate

QCM-108

QCM-126

REJECT

QC Outgoing & Shipping Gate

(see note 1)

Final Visual Inspection (For visual reject)

MAM-235

SOM-171

MAM-212

MAM-236

MAM-067

QCM-301

Finished Goods

Bake Out (for VQFP/QFP/TQFP)

Tape & Reel (as required per PSI)

Pack

Shipping Audit

Ship

ZAC03-0004

5- 3

ZiLOG

2002 Quality and Reliability Report

ATTACHMENT 2

PLASTIC-STANDARD ASSEMBLY/TEST PROCESS

PLASTIC – STANDARD (C FLOW)

PLASTIC – STRESSED (D FLOW)

DIE BANK

•

DIE BANK

•

WAFER SAW

EPOXY DIE ATTACH

WIREBOND

WAFER SAW

EPOXY DIE ATTACH

WIREBOND

MOLD

STRIPMARK

SOLDER PLATE

BAKEOUT (FOR PLCC)

TRIM/FORM

SOLDER PLATE

BAKEOUT (FOR PLCC)

TRIM/FORM

•

100% ELECTRICAL TEST – HOT

AND QC SAMPLE ELECTRICAL

AT 25ºC

•

100% ELECTRICAL TEST – HOT

•

QC PRESHIP INSPECTION

•

BURN-IN 48 HOURS AT 125ºC

BAKEOUT FOR QFP/VQFP INT

RAY

100% ELECTRICAL TEST AT

ROOM

•

TAPE AND REEL (OPTIONAL

FOR SOIC, QFP AND PLCC)

•

QC PRESHIP INSPECTION

BAKEOUT FOR QFP/VQFP IN

TRAY

PACK

•

TAPE AND REEL (OPTIONAL FOR

PLCC, QFP, SOIC)

PACK

ZAC03-0004

5- 4

ZiLOG

2002 Quality and Reliability Report

ATTACHMENT 3

GENERAL MATERIAL SPECIFICATION

MATERIAL

DIE ATTACH

EPOXY

Silver Filled Epoxy 1.0 - 1.3 mil Au

WIRE SIZE

MOLD

COMPOUND

EME6300H / HJ /

RQ

MARKING

PLATING

PDIP

Laser / Padmark 85/15 Tin Lead

EN4065D

84-1 LMIS

84-1 LMISR4

CRM 1033B

8390A

EME6600CS

EME6600

CEL4630 SXT / SX

CEL 4600P8/P8T

SDIP -

REGULAR

Silver Filled Epoxy 1.0 - 1.3 mil Au

EME6300H /HJ /RQ Laser / Padmark 85/15 Tin Lead

EN4065D

CEL4660 SXT

84-1 LMIS

84-1 LMISR4

CRM1033B

CEL4630 SXT / SX

EME6600CS

CEL4600P8/P8T

SDIP - MCM

PLCC

Silver Filled Epoxy 1.2 mil Au

8390A

DONG JIN 200NF Laser / Padmark 85/15 Tin Lead

Silver Filled Epoxy 1.0 - 1.3 mil Au

EN4065D

84-1 LMISR4

EME6300H

Laser / Padmark 85/15 Tin Lead

EME6600

EME6600CS

CEL 4630SX / SXT

CRM 1033B

SOIC

Silver Filled Epoxy 1.0 - 1.3 mil Au

84-1 LMISR4

MP AN 8000 AN

EME6300H

CRM1033D

CRM1033B

EME6600CS

EME6600

CEL4630SX / SXT

SSOP

Silver Filled Epoxy 1.0 - 1.2 mil Au MP AN 8000 AN

84-1 LMISR4

Laser/ Padmark 85/15 Tin Lead

Laser / Padmark 85/15 Tin Lead

EPTSSOP

QFP

Silver Filled Epoxy 1.2 mil Au

8290

7050B

Silver Filled Epoxy 1.0 - 1.3 mil Au

84-1 LMISR4

EN4065D

EME6300H / HJ

EME6600CS

EME6600H

CRM 1033B

EME7320CR

CEL4630SXT

TQFP/VQFP Silver Filled Epoxy 1.0 - 1.3 mil Au

EME7320CR

Laser / Padmark 85/15 Tin Lead

84-1 LMISR4

8360

CRM 1033B

ZAC03-0004

5- 5

ZiLOG

2002 Quality and Reliability Report

CHAPTER 6

The Handling and Storage

of Surface Mount Devices

1. Handling

Components should be handled with vacuum pick to ensure that coplanarity of leads is

maintained.

ZAC03-0004

6-1

ZiLOG

2002 Quality and Reliability Report

2. Lead Protection

Avoid sliding of units with leads in contact. The solder coating is prone to

contamination/scraping. If sliding cannot be avoided, the contact surface should be clean and

smooth.

3. ESD Protection

Observe ESD protection at all times. These are static sensitive devices.

ZAC03-0004

6-2

ZiLOG

2002 Quality and Reliability Report

4. Storage/Unpacking Caution

The plastic body of a surface mount product may be subjected to high temperatures during the

printed circuit board assembly operation. Any moisture that may be present in the plastic may

expand and damage the unit. Therefore, it is very important that the surface mount IC be dry

before the printed circuit board operation begins.

ZiLOG assures that the unit is thoroughly dry before final packing for shipment. The units are

shipped in a "dry pack" envelope designed to keep moisture away from the IC's. The user

should carefully observe the following practices to assure that the units remain moisture free at

the time of the printed circuit board soldering operation:

•

Do not open the dry pack until you are ready to solder. Product may be exposed to ambient

conditions of 30C/60%RH (or less) for no more than 168 hours. This corresponds to a

moisture sensitivity level of 3.

•

Unopened dry packs may be stored at <40^oC/90% RH.

When the dry pack must be opened for a short period of time (such as for incoming

inspection) it should be resealed as soon as possible, ensuring that the desiccant remains

inside the dry pack. Resealing should be done with heat seal for best closure of the bag.

•

If the units have been exposed to more than 168 hours at ambient conditions of

30C/60%RH(or less) or if the humidity indicator card in the bag shows humidity above

20%, devices should be baked for 8 hours at 125^oC, before board soldering.

5. Soldering

Recommended surface mount profile is as follows:

☛ Maximum 3^oC/sec. ramp up.

☛ Maximum 220^oC peak temp.

☛ Minimum 1 min. cool down from peak temp. to 50^oC.

6. Desoldering

Parts removed due to board assembly problems or suspected failure.

If boxed-in type desoldering fixture is used, the following are recommended operating

parameters:

☛ Package Temp: 220^oC max.

☛ Dwell Time: 1 min. max.

It is important that the above precautions are followed to ensure integrity of the packages.

ZAC03-0004

6-3

ZiLOG

2002Quality and Reliability Report

CHAPTER 7

Quality Systems

QUALITY SYSTEMS

•

Organization: Quality control departments are located at all plants

Equipment: Nampa and Manila can conduct failed material analysis including decapsulation,

SEM, microprobe, Emission microscope, X-Ray, EDX, cross-section and Sonoscan acoustic

microscope. See Table 3-1 for a complete list of QC test equipment.

SUBCONTRACTING: 100% of assembly is subcontracted.

LOT TRACEABILITY: There is complete lot traceability by product date code back through the

assembly process and wafer manufacturing process to the starting material.

AVAILABILITY OF DOCUMENTATION ON MONITORING: Documents are available in

either hard copy or electronic form (SOP0937).

QUALITY DATA:

•

Data availability: Outgoing quality is measured by the quality control acceptance/rejection data

and on each production lot which is reported on a PPM basis. In addition, ZiLOG cooperates

with certain customers who provide their incoming inspection data on a PPM basis for

correlation, per Procedures SOP0903 and SOP0927.

•

Mechanism of transfer: Hard copy/electronic

Details/attributes provided: PPM

Method of calculation: See Procedure SOP0927

ZAC03-0004

7 - 1

ZiLOG

2002Quality and Reliability Report

•

Current levels (by family/technology/package) per attribute: 30 PPM on mature products

(mature products defined as those which have transited the initial startup experience curve).

PPM detail is provided to the customer in ZiLOG's semi-annual quality and reliability report.

•

Goals for next three to five years: ZiLOG desires to have all mature products at better than 20

PPM during this period.

TESTING (QA/Operating)

•

Test program release procedure: ZiLOG has a formal test program review/release procedure,

per Procedures SOP1239.

Does QA sample test? Yes. Lots are sampled by QA using a statistically valid sampling plan.

If the QA sample fails, the entire lot is re-tested and a second QA sample is drawn.

Is datasheet tested or guaranteed? ZiLOG provides its product specifications to the customer in

a document called a data sheet (SOP0302). The product specification describes the attributes

that ZiLOG warrants.

•

Is the product tested at full temperature range? Yes

Is the product 100% electrically tested prior to QA? Yes

Does QA pull samples for both AC and DC Testing? Yes

How is propagation delay tested (e.g., simultaneous switching effect): Simultaneous

Fault coverage (Operating vs. QA): As close to 100% as practical

Coplanarity requirement on SMD: 4 mils maximum; reference the seating plane

Define failure: Does not meet specifications

TEST TAPE SUPPORT: Test tapes, load boards and documentation are available

WHAT HAPPENS WHEN FAILURES OCCUR?

•

Is sample truncated? No

Corrective action plan: Plant sample failure analysis overviewed by HQ R/QA

How is product segregated (i.e., is there protection from mixing)? Automatic binning during

electrical test is used to segregate product. Product traceability to the customer order is

maintained by a unique part numbering system (SOP0937 and SOP0902).

ZAC03-0004

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ZiLOG

2002Quality and Reliability Report

WHEN MANUFACTURING IS PERFORMED OFFSHORE, WHAT ARE THE

CONTROLS?:

Same as onshore; the Manila plant is monitored through the Inventory Activity Yield (IAY) data

collection system by the Director of Quality Assurance and Reliability on a contemporaneous basis,

as is the Nampa plant. Reporting is continuous. Periodic audits are performed on all offshore

facilities by ZiLOG personnel.

AVAILABILITY OF PROGRAMMING FACILITIES:

ZiLOG develops its own test programs with facilities located in Manila, Campbell and Nampa.

DOCUMENTATION CONTROL: (Include procedure for changes and updates.)

See Procedures SOP0922, SOP0901, and SOP0937. R/QA operates Document Control.

QA AUDIT:

•

Availability of audit reports: Serialized run sheets and audit checklists are maintained by the

Quality Control organization.

MATERIALS CONTROL: See Procedures SOP0811,SPOL025.

ZAC03-0004

7 - 3

ZiLOG

2002 Quality and Reliability Report

VENDOR OF THE YEAR AWARD:

ZiLOG has an aggressive commitment to the continuous improvement of the quality and reliability

of our products. This concern affects not only material produced, but all materials and/or services

procured by ZiLOG. Toward this end, ZiLOG has embarked on a program of ongoing vendor

reviews at each site. These reviews culminate in a Vendor of the Year Award(s) from each site.

VENDOR OF THE YEAR

Year

Winner

2002

Nampa, Idaho Site

Category 1 Silicon - LG Siltron

Category 1 Raw Materials - Arch Chemicals

Category 2 Raw Materials - Honeywell

Freight Carriers - Air Van North American

Contracted Services - Tri-State Electric

Year

Winner

2001

Nampa, Idaho Site

Category 1 Silicon - LG Siltron

Category 1 Raw Materials - Tosoh SMD

Category 2 Raw Materials - Microsil

Freight Carriers - Air Van North American

Contracted Services - Tri-State Electric

Year

Winner

2000

Nampa, Idaho Site

Category 1 Silicon - LG Siltron

Category 2 Raw Materials - Microsil

Logistics - Air Van North American

ZAC03-0004

7 - 1

ZiLOG

2002 Quality and Reliability Report

VENDOR OF THE YEAR

(Continued)

Year

Winner

Nampa, Idaho Site

1998/1999

1997

L.G. Electronics

Photronic Labs, Inc.

1996

1995

1994

Astra Microtronics (AMT)

Mitsubishi Silicon America

Thesys GmbH

1993

Kawasaki Steel Corporation

1992

1991

Schlumberger Technologies ATE Division

OCG/Olin Hunt

1990

Sumitomo

1989

Photronic Labs, Inc.

ZAC03-0004

7 - 2

ZiLOG

2002 Quality and Reliability Report

CHAPTER 8

Statistical Process Control

STATISTICAL PROCESS CONTROL

SCOPE:

All major manufacturing processes are under SPC control Process stability and capability analyses

are reported monthly.

A corporate-wide specification defines the scope of the program and provides detailed instructions

for implementing SPC at an operation. It also defines the frequency of evaluation of control limits,

training requirements, and responsibilities (SOP0918)

CONTROL CHARTS:

ZiLOG (Nampa) uses the 8-Point Zone Control Chart. The Zone Control Chart is easily adapted to

nonstandard distributions. All Technicians are certified on the use of the Zone Control Chart.

Control limits and out-of-control action plans are written into the process specifications. Control

limits are changed as process improvements are implemented.

DESIGN OF EXPERIMENTS:

New processes require rigorous qualification through one or more Statistical Design of

Experiments (SDE). Research is ongoing to improve the traditional SDE methodology.

ZAC03-0004

8 1

ZiLOG

2002 Quality and Reliability Report

CHAPTER 9

Document Control

DOCUMENT CONTROL SYSTEM

ZiLOG’s Document Control Department promotes reliability and quality through efficient, global

document management and revision control systems. The Document Control Department

maintains an electronic document management system that is accessible by ZiLOG employees

worldwide 24 hours a day. Manufacturing documents are available electronically for all wafer

foundry and assembly subcontractors. The system automatically manages revision control; ensuring

users have the most up-to-date version every time.

Corporate Document Control in Campbell, California, oversees the worldwide document

management processes for revision controlled documents. They are also responsible for managing

design, engineering and marketing documents and records as well as company-wide policies and

procedures. Document Control departments in Nampa, Idaho, and Manila, Philippines, manage the

manufacturing, assembly and test procedures and specifications.

Additional details regarding any of the sections contained in this document may be found in ZiLOG

policies, procedures or specifications. General categories are listed below. Please contact the

ZiLOG Director of Quality and Reliability with specific questions.

•

Corporate-Wide Policies

Standard Operating Procedures for Business Units, Corporate Communications, Finance,

Human Resources, Information Technology, Legal, Operations, Reliability and QA, Sales,

Strategy, Technology, Design & Test

•

Core Process Documents for all Phases of the Product Life Cycle

Product and Process Specific Manufacturing, Assembly and Test Procedures and

Specifications

ZAC03-0004

9- 1

ZiLOG

2002 Quality and Reliability Report

Document #

POL025

Document Title

Procurement Organization Roles And Responsibilities

Zilog Testing Policy

POL003

POL013

Tooling Revision Customer Qualification Policy

Manufacturing Management Fundamentals

CMOS D.C. Latch-Up Test Procedure

Electrostatic Discharge Procedure (Mil-Std)

POL031

QCC1425

QCC1478

SOP0302

SOP0811

SOP0817

SOP0901

SOP0902

SOP0903

SOP0906

SOP0908

SOP0913

SOP0916

SOP0918

SOP0922

SOP0923

SOP0925

SOP0927

SOP0932

SOP0936

SOP0937

SOP1233

Procedure For Administering A Technical Specification (CPS and/or DS)

Procedure For The Return of Purchased Material

Die and Wafer Procedure

Procedure For Submitting A Change Notice Form

Product Number Identity System

Quality And Reliability Program

EMC Testing Standards Procedure

Ship-To-Stock Procedure

Customer Notification Procedure

Fits Program Procedure

Statistical Process Control Procedure

Procedure For Creating Or Revising Policies Or Cross-Functional Procedures

Hast Testing Procedure

Military Group C And D Qualifications

PPM Measurement Program

Customer Order Reschedule And Cancellation Procedure

Product/Process Characterization Testing

Master Specification System Procedure

Procedure For Naming And Controlling Product Mask Step And Layer Revisions

ZAC03-0004

9- 2

ZiLOG

2002 Quality and Reliability Report

ATTACHMENT 6

Input

Product Demand

Wafer Fab

Foundry

ZiLOG, Nampa, ID

Wafer Probe

ZiLOG, Manila, PI

Subcontractor

Assembly

Subcontractor

Final Test

ZEPI

Final Test

Subcontractor

Ship to

Customer

ZAC03-0004

9- 3

ZiLOG

2002 Quality and Reliability Report

ATTACHMENT 7

SPC Fabrication

Typical Process

Thickness/

Critical

Dimension Concentration

Thickness

Particulate

Uniformity

Etch Rate

Barrier Oxidation

Silicon Nitride Deposition

N-Well Mask

SDG Mask

P Field Implant

Poly Mask

S/D Implant Mask

Source Drain Reoxidation

Contact Mask

Metal-I Mask

Spin on Glass

Final Inspect

Via Mask

Metal II Mask

Pad Mask

Pad Mask Pix

X

-

X

-

X

-

X

-

X

-

X

-

X

-

X

-

X

-

X

-

X

-

X

-

X

-

X

-

X

-

X

-

ZAC03-0004

9- 4

ZiLOG

2002 Quality and Reliability Report

CHAPTER 10

Thermal Properties

THERMAL CHARACTERISTICS

Calculation of Device Junction Temperature

Failure rates and Failures in Time (FITS) obtained from life test data are based on ambient

temperatures (TA), and are not corrected to junction temperature (TJ). However, when a significant

difference between TA and TJ exists, TJ can be incorporated into the Arrhenius Equation for

accelerated failure rates by using the following equations:

Junction Temp. (T_J):

where:

T_J= (θ_JA) (P_D) + T_A

θ_JAis the thermal resistance of junction with respect to ambient (C/W). P_Dis

the maximum power dissipation at T_Ain watts

and:

T_Ais the ambient temperature °C.

Case Temperature (T_C):

where:

Illustration:

T_C= T_J– (θ_JC) (P_D)

θ_JCis the thermal resistance of junction with respect to case.

In order to calculate junction temperature (T_J) and case temperature (T_C) for

static airflow for the Z86C04 in an 18L PDIP, we do the following:

1.

2.

At 25°C, maximum power dissipation for this device is 0.08 watts.

For our example, ambient temperature is denoted by T_Aand is assumed to be 25°C.

For the Z86C04 in plastic (copper); θ_JAand θ_JCare 75 and 18°C/watt respectively.

Therefore,

T_J= 75 x (0.08) + 25 = 31.2°C, and

T_C= 31.2 – (18 x 0.08) = 29.8°C

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

Table 11-1. Device θ_JA, θ_JCTable Summary Of Thermal Characteristics For

ZiLOG Plastic Packages

Package Type

Package Code

Lead Frame

θ_JA

θ_JC

PDIP

18L

P

75

60

43

42

40

38

42

18

12

11

8

Cu

20L

28L

40L

42L

48L

52L

8

64L

14

PLCC

44L

V

F

46

43

42

13

14

12

Cu

68L

84L

QFP

44L

45

43

38

10

16

17

Cu

80L

100L

VQFP

64L

A

S

70

19

25

Cu

100L

SOIC

8L

100

110

70

N/A

18L

Cu

20L

28L

75

60

SSOP

20L

HZ

75

60

45

18

12

Cu

28L

48L

EPT SSOP

28

HT

L

36

10

Cu

LCC

44L

53

48

40

7

10

6

52L

68L

ZAC03-0004

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ZiLOG

2002 Quality and Reliability Report

Table 11-2. Device θ_JA, θ_JCTable Summary Of Thermal Resistance For Hermetic

Packages

PBGA

256L

B

D

25

21

N/A

2 Layer

4 Layer

256L

CERDIP

28

52

41

32

14

11

5

40

48

Ceramic Side Braze

18

C

81

21

28

40

49

48

36

11

4

48

Ceramic Window

44L

K

G

32

36

3

6

Pin Grid Array

68L

Notes:

P=Plastic DIP

C=Ceramic DIP

D=Cerdip

L=LCC-Ceramic Leadless Chip Carrier

V=PLCC-Plastic Leaded Chip Carrier

F=QFP-Plastic Quad Flat Pack

A=VQFP-Very Small Quad Flat Pack

G=Ceramic Pin Grid Array

S=SOIC-Small Outline Integrated Circuit

B=PBGA-Plastic Ball Grid Array

HZ=SSOP-Shrink Small Outline Package

HT=EPT SSOP-Exposed Pad Thin SSOP

ZAC03-0004

10- 3

ZiLOG

2002 Quality and Reliability Report

CHAPTER 11

Glossary

TERM

Ǻ:

DEFINITION

Symbol for Angstrom, which equals 10^-10meters (one ten-billionth

of a meter).

A life test, in which the applied stress level exceeds that needed in

actual use in order to shorten the time required to observe failure. A

good accelerated test should not alter the basic modes and/or

mechanisms of failure.

Accelerated Life Test:

Acceleration Factor:

The ratio of the times needed to obtain the same failure rates under

two different sets of stress conditions involving the same failure

modes or mechanisms.

The energy level needed to activate a specific failure mechanism.

Activation Energy (Ae):

AES:

Auger Electron Spectroscopy typically used for interlayer

dielectrics and passivation films.

The operation of exposing a resist covered wafer in a projection

printer.

Align:

Atmospheric Pressure Chemical Vapor Deposition. One method for

deposition of glass used for interlayer or passivation dielectric.

APCVD:

Application Specific Standard Product.

ASSP:

AQL:

Acceptable Quality Level. Generally, 95 percent confidence that

material of the stated AQL will pass sample inspection.

The act of connecting package leads to specified locations on the

chip via fine wire.

Bonding:

Bond Pads:

Burn-In:

Exposed aluminum pads on a chip to which wires from the package

lead frame are bonded during assembly.

The operation of a device prior to its application, at elevated

temperature and/or voltage for a specific period of time. The

purpose is to stabilize the device characteristics, identify early

failures, and eliminate devices subject to infant mortality or

excessive parametric drift.

ZAC03-0004

11- 1

ZiLOG

2002 Quality and Reliability Report

TERM

DEFINITION

Boron doped Phosphosilicate Glass.

BPSG:

CD:

Critical Dimension.

Customer Failure Analysis/Correlation Request.

Certificate of Conformance.

CFA:

C of C:

CMOS:

Complementary MOS technology combining n and p transistors in

the same product. Advantages include low power dissipation.

A specialized statistical term which refers to the probability of a

statement being true.

Confidence:

Check:

A visual check done at the conclusion of a (dry or wet) masking

step.

One square on a wafer containing a single integrated circuit. The

substrate on which all active and passive components of a circuit

are fabricated; also called a die.

Chip:

The room in a chip fabrication plant in which wafers are processed.

This area features a controlled environment with filtered air that

eliminates essentially all dust and dirt.

Clean Room:

A connection between two conductive layers, e.g., metal-to-silicon

contact.

Contact:

A statistically defined limit which determines whether or not a

process has changed significantly as compared to past history. A

measure of statistical process control.

Control limit:

C-Mode Scanning Acoustic Microscope which examines packaged

units and produces high resolution, ultrasonic images.

C-SAM:

CVD:

Chemical Vapor Deposition of thin films. Gaseous reactants are

brought together over the silicon wafer, depositing required layers

typically used for interlayer dielectrics and passivation films.

Document Control.

DC:

Defense Electronic Supply Center.

Deionized water.

DESC:

DI:

Dual-in-Line Package.

Design Rule Check.

DIP:

DRC:

Device Under Test.

DUT:

A MOSFET with a permanently “on” channel; requires a negative

applied gate voltage to turn off (see “enhancement transistor”).

Depletion transistor:

ZAC03-0004

11- 2

ZiLOG

2002 Quality and Reliability Report

TERM

DEFINITION

A chemical process that solidifies photoresist where it has been

exposed and removes it elsewhere (for negative resist) or vice versa

(for positive resist).

Develop:

A visual check following dry masking to verify proper resist

patterning before etch, e.g., alignment and thickness are checked.

Develop inspect:

Die:

A single integrated circuit separated from the wafer on which it was

made; also called a chip.

The process of doping silicon by diffusing impurities from the

surface into the wafer at high temperature. Any region in the

silicon substrate doped by diffusion or by ion implant (e.g., source

and drain diffusions).

Diffusion:

Any impurity intentionally introduced into silicon to control its

electronic behavior (e.g., Boron, Arsenic, and Phosphorus).

Dopant:

Dose:

In ion implant, a measure of the amount of dopant implanted;

usually expressed in ions per square centimeter.

A highly doped region adjacent to a transistor currently carrying

channel. It carries electrons out of the transistor to the next circuit

element or conductor.

Drain:

A process segment where a photoresist is spun onto the wafer, soft

baked, exposed, and developed to obtain a desired pattern ready for

etch or implant (see "wet masking”).

Dry Masking:

EDX:

Energy Dispersive X-ray analysis. Normally uses electron beam

excitation in the scanning electron microscope.

Electrical overstress, common application failure mechanism.

Electrostatic discharge, common handling failure mechanism.

EOS:

ESD:

A MOSFET with a normally “off” channel; requires a positive

applied gate voltage to turn on (see “depletion transistor”).

Enhancement transistor:

The rate at which a given layer is etched off in a given standard

acid solution, expressed in Å/sec.

Etch rate:

Deposition technique for Aluminum, Gold, and Chromium thin

films.

Evaporation:

Expose a photoresist-coated wafer to light through a mask.

Field Application Engineer.

Expose:

FAE:

Measurement of assembled device performance. Products are

categorized by speed/power/performance criteria.

Final Test:

ZAC03-0004

11- 3

ZiLOG

2002 Quality and Reliability Report

TERM

DEFINITION

“Failure units” or “Failure in Time,” a measure of failure rate

defined as one failure in 10⁹, or one billion device hours.

FIT:

Finish Process Order. A lot traveler, which accompanies each lot

through the finish (Mark and Pack and FQA) areas.

FPO:

Field Quality Engineer.

The gate of a transistor.

FQE:

Gate:

Dielectric oxide between the gate and the channel region of a

transistor.

Gate oxide:

Devices similar in process or function. ZiLOG uses a generic

approach in its Reliability Program. Devices built in the same wafer

fab process and having similar complexity or function are grouped

into a “generic” product family. Data on any device within a family

is considered indicative of the performance of all other devices in

that group and process line.

Generic:

Trapping of contamination atoms (especially alkali ions) to prevent

their drift into device regions where they may affect electrical

performance.

Gettering:

The amorphous form of SiO₂, used in various insulating layers on

the wafer.

Glass:

A step following dry masking, where the resist is heated to prepare

it for wet etch.

Hard Bake:

Highly Accelerated Stress Test.

High Temperature Operating Life.

Integrated Circuit.

HAST:

HTOL:

IC:

Initial failure rate in life studies. It is followed by early failure

period and then final wear out portion of failure “bathtub” curve.

Infant Mortality:

Incoming Quality Control.

Kilo, thousand, 10³.

IQC:

K:

A magnified, physical representation of an electronic circuit at the

transistor level.

Layout:

Leadless Chip Carrier.

LCC:

The external connection to a packaged integrated circuit.

Lead:

A test for the purpose of estimating some characteristic(s) of a

device’s useful lifetime.

Life Test:

Large Scale Integration

LSI:

ZAC03-0004

11- 4

ZiLOG

2002 Quality and Reliability Report

TERM

DEFINITION

Low Pressure Chemical Vapor Deposition. Typical method for

deposition of glass used for interlayer or passivation dielectric.

LPCVD:

Low Temperature Oxide glass used for interlayer or passivation

dielectric. Typically deposited at the same temperature as APCVD

deposited glasses used for passivation, but at low pressure.

LTO glass:

Lot Tolerance Percent Defective. A sample plan that will reject 90

percent of the lots equal to or worse than the stated LTPD value.

LTPD:

Mask:

A pattern usually “printed” on glass, used to define areas of the

chip on the wafer for production purposes.

The lithography portion of the process or physical area where

lithography occurs.

Masking:

Million electron Volts.

MeV:

Milli electron Volts.

meV:

Manufacturing.

MFG:

Mil:

0.001 inch.

Military.

MIL:

Nampa Fabrication Module.

Metal Oxide Semiconductor integrated circuit technology.

Material Review Board.

Mod:

MOS:

MRB:

MTBF:

MTTF:

Nano:

Mean Time Between Failures.

Mean Time to Fail. Time to 50 percent Cumulative Fail.

10^–9.

A resist material in which unexposed areas are developed away.

National Institute of Standards and Technology.

Silicon Nitride, Si₃N₄.

Negative photoresist:

NIST:

Nitride:

NMOS:

Nm:

Ns:

OEM:

OTP:

N channel MOS technology.

Nanometer (1nm = 10A = 10^–9meters).

Nanoseconds (10^–9seconds).

Original Equipment Manufacturer.

One Time Programmable Product sold in plastic packaging. No

window is provided for UV erasure.

A process whereby thick oxide islands are grown between active

device regions for better isolation and performance.

“Oxi”:

ZAC03-0004

11- 5

ZiLOG

2002 Quality and Reliability Report

TERM

DEFINITION

A plasma deposited passivation or interlayer dielectric film

consisting of silicon, oxygen, and nitrogen.

Oxynitride:

Phosphorous.

P:

Plastic Dual In-Line Package.

Product Engineer.

PDIP:

PE:

Plasma Enhanced Chemical Vapor Deposition.

Pin Grid Array (package).

PECVD:

PGA:

PLCC:

PM:

POA:

PPM:

Plastic Leaded Chip Carriers.

Procedural Manual that contains ZiLOG’s policies and procedures.

Point of Acceptance.

PPM Quality Data, Parts per Million defective; 1000 PPM = 0.1

percent defective.

Pressure Pot.

PPOT:

PROM:

PSG:

Programmable Read Only Memory.

Phosphosilicate Glass. A glass containing phosphorus (in the form

of P₂0₅). LTO, Pyrox and Pyroglass are all types of PSG.

The container used to hold an active semiconductor device.

Package:

The portion of the process involving the use of light sensitive

photoresist material for layer definition.

Photolithography:

(1) A patterned chrome on glass photographic plate used to transfer

a pattern to photo-resist in dry masking. (2) A process segment

involving the patterning of a given layer by use of a photomask.

Photomask:

Photoresist:

A light sensitive polymer material which is used as a mask for

etching and ion implant steps. See also Negative and Positive

Photoresist.

A process using a gas transformed by an RF field into a reactive

plasma.

Plasma ash:

Plasma deposition:

Plasma etch:

Poly:

Deposition of thin films using gaseous reactants in the presence of

a plasma for lower temperatures.

An etching process using a gas transformed by an RF field into a

reactive plasma.

Polycrystalline silicon made up of many tiny crystals (as opposed

to single crystal silicon.

ZAC03-0004

11- 6

ZiLOG

2002 Quality and Reliability Report

TERM

DEFINITION

Oxidation of the poly after it has been defined. The re-ox provides

the interpoly di-electric in a double (two layer) poly process.

Poly Re-ox:

A photosensitive organic polymer material in which exposed areas

are developed away.

Positive photoresist:

Prebake:

First step of dry masking, in which the wafers are dried in an oven

prior to resist application.

The first electrical test of processed wafers.

Probe:

The profile displayed by the process evaluation parameters, which

are automatically recorded from the test patterns on wafers as they

proceed through the production line.

Process Templating:

A machine which projects the photomask onto the resist-coated

wafer. The mask is the same size as the wafer and imaged 1:1 on

the wafer.

Projection Aligner:

Pyrox:

A type of phosphosilicate glass containing approximately 4.5 wt

Phosphorous.

Quality Assurance.

QA:

Quality Engineer.

QE:

Product or Process Qualification Report (XXXX = report number).

QR-XXXX:

RBS:

Rutherford Back Scattering. A method for non-destructive depth

profile analysis of thin films by back scattering of high-energy

helium ions.

Reliability Engineer.

RE:

Residual Gas Analysis.

Quad Flat Package.

RGA:

QFP:

Quality Improvement Process.

Quality and Reliability.

Relative Humidity.

QIP:

Q&R:

RH:

Reactive Ion Etch.

RIE:

Return Material Authorization.

Read Only Memory.

RMA:

ROM:

Refractive Index:

A basic physical property which determines the extent of light

bending (refraction) upon entering the surface. Used in thin film

process control as an indirect measure of chemistry.

See Photoresist.

Resist:

ZAC03-0004

11- 7

ZiLOG

2002 Quality and Reliability Report

TERM

DEFINITION

Statistical Design of Experiments.

SDE:

SEM:

Scanning Electron Microscope. A microscope which makes use of

a scanning beam of electrons to image detail less than 100A in size

(surface only).

Secondary Ion Mass Spectroscopy.

SIMS:

Special Lot. ZiLOG identification used to identify products

designed to unique customer requirements.

SL-Lot:

Statistical Process Control.

SPC:

Ship-to-Stock. Eliminates need for customer IQC.

STS:

Metallic element which forms the substrate in most semiconductor

devices.

Silicon:

A step preparing freshly spun photoresist for exposure by baking it

in an oven (to remove excess solvent).

Soft bake:

Small Outline Integrated Circuit package.

SOIC:

Equivalent to the drain of a transistor with the exception that

electrons leave the source into the channel of the active device.

Source:

Absolute acceptable limit for a process parameter.

Spec. Limit:

Spin:

A process step which coats a spinning wafer with liquid photoresist

by dispensing the liquid onto its center.

Deposition of a metal layer by bombarding a metal target with

heavy ions from a gaseous (e.g., argon) plasma. Metal atoms are

removed from the target and deposited onto the wafer during this

process.

Sputtering:

Technology Development.

TD:

Time Dependent Dielectric Breakdown.

TDDB:

TEM:

Transmission Electron Microscope. A microscope used to obtain

high-resolution images with a transmitted electron beam by

electron lens imaging rather than scanning.

Temperature Humidity Bias (85°C/85% RH).

Thin small outline package.

THB:

TSOP:

Special electrical test structures included on production device

wafers for monitoring critical parameters.

Test patterns:

A high quality Si_O2layer grown by oxidizing the silicon in a

furnace (as opposed to externally deposited glass).

Thermal oxide:

UL:

Underwriters Laboratory.

ZAC03-0004

11- 8

ZiLOG

2002 Quality and Reliability Report

TERM

DEFINITION

Ultra Violet.

UV:

V/I:

A monitor measuring voltage and current between probes applied

to a semiconductor layer. Measures layer resistivity.

A check of process quality by examination of wafers under a light

microscope.

Visual:

Very Large Scale Integration.

VLSI:

VQFP:

Vt:

Very small Quad Flat Pack package.

Transistor threshold voltage. Voltage at which the transistor turns

on.

A thin piece of silicon sliced from a cylinder shaped crystal. It is

polished so that the surface is like a mirror. It is most commonly

found in 4, 5, and 6-inch diameters. The wafer is the base material

for most of the world’s integrated circuits.

Wafer:

A flat area ground onto the original silicon ingot from which the

wafers are sliced. Gives crystallographic orientation.

Wafer flat:

The technique of testing a circuit at different levels of the

manufacturing process, to insure above marginal product

performance and compliance.

Waterfall Guardbanding:

Process segment following “dry masking” in which the wafer,

covered with the resist pattern, is etched to transfer the resist

pattern to the wafer. The resist is then removed (includes wet

and/or plasma etching).

Wet masking:

Etching in a liquid acid or solution.

Wet etch:

The process of connecting thin wires from the chip’s bond pads to

the package lead. (This is done at assembly.)

Wire bonding:

Zero Defects.

ZD:

ZiLOG Electronics Philippines, Inc.

ZiLOG Corporate Headquarters, San Jose, California.

ZEPI:

ZUS:

ZAC03-0004

11- 9


型号：	Z0803008DEA
厂家：	ZILOG, INC.
描述：	Micro Peripheral IC, MOS, CDIP40, CD
文件：	总98页 (文件大小：623K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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