S3F82NB_技术文档

S3 Family 8-Bit Microcontrollers

S3F82NB

Product Specification

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P R E L I M I N A R Y

www.zilog.com

S3F82NB

Product Specification

ii

DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.

Warning:

LIFE SUPPORT POLICY

ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE

SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF

THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.

As used herein

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)

support or sustain life and whose failure to perform when properly used in accordance with instructions for

use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti-

cal component is any component in a life support device or system whose failure to perform can be reason-

ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

Document Disclaimer

or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES

NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE

INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO

DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED

IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED

HEREIN OR OTHERWISE. The information contained within this document has been verified according

to the general principles of electrical and mechanical engineering.

S3 and Z8 are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the

property of their respective owners.

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S3F82NB

Product Specification

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Revision History

Each instance in this document’s revision history reflects a change from its previous edi-

tion. For more details, refer to the corresponding page(s) or appropriate links furnished in

the table below.

Revision

Date Level

Description

Page

Aug

2013

01

Original Zilog issue. A table of contents and PDF bookmarks will appear in the All

next edition, due to be published on or before Winter 2013.

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Revision History

S3F82NB

Product Specification

1

PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLERS

Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range

of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are:

— Efficient register-oriented architecture

— Selectable CPU clock sources

— Idle and Stop power-down mode release by interrupts

— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more

interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to

specific interrupt levels.

S3F82NB MICROCONTROLLER

The S3F82NB single-chip CMOS microcontrollers

are fabricated using the highly advanced CMOS

process, based on Samsung’s newest CPU

architecture.

— One 8-bit timer/counter and One 16-bit

timer/counter with selectable operating modes

— Watch timer for real time

— LCD Controller/driver

The S3F82NB is a microcontroller with a 64K-byte

Flash ROM embedded.

— A/D converter with 8 selectable input pins

— Synchronous SIO modules

— Comparator

Using a proven modular design approach, Samsung

engineers have successfully developed the

S3F82NB by integrating the following peripheral

modules with the powerful SAM8 core:

They are currently available in 128-pin QFP package

— Eleven programmable I/O ports, including ten 8-

bit ports, and one 3-bit port, for a total of 83 pins

— Twelve bit-programmable pins for external

interrupts

— One 8-bit basic timer for oscillation stabilization

and watchdog functions (system reset)

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FEATURES

CPU

Watch Timer

•

Interval time: 3.91mS, 0.125S, 0.25S, and 0.5S

at 32.768 kHz

0.5/1/2/4 kHz Selectable buzzer output

•

SAM88 RC CPU core

Memory

•

Program Memory (ROM)

LCD Controller/Driver

- 64K ꢀ 8 bits program memory

- Internal flash memory (program memory)

•

80 segments and 16 common terminals

1/8 and 1/16 duty selectable

Internal resistor bias selectable

˲

Sector size: 128 bytes

10 years data retention

Fast programming time:

User program and sector erase available

Endurance: 10,000 erase/program cycles

External serial programming support

Expandable OBP^TM(on board program)

sector

16 level LCD contrast control by software

Analog to Digital Converter

•

8-channel analog input

10-bit conversion resolution

25uS conversion time

•

Data Memory (RAM)

- Including LCD display data memory

- 4,112 ꢀ 8 bits data memory

8-bit Serial I/O Interface

•

8-bit transmit/receive mode

8-bit receive mode

LSB-first or MSB-first transmission selectable

Internal or External clock source

Instruction Set

•

78 instructions

Idle and stop instructions added for power-down

modes

Comparator

•

3-Channel mode: Internal reference (4-bit

resolution); 16-step variable reference voltage

2-Channel mode: External reference

83 I/O Pins

•

I/O: 19 pins (Sharing with other signal pins)

I/O: 64 pins (Sharing with LCD signal outputs)

•

Low Voltage Reset (LVR)

Interrupts

•

Criteria voltage: 2.0V

En/Disable by smart option (ROM address: 3FH)

•

8 interrupt levels and 19 interrupt sources

Fast interrupt processing feature

Two Power-Down Modes

8-Bit Basic Timer

•

Idle: only CPU clock stops

Stop: selected system clock and CPU clock stop

•

Watchdog timer function

4 kinds of clock source

Oscillation Sources

8-Bit Timer/Counter 0

•

Crystal, ceramic, or RC for main clock

•

Programmable 8-bit internal timer

External event counter function

PWM and capture function

•

Main clock frequency: 0.4 MHz ꢁ 12.0 MHz

32.768 kHz crystal oscillation circuit for

sub clock

Timer/Counter 1

Instruction Execution Times

•

Programmable 16-bit internal timer

Two 8-bit timer/counters A/B mode

PWM and capture function

•

333nS at 12.0 MHz fx (minimum)

122.1uS at 32.768 kHz fxt (minimum)

External event counter function

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FEATURES (Continued)

Operating Voltage Range

Smart Option

•

Low Voltage Reset (LVR) enable/disable and

AV_REFor P1.0/INT0 selection are at your

hardwired option (ROM address 3FH)

•

1.8 V to 5.5 V at 0.4 ꢁ 4.2 MHz

2.2 V to 5.5 V at 0.4 ꢁ 12.0 MHz

Operating Temperature Range

ꢁꢂ40ꢃC to + 85ꢃC

•

ISP related option selectable

(ROM address 3EH)

•

Package Type

128-QFP-1420

•

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4

BLOCK DIAGRAM

XTIN

XOUT

XIN

XTOUT

Main OSC.

Sub OSC.

Watchdog

Timer

Basic Timer

Port 10

P10.0-P10.7/SEG24-SEG31

P9.0-P9.7/SEG32-SEG39

P8.0-P8.7/SEG40-SEG47

P7.0-P7.7/SEG48-SEG55

P6.0-P6.2/CIN1-CIN2

Low Voltage

Reset

Port 9

Port 8

Port 7

Port 6

Port I/O and Interrupt Control

T0CLK/AD1/P0.1

T0OUT/T0PWM/T0CAP/AD3/P0.3

8-Bit

Timer/Counter0

8-Bit TimerA

8-Bit TimerB

T1CLK/AD0/P0.0

T1OUT/T1PWM/T1CAP/AD2/P0.2

BUZ/INT4/P1.4

Watch Timer

10-bit ADC

Comparator

SAM88RC CPU

AD0-AD7/P0.0-P0.7

AVREF/INT0/P1.0

P5.0/SEG80

P5.1/SEG81

P5.2/SEG82

CIN0/P6.0

CIN1/P6.1

CIN2/P6.2

P5.3/SEG83

Port 5

P5.4/SEG84/INT8

P5.5/SEG85/INT9

P5.6/SEG86/INT10

P5.7/SEG87/INT11

SCK/INT7/P1.7

SO/INT6/P1.6

SI/INT5/P1.5

SIO

P4.0-P4.7/SEG72-SEG79

P3.0-P3.7/SEG64-SEG71

P2.0-P2.7/SEG56-SEG63

Port 4

Port 3

Port 2

64 K-byte

ROM

4,112 byte

Register File

VLC0-VLC4

COM0-COM7

COM8-COM15/SEG0-SEG7

SEG8-SEG55

SEG56-SEG87/P3.0-P5.7

LCD

Controller/

Driver

P0.0/AD0/T1CLK

P0.1/AD1/T0CLK

P1.0/INT0/VREF

P1.1/INT1

P0.2/AD2/T1OUT/T1PWM/T1CAP

P0.3/AD3/T0OUT/T0PWM/T0CAP

P0.4/AD4

P1.2/INT2

P1.3/INT3

Port 0

Port 1

P1.4/INT4/BUZ

P1.5/INT5/SI

P1.6/INT6/SO

P1.7/INT7/SCK

P0.5/AD5

P0.6/AD6

VDD

VSS

nRESET

TEST

P0.7/AD7

Figure 1-1. Block Diagram

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PIN ASSIGNMENT

COM9/SEG1

1

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

P10.4/SEG28

P10.5/SEG29

P10.6/SEG30

P10.7/SEG31

P9.0/SEG32

P9.1/SEG33

P9.2/SEG34

P9.3/SEG35

P9.4/SEG36

P9.5/SEG37

P9.6/SEG38

P9.7/SEG39

P8.0/SEG40

P8.1/SEG41

P8.2/SEG42

P8.3/SEG43

P8.4/SEG44

P8.5/SEG45

P8.6/SEG46

P8.7/SEG47

P7.0/SEG48

P7.1/SEG49

P7.2/SEG50

P7.3/SEG51

P7.4/SEG52

P7.5/SEG53

P7.6/SEG54

P7.7/SEG55

P2.0/SEG56

P2.1/SEG57

P2.2/SEG58

P2.3/SEG59

P2.4/SEG60

P2.5/SEG61

P2.6/SEG62

P2.7/SEG63

P3.0/SEG64

P3.1/SEG65

COM8/SEG0

2

COM7

3

COM6

4

COM5

5

COM4

6

COM3

7

COM2

8

COM1

9

COM0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

VLC4

VLC3

VLC2

VLC1

VLC0

P1.7/SCK/INT7

P1.6/SO/INT6

P1.5/SI/INT5

P1.4/BUZ/INT4

S3F82NB

VDD

128-QFP-1420

VSS

XOUT

XIN

TEST

XTIN

XTOUT

nRESET

P1.3/INT3

P1.2/INT2

P1.1/INT1

P1.0/AVREF/INT0

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/T0OUT/T0PWM/T0CAP/AD3

P0.2/T1OUT/T1PWM/T1CAP/AD2

P0.1/T0CLK/AD1

Figure 1-2. S3F82NB Pin Assignments (128-QFP-1420)

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PIN DESCRIPTIONS

Table 1-1. S3F82NB Pin Descriptions

Names

Type

Description

Circuit

Type

Numbers

Share

Pins

P0.0

I/O I/O port with 1-bit-programmable pins;

Input (P0.0 and P0.1: Schmitt trigger

input) or push-pull, open-drain output and

software assignable pull-ups.

F-4

39

38

AD0/T1CLK

AD1/T0CLK

P0.1

P0.2

F-3

37

AD2/T1OUT/

T1PWM/T1CAP

AD3/T0OUT/

T0PWM/T0CAP

AD4–AD7

P0.3

36

P0.4–P0.7

P1.0

35–32

31

INT0/ AV

REF

I/O I/O port with 1-bit-programmable pins;

Schmitt trigger Input or push-pull, open-

drain output and software assignable pull-

ups.

E-5

E-4

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

30

29

28

19

18

17

16

INT1

INT2

INT3

Alternately used for external interrupt

input (noise filters, interrupt enable and

pending control).

INT4/BUZ

INT5/SI

INT6/SO

INT7/SCK

The P1.0 is configured as one of the

P1.0/INT0 and AV

by “Smart option”.

REF

P2.0–P2.7

P3.0–P3.7

P4.0–P4.7

P5.0–P5.3

P5.4–P5.7

I/O I/O port with 1-bit-programmable pins;

Input or push-pull, open-drain output and

software assignable pull-ups.

H-8

H-9

74–67

66–59

58–51

50–47

46–43

SEG56–SEG63

SEG64–SEG71

SEG72–SEG79

SEG80–SEG83

I/O I/O port with 1-bit-programmable pins;

Input or push-pull, open-drain output and

software assignable pull-ups.

I/O I/O port with 1-bit-programmable pins;

Input or push-pull, open-drain output and

software assignable pull-ups.

I/O I/O port with 1-bit-programmable pins;

Input or push-pull, open-drain output and

software assignable pull-ups.

I/O I/O port with 1-bit-programmable pins;

Schmitt trigger Input or push-pull, open-

drain output and software assignable pull-

ups.

SEG84–SEG87

INT8–INT11

Alternately used for external interrupt

input (noise filters, interrupt enable and

pending control).

P6.0–P6.1

P6.2

I/O I/O port with 1-bit-programmable pins;

Schmitt trigger Input or push-pull output

and software assignable pull-ups.

H-26

H-27

42–41

40

CIN0–CIN1

CIN2

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Table 1-1. S3F82NB Pin Descriptions (Continued)

Names

Type

Description

Circuit

Type

Numbers

Share

Pins

P7.0–P7.7

P8.0–P8.7

P9.0–P9.7

P10.0–P10.7

I/O I/O port with 4-bit-programmable pins;

Input or push-pull output and software

assignable pull-ups.

H-10

82–75

90–83

98–91

106–99

SEG48–SEG55

SEG40–SEG47

SEG32–SEG39

SEG24–SEG31

I/O I/O port with 4-bit-programmable pins;

Input or push-pull output and software

assignable pull-ups.

I/O I/O port with 4-bit-programmable pins;

Input or push-pull output and software

assignable pull-ups.

I/O I/O port with 4-bit-programmable pins;

Input or push-pull output and software

assignable pull-ups.

COM0–COM7

COM8–COM15

O

LCD common signal output.

H-4

10–3

–

2–123

SEG0–SEG7

SEG8–SEG23

O

LCD segment signal output.

2–123

122–107

COM8–COM15

–

SEG24–SEG31

SEG32–SEG39

SEG40–SEG47

SEG48–SEG55

I/O

H-10

106–99

98–91

90–83

82–75

P10.0–P10.7

P9.0–P9.7

P8.0–P8.7

P7.0–P7.7

SEG56–SEG63

SEG64–SEG71

SEG72–SEG79

SEG80–SEG83

H-8

H-9

74–67

66–59

58–51

50–47

P2.0–P2.7

P3.0–P3.7

P4.0–P4.7

P5.0–P5.3

SEG84–SEG87

46–43

P5.4–P5.7/

INT8–INT11

V

– V

–

LCD power supply pins.

–

15–11

–

LC0 LC4

AD0

AD1

I/O A/D converter analog input channels.

F-4

39

38

P0.0/T1CLK

P0.1/T0CLK

AD2

F-3

37

P0.2/T1OUT/

T1PWM/T1CAP

P0.3/T0OUT/

T0PWN/T0CAP

P0.4–P0.7

AD3

36

AD4–AD7

35–32

31

AV

–

A/D converter reference voltage.

The AV is configured as one of the

E-5

P1.0/INT0

REF

P1.0/INT0 and AV

option”.

by “Smart

REF

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Table 1-1. S3F82NB Pin Descriptions (Continued)

Circuit

Type

Share

Pins

Names

Type

Description

Numbers

42–41

40

3-channel comparator input

CIN0, CIN1: comparator input only

CIN2: comparator input or external

reference input.

CIN0–CIN1

CIN2

I/O

H-26

H-27

P6.0–P6.1

P6.2

SCK

I/O Serial interface clock.

E-4

F-3

16

17

18

19

36

P1.7/INT7

P1.6/INT6

P1.5/INT5

P1.4/INT4

SO

I/O Serial interface data output.

I/O Serial interface data input.

I/O Output pin for buzzer signal.

I/O Timer 0 clock output and PWM output.

SI

BUZ

T0OUT/T0PWM

P0.3/AD3/

T0CAP

I/O Timer 0 capture input.

F-3

36

P0.3/AD3/

T0OUT/T0PWM

T0CLK

I/O Timer 0 external clock input.

F-4

F-3

38

37

P0.1/AD1

T1OUT/T1PWM

I/O Timer 1 clock output and PWM output.

P0.2/AD2/

T1CAP

I/O Timer 1 capture input.

F-3

37

P0.2/AD2/

T1OUT/T1PWM

T1CLK

INT0

I/O Timer 1 external clock input.

F-4

E-5

39

31

P0.0/AD0

P1.0/AV

REF

I/O External interrupts input pins.

The INT0 is configured as one of the

INT1–INT3

INT4

E-4

30–28

19

P1.1–P1.3

P1.4/BUZ

P1.5/SI

P1.6/SO

P1.7/SCK

P1.0/INT0 and AV

option”.

by “Smart

REF

INT5

18

INT6

17

INT7

16

P5.4–P5.7/

SEG84–SEG87

INT8–INT11

H-9

46–43

nRESET

I

System reset pin

B

–

27

–

X

–

Main oscillator pins.

23

22

IN

OUT

XT

–

I

Crystal oscillator pins for sub clock.

–

25

26

–

IN

OUT

TEST

Test input: it must be connected to

24

V

SS

V

–

Power supply input pins.

Ground pins.

–

20

21

–

DD

V

SS

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9

PIN CIRCUITS

V

DD

V

DD

P-Channel

N-Channel

Pull-up

Resistor

In

Schmitt Trigger

Figure 1-3. Pin Circuit Type A

Figure 1-4. Pin Circuit Type B

VDD

P-Channel

N-Channel

Data

Output

DIsable

Figure 1-5. Pin Circuit Type C

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VDD

Pull-up

Resistor

VDD

Open drain

Enable

Resistor

Enable

P-CH

N-CH

Data

I/O

Output

Disable

Alternative

Function

Data

ADCEN

ADC Select

To ADC

Figure 1-6. Pin Circuit Type F-3 (P0.2-P0.7)

VDD

Pull-up

Resistor

VDD

Open drain

Enable

Resistor

Enable

P-CH

N-CH

Data

I/O

Output

Disable

Schmitt Trigger

Figure 1-7. Pin Circuit Type E-4 (P1 except P1.0)

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VDD

Pull-up

Resistor

VDD

Open drain

Enable

Resistor

Enable

P-CH

N-CH

Data

MUX

I/O

Output

Disable

Smart Option

Schmitt Trigger

AVREF

Figure 1-8. Pin Circuit Type E-5 (P1.0)

VDD

Pull-up

Resistor

VDD

Open drain

Enable

Resistor

Enable

P-CH

N-CH

Data

I/O

Output

Disable

Alternative

Function

Data

ADCEN

ADC Select

To ADC

Figure 1-9. Pin Circuit Type F-4 (P0.0 – P0.1)

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VLC0

VLC1

VLC2

COM/SEG

Out

Output

Disable

VLC3

VLC4

VSS

Figure 1-10. Pin Circuit Type H-4

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VDD

Pull-up

Resistor

VDD

Resistor

Enable

Open Drain

Data

P-CH

I/O

Output

Disable1

N-CH

SEG

Circuit

Type H-4

Output

Disable2

Figure 1-11. Pin Circuit Type H-8 (P2–P4, P5.0–P5.3)

VDD

Pull-up

Resistor

VDD

Resistor

Enable

Open Drain

Data

P-CH

I/O

Output

Disable1

N-CH

SEG

Circuit

Type H-4

Output

Disable2

Figure 1-12. Pin Circuit Type H-9 (P5.4–P5.7)

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VDD

Pull-up

Resistor

VDD

Resistor

Enable

P-CH

Data

I/O

Output

Disable1

N-CH

SEG

Circuit

Type H-4

Output

Disable2

Figure 1-13. Pin Circuit Type H-10 (P7–P10)

VDD

Pull-up

Resistor

Pull-up

Enable

Data

Output

Disable

CIRCUIT

TYPE C

I/O

Analog

Input SEL

Digital In

Analog In

Figure 1-14. Pin Circuit Type H-26 (P6.0–P6.1)

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VDD

Pull-up

Resistor

Enable

Data

Output

Disable

CIRCUIT

TYPE C

I/O

Analog

Input SEL

Digital In

External

REF SEL

Analog In

External

VREF In

Figure 1-15. Pin Circuit Type H-27 (P6.2)

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2

ADDRESS SPACES

OVERVIEW

The S3F82NB microcontroller has two types of address space:

— Internal program memory (ROM)

— Internal register file

A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and

data between the CPU and the register file.

The S3F82NB has an internal 64-Kbyte Flash ROM.

The 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing

modes.

A 176-byte LCD display register file is implemented.

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Product Specification

17

PROGRAM MEMORY (ROM)

Program memory (ROM) stores program codes or table data. The S3F82NB has 64K bytes internal Flash

program memory.

The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this

address range can be used as normal program memory. If you use the vector address area to store a program

code, be careful not to overwrite the vector addresses stored in these locations.

The ROM address at which a program execution starts after a reset is 0100H in the S3F82NB.

The reset address of ROM can be changed by a smart option only in the S3F82NB (Full-Flash Device). Refer to

the chapter 18. Embedded Flash Memory Interface for more detail contents.

(Decimal)

65,535

(Hex)

FFFFH

64K-bytes

Internal

Program

Memory Area

8FFH

FFH

Available

ISP Sector Area

255

0

Interrupt Vector Area

Smart Option

3FH

3CH

00H

Figure 2-1. Program Memory Address Space

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18

SMART OPTION

ROM Address: 003EH

.5 .4 .3 .2

MSB

.7

.6

.1

.0

LSB

Not used

ISP protection size selection bits:(4)(5)

00 = 256 bytes

ISP reset vector change selection

bit:(1)

0 = OBP reset vector address

1 = Normal vector (address 0100H)

01 = 512 bytes

10 = 1024 bytes

11 = 2048 bytes

ISP reset vector address selection bits:(2)

00 = 200H(ISP area size: 256 byte)

01 = 300H(ISP area size: 512 byte)

10 = 500H(ISP area size: 1024 byte)

11 = 900H(ISP area size: 2048 byte)

ISP protection enable/disable bit:(3)

0 = Enable (not erasable by LDC)

1 = Disable (Erasable by LDC)

ROM Address: 003FH

.5 .4 .3 .2

MSB

.7

.6

.1

.0

LSB

AVREF or P1.0/INT0 selection bit:

0 = AVREF

1 = P1.0/INT0

LVR enable/disable bit

(Criteria Voltage: 2.0V)

0 = Disable LVR

These bits should be

always logic "111111b".

1 = Enable LVR

ROM Address: 003CH

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used

ROM Address: 003DH

.5

.4

.3

.2

.0

LSB

Not used

NOTES:

1. By setting ISP reset vector change selection bit (3E.7) to '0', user can have the available ISP area.

If ISP reset vector change selection bit (3EH.7) is '1', 3EH.6 and 3EH.5 are meaningless.

2. If ISP reset vector change selection bit (3EH.7) is '0', user must change ISP reset vector address from

0100H to some address which user want to set reset address (0200H, 0300H, 0500H or 0900H).

If the reset vector address is 0200H, the ISP area can be assigned from 0100H to 01FFH (256bytes).

If 0300H, the ISP area can be assigned from 0100H to 02FFH (512bytes). If 0500H, the ISP area can

be assigned from 0100H to 04FFH (1024bytes). If 0900H, the ISP area can be assigned from 0100H

to 08FFH (2048bytes).

3. If ISP protection enable/disable bit is '0', user can't erase or program the ISP area selected by 3EH.1

and 3EH.0 in flash memory.

4. User can select suitable ISP protection size by 3EH.1 and 3EH.0. If ISP protection enable/disable bit

(3EH.2) is '1', 3EH.1 and 3EH.0 are meaningless.

5. After selecting ISP reset vector address in selecting ISP protection size, don't select upper than ISP

area size.

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Figure 2-2. Smart Option

S3F82NB

Product Specification

19

Smart option is the ROM option for start condition of the chip. The ROM address used by smart option is from

003CH to 003FH. The S3F82NB only use 003EH to 003FH.

When any values are written in the Smart Option area (003CH-003FH) by LDC instruction, the data of the area

may be changed but the Smart Option is not affected. The data for Smart Option should be written in the Smart

Option area (003CH-003FH) by OTP/MTP programmer (Writer tools).

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S3F82NB

Product Specification

20

REGISTER ARCHITECTURE

In the S3F82NB implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set

1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1),

and the lower 32-byte area is a single 32-byte common area.

In case of S3F82NB the total number of addressable 8-bit registers is 4,193. Of these 4,193 registers, 13 bytes

are for CPU and system control registers, 68 bytes are for peripheral control and data registers, 16 bytes are used

as a shared working registers, and 4,096 registers are for general-purpose use, page 0-page15 (including 176

bytes for LCD display registers and 1 byte for peripheral control register).

You can always address set 1 register locations, regardless of which of the ten register pages is currently

selected. Set 1 locations, however, can only be addressed using register addressing modes.

The extension of register space into separately addressable areas (sets, banks, and pages) is supported by

various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer

(PP).

Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2-1.

Table 2-1. S3F82NB Register Type Summary

Register Type

Number of Bytes

General-purpose registers (including the 16-byte common working register

area, sixteen 192-byte prime register area (including LCD data registers

and peripheral control register), and sixteen 64-byte set 2 area)

CPU and system control registers

4,112

13

68

Mapped clock, peripheral, I/O control, and data registers

Total Addressable Bytes

4,193

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21

Page 15

Page 14

FFH

Set1

Page 13

Bank 1

FFH

Page 3

Page 2

Page 1

Page 0

FFH

Bank 0

System and

32

Bytes

Peripheral Control

System and

Registers

Peripheral Control

Registers

Set 2

(Register Addressing Mode)

E0H

DFH

64

Bytes

General-Purpose

Data Registers

System Registers

256

Bytes

(Register Addressing Mode)

D0H

CFH

(Indirect Register,

Indexed Mode, and

Stack Operations)

General Purpose Register

(Register Addressing Mode)

C0H

BFH

Page 0

B0H

Page 15

Peripheral Control Register

(All addressing modes)

~

1 Byte

AFH

~

Prime

Data Registers

~

192

Bytes

~

Prime

Data Registers

(All addressing modes)

LCD Display Reigster

176

(All Addressing

Modes)

Bytes

00H

Figure 2-3. Internal Register File Organization (S3F82NB)

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S3F82NB

Product Specification

22

REGISTER PAGE POINTER (PP)

The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using

an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the

register page pointer (PP, DFH). In the S3F82NB microcontroller, a paged register file expansion is implemented

for LCD data registers, and the register page pointer must be changed to address other pages.

After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always

"0000", automatically selecting page 0 as the source and destination page for register addressing.

Register Page Pointer (PP)

DFH ,Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Destination register page selection bits: Source register page selection bits:

0000 Destination: Page 0

0001 Destination: Page 1

0010 Destination: Page 2

0011 Destination: Page 3

0100 Destination: Page 4

0101 Destination: Page 5

0110 Destination: Page 6

0111 Destination: Page 7

1000 Destination: Page 8

1001 Destination: Page 9

1010 Destination: Page 10

1011 Destination: Page 11

1100 Destination: Page 12

1101 Destination: Page 13

1110 Destination: Page 14

1111 Destination: Page 15

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Source: page 0

Source: page 1

Source: page 2

Source: page 3

Source: page 4

Source: page 5

Source: page 6

Source: page 7

Source: page 8

Source: page 9

Source: page 10

Source: page 11

Source: page 12

Source: page 13

Source: page 14

Source: page 15

NOTES:

1. In the S3F82NB microcontroller, the internal register file is configured as sixteen pages (Pages 0-15).

2. The page 0-14 are used for general purpose register file and page 15 is used for the LCD data register

(00H-AFH) and peripheral control regiser (B0H).

Figure 2-4. Register Page Pointer (PP)

ꢀ

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23

ꢁ

PROGRAMMING TIP — Using the Page Pointer for RAM Clear (Page 0, Page 1)

LD

PP,#00H

#0C0H

; Destination

ꢄ

0, Source

ꢄ

0

SRP

LD

R0,#0FFH

@R0

; Page 0 RAM clear starts

RAMCL0

CLR

DJNZ

CLR

R0,RAMCL0

@R0

; R0 = 00H

LD

CLR

DJNZ

CLR

PP,#10H

R0,#0FFH

@R0

R0,RAMCL1

@R0

; Destination

; Page 1 RAM clear starts

ꢄ

1, Source

ꢄ

RAMCL1

; R0 = 00H

NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.

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24

REGISTER SET 1

The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.

The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and

bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware

reset operation always selects bank 0 addressing.

The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H–FFH) contains 68 mapped system and peripheral

control registers. The lower 32-byte area contains 16 system registers (D0H–DFH) and a 16-byte common

working register area (C0H–CFH). You can use the common working register area as a “scratch” area for data

operations being performed in other areas of the register file.

Registers in set 1 location are directly accessible at all times using Register addressing mode. The 16-byte

working register area can only be accessed using working register addressing (For more information about

working register addressing, please refer to Chapter 3, “Addressing Modes.”)

REGISTER SET 2

The same 64-byte physical space that is used for set 1 location C0H–FFH is logically duplicated to add another

64 bytes of register space. This expanded area of the register file is called set 2. For the S3F82NB,

the set 2 address range (C0H–FFH) is accessible on pages 0-15.

The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only

Register addressing mode to access set 1 location. In order to access registers in set 2, you must use Register

Indirect addressing mode or Indexed addressing mode.

The set 2 register area of page 0 is commonly used for stack operations.

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PRIME REGISTER SPACE

The lower 192 bytes (00H–BFH) of the S3C82NB's sixteen 256-byte register pages is called prime register area.

Prime registers can be accessed using any of the seven addressing modes

(see Chapter 3, "Addressing Modes.")

The prime register area on page 0 is immediately addressable following a reset. In order to address prime

registers on pages 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 or 15 you must set the register page pointer (PP) to

the appropriate source and destination values.

FFH

Page15

Page 14

Page 13

FFH

Page 3

Page 2

Page 1

Page 0

Set 1

Bank 0

Bank 1

FFH

FCH

E0H

D0H

C0H

Set 2

C0H

BFH

Page 0

B0H

AFH

Page15

Prime

Space

CPU and system control

General-purpose

LCD Data

Register Area

Peripheral and I/O

LCD data register

00H

Figure 2-5. Set 1, Set 2, Prime Area Register, and LCD Data Register Map

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S3F82NB

Product Specification

26

WORKING REGISTERS

Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.

When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one

that consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers.

Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to

form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block

anywhere in the addressable register file, except the set 2 area.

The terms slice and block are used in this manual to help you visualize the size and relative locations of selected

working register spaces:

— One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15)

— One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15)

All the registers in an 8-byte working register slice have the same binary value for their five most significant

address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The

base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.

After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).

FFH

Slice 32

F8H

F7H

F0H

Slice 31

1 1 1 1 1 X X X

Set 1

Only

RP1 (Registers R8-R15)

Each register pointer points to

one 8-byte slice of the register

space, selecting a total 16-byte

working register block.

CFH

C0H

~

0 0 0 0 0 X X X

10H

FH

8H

7H

0H

RP0 (Registers R0-R7)

Slice 2

Slice 1

Figure 2-6. 8-Byte Working Register Areas (Slices)

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S3F82NB

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27

USING THE REGISTER POINTS

Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable

8-byte working register slices in the register file. After a reset, they point to the working register common area:

RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.

To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction.

(see Figures 2-7 and 2-8).

With working register addressing, you can only access those two 8-bit slices of the register file that are currently

pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in

set 2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed

addressing modes.

The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general

programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice

(see Figure 2-7). In some cases, it may be necessary to define working register areas in different (non-

contiguous) areas of the register file. In Figure 2-8, RP0 points to the "upper" slice and RP1 to the "lower" slice.

Because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly

define the working register area to support program requirements.

ꢁ

PROGRAMMING TIP — Setting the Register Pointers

SRP

SRP1

SRP0

CLR

LD

#70H

; RP0

ꢄ

70H, RP1

ꢄ

78H

#48H

no change, RP1

ꢄ

48H,

#0A0H

RP0

RP1,#0F8H

A0H, RP1

00H, RP1

no change, RP1

ꢄ

no change

ꢄ

0F8H

Register File

Contains 32

8-Byte Slices

0 0 0 0 1 X X X

RP1

FH (R15)

16-Byte

8-Byte Slice

Contiguous

Working

8H

7H

0 0 0 0 0 X X X

RP0

Register block

0H (R0)

Figure 2-7. Contiguous 16-Byte Working Register Block

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Product Specification

28

F7H (R7)

8-Byte Slice

F0H (R0)

16-Byte

Register File

Contains 32

8-Byte Slices

Contiguous

working

1 1 1 1 0 X X X

Register block

RP0

0 0 0 0 0 X X X

RP1

7H (R15)

0H (R0)

8-Byte Slice

Figure 2-8. Non-Contiguous 16-Byte Working Register Block

ꢁ

PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers

Calculate the sum of registers 80H–85H using the register pointer. The register addresses from 80H through 85H

contain the values 10H, 11H, 12H, 13H, 14H, and 15H, respectively:

SRP0

ADD

ADC

#80H

; RP0

; R0

ꢄ

80H

R0,R1

R0,R2

R0,R3

R0,R4

R0,R5

R0

+

R1

R0

R2 + C

R3 + C

R4 + C

R5 + C

The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this

example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to

calculate the sum of these registers, the following instruction sequence would have to be used:

ADD

ADC

80H,81H

80H,82H

80H,83H

80H,84H

80H,85H

; 80H

ꢄ

(80H)

+

(81H)

(82H)

(83H)

(84H)

(85H)

+

C

Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of

instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.

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29

REGISTER ADDRESSING

The S3C8-series register architecture provides an efficient method of working register addressing that takes full

advantage of shorter instruction formats to reduce execution time.

With Register (R) addressing mode, in which the operand value is the content of a specific register or register

pair, you can access any location in the register file except for set 2. With working register addressing, you use a

register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that

space.

Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register

pair, the address of the first 8-bit register is always an even number and the address of the next register is always

an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and

the least significant byte is always stored in the next (+1) odd-numbered register.

Working register addressing differs from Register addressing as it uses a register pointer to identify a specific

8-byte working register space in the internal register file and a specific 8-bit register within that space.

MSB

Rn

LSB

n = Even address

Rn+1

Figure 2-9. 16-Bit Register Pair

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30

Special-Purpose Registers

Bank 1 Bank 0

General-Purpose Register

FFH

Control

Registers

E0H

D0H

Set 2

System

Registers

CFH

C0H

BFH

RP1

RP0

Register

Pointers

Peripheral

Control

Registers

Each register pointer (RP) can independently point

to one of the 24 8-byte "slices" of the register file

(other than set 2). After a reset, RP0 points to

locations C0H-C7H and RP1 to locations C8H-CFH

(that is, to the common working register area).

Prime

Registers

LCD Data

Registers

NOTE:

In the S3F82NB microcontroller,

pages 0-15 are implemented.

Pages 0-15 contain all of the addressable

registers in the internal register file.

00H

Page 0

Register Addressing Only

All

Indirect Register,

Indexed

All

Addressing

Modes

Addressing

Modes

Addressing

Modes

Can be Pointed to

By register Pointer

Can be Pointed by Register Pointer

Figure 2-10. Register File Addressing

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COMMON WORKING REGISTER AREA (C0H–CFH)

After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations

C0H–CFH, as the active 16-byte working register block:

RP0

RP1

ꢅ

C0H–C7H

C8H–CFH

This 16-byte address range is called common area. That is, locations in this area can be used as working

registers by operations that address any location on any page in the register file. Typically, these working

registers serve as temporary buffers for data operations between different pages.

FFH

Page 15

Page 14

Page 13

FFH

Page 3

Page 2

Page 1

Set 1

Page 0

FFH

FCH

Set 2

E0H

D0H

C0H

BFH

~

Page 0

B0H

AFH

Page 15

Peripheral

Control

~

Register Area

Following a hardware reset, register

pointers RP0 and RP1 point to the

common working register area,

locations C0H-CFH.

~

Prime

Space

~

LCD Data

Register Area

RP0 = 1 1 0 0

RP1 = 1 1 0 0

0 0 0 0

1 0 0 0

00H

Figure 2-11. Common Working Register Area

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32

ꢁ

PROGRAMMING TIP — Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0H–CFH,

using working register addressing mode only.

Examples 1. LD

0C2H,40H

; Invalid addressing mode!

Use working register addressing instead:

SRP

LD

#0C0H

R2,40H

; R2 (C2H) ꢅ the value in location 40H

2. ADD

0C3H,#45H

; Invalid addressing mode!

Use working register addressing instead:

SRP

ADD

#0C0H

R3,#45H

; R3 (C3H) ꢅ R3 + 45H

4-BIT WORKING REGISTER ADDRESSING

Each register pointer defines a movable 8-byte slice of working register space. The address information stored in

a register pointer serves as an addressing "window" that makes it possible for instructions to access working

registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected

working register area, the address bits are concatenated in the following way to form a complete 8-bit address:

— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1).

— The five high-order bits in the register pointer select an 8-byte slice of the register space.

— The three low-order bits of the 4-bit address select one of the eight registers in the slice.

As shown in Figure 2-12, the result of this operation is that the five high-order bits from the register pointer are

concatenated with the three low-order bits from the instruction address to form the complete address. As long as

the address stored in the register pointer remains unchanged, the three bits from the address will always point to

an address in the same 8-byte register slice.

Figure 2-13 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction

"INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the

three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).

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RP0

RP1

Selects

RP0 or RP1

Address

OPCODE

4-bit address

provides three

low-order bits

Register pointer

provides five

high-order bits

Together they create an

8-bit register address

Figure 2-12. 4-Bit Working Register Addressing

RP0

0 1 1 1 0

RP1

0 1 1 1 1

0 0 0

Selects RP0

R6

OPCODE

1 1 1 0

Register

address

(76H)

Instruction

'INC R6'

0 1 1 1 0

1 1 0

0 1 1 0

Figure 2-13. 4-Bit Working Register Addressing Example

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8-BIT WORKING REGISTER ADDRESSING

You can also use 8-bit working register addressing to access registers in a selected working register area. To

initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value

"1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working

register addressing.

As shown in Figure 2-14, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit

addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the

three low-order bits of the complete address are provided by the original instruction.

Figure 2-15 shows an example of 8-bit working register addressing. The four high-order bits of the instruction

address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in

RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register

address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from

RP1 and the three address bits from the instruction are concatenated to form the complete register address,

0ABH (10101011B).

RP0

RP1

Selects

RP0 or RP1

Address

These address

bits indicate 8-bit

working register

addressing

8-bit logical

address

1

0

Register pointer

provides five

high-order bits

Three low-order bits

8-bit physical address

Figure 2-14. 8-Bit Working Register Addressing

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RP0

0 1 1 0 0

RP1

1 0 1 0 1

0 0 0

Selects RP1

R11

8-bit address

form instruction

'LD R11, R2'

Register

address

(0ABH)

1 1 0 0

1

0 1 1

1 0 1 0 1

0 1 1

Specifies working

register addressing

Figure 2-15. 8-Bit Working Register Addressing Example

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SYSTEM AND USER STACK

The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH

and POP instructions are used to control system stack operations. The S3F82NB architecture supports stack

operations in the internal register file.

Stack Operations

Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are

saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents

of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to

their original locations. The stack address value is always decreased by one before a push operation and

increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top

of the stack, as shown in Figure 2-16.

High Address

PCL

PCH

Top of

PCH

stack

Top of

stack

Flags

Stack contents

after a call

instruction

Stack contents

after an

interrupt

Low Address

Figure 2-16. Stack Operations

User-Defined Stacks

You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,

PUSHUD, POPUI, and POPUD support user-defined stack operations.

Stack Pointers (SPL, SPH)

Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations.

The most significant byte of the SP address, SP15–SP8, is stored in the SPH register (D8H), and the least

significant byte, SP7–SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined.

Because only internal memory space is implemented in the S3F82NB, the SPL must be initialized to an 8-bit

value in the range 00H–FFH. The SPH register is not needed and can be used as a general-purpose register, if

necessary.

When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the

register file), you can use the SPH register as a general-purpose data register. However, if an overflow or

underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register

during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register,

overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can

initialize the SPL value to "FFH" instead of "00H".

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ꢁ

PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and

POP instructions:

LD

SPL,#0FFH

; SPL

ꢄ

FFH

; (Normally, the SPL is set to 0FFH by the initialization

; routine)

•

PUSH

•

PP

; Stack address 0FEH

; Stack address 0FDH

; Stack address 0FCH

; Stack address 0FBH

ꢄ

PP

RP0

RP1

R3

RP0

RP1

R3

•

POP

R3

; R3

ꢄ

Stack address 0FBH

RP1

RP0

PP

; RP1 ꢄ Stack address 0FCH

; RP0 ꢄ Stack address 0FDH

; PP

ꢄ

Stack address 0FEH

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3

ADDRESSING MODES

OVERVIEW

Instructions that are stored in program memory are fetched for execution using the program counter. Instructions

indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to

determine the location of the data operand. The operands specified in SAM88RC instructions may be condition

codes, immediate data, or a location in the register file, program memory, or data memory.

The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are

available for each instruction. The seven addressing modes and their symbols are:

— Register (R)

— Indirect Register (IR)

— Indexed (X)

— Direct Address (DA)

— Indirect Address (IA)

— Relative Address (RA)

— Immediate (IM)

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REGISTER ADDRESSING MODE (R)

In Register addressing mode (R), the operand value is the content of a specified register or register pair

(see Figure 3-1).

Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte

working register space in the register file and an 8-bit register within that space (see Figure 3-2).

Program Memory

Register File

OPERAND

8-bit Register

File Address

dst

OPCODE

Point to One

Register in Register

File

One-Operand

Instruction

(Example)

Value used in

Instruction Execution

Sample Instruction:

DEC

CNTR

;

Where CNTR is the label of an 8-bit register address

Figure 3-1. Register Addressing

Register File

MSB Point to

RP0 ot RP1

RP0 or RP1

OPERAND

Selected

RP points

to start

Program Memory

of working

register

block

4-bit

Working Register

3 LSBs

dst

OPCODE

src

Point to the

Working Register

(1 of 8)

Two-Operand

Instruction

(Example)

Sample Instruction:

ADD

R1, R2

;

Where R1 and R2 are registers in the currently

selected working register area.

Figure 3-2. Working Register Addressing

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INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the

operand. Depending on the instruction used, the actual address may point to a register in the register file, to

program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to

indirectly address another memory location. Please note, however, that you cannot access locations C0H–FFH in

set 1 using the Indirect Register addressing mode.

Program Memory

Register File

ADDRESS

8-bit Register

File Address

dst

OPCODE

Point to One

Register in Register

File

One-Operand

Instruction

Address of Operand

used by Instruction

(Example)

OPERAND

Value used in

Instruction Execution

Sample Instruction:

RL

@SHIFT

;

Where SHIFT is the label of an 8-bit register address

Figure 3-3. Indirect Register Addressing to Register File

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INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

Program Memory

Example

REGISTER

PAIR

dst

Instruction

References

Program

Points to

Register Pair

OPCODE

16-Bit

Memory

Address

Points to

Program

Memory

Program Memory

OPERAND

Sample Instructions:

Value used in

Instruction

CALL

JP

@RR2

Figure 3-4. Indirect Register Addressing to Program Memory

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INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

MSB Points to

RP0 or RP1

Selected

RP points

to start fo

working register

block

Program Memory

~

4-bit

Working

Register

Address

3 LSBs

dst

src

Point to the

Working Register

(1 of 8)

ADDRESS

OPERAND

OPCODE

~

Sample Instruction:

Value used in

Instruction

OR

R3, @R6

Figure 3-5. Indirect Working Register Addressing to Register File

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INDIRECT REGISTER ADDRESSING MODE (Concluded)

Register File

MSB Points to

RP0 or RP1

Selected

RP points

to start of

working

register

block

Program Memory

4-bit Working

Register Address

dst

src

Register

Pair

Next 2-bit Point

to Working

Register Pair

(1 of 4)

OPCODE

Example Instruction

References either

Program Memory or

Data Memory

16-Bit

address

points to

program

memory

or data

Program Memory

or

Data Memory

LSB Selects

memory

Value used in

Instruction

OPERAND

Sample Instructions:

LCD

LDE

R5,@RR6

R3,@RR14

@RR4, R8

; Program memory access

; External data memory access

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

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INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to

calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access

locations in the internal register file or in external memory. Please note, however, that you cannot access

locations C0H–FFH in set 1 using Indexed addressing mode.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128

to +127. This applies to external memory accesses only (see Figure 3-8.)

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained

in a working register. For external memory accesses, the base address is stored in the working register pair

designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address

(see Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction

(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for

external data memory, when implemented.

Register File

RP0 or RP1

~

Selected RP

points to

start of

working

register

block

Value used in

Instruction

OPERAND

INDEX

+

Program Memory

Base Address

3 LSBs

Two-Operand

Instruction

Example

dst/src

x

Point to One of the

Woking Register

(1 of 8)

OPCODE

Sample Instruction:

LD R0, #BASE[R1]

;

Where BASE is an 8-bit immediate value

Figure 3-7. Indexed Addressing to Register File

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INDEXED ADDRESSING MODE (Continued)

Register File

RP0 or RP1

MSB Points to

RP0 or RP1

Selected

RP points

to start of

working

register

block

~

Program Memory

OFFSET

NEXT 2 Bits

4-bit Working

Register Address

dst/src

x

Register

Pair

Point to Working

Register Pair

(1 of 4)

OPCODE

16-Bit

address

added to

offset

Program Memory

or

Data Memory

LSB Selects

+

16-Bits

8-Bits

Value used in

Instruction

OPERAND

16-Bits

Sample Instructions:

LDC

LDE

R4, #04H[RR2]

R4,#04H[RR2]

; The values in the program address (RR2 + 04H)

are loaded into register R4.

; Identical operation to LDC example, except that

external program memory is accessed.

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

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INDEXED ADDRESSING MODE (Concluded)

Register File

MSB Points to

RP0 or RP1

Selected

RP points

to start of

working

register

block

Program Memory

~

OFFSET

NEXT 2 Bits

4-bit Working

Register Address

dst/src

src

Register

Pair

Point to Working

Register Pair

OPCODE

16-Bit

address

added to

offset

Program Memory

or

Data Memory

LSB Selects

+

16-Bits

8-Bits

Value used in

Instruction

OPERAND

16-Bits

Sample Instructions:

LDC

LDE

R4, #1000H[RR2]

R4,#1000H[RR2]

; The values in the program address (RR2 + 1000H)

are loaded into register R4.

; Identical operation to LDC example, except that

external program memory is accessed.

Figure 3-9. Indexed Addressing to Program or Data Memory

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DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call

(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC

whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for

Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

Program or

Data Memory

Memory

Address

Used

Program Memory

Upper Address Byte

Lower Address Byte

dst/src "0" or "1"

OPCODE

LSB Selects Program

Memory or Data Memory:

"0" = Program Memory

"1" = Data Memory

Sample Instructions:

LDC

LDE

R5,1234H

;

The values in the program address (1234H)

are loaded into register R5.

Identical operation to LDC example, except that

external program memory is accessed.

Figure 3-10. Direct Addressing for Load Instructions

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DIRECT ADDRESS MODE (Continued)

Program Memory

Next OPCODE

Memory

Address

Used

Upper Address Byte

Lower Address Byte

OPCODE

Sample Instructions:

JP

C,JOB1

;

Where JOB1 is a 16-bit immediate address

Where DISPLAY is a 16-bit immediate address

CALL DISPLAY

Figure 3-11. Direct Addressing for Call and Jump Instructions

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INDIRECT ADDRESS MODE (IA)

In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program

memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.

Only the CALL instruction can use the Indirect Address mode.

Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program

memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are

assumed to be all zeros.

Program Memory

Next Instruction

LSB Must be Zero

dst

OPCODE

Current

Instruction

Lower Address Byte

Upper Address Byte

Program Memory

Locations 0-255

Sample Instruction:

CALL #40H

; The 16-bit value in program memory addresses 40H

and 41H is the subroutine start address.

Figure 3-12. Indirect Addressing

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RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in

the instruction. The displacement value is then added to the current PC value. The result is the address of the

next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction

immediately following the current instruction.

Several program control instructions use the Relative Address mode to perform conditional jumps. The

instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.

Program Memory

Next OPCODE

Program Memory

Address Used

Current

PC Value

+

Displacement

OPCODE

Current Instruction

Signed

Displacement Value

Sample Instructions:

JR

ULT,$+OFFSET

;

Where OFFSET is a value in the range +127 to -128

Figure 3-13. Relative Addressing

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IMMEDIATE MODE (IM)

In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand

field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate

addressing mode is useful for loading constant values into registers.

Program Memory

OPERAND

OPCODE

(The Operand value is in the instruction)

Sample Instruction:

LD

R0,#0AAH

Figure 3-14. Immediate Addressing

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4

CONTROL REGISTERS

OVERVIEW

In this chapter, detailed descriptions of the S3F82NB control registers are presented in an easy-to-read format.

You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates

the important features of the standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed

information about control registers is presented in the context of the specific peripheral hardware descriptions in

Part II of this manual.

Data and counter registers are not described in detail in this reference chapter. More information about all of the

registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this

manual.

The locations and read/write characteristics of all mapped registers in the S3F82NB register file are listed in

Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, "RESET and Power-

Down."

Table 4-1. Set 1 Registers

Register Name

Mnemonic

Decimal

Hex

R/W

Location D0H–D2H is not mapped.

Basic Timer Control Register

System Clock Control Register

System Flags Register

Register Pointer 0

BTCON

CLKCON

FLAGS

RP0

211

212

213

214

215

216

217

218

219

220

221

222

223

D3H

D4H

D5H

D6H

D7H

D8H

D9H

DAH

DBH

DCH

DDH

DEH

DFH

R/W

R

Register Pointer 1

RP1

Stack Pointer (High Byte)

Stack Pointer (Low Byte)

Instruction Pointer (High Byte)

Instruction Pointer (Low Byte)

Interrupt Request Register

Interrupt Mask Register

System Mode Register

Register Page Pointer

SPH

SPL

IPH

IPL

IRQ

IMR

R/W

SYM

PP

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Table 4-2. Set 1, Bank 0 Registers

Register Name

Port Group 0 Control Register

Port Group 1 Control Register

Port 6 Control Register

Mnemonic

PG0CON

PG1CON

P6CON

Decimal

Hex

D0H

D1H

D2H

E0H

E1H

E2H

E3H

E4H

E5H

E6H

E7H

E8H

E9H

EAH

EBH

ECH

EDH

EEH

EFH

F0H

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

F9H

FAH

FBH

R/W

R

208

209

210

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

A/D Converter Data Register (High Byte)

A/D Converter Data Register (Low Byte)

A/D Converter Control Register

Timer 0 Counter Register

ADDATAH

ADDATAL

ADCON

T0CNT

R

R/W

R

Timer 0 Data Register

T0DATA

T0CON

R/W

R

Timer 0 Control Register

Timer B Counter Register

TBCNT

Timer A Counter Register

TACNT

R

Timer B Data Register

TBDATA

TADATA

TBCON

R/W

R

Timer A Data Register

Timer B Control Register

Timer 1/A Control Register

Timer Interrupt Pending Register

Timer Interrupt Control Register

Watch Timer Control Register

LCD Control Register

TACON

TINTPND

TINTCON

WTCON

LCON

LCD Mode Register

LMOD

Comparator Control Register

Comparator Result Register

SIO Control Register

CMPCON

CMPREG

SIOCON

SIODATA

SIOPS

R/W

SIO Data Register

SIO Pre-Scaler Register

FMSECH

FMSECL

FMUSR

FMCON

OSCCON

STPCON

Flash Memory Sector Address Register (High Byte)

Flash Memory Sector Address Register (Low Byte)

Flash Memory User Programming Enable Register

Flash Memory Control Register

Oscillator Control Register

STOP Control Register

Location FCH is not mapped.

Basic Timer Counter

BTCNT

Location FEH is not mapped.

253

FDH

FFH

R

Interrupt Priority Register

IPR

255

R/W

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Table 4-3. Set 1, Bank 1 Registers

Register Name

Port 4 Control Register (High Byte)

Port 4 Control Register (Low Byte)

Port 4 Pull-up Resistor Enable Register

Port 0 Control Register (High Byte)

Port 0 Control Register (Low Byte)

Port 0 Pull-up Resistor Enable Register

Alternative Function Selection Register

Port 1 Control Register (High Byte)

Port 1 Control Register (Low Byte)

Port 1 Pull-up Resistor Enable Register

Port 1 Interrupt Pending Register

Mnemonic

P4CONH

P4CONL

P4PUR

Decimal

Hex

D0H

D1H

D2H

E0H

E1H

E2H

E3H

E4H

E5H

E6H

E7H

E8H

E9H

EAH

EBH

ECH

EDH

EEH

EFH

F0H

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

F9H

FAH

FBH

FCH

FDH

FEH

FFH

R/W

208

209

210

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

R/W

P0CONH

P0CONL

P0PUR

AFSEL

P1CONH

P1CONL

P1PUR

P1PND

Port 1 Interrupt Control Register (High Byte)

Port 1 Interrupt Control Register (Low Byte)

Port 2 Control Register (High Byte)

Port 2 Control Register (Low Byte)

Port 2 Pull-up Resistor Enable Register

Port 3 Pull-up Resistor Enable Register

Port 3 Control Register (High Byte)

Port 3 Control Register (Low Byte)

Port 0 Data Register

P1INTH

P1INTL

P2CONH

P2CONL

P2PUR

P3PUR

P3CONH

P3CONL

P0

Port 1 Data Register

P1

Port 2 Data Register

P2

Port 3 Data Register

P3

Port 4 Data Register

P4

Port 5 Data Register

P5

Port 6 Data Register

P6

Port 7 Data Register

P7

Port 8 Data Register

P8

P9

Port 9 Data Register

Port 10 Data Register

P10

Port 5 Interrupt Control Register

Port 5 Interrupt Pending Register

Port 5 Pull-up Resistor Enable Register

Port 5 Control Register (High Byte)

Port 5 Control Register (Low Byte)

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P5PND

P5PUR

P5CONH

P5CONL

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Table 4-4. Page 15 Registers

Register Name

Reset Source Indicating Register

Mnemonic

Decimal

176

Hex

R/W

RESETID

B0H

R/W

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Bit number(s) that is/are appended to

the register name for bit addressing

Name of individual

bit or related bits

Register location

in the internal

register file

Register address

(hexadecimal)

Register ID

Full Register name

FLAGS - System Flags Register

D5H

Set 1

Bit Identifier

RESET Value

Read/Write

Bit Addressing

Mode

.7

x

.6

x

.5

x

.4

x

.3

x

.2

.1

.0

0

x

R/W

Register addressing mode only

.7

Carry Flag (C)

0

Operation does not generate a carry or borrow condition

Operation generates carry-out or borrow into high-order bit 7

.6

.5

Zero Flag (Z)

Operation result is a non-zero value

Operation result is zero

0

Sign Flag (S)

Operation generates positive number (MSB = "0")

0

Operation generates negative number (MSB = "1")

R = Read-only

W = Write-only

R/W = Read/write

'-' = Not used

Description of the

effect of specific

bit settings

Bit number:

MSB = Bit 7

LSB = Bit 0

Type of addressing

RESET value notation:

'-' = Not used

that must be used to

address the bit

'x' = Undetermined value

'0' = Logic zero

(1-bit, 4-bit, or 8-bit)

'1' = Logic one

Figure 4-1. Register Description Format

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ADCON — A/D Converter Control Register

E2H

Set 1, Bank 0

Bit Identifier

.7

ꢁꢂ

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

R

R/W

Addressing Mode

Register addressing mode only

Not used for the S3F82NB

A/D Input Pin Selection Bits

.7

.6–.4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

.3

End-of-Conversion Bit (Read-only)

0

1

Conversion not complete

Conversion complete

.2–.1

Clock Source Selection Bits

0

1

0

1

0

1

fxx/16

fxx/8

fxx/4

fxx/1

.0

Start or Enable Bit

0

1

Disable operation

Start operation

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AFSEL — Alternative Function Selection Register

E3H

Set 1, Bank 1

Bit Identifier

.7

ꢁꢂ

.6

ꢁꢂ

.5

ꢁꢂ

.4

ꢁꢂ

.3

ꢁꢂ

.2

ꢁꢂ

.1

.0

0

RESET Value

Read/Write

0

R/W

Addressing Mode

Register addressing mode only

.7–.2

.1

Not used for the S3F82NB

P0.3 Alternative Mode Selection Bit

0

1

Alternative function (AD3)

Alternative function (T0OUT/T0PWM)

.0

P0.2 Alternative Mode Selection Bit

0

1

Alternative function (AD2)

Alternative function (T1OUT/T1PWM)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

59

BTCON — Basic Timer Control Register

D3H

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.4

Watchdog Timer Function Disable Code (for System Reset)

1

0

1

0

Disable watchdog timer function

Enable watchdog timer function

Others

Basic Timer Input Clock Selection Bits ⁽³⁾

.3–.2

0

1

0

1

0

1

fxx/4096

fxx/1024

fxx/128

fxx/16

Basic Timer Counter Clear Bit ⁽¹⁾

.1

0

1

No effect

Clear the basic timer counter value

Clock Frequency Divider Clear Bit for Basic Timer and Timer/Counters ⁽²⁾

.0

0

1

No effect

Clear both clock frequency dividers

NOTES:

1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write

operation, the BTCON.1 value is automatically cleared to “0”.

2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the

write operation, the BTCON.0 value is automatically cleared to "0".

3. The fxx is selected clock for system (main OSC. or sub OSC.).

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

60

CLKCON — System Clock Control Register

D4H

Set 1

Bit Identifier

.7

0

.6

ꢁ

.5

ꢁ

.4

0

.3

0

.2

ꢁ

.1

ꢁ

.0

ꢁ

RESET Value

Read/Write

R/W

ꢁ

Addressing Mode

Register addressing mode only

.7

Oscillator IRQ Wake-up Function Bit

0

1

Enable IRQ for main wake-up in power down mode

Disable IRQ for main wake-up in power down mode

.6–.5

.4–.3

Not used for the S3F82NB

CPU Clock (System Clock) Selection Bits ^(note)

0

1

0

1

0

1

fxx/16

fxx/8

fxx/2

fxx/1

.2–.0

Not used for the S3F82NB

NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load

the appropriate values to CLKCON.3 and CLKCON.4.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

61

CMPCON — Comparator Control Register

F1H

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

–

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

–

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

Comparator Enable Bit

0

1

Disable Comparator

Enable Comparator

Conversion Time Selection Bit

8 X 2⁵/fx

8 X 2⁴/fx

0

1

External/Internal Reference Selection Bit

0

1

Internal reference, CIN0–CIN2; analog input

CIN2; External reference, CIN0–CIN1; analog input

.4

Not used, But you must keep “0”

.3–.0

Reference Voltage Selection Bits

Selected V_REF= V_DDX (N+0.5)/16, N = 0 to 15

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

62

FLAGS — System Flags Register

D5H

Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

0

.0

0

RESET Value

Read/Write

R/W

R

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

Carry Flag (C)

0

1

Operation does not generate a carry or borrow condition

Operation generates a carry-out or borrow into high-order bit 7

Zero Flag (Z)

0

1

Operation result is a non-zero value

Operation result is zero

Sign Flag (S)

0

1

Operation generates a positive number (MSB = "0")

Operation generates a negative number (MSB = "1")

Overflow Flag (V)

0

1

Operation result is ꢆ +127 or ꢇ –128

Operation result is > +127 or < –128

Decimal Adjust Flag (D)

0

1

Add operation completed

Subtraction operation completed

Half-Carry Flag (H)

0

1

No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction

Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3

Fast Interrupt Status Flag (FIS)

0

1

Interrupt return (IRET) in progress (when read)

Fast interrupt service routine in progress (when read)

Bank Address Selection Flag (BA)

0

1

Bank 0 is selected

Bank 1 is selected

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

63

FMCON — Flash Memory Control Register

F9H

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

ꢁ

.1

ꢁ

.0

0

RESET Value

Read/Write

R/W

R

R/W

ꢁ

Addressing Mode

Register addressing mode only

.7–.4

Flash Memory Mode Selection Bits

0

1

0

1

0

1

0

1

0

Programming mode

Sector erase mode

Hard lock mode

Not available

Others

.3

Sector Erase Status Bit (Read-only)

0

1

Success sector erase

Fail sector erase

.2–.1

.0

Not used for the S3F82NB

Flash Operation Start Bit

0

1

Operation stop bit

Operation start bit

NOTE: The FMCON.0 will be cleared automatically just after the corresponding operation completed.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

64

FMSECH — Flash Memory Sector Address Register (High Byte) F6H Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.0

Flash Memory Sector Address Bits (High Byte)

The 15^th-8^thto select a sector of Flash ROM

NOTE: The high-byte flash memory sector address pointer value is higher eight bits of the 16-bit pointer address.

FMSECL — Flash Memory Sector Address Register (Low Byte) F7H

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

0

R/W

Addressing Mode

Register addressing mode only

.7

Flash Memory Sector Address Bit (Low Byte)

The 7^thbit to select a sector of Flash ROM

.6–.0

Don’t care

NOTE: The low-byte flash memory sector address pointer value is lower eight bits of the 16-bit pointer address.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

65

FMUSR — Flash Memory User Programming Enable Register F8H

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

RESET Value

Read/Write

0

R/W

Addressing Mode

Register addressing mode only

.7–.0

Flash Memory User Programming Enable Bits

1

0

1

0

1

0

1

Enable user programming mode

Disable user programming mode

Others

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

66

IMR — Interrupt Mask Register

DDH

Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P5.4–P5.7

0

1

Disable (mask)

Enable (unmask)

Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P1.4–P1.7

0

1

Disable (mask)

Enable (unmask)

Interrupt Level 5 (IRQ5) Enable Bit; External Interrupts P1.0–P1.3

0

1

Disable (mask)

Enable (unmask)

Interrupt Level 4 (IRQ4) Enable Bit; Watch Timer

0

1

Disable (mask)

Enable (unmask)

Interrupt Level 3 (IRQ3) Enable Bit; SIO

0

1

Disable (mask)

Enable (unmask)

Interrupt Level 2 (IRQ2) Enable Bit; Timer B Match

0

1

Disable (mask)

Enable (unmask)

Interrupt Level 1 (IRQ1) Enable Bit; Timer 1/A Match/Capture or Overflow

0

1

Disable (mask)

Enable (unmask)

Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match/Capture or Overflow

0

1

Disable (mask)

Enable (unmask)

NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

67

IPH — Instruction Pointer (High Byte)

DAH

Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.0

Instruction Pointer Address (High Byte)

The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction

pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL

register (DBH).

IPL — Instruction Pointer (Low Byte)

DBH

Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.0

Instruction Pointer Address (Low Byte)

The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction

pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH

register (DAH).

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

68

IPR — Interrupt Priority Register

FFH

Set 1, Bank 0

Bit Identifier

RESET Value

Read/Write

.7

x

R/W

.6

x

R/W

.5

x

R/W

.4

x

R/W

.3

x

R/W

.2

x

R/W

.1

x

R/W

.0

x

R/W

Addressing Mode

Register addressing mode only

.7, .4, and .1

Priority Control Bits for Interrupt Groups A, B, and C

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Group priority undefined

B

A

B

C

A

>

C

B

A

B

C

>

A

C

B

A

B

Group priority undefined

.6

.5

.3

.2

.0

Interrupt Subgroup C Priority Control Bit

0

1

IRQ6

IRQ7

>

IRQ7

IRQ6

Interrupt Group C Priority Control Bit

0

1

IRQ5

(IRQ6, IRQ7)

>

(IRQ6, IRQ7)

IRQ5

>

Interrupt Subgroup B Priority Control Bit

0

1

IRQ3 > IRQ4

IRQ4 > IRQ3

Interrupt Group B Priority Control Bit

0

1

IRQ2

(IRQ3, IRQ4)

>

(IRQ3, IRQ4)

IRQ2

>

Interrupt Group A Priority Control Bit

0

1

IRQ0

IRQ1

>

IRQ1

IRQ0

NOTE: Interrupt group A -IRQ0, IRQ1

Interrupt group B -IRQ2, IRQ3, IRQ4

Interrupt group C -IRQ5, IRQ6, IRQ7

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

69

IRQ — Interrupt Request Register

DCH

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

Level 7 (IRQ7) Request Pending Bit; External Interrupts P5.4–P5.7

0

1

Not pending

Pending

Level 6 (IRQ6) Request Pending Bit; External Interrupts P1.4–P1.7

0

1

Not pending

Pending

Level 5 (IRQ5) Request Pending Bit; External Interrupts P1.0–P1.3

0

1

Not pending

Pending

Level 4 (IRQ4) Request Pending Bit; Watch Timer

0

1

Not pending

Pending

Level 3 (IRQ3) Request Pending Bit; SIO

0

1

Not pending

Pending

Level 2 (IRQ2) Request Pending Bit; Timer B Match

0

1

Not pending

Pending

Level 1 (IRQ1) Request Pending Bit; Timer 1/A Match/Capture or Overflow

0

1

Not pending

Pending

.0

Level 0 (IRQ0) Request Pending Bit; Timer 0 Match/Capture or Overflow

0

1

Not pending

Pending

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

70

LCON — LCD Control Register

EFH

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

ꢁ

.1

.0

0

RESET Value

Read/Write

ꢁ

R/W

ꢁ

Addressing Mode

Register addressing mode only

.7–.5

LCD Clock Selection Bits

fw/2⁷(256 Hz)

fw/2⁶(512 Hz)

fw/2⁵(1024 Hz)

fw/2⁴(2048 Hz)

fw/2³(4096 Hz)

Not available

0

1

0

1

0

1

0

1

0

Others

.4

.3

LCD Bias Selection Bit

0

1

1/4 bias

1/5 bias

LCD Duty Selection Bit

0

1

1/8 duty

1/16 duty

.2–.1

.0

Not used for the S3F82NB

LCD Display Control Bits

0

1

Display off

Display on

NOTES: The clock and duty for LCD controller/driver is automatically initialized by hardware, whenever LCON register data

value is re-write. So, the LCON register don’t re-write frequently.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

71

LMOD — LCD Mode Control Register

F1H

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

ꢁ

.1

ꢁ

.0

ꢁ

RESET Value

Read/Write

R/W

ꢁ

Addressing Mode

Register addressing mode only

.7–.4

LCD Contrast Level Control Bits

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1/16 step (The dimmest level)

2/16 step

3/16 step

4/16 step

5/16 step

6/16 step

7/16 step

8/16 step

9/16 step

10/16 step

11/16 step

12/16 step

13/16 step

14/16 step

15/16 step

16/16 step (The brightest level)

.3

Enable/Disable LCD Contrast Control Bit

0

1

Disable LCD contrast control

Enable LCD contrast control

.2–.0

Not used for the S3F82NB

NOTES: V_LCD= V_DDx (n+17)/32, where n = 0 - 15.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

72

OSCCON — Oscillator Control Register

FAH

Set 1, Bank 0

Bit Identifier

.7

ꢁ

.6

ꢁ

.5

ꢁ

.4

ꢁ

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

ꢁ

R/W

ꢁ

Addressing Mode

Register addressing mode only

Not used for the S3F82NB

Main Oscillator Control Bit

.7–.4

.3

0

1

Main oscillator RUN

Main oscillator STOP

.2

Sub Oscillator Control Bit

0

1

Sub oscillator RUN

Sub oscillator STOP

.1

.0

Not used for the S3F82NB

System Clock Selection Bit

0

1

Select main oscillator for system clock

Select sub oscillator for system clock

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

73

P0CONH — Port 0 Control Register (High Byte)

E0H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P0.7/AD7 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (AD7)

P0.6/AD6 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (AD6)

P0.5/AD5 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (AD5)

P0.4/AD4 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (AD4)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

74

P0CONL — Port 0 Control Register (Low Byte)

E1H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

0

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P0.3/AD3/T0OUT/T0PWM/T0CAP Configuration Bits

0

1

0

1

0

1

Input mode (T0CAP)

Output mode, open-drain

Output mode, push-pull

Alternative function (AD3 or T0OUT/T0PWM)

P0.2/AD2/T1OUT/T1PWM/T1CAP Configuration Bits

0

1

0

1

0

1

Input mode (T1CAP)

Output mode, open-drain

Output mode, push-pull

Alternative function (AD2 or T1OUT/T1PWM)

P0.1/AD1/T0CLK Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode (T0CLK)

Output mode, open-drain

Output mode, push-pull

Alternative function (AD1)

P0.0/AD0/T1CLK Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode (T1CLK)

Output mode, open-drain

Output mode, push-pull

Alternative function (AD0)

NOTES: The P0.2 and P0.3 Alternative functions depend on AFSEL.0 and AFSEL.1, respectively.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

75

P0PUR — Port 0 Pull-up Resistor Enable Register

E2H

Set 1, Bank 1

Bit Identifier

RESET Value

Read/Write

.7

0

R/W

.6

0

R/W

.5

0

R/W

.4

0

R/W

.3

0

R/W

.2

0

R/W

.1

0

R/W

.0

0

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

P0.7 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P0.6 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P0.5 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P0.4 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P0.3 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P0.2 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P0.1 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P0.0 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

NOTE: A pull-up resistor of port 0 is automatically disabled only when the corresponding pin is selected as push-pull

output or alternative function.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

76

P1CONH — Port 1 Control Register (High Byte)

E4H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

0

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P1.7/INT7/SCK Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode (SCK)

Output mode, open-drain

Output mode, push-pull

Alternative function (SCK out)

P1.6/INT6/SO Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SO)

P1.5/INT5/SI Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode (SI)

Output mode, open-drain

Output mode, push-pull

Not available

P1.4/INT4/BUZ Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (BUZ)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

77

P1CONL — Port 1 Control Register (Low Byte)

E5H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P1.3/INT3 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode

Output mode, open-drain

Output mode, push-pull

Not available

P1.2/INT2 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode

Output mode, open-drain

Output mode, push-pull

Not available

P1.1/INT1 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode

Output mode, open-drain

Output mode, push-pull

Not available

P1.0/INT0/ AV

REF

T Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode

Output mode, open-drain

Output mode, push-pull

Not available

NOTE: Refer to the SMART OPTION for configuring as one of the P1.0/INT0 and AV_REF

.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

78

P1PUR — Port 1 Pull-up Resistor Enable Register

E6H

Set 1, Bank 1

Bit Identifier

RESET Value

Read/Write

.7

0

R/W

.6

0

R/W

.5

0

R/W

.4

0

R/W

.3

0

R/W

.2

0

R/W

.1

0

R/W

.0

0

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

P1.7 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P1.6 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P1.5 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P1.4 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P1.3 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P1.2 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P1.1 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P1.0 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

NOTE: A pull-up resistor of port 1 is automatically disabled only when the corresponding pin is selected as push-pull

output or alternative function.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

79

P1INTH — Port 1 Interrupt Control Register (High Byte)

E8H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P1.7/External interrupt (INT7) Enable Bits

0

1

0

1

0

1

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

P1.6/External interrupt (INT6) Enable Bits

0

1

0

1

0

1

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

P1.5/External interrupt (INT5) Enable Bits

0

1

0

1

0

1

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

P1.4/External interrupt (INT4) Enable Bits

0

1

0

1

0

1

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

80

P1INTL — Port 1 Interrupt Control Register (Low Byte)

E9H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

0

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P1.3/External interrupt (INT3) Enable Bits

0

1

0

1

0

1

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

P1.2/External interrupt (INT2) Enable Bits

0

1

0

1

0

1

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

P1.1/External interrupt (INT1) Enable Bits

0

1

0

1

0

1

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

P1.0/External interrupt (INT0) Enable Bits

0

1

0

1

0

1

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

81

P1PND — Port 1 Interrupt Pending Register

E7H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

P1.7/External Interrupt (INT7) Pending Bit

0

1

Clear pending bit (when write)

P1.7/INT7 interrupt request is pending (when read)

P1.6/External Interrupt (INT6) Pending Bit

0

1

Clear pending bit (when write)

P1.6/INT6 interrupt request is pending (when read)

P1.5/External Interrupt (INT5) Pending Bit

0

1

Clear pending bit (when write)

P1.5/INT5 interrupt request is pending (when read)

P1.4/External Interrupt (INT4) Pending Bit

0

1

Clear pending bit (when write)

P1.4/INT4 interrupt request is pending (when read)

P1.3/External Interrupt (INT3) Pending Bit

0

1

Clear pending bit (when write)

P1.3/INT3 interrupt request is pending (when read)

P1.2/External Interrupt (INT2) Pending Bit

0

1

Clear pending bit (when write)

P1.2/INT2 interrupt request is pending (when read)

P1.1/External Interrupt (INT1) Pending Bit

0

1

Clear pending bit (when write)

P1.1/INT1 interrupt request is pending (when read)

.0

P1.0/External Interrupt (INT0) Pending Bit

0

1

Clear pending bit (when write)

P1.0/INT0 interrupt request is pending (when read)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

82

P2CONH — Port 2 Control Register (High Byte)

EAH

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

0

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5-.4

.3–.2

.1–.0

P2.7/SEG63 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG63)

P2.6/SEG62 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG62)

P2.5/SEG61 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG61)

P2.4/SEG60 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG60)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

83

P2CONL — Port 2 Control Register (Low Byte)

EBH

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5-.4

.3–.2

.1–.0

P2.3/SEG59 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG59)

P2.2/SEG58 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG58)

P2.1/SEG57 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG57)

P2.0/SEG56 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG56)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

84

P2PUR — Port 2 Pull-up Resistor Enable Register

ECH

Set 1, Bank 1

Bit Identifier

RESET Value

Read/Write

.7

0

R/W

.6

0

R/W

.5

0

R/W

.4

0

R/W

.3

0

R/W

.2

0

R/W

.1

0

R/W

.0

0

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

P2.7 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P2.6 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P2.5 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P2.4 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P2.3 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P2.2 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P2.1 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P2.0 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

NOTE: A pull-up resistor of port 2 is automatically disabled only when the corresponding pin is selected as push-pull

output or alternative function.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

85

P3CONH — Port 3 Control Register (High Byte)

EEH

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P3.7/SEG71 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG71)

P3.6/SEG70 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG70)

P3.5/SEG69 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG69)

P3.4/SEG68 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG68)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

86

P3CONL — Port 3 Control Register (Low Byte)

EFH

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

0

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P3.3/SEG67 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG67)

P3.2/SEG66 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG66)

P3.1/SEG65 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG65)

P3.0/SEG64 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG64)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

87

P3PUR — Port 3 Pull-up Resistor Enable Register

EDH

Set 1, Bank 1

Bit Identifier

RESET Value

Read/Write

.7

0

R/W

.6

0

R/W

.5

0

R/W

.4

0

R/W

.3

0

R/W

.2

0

R/W

.1

0

R/W

.0

0

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

P3.7 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P3.6 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P3.5 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P3.4 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P3.3 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P3.2 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P3.1 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P3.0 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

NOTE: A pull-up resistor of port 3 is automatically disabled only when the corresponding pin is selected as push-pull

output or alternative function.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

88

P4CONH — Port 4 Control Register (High Byte)

D0H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

0

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P4.7/SEG79 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG79)

P4.6/SEG78 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG78)

P4.5/SEG77 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG77)

P4.4/SEG76 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG76)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

89

P4CONL — Port 4 Control Register (Low Byte)

D1H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P4.3/SEG75 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG75)

P4.2/SEG74 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG74)

P4.1/SEG73 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG73)

P4.0/SEG72 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG72)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

90

P4PUR — Port 4 Pull-up Resistor Enable Register

D2H

Set 1, Bank 1

Bit Identifier

RESET Value

Read/Write

.7

0

R/W

.6

0

R/W

.5

0

R/W

.4

0

R/W

.3

0

R/W

.2

0

R/W

.1

0

R/W

.0

0

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

P4.7 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P4.6 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P4.5 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P4.4 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P4.3 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P4.2 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P4.1 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P4.0 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

NOTE: A pull-up resistor of port 4 is automatically disabled only when the corresponding pin is selected as push-pull

output or alternative function.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

91

P5CONH — Port 5 Control Register (High Byte)

FEH

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P5.7/SEG87/INT11 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG87)

P5.6/SEG86/INT10 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG86)

P5.5/SEG85/INT9 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG85)

P5.4/SEG84/INT8 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG84)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

92

P5CONL — Port 5 Control Register (Low Byte)

FFH

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

0

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P5.3/SEG83 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG83)

P5.2/SEG82 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG82)

P5.1/SEG81 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG81)

P5.0/ SEG80 Configuration Bits

0

1

0

1

0

1

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (SEG80)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

93

P5PUR — Port 5 Pull-up Resistor Enable Register

FDH

Set 1, Bank 1

Bit Identifier

RESET Value

Read/Write

.7

0

R/W

.6

0

R/W

.5

0

R/W

.4

0

R/W

.3

0

R/W

.2

0

R/W

.1

0

R/W

.0

0

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

P5.7 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P5.6 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P5.5 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P5.4 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P5.3 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P5.2 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P5.1 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

P5.0 Pull-up Resistor Enable Bit

0

1

Pull-up disable

Pull-up enable

NOTE: A pull-up resistor of port 5 is automatically disabled only when the corresponding pin is selected as push-pull

output or alternative function.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

94

P5INT — Port 5 Interrupt Control Register

FBH

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

0

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P5.7/External Interrupt (INT11) Enable Bits

0

1

0

1

0

1

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

P5.6/External Interrupt (INT10) Enable Bits

0

1

0

1

0

1

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

P5.5/External Interrupt (INT9) Enable Bits

0

1

0

1

0

1

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

P5.4/External Interrupt (INT8) Enable Bits

0

1

0

1

0

1

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

95

P5PND — Port 5 Interrupt Pending Register

FCH

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

ꢁ

.2

ꢁ

.1

ꢁ

.0

ꢁ

RESET Value

Read/Write

R/W

ꢁ

Addressing Mode

Register addressing mode only

.7

P5.7/External Interrupt (INT11) Pending Bit

0

1

Clear pending bit (when write)

P5.7/INT11 interrupt request is pending (when read)

.6

P5.6/External Interrupt (INT10) Pending Bit

0

1

Clear pending bit (when write)

P5.6/INT10 interrupt request is pending (when read)

.5

P5.5/External Interrupt (INT9) Pending Bit

0

1

Clear pending bit (when write)

P5.5/INT9 interrupt request is pending (when read)

.4

P5.4/External Interrupt (INT8) Pending Bit

0

1

Clear pending bit (when write)

P5.4/INT8 interrupt request is pending (when read)

.3–.0

Not used for the S3F82NB

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

96

P6CON — Port 6 Control Register

D2H

Set 1, Bank 0

Bit Identifier

.7

ꢁ

.6

ꢁ

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

0

R/W

ꢁ

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

Not used for the S3F82NB

P6.2/CIN2 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input mode, pull-up

Output mode, push-pull

Alternative function (CIN2)

.3–.2

.1–.0

P6.1/CIN1 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input mode, pull-up

Output mode, push-pull

Alternative function (CIN1)

P6.0/CIN0 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input mode, pull-up

Output mode, push-pull

Alternative function (CIN0)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

97

PG0CON — Port Group 0 Control Register

D0H

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P10.4–P10.7/SEG28–SEG31 Configuration Bits

0

1

0

1

0

1

Input mode

Input mode, pull-up

Output mode, push-pull

Alternative function (SEG28–SEG31)

P10.0–P10.3/SEG24–SEG27 Configuration Bits

0

1

0

1

0

1

Input mode

Input mode, pull-up

Output mode, push-pull

Alternative function (SEG24–SEG27)

P9.4–P9.7/SEG36–SEG39 Configuration Bits

0

1

0

1

0

1

Input mode

Input mode, pull-up

Output mode, push-pull

Alternative function (SEG36–SEG39)

P9.0–P9.3/SEG32–SEG35 Configuration Bits

0

1

0

1

0

1

Input mode

Input mode, pull-up

Output mode, push-pull

Alternative function (SEG32–SEG35)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

98

PG1CON — Port Group 1 Control Register

D1H

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

0

R/W

Addressing Mode

Register addressing mode only

.7–.6

.5–.4

.3–.2

.1–.0

P8.4–P8.7/SEG44–SEG47 Configuration Bits

0

1

0

1

0

1

Input mode

Input mode, pull-up

Output mode, push-pull

Alternative function (SEG44–SEG47)

P8.0–P8.3/SEG40–SEG43 Configuration Bits

0

1

0

1

0

1

Input mode

Input mode, pull-up

Output mode, push-pull

Alternative function (SEG40–SEG43)

P7.4–P7.7/SEG52–SEG55 Configuration Bits

0

1

0

1

0

1

Input mode

Input mode, pull-up

Output mode, push-pull

Alternative function (SEG52–SEG55)

P7.0–P7.3/SEG48–SEG51 Configuration Bits

0

1

0

1

0

1

Input mode

Input mode, pull-up

Output mode, push-pull

Alternative function (SEG48–SEG51)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

99

PP — Register Page Pointer

DFH

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.4

Destination Register Page Selection Bits

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Destination: page 0

Destination: page 1

Destination: page 2

Destination: page 3

Destination: page 4

Destination: page 5

Destination: page 6

Destination: page 7

Destination: page 8

Destination: page 9

Destination: page 10

Destination: page 11

Destination: page 12

Destination: page 13

Destination: page 14

Destination: page 15

.3 – .0

Source Register Page Selection Bits

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Source: page 0

Source: page 1

Source: page 2

Source: page 3

Source: page 4

Source: page 5

Source: page 6

Source: page 7

Source: page 8

Source: page 9

Source: page 10

Source: page 11

Source: page 12

Source: page 13

Source: page 14

Source: page 15

P R E L I M I N A R Y

PS031601-0813

S3F82NB

Product Specification

100

RP0 — Register Pointer 0

D6H

Set 1

Bit Identifier

.7

1

.6

1

.5

0

.4

0

.3

0

.2

ꢁ

.1

ꢁ

.0

ꢁ

RESET Value

Read/Write

R/W

ꢁ

Addressing Mode

Register addressing only

.7–.3

.2–.0

Register Pointer 0 Address Value

Register pointer 0 can independently point to one of the 256-byte working register

areas in the register file. Using the register pointers RP0 and RP1, you can select

two 8-byte register slices at one time as active working register space. After a reset,

RP0 points to address C0H in register set 1, selecting the 8-byte working register

slice C0H–C7H.

Not used for the S3F82NB

RP1 — Register Pointer 1

D7H

Set 1

Bit Identifier

.7

1

.6

1

.5

0

.4

0

.3

1

.2

ꢁ

.1

ꢁ

.0

ꢁ

RESET Value

Read/Write

R/W

ꢁ

Addressing Mode

Register addressing only

.7 – .3

Register Pointer 1 Address Value

Register pointer 1 can independently point to one of the 256-byte working register

areas in the register file. Using the register pointers RP0 and RP1, you can select

two 8-byte register slices at one time as active working register space. After a reset,

RP1 points to address C8H in register set 1, selecting the 8-byte working register

slice C8H–CFH.

.2 – .0

Not used for the S3F82NB

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

101

RESETID — Reset Source Indicating Register

B0H

Page 15

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

Read/Write

R/W

ꢁ

Addressing Mode

Register addressing mode only

Not used for the S3F82NB

nRESET Pin Indicating Bit

.7– .5

.4

0

1

Reset is not generated by nReset Pin (when read), cleared to ‘0’(when write)

Reset is generated by nReset Pin (when read), no effect (when write)

Not used for the S3F82NB

.3

.2

WDT Reset Indicating Bit

0

1

Reset is not generated by WDT (when read), cleared to ‘0’(when write)

Reset is generated by WDT (when read), no effect (when write)

LVR Reset Indicating Bit

.1

.0

0

1

Reset is not generated by LVR (when read), cleared to ‘0’(when write)

Reset is generated by LVR (when read), no effect (when write)

Not used for the S3F82NB

State of RESETID Depends on Reset Source

.7

ꢁ

.6

ꢁ

.5

ꢁ

.4

0

.3

ꢁ

.2

0

.1

1

.0

ꢁ

LVR

Note3

Note2

ꢁ

WDT, nRESET

NOTES:

1. To clear an indicating register, write “0” to indicating flag bit. Writing a “1” to a reset indicating flag (RESETID.1–.2 and .4)

has no effect.

2. Not effected by any other reset.

3. Bits corresponding to sources that are active at the time of reset will be set.

4. The RESETID.2–.1 are unknown values when a power-on reset occurs.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

102

SIOCON — SIO Control Register

F3H

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

0

R/W

Addressing Mode

Register addressing mode only

SIO Shift Clock Selection Bit

.7

.6

.5

.4

0

1

Internal clock (P.S clock)

External clock (SCK)

Data Direction Control Bit

0

1

MSB-first mode

LSB-first mode

SIO Mode Selection Bit

0

1

Receive-only mode

Transmit/Receive mode

Shift Clock Edge Selection Bit

0

1

Tx at falling edges, Rx at rising edges

Tx at rising edges, Rx at falling edges

SIO Counter Clear and Shift Start Bit

.3

.2

.1

.0

0

1

No action

Clear 3-bit counter and start shifting

SIO Shift Operation Enable Bit

0

1

Disable shifter and clock counter

Enable shifter and clock counter

SIO Interrupt Enable Bit

0

1

Disable SIO Interrupt

Enable SIO Interrupt

SIO Interrupt Pending Bit

0

1

No interrupt pending (when read), Clear pending condition (when write)

Interrupt is pending

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

103

SPH — Stack Pointer (High Byte)

D8H

Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

RESET Value

Read/Write

x

R/W

Addressing Mode

Register addressing mode only

.7–.0

Stack Pointer Address (High Byte)

The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer

address (SP15–SP8). The lower byte of the stack pointer value is located in register

SPL (D9H). The SP value is undefined following a reset.

SPL— Stack Pointer (Low Byte)

D9H

Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.0

Stack Pointer Address (Low Byte)

The low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer

address (SP7–SP0). The upper byte of the stack pointer value is located in register

SPH (D8H). The SP value is undefined following a reset.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

104

STPCON — Stop Control Register

FBH

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

0

R/W

Addressing Mode

Register addressing mode only

.7–.0

STOP Control Bits

1 0 1 0 0 1 0 1 Enable stop instruction

Other values Disable stop instruction

NOTE: Before execute the STOP instruction. You must set this STPCON register as “10100101b”. Otherwise the STOP

instruction will not execute as well as reset will be generated.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

105

SYM — System Mode Register

DEH

Set 1

Bit Identifier

.7

0

.6

ꢁ

.5

ꢁ

.4

x

.3

x

.2

x

.1

0

.0

0

RESET Value

Read/Write

R/W

ꢁ

Addressing Mode

Register addressing mode only

Not used, But you must keep “0”

Not used for the S3F82NB

.7

.6–.5

.4–.2

Fast Interrupt Level Selection Bits ⁽¹⁾

0

1

0

1

0

1

0

1

0

1

0

1

0

1

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

Fast Interrupt Enable Bit ⁽²⁾

.1

0

1

Disable fast interrupt processing

Enable fast interrupt processing

Global Interrupt Enable Bit ⁽³⁾

.0

0

1

Disable all interrupt processing

Enable all interrupt processing

NOTES:

1. You can select only one interrupt level at a time for fast interrupt processing.

2. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2–SYM.4.

3. Following a reset, you must enable global interrupt processing by executing an EI instruction

(not by writing a "1" to SYM.0).

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

106

T0CON — Timer 0 Control Register

E5H

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

ꢁ

RESET Value

Read/Write

0

R/W

ꢁ

Addressing Mode

Register addressing mode only

.7–.5

Timer 0 Input Clock Selection Bits

0

1

0

1

0

1

0

1

0

1

0

1

0

1

fxx/1024

fxx/256

fxx/64

fxx/8

fxx/1

External clock (T0CLK) falling edge

External clock (T0CLK) rising edge

Not available

.4–.3

Timer 0 Operating Mode Selection Bits

0

1

0

1

0

1

Interval mode (T0OUT)

Capture mode (Capture on rising edge, counter running, OVF can occur)

Capture mode (Capture on falling edge, counter running, OVF can occur)

PWM mode (OVF and match interrupt can occur)

.2

.1

.0

Timer 0 Counter Clear Bit

0

1

No effect

Clear the timer 0 counter (when write)

Timer 0 Counter Operating Enable Bit

0

1

Disable counting operation

Enable counting operation

Not used for the S3F82NB

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

107

TACON — Timer 1/A Control Register

EBH

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.5

Timer 1/A Input Clock Selection Bits

0

1

0

1

0

1

0

1

0

1

0

1

0

1

fxx/1024

fxx/256

fxx/64

fxx/8

fxx/1

External clock (T1CLK) falling edge

External clock (T1CLK) rising edge

Not available

.4–.3

Timer 1/A Operating Mode Selection Bits

0

1

0

1

0

1

Interval mode (T1OUT)

Capture mode (Capture on rising edge, counter running, OVF can occur)

Capture mode (Capture on falling edge, counter running, OVF can occur)

PWM mode (OVF and match interrupt can occur)

.2

.1

.0

Timer 1/A Counter Clear Bit

0

1

No effect

Clear the timer 1/A counter (when write)

Timer 1/A Match/Capture Interrupt Enable Bit

0

1

Disable counting operation

Enable counting operation

Timer 1/A Operating Mode Selection Bit

0

1

Two 8-bit timers mode (Timer A/B)

One 16-bit timer mode (Timer 1)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

108

TBCON — Timer B Control Register

EAH

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

ꢁ

.3

ꢁ

.2

0

.1

.0

ꢁ

RESET Value

Read/Write

0

R/W

ꢁ

Addressing Mode

Register addressing mode only

.7–.5

Timer B Input Clock Selection Bits

0

1

0

1

0

1

0

fxx/1024

fxx/256

fxx/64

0

1

0

fxx/8

fxx/1

Others

Not available

.4–.3

.2

Not used for the S3F82NB

Timer B Counter Clear Bit

0

1

No effect

Clear the timer B counter (when write)

.1

.0

Timer B Counter Operating Enable Bit

0

1

Disable counting operation

Enable counting operation

Not used for the S3F82NB

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

109

TINTCON — Timer Interrupt Control Register

EDH

Set 1, Bank 0

Bit Identifier

.7

ꢁ

.6

ꢁ

.5

ꢁ

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

ꢁ

Addressing Mode

Register addressing mode only

.7–.5

.4

Not used for the S3F82NB

Timer B Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

.3

.2

.1

.0

Timer 1/A Match/Capture Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

Timer 1/A Overflow Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

Timer 0 Match/Capture Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

Timer 0 Overflow Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

110

TINTPND — Timer Interrupt Pending Register

ECH

Set 1, Bank 0

Bit Identifier

.7

ꢁ

.6

ꢁ

.5

ꢁ

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

0

R/W

ꢁ

Addressing Mode

Register addressing mode only

.7–.5

.4

Not used for the S3F82NB

Timer B Interrupt Pending Bit

No interrupt pending (when read), clear pending bit (when write)

Interrupt is pending (when read)

0

1

.3

.2

.1

.0

Timer 1/A Match/Capture Interrupt Pending Bit

0

1

No interrupt pending (when read), clear pending bit (when write)

Interrupt is pending (when read)

Timer 1/A Overflow Interrupt Pending Bit

0

1

No interrupt pending (when read), clear pending bit (when write)

Interrupt is pending (when read)

Timer 0 Match/Capture Interrupt Pending Bit

0

1

No interrupt pending (when read), clear pending bit (when write)

Interrupt is pending (when read)

Timer 0 Overflow Interrupt Pending Bit

0

1

No interrupt pending (when read), clear pending bit (when write)

Interrupt is pending (when read)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

111

WTCON — Watch Timer Control Register

EEH

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

Watch Timer Clock Selection Bit

Main system clock divided by 2⁷(fxx/128)

0

1

Sub system clock (fxt)

.6

Watch Timer Interrupt Enable Bit

0

1

Disable watch timer interrupt

Enable watch timer interrupt

.5–.4

Buzzer Signal Selection Bits

0

1

0

1

0

1

0.5 kHz

1 kHz

2 kHz

4 kHz

.3–.2

Watch Timer Speed Selection Bits

0

1

0

1

0

1

Set watch timer interrupt to 0.5s

Set watch timer interrupt to 0.25s

Set watch timer interrupt to 0.125s

Set watch timer interrupt to 3.91ms

.1

.0

Watch Timer Enable Bit

0

1

Disable watch timer; Clear frequency dividing circuits

Enable watch timer

Watch Timer Interrupt Pending Bit

0

1

No interrupt pending (when read), clear pending bit (when write)

Interrupt is pending (when read)

NOTE: Watch timer clock frequency (fw) is assumed to be 32.768 kHz.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

112

5

INTERRUPT STRUCTURE

OVERVIEW

The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPU

recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has

more than one vector address, the vector priorities are established in hardware. A vector address can be

assigned to one or more sources.

Levels

Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks

can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight

possible interrupt levels: IRQ0–IRQ7, also called level 0–level 7. Each interrupt level directly corresponds to an

interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from

device to device. The S3F82NB interrupt structure recognizes eight interrupt levels.

The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just

identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is

determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR

settings lets you define more complex priority relationships between different levels.

Vectors

Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The

maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors used for

S3C8-series devices is always much smaller). If an interrupt level has more than one vector address, the vector

priorities are set in hardware. S3F82NB uses nineteen vectors.

Sources

A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow.

Each vector can have several interrupt sources. In the S3F82NB interrupt structure, there are nineteen possible

interrupt sources.

When a service routine starts, the respective pending bit should be either cleared automatically by hardware or

cleared "manually" by program software. The characteristics of the source's pending mechanism determine which

method would be used to clear its respective pending bit.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

113

INTERRUPT TYPES

The three components of the S3C8 interrupt structure described before — levels, vectors, and sources — are

combined to determine the interrupt structure of an individual device and to make full use of its available interrupt

logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3.

The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1):

Type 1:

Type 2:

Type 3:

One level (IRQn) + one vector (V₁) + one source (S₁)

One level (IRQn) + one vector (V₁) + multiple sources (S₁– S_n)

One level (IRQn) + multiple vectors (V₁– V_n) + multiple sources (S₁– S_n, S_n+1– S_n+m

)

In the S3F82NB microcontroller, two interrupt types are implemented.

Levels

Vectors

Sources

Type 1:

Type 2:

IRQn

V1

S1

IRQn

V1

S2

S3

Sn

V1

V2

V3

Vn

S1

Type 3:

NOTES:

S2

S3

Sn

Sn + 1

Sn + 2

Sn + m

1. The number of Sn and Vn value is expandable.

2. In the S3F82NB implementation, interrupt types

1 and 3 are used.

Figure 5-1. S3C8-Series Interrupt Types

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

114

S3F82NB INTERRUPT STRUCTURE

The S3F82NB microcontroller supports nineteen interrupt sources. All nineteen of the interrupt sources have a

corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device-specific

interrupt structure, as shown in Figure 5-2.

When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which

contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt

with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a single

level are fixed in hardware).

When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the

program counter value and status flags are pushed to stack. The starting address of the service routine is fetched

from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the

service routine is executed.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

115

Levels

Vectors

Sources

Reset/Clear

nRESET

IRQ0

100H

DAH

DCH

DEH

E0H

E2H

E4H

E6H

E8H

EAH

ECH

EEH

F0H

F2H

F4H

F6H

F8H

FAH

FCH

FEH

Basic Timer Overflow

Timer 0 Match/Capture

Timer 0 Overflow

Timer 1/A Match/Capture

Timer 1/A Overflow

H/W

S/W

H/W, S/W

S/W

H/W, S/W

S/W

IRQ1

IRQ2

IRQ3

IRQ4

Timer B Match

SIO Interrupt

Watch Timer Overflow

P1.0 External Interrupt

P1.1 External Interrupt

P1.2 External Interrupt

P1.3 External Interrupt

P1.4 External Interrupt

P1.5 External Interrupt

P1.6 External Interrupt

P1.7 External Interrupt

P5.4 External Interrupt

P5.5 External Interrupt

P5.6 External Interrupt

P5.7 External Interrupt

IRQ5

IRQ6

IRQ7

S/W

NOTES:

1. Within a given interrupt level, the low vector address has high priority.

For example, DAH has higher priority than DCH within the level IRQ0 the priorities

within each level are set at the factory.

2. External interrupts are triggered by a rising or falling edge, depending on the

corresponding control register setting.

Figure 5-2. S3F82NB Interrupt Structure

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INTERRUPT VECTOR ADDRESSES

All interrupt vector addresses for the S3F82NB interrupt structure are stored in the vector address area of the

internal 64-Kbyte ROM, 0H–FFFFH. (see Figure 5-3).

You can allocate unused locations in the vector address area as normal program memory. If you do so, please be

careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).

The program reset address in the ROM is 0100H.

The reset address of ROM can be changed by Smart Option in the S3F82NB (full-flash device). Refer to the

Chapter 18. Embedded Flash Memory Interface for more detailed contents.

(Decimal)

65,535

(Hex)

FFFFH

64K-bytes

Internal

Program

Memory Area

8FFH

FFH

Available

ISP Sector Area

255

0

Interrupt Vector Area

Smart Option

3FH

3CH

00H

Figure 5-3. ROM Vector Address Area

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Table 5-1. Interrupt Vectors

Interrupt Source

Vector Address

Request

Interrupt

Level

Reset

IRQ0

Reset/Clear

Decimal

Hex

Value

Priority in H/W

S/W

Value

256

218

220

222

224

226

228

230

232

234

236

238

240

242

244

246

248

250

252

254

Level

100H

DAH

DCH

DEH

E0H

E2H

E4H

E6H

E8H

EAH

ECH

EEH

F0H

F2H

F4H

F6H

F8H

FAH

FCH

FEH

Basic timer overflow

–

0

1

0

1

–

0

1

2

3

0

1

2

3

0

1

2

3

Timer 0 match/capture

Timer 0 overflow

3

Timer 1/A match/capture

Timer 1/A overflow

IRQ1

Timer B match

IRQ2

IRQ3

IRQ4

IRQ5

SIO interrupt

Watch timer overflow

P1.0 external interrupt

P1.1 external interrupt

P1.2 external interrupt

P1.3 external interrupt

P1.4 external interrupt

P1.5 external interrupt

P1.6 external interrupt

P1.7 external interrupt

P5.4 external interrupt

P5.5 external interrupt

P5.6 external interrupt

P5.7 external interrupt

IRQ6

IRQ7

NOTES:

1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.

2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority over

one with a higher vector address. The priorities within a given level are fixed in hardware.

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ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)

Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then

serviced as they occur according to the established priorities.

NOTE

The system initialization routine executed after a reset must always contain an EI instruction to globally

enable the interrupt structure.

During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable

interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register.

SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS

In addition to the control registers for specific interrupt sources, four system-level registers control interrupt

processing:

— The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.

— The interrupt priority register, IPR, controls the relative priorities of interrupt levels.

— The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to

each interrupt source).

— The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable

fast interrupts and control the activity of external interface, if implemented).

Table 5-2. Interrupt Control Register Overview

Control Register

ID

R/W

Function Description

Interrupt mask register

IMR

R/W

Bit settings in the IMR register enable or disable interrupt

processing for each of the eight interrupt levels: IRQ0–IRQ7.

Interrupt priority register

IPR

R/W

Controls the relative processing priorities of the interrupt levels.

The seven levels of S3F82NB are organized into three groups:

A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ2,

IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.

Interrupt request register

System mode register

IRQ

R

This register contains a request pending bit for each interrupt

level.

SYM

R/W

This register enables/disables fast interrupt processing,

dynamic global interrupt processing, and external interface

control (An external memory interface is implemented in the

S3F82NB microcontroller).

NOTE: Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended.

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INTERRUPT PROCESSING CONTROL POINTS

Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The

system-level control points in the interrupt structure are:

— Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0)

— Interrupt level enable/disable settings (IMR register)

— Interrupt level priority settings (IPR register)

— Interrupt source enable/disable settings in the corresponding peripheral control registers

NOTE

When writing an application program that handles interrupt processing, be sure to include the necessary

register file address (register pointer) information.

EI

S

R

Q

Interrupt Request Register

(Read-only)

Polling

Cycle

RESET

IRQ0-IRQ7,

Interrupts

Interrupt Priority

Register

Vector

Interrupt

Cycle

Interrupt Mask

Register

Global Interrupt Control (EI,

DI or SYM.0 manipulation)

Figure 5-4. Interrupt Function Diagram

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PERIPHERAL INTERRUPT CONTROL REGISTERS

For each interrupt source there is one or more corresponding peripheral control registers that let you control the

interrupt generated by the related peripheral (see Table 5-3).

Table 5-3. Interrupt Source Control and Data Registers

Interrupt Source

Interrupt Level

Register(s)

Location(s) in Set 1

Timer 0 match/capture

Timer 0 overflow

IRQ0

T0CON

T0CNT

T0DATA

E5H, bank 0

E3H, bank 0

E4H, bank 0

Timer 1/A match/capture

Timer 1/A overflow

IRQ1

IRQ2

IRQ3

TACON

TACNT

TADATA

EBH, bank 0

E7H, bank 0

E9H, bank 0

Timer B match

TBCON

TBCNT

TBDATA

EAH, bank 0

E6H, bank 0

E8H, bank 0

SIO interrupt

SIOCON

SIODATA

SIOPS

F3H, bank 0

F4H, bank 0

F5H, bank 0

Watch timer overflow

IRQ4

IRQ5

WTCON

EEH, bank 0

P1.0 external interrupt

P1.1 external interrupt

P1.2 external interrupt

P1.3 external interrupt

P1CONlL

P1INTL

P1PND

E5H, bank 1

E9H, bank 1

E7H, bank 1

P1.4 external interrupt

P1.5 external interrupt

P1.6 external interrupt

P1.7 external interrupt

IRQ6

IRQ7

P1CONH

P1INTH

P1PND

E4H, bank 1

E8H, bank 1

E7H, bank 1

P5.4 external interrupt

P5.5 external interrupt

P5.6 external interrupt

P5.7 external interrupt

P5CONH

P5INT

P5PND

FEH, bank 1

FBH, bank 1

FCH, bank 1

NOTE: If a interrupt is un-mask (Enable interrupt level) in the IMR register, the pending bit and enable bit of the interrupt

should be written after a DI instruction is executed.

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SYSTEM MODE REGISTER (SYM)

The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to

control fast interrupt processing (see Figure 5-5).

A reset clears SYM.1 and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4–SYM.2, is

undetermined.

The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0

value of the SYM register. In order to enable interrupt processing an Enable Interrupt (EI) instruction must be

included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly

to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions

for this purpose.

System Mode Register (SYM)

DEH, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Always logic "0"

Global interrupt enable bit: (3)

0 = Disable all interrupts processing

1 = Enable all interrupts processing

Fast interrupt level

selection bits: (1)

Fast interrupt enable bit: (2)

0 = Disable fast interrupts processing

1 = Enable fast interrupts processing

0 0 0 = IRQ0

0 0 1 = IRQ1

0 1 0 = IRQ2

0 1 1 = IRQ3

1 0 0 = IRQ4

1 0 1 = IRQ5

1 1 0 = IRQ6

1 1 1 = IRQ7

Not used for the S3F82NB

NOTES:

1. You can select only one interrupt level at a time for fast interrupt processing.

2. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt processing for the

interrupt level currently selected by SYM.2-SYM.4.

3. Following a reset, you must enable global interrupt processing by executing EI instruction

(not by writing a "1" to SYM.0)

Figure 5-5. System Mode Register (SYM)

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INTERRUPT MASK REGISTER (IMR)

The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual

interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required

settings by the initialization routine.

Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of

an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's

IMR bit to "1", interrupt processing for the level is enabled (not masked).

The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions

using the Register addressing mode.

Interrupt Mask Register (IMR)

DDH, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

Interrupt level enable :

0 = Disable (mask) interrupt level

1 = Enable (un-mask) interrupt level

NOTE:

Before IMR register is changed to any value, all interrupts must be disable.

Using DI instruction is recommended.

Figure 5-6. Interrupt Mask Register (IMR)

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INTERRUPT PRIORITY REGISTER (IPR)

The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in

the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be

written to their required settings by the initialization routine.

When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two

sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This

priority is fixed in hardware).

To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by

the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register

priority definitions (see Figure 5-7):

Group A

Group B

Group C

IRQ0, IRQ1

IRQ2, IRQ3, IRQ4

IRQ5, IRQ6, IRQ7

IPR

Group A

IPR

Group B

IPR

Group C

A1

A2

B1

B2

C1

C2

B21

IRQ2 IRQ3

B22

IRQ4

C21

IRQ5 IRQ6

C22

IRQ7

IRQ0

IRQ1

Figure 5-7. Interrupt Request Priority Groups

As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.

For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B"

would select the relationship C > B > A.

The functions of the other IPR bit settings are as follows:

— IPR.5 controls the relative priorities of group C interrupts.

— Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5,

6, and 7. IPR.6 defines the subgroup C relationship. IPR.5 controls the interrupt group C.

— IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.

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Interrupt Priority Register (IPR)

FFH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Group priority:

D7 D4 D1

Group A:

0 = IRQ0 > IRQ1

1 = IRQ1 > IRQ0

Group B:

0

1

0

1

0

1

0 = Undefined

1 = B > C > A

0 = A > B > C

1 = B > A > C

0 = C > A > B

1 = C > B > A

0 = A > C > B

1 = Undefined

0 = IRQ2 > (IRQ3, IRQ4)

1 = (IRQ3, IRQ4) > IRQ2

Subgroup B:

0 = IRQ3 > IRQ4

1 = IRQ4 > IRQ3

Group C:

0 = IRQ5 > (IRQ6, IRQ7)

1 = (IRQ6, IRQ7) > IRQ5

Subgroup C:

0 = IRQ6 > IRQ7

1 = IRQ7 > IRQ6

Figure 5-8. Interrupt Priority Register (IPR)

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INTERRUPT REQUEST REGISTER (IRQ)

You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all

levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number:

bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that

level. A "1" indicates that an interrupt request has been generated for that level.

IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the

IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific

interrupt levels. After a reset, all IRQ status bits are cleared to “0”.

You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing

is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can,

however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events

occurred while the interrupt structure was globally disabled.

Interrupt Request Register (IRQ)

DCH, Set 1, Read-only

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

Interrupt level request pending bits:

0 = Interrupt level is not pending

1 = Interrupt level is pending

Figure 5-9. Interrupt Request Register (IRQ)

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INTERRUPT PENDING FUNCTION TYPES

Overview

There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt

service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine.

Pending Bits Cleared Automatically by Hardware

For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding

pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting

to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine,

and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written

by application software.

In the S3F82NB interrupt structure, the timer 0 match/capture and overflow interrupt (IRQ0), the timer 1/A

match/capture and overflow interrupt (IRQ1), the timer B match interrupt (IRQ2), the SIO interrupt (IRQ3) belongs

to this category of interrupts in which pending condition is cleared automatically by hardware.

Pending Bits Cleared by the Service Routine

The second type of pending bit is the one that should be cleared by program software. The service routine must

clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be

written to the corresponding pending bit location in the source’s mode or control register.

ꢁ

ꢀ

Programming Tip — How to clear an interrupt pending bit

As the following examples are shown, a load instruction should be used to clear an interrupt pending bit.

Examples:

1.

2.

SB1

LD

P1PND, #11111011B

; Clear P1.2's interrupt pending bit

ꢈ

IRET

SB0

LD

TINTPND, #11111101B

; Clear timer 0 match/capture interrupt pending bit

ꢈ

IRET

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INTERRUPT SOURCE POLLING SEQUENCE

The interrupt request polling and servicing sequence is as follows:

1. A source generates an interrupt request by setting the interrupt request bit to "1".

2. The CPU polling procedure identifies a pending condition for that source.

3. The CPU checks the sources interrupt level.

4. The CPU generates an interrupt acknowledge signal.

5. Interrupt logic determines the interrupt's vector address.

6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).

7. The CPU continues polling for interrupt requests.

INTERRUPT SERVICE ROUTINES

Before an interrupt request is serviced, the following conditions must be met:

— Interrupt processing must be globally enabled (EI, SYM.0 = "1")

— The interrupt level must be enabled (IMR register)

— The interrupt level must have the highest priority if more than one levels are currently requesting service

— The interrupt must be enabled at the interrupt's source (peripheral control register)

When all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle.

The CPU then initiates an interrupt machine cycle that completes the following processing sequence:

1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.

2. Save the program counter (PC) and status flags to the system stack.

3. Branch to the interrupt vector to fetch the address of the service routine.

4. Pass control to the interrupt service routine.

When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores

the PC and status flags, setting SYM.0 to "1". It allows the CPU to process the next interrupt request.

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GENERATING INTERRUPT VECTOR ADDRESSES

The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that

correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence:

1. Push the program counter's low-byte value to the stack.

2. Push the program counter's high-byte value to the stack.

3. Push the FLAG register values to the stack.

4. Fetch the service routine's high-byte address from the vector location.

5. Fetch the service routine's low-byte address from the vector location.

6. Branch to the service routine specified by the concatenated 16-bit vector address.

NOTE

A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H–FFH.

NESTING OF VECTORED INTERRUPTS

It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this,

you must follow these steps:

1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).

2. Load the IMR register with a new mask value that enables only the higher priority interrupt.

3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it

occurs).

4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the

previous mask value from the stack (POP IMR).

5. Execute an IRET.

Depending on the application, you may be able to simplify the procedure above to some extent.

INSTRUCTION POINTER (IP)

The instruction pointer (IP) is adopted by all the S3C8-series microcontrollers to control the optional high-speed

interrupt processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The names of IP

registers are IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0).

FAST INTERRUPT PROCESSING

The feature called fast interrupt processing allows an interrupt within a given level to be completed in

approximately 6 clock cycles rather than the usual 16 clock cycles. To select a specific interrupt level for fast

interrupt processing, you write the appropriate 3-bit value to SYM.4–SYM.2. Then, to enable fast interrupt

processing for the selected level, you set SYM.1 to “1”.

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FAST INTERRUPT PROCESSING (Continued)

Two other system registers support fast interrupt processing:

— The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the

program counter values), and

— When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register

called FLAGS' (“FLAGS prime”).

NOTE

For the S3F82NB microcontroller, the service routine for any one of the eight interrupts levels: IRQ0–

IRQ7 can be selected for fast interrupt processing.

Procedure for Initiating Fast Interrupts

To initiate fast interrupt processing, follow these steps:

1. Load the start address of the service routine into the instruction pointer (IP).

2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2)

3. Write a "1" to the fast interrupt enable bit in the SYM register.

Fast Interrupt Service Routine

When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:

1. The contents of the instruction pointer and the PC are swapped.

2. The FLAG register values are written to the FLAGS' (“FLAGS prime”) register.

3. The fast interrupt status bit in the FLAGS register is set.

4. The interrupt is serviced.

5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction

pointer and PC values are swapped back.

6. The content of FLAGS' (“FLAGS prime”) is copied automatically back to the FLAGS register.

7. The fast interrupt status bit in FLAGS is cleared automatically.

Relationship to Interrupt Pending Bit Types

As described previously, there are two types of interrupt pending bits: One type that is automatically cleared by

hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared by the

application program's interrupt service routine. You can select fast interrupt processing for interrupts with either

type of pending condition clear function — by hardware or by software.

Programming Guidelines

Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the

SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing,

including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast

interrupt service routine ends.

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6

INSTRUCTION SET

OVERVIEW

The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8

microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the

instruction set include:

— A full complement of 8-bit arithmetic and logic operations, including multiply and divide

— No special I/O instructions (I/O control/data registers are mapped directly into the register file)

— Decimal adjustment included in binary-coded decimal (BCD) operations

— 16-bit (word) data can be incremented and decremented

— Flexible instructions for bit addressing, rotate, and shift operations

DATA TYPES

The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can

be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least

significant (right-most) bit.

REGISTER ADDRESSING

To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is

specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory

addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces."

ADDRESSING MODES

There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative

(RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please refer to

Section 3, "Addressing Modes."

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Table 6-1. Instruction Group Summary

Operands Instruction

Mnemonic

Load Instructions

CLR

dst

Clear

LD

dst,src

dst

Load

LDB

Load bit

LDE

Load external data memory

Load program memory

LDC

LDED

LDCD

LDEI

Load external data memory and decrement

Load program memory and decrement

Load external data memory and increment

Load program memory and increment

Load external data memory with pre-decrement

Load program memory with pre-decrement

Load external data memory with pre-increment

Load program memory with pre-increment

Load word

LDCI

LDEPD

LDCPD

LDEPI

LDCPI

LDW

POP

Pop from stack

POPUD

POPUI

PUSH

PUSHUD

PUSHUI

dst,src

src

Pop user stack (decrementing)

Pop user stack (incrementing)

Push to stack

dst,src

Push user stack (decrementing)

Push user stack (incrementing)

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Table 6-1. Instruction Group Summary (Continued)

Operands Instruction

Mnemonic

Arithmetic Instructions

ADC

ADD

CP

dst,src

Add with carry

Add

dst,src

dst

Compare

DA

Decimal adjust

Decrement

Decrement word

Divide

DEC

DECW

DIV

dst

dst,src

dst

INC

Increment

INCW

MULT

SBC

SUB

dst

Increment word

Multiply

dst,src

Subtract with carry

Subtract

Logic Instructions

AND

COM

OR

dst,src

dst

Logical AND

Complement

dst,src

Logical OR

XOR

Logical exclusive OR

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Table 6-1. Instruction Group Summary (Continued)

Operands Instruction

Mnemonic

Program Control Instructions

BTJRF

BTJRT

CALL

CPIJE

CPIJNE

DJNZ

ENTER

EXIT

IRET

JP

dst,src

dst

Bit test and jump relative on false

Bit test and jump relative on true

Call procedure

dst,src

r,dst

Compare, increment and jump on equal

Compare, increment and jump on non-equal

Decrement register and jump on non-zero

Enter

Exit

Interrupt return

Jump on condition code

Jump unconditional

Jump relative on condition code

dst

JP

JR

cc,dst

Return

WFI

Wait for interrupt

Bit Manipulation Instructions

BAND

BCP

BITC

BITR

BITS

BOR

BXOR

TCM

TM

dst,src

dst

Bit AND

Bit compare

Bit complement

Bit reset

dst

Bit set

dst,src

Bit OR

Bit XOR

Test complement under mask

Test under mask

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Table 6-1. Instruction Group Summary (Concluded)

Operands Instruction

Mnemonic

Rotate and Shift Instructions

RL

dst

Rotate left

RLC

RR

Rotate left through carry

Rotate right

RRC

SRA

SWAP

Rotate right through carry

Shift right arithmetic

Swap nibbles

CPU Control Instructions

CCF

DI

Complement carry flag

Disable interrupts

Enable interrupts

Enter Idle mode

No operation

EI

IDLE

NOP

RCF

SB0

SB1

SCF

Reset carry flag

Set bank 0

Set bank 1

Set carry flag

SRP

src

Set register pointers

Set register pointer 0

Set register pointer 1

Enter Stop mode

SRP0

SRP1

STOP

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FLAGS REGISTER (FLAGS)

The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these

bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and

FLAGS.2 are used for BCD arithmetic.

The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank

address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register

can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.

Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For

example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND

instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will

occur to the Flags register producing an unpredictable result.

System Flags Register (FLAGS)

D5H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Bank address

status flag (BA)

Carry flag (C)

First interrupt

status flag (FIS)

Zero flag (Z)

Sign flag (S)

Overflow (V)

Half-carry flag (H)

Decimal adjust flag (D)

Figure 6-1. System Flags Register (FLAGS)

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FLAG DESCRIPTIONS

C

Carry Flag (FLAGS.7)

The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to

the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the

specified register. Program instructions can set, clear, or complement the carry flag.

Z

Zero Flag (FLAGS.6)

For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For

operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is

logic zero.

S

V

D

Sign Flag (FLAGS.5)

Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the

result. A logic zero indicates a positive number and a logic one indicates a negative number.

Overflow Flag (FLAGS.4)

The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than

– 128. It is also cleared to "0" following logic operations.

Decimal Adjust Flag (FLAGS.3)

The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a

subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by

programmers, and cannot be used as a test condition.

H

Half-Carry Flag (FLAGS.2)

The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows

out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous

addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a

program.

FIS Fast Interrupt Status Flag (FLAGS.1)

The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing.

When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET

instruction is executed.

BA Bank Address Flag (FLAGS.0)

The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected,

bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0 instruction and

is set to "1" (select bank 1) when you execute the SB1 instruction.

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INSTRUCTION SET NOTATION

Flag

Table 6-2. Flag Notation Conventions

Description

C

Z

S

V

D

H

0

1

*

Carry flag

Zero flag

Sign flag

Overflow flag

Decimal-adjust flag

Half-carry flag

Cleared to logic zero

Set to logic one

Set or cleared according to operation

Value is unaffected

Value is undefined

–

x

Table 6-3. Instruction Set Symbols

Symbol

dst

src

@

Description

Destination operand

Source operand

Indirect register address prefix

Program counter

PC

IP

Instruction pointer

FLAGS

RP

#

Flags register (D5H)

Register pointer

Immediate operand or register address prefix

Hexadecimal number suffix

Decimal number suffix

Binary number suffix

H

D

B

opc

Opcode

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Table 6-4. Instruction Notation Conventions

Description Actual Operand Range

Notation

cc

r

Condition code

See list of condition codes in Table 6-6.

Rn (n = 0–15)

Working register only

rb

r0

rr

Bit (b) of working register

Rn.b (n = 0–15, b = 0–7)

Rn (n = 0–15)

Bit 0 (LSB) of working register

Working register pair

RRp (p = 0, 2, 4, ..., 14)

reg or Rn (reg = 0–255, n = 0–15)

reg.b (reg = 0–255, b = 0–7)

R

Register or working register

Bit 'b' of register or working register

Register pair or working register pair

Rb

RR

reg or RRp (reg = 0–254, even number only, where

p = 0, 2, ..., 14)

IA

Ir

Indirect addressing mode

addr (addr = 0–254, even number only)

@Rn (n = 0–15)

Indirect working register only

IR

Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)

Irr

Indirect working register pair only

@RRp (p = 0, 2, ..., 14)

IRR

Indirect register pair or indirect working

register pair

@RRp or @reg (reg = 0–254, even only, where

p = 0, 2, ..., 14)

X

Indexed addressing mode

#reg [Rn] (reg = 0–255, n = 0–15)

XS

Indexed (short offset) addressing mode

#addr [RRp] (addr = range –128 to +127, where

p = 0, 2, ..., 14)

xl

Indexed (long offset) addressing mode

#addr [RRp] (addr = range 0–65535, where

p = 0, 2, ..., 14)

da

ra

Direct addressing mode

Relative addressing mode

addr (addr = range 0–65535)

addr (addr = number in the range +127 to –128 that is

an offset relative to the address of the next instruction)

im

Immediate addressing mode

#data (data = 0–255)

iml

Immediate (long) addressing mode

#data (data = range 0–65535)

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Table 6-5. Opcode Quick Reference

OPCODE MAP

LOWER NIBBLE (HEX)

–

0

1

2

3

4

5

6

7

DEC

R1

DEC

IR1

ADD

r1,r2

ADD

r1,Ir2

ADD

R2,R1

ADD

IR2,R1

ADD

R1,IM

BOR

r0–Rb

U

P

E

R

RLC

R1

RLC

IR1

ADC

r1,r2

ADC

r1,Ir2

ADC

R2,R1

ADC

IR2,R1

ADC

R1,IM

BCP

r1.b, R2

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

INC

R1

INC

IR1

SUB

r1,r2

SUB

r1,Ir2

SUB

R2,R1

SUB

IR2,R1

SUB

R1,IM

BXOR

r0–Rb

JP

IRR1

SRP/0/1

IM

SBC

r1,r2

SBC

r1,Ir2

SBC

R2,R1

SBC

IR2,R1

SBC

R1,IM

BTJR

r2.b, RA

DA

R1

DA

IR1

OR

r1,r2

OR

r1,Ir2

OR

R2,R1

OR

IR2,R1

OR

R1,IM

LDB

r0–Rb

POP

R1

POP

IR1

AND

r1,r2

AND

r1,Ir2

AND

R2,R1

AND

IR2,R1

AND

R1,IM

BITC

r1.b

COM

R1

COM

IR1

TCM

r1,r2

TCM

r1,Ir2

TCM

R2,R1

TCM

IR2,R1

TCM

R1,IM

BAND

r0–Rb

N

I

PUSH

R2

PUSH

IR2

TM

r1,r2

TM

r1,Ir2

TM

R2,R1

TM

IR2,R1

TM

R1,IM

BIT

r1.b

DECW

RR1

DECW

IR1

PUSHUD PUSHUI

IR1,R2

MULT

R2,RR1

MULT

IR2,RR1

MULT

IM,RR1

LD

r1, x, r2

B

L

E

IR1,R2

RL

R1

RL

IR1

POPUD

IR2,R1

POPUI

IR2,R1

DIV

R2,RR1

DIV

IR2,RR1

DIV

IM,RR1

LD

r2, x, r1

INCW

RR1

INCW

IR1

CP

r1,r2

CP

r1,Ir2

CP

R2,R1

CP

IR2,R1

CP

R1,IM

LDC

r1, Irr2, xL

CLR

R1

CLR

IR1

XOR

r1,r2

XOR

r1,Ir2

XOR

R2,R1

XOR

IR2,R1

XOR

R1,IM

LDC

r2, Irr2, xL

RRC

R1

RRC

IR1

CPIJE

Ir,r2,RA

LDC

r1,Irr2

LDW

LD

r1, Ir2

RR2,RR1 IR2,RR1 RR1,IML

SRA

R1

SRA

IR1

CPIJNE

Irr,r2,RA

LDC

r2,Irr1

CALL

IA1

LD

IR1,IM

LD

Ir1, r2

H

E

X

RR

R1

RR

IR1

LDCD

r1,Irr2

LDCI

r1,Irr2

LD

R2,R1

LD

R2,IR1

LD

R1,IM

LDC

r1, Irr2, xs

SWAP

R1

SWAP

IR1

LDCPD

r2,Irr1

LDCPI

r2,Irr1

CALL

IRR1

LD

IR2,R1

CALL

DA1

LDC

r2, Irr1, xs

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Table 6-5. Opcode Quick Reference (Continued)

OPCODE MAP

LOWER NIBBLE (HEX)

–

0

8

9

A

B

C

D

E

F

U

P

E

R

LD

r1,R2

LD

r2,R1

DJNZ

r1,RA

JR

cc,RA

LD

r1,IM

JP

cc,DA

INC

r1

EXIT

WFI

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

ꢉ

SB0

SB1

N

I

IDLE

STOP

DI

B

L

E

EI

RET

IRET

RCF

SCF

CCF

NOP

H

E

X

LD

r1,R2

LD

r2,R1

DJNZ

r1,RA

JR

cc,RA

LD

r1,IM

JP

cc,DA

INC

r1

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CONDITION CODES

The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under

which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal"

after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.

The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump

instructions.

Table 6-6. Condition Codes

Binary

Mnemonic

Description

Always false

Flags Set

0000

1000

F

–

T

Always true

–

0111 ^(note)

1111 ^(note)

0110 ^(note)

1110 ^(note)

1101

C

Carry

C = 1

C = 0

Z = 1

Z = 0

S = 0

S = 1

V = 1

V = 0

Z = 1

Z = 0

NC

Z

No carry

Zero

NZ

PL

MI

OV

Not zero

Plus

0101

Minus

0100

Overflow

1100

NOV

EQ

No overflow

Equal

0110 ^(note)

1110 ^(note)

1001

NE

Not equal

GE

Greater than or equal

Less than

(S XOR V) = 0

(S XOR V) = 1

(Z OR (S XOR V)) = 0

(Z OR (S XOR V)) = 1

C = 0

0001

LT

1010

GT

Greater than

Less than or equal

Unsigned greater than or equal

Unsigned less than

Unsigned greater than

Unsigned less than or equal

0010

LE

1111 ^(note)

0111 ^(note)

1011

UGE

ULT

UGT

ULE

C = 1

(C = 0 AND Z = 0) = 1

(C OR Z) = 1

0011

NOTES:

1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For

example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;

after a CP instruction, however, EQ would probably be used.

2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.

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INSTRUCTION DESCRIPTIONS

This section contains detailed information and programming examples for each instruction in the SAM8

instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The

following information is included in each instruction description:

— Instruction name (mnemonic)

— Full instruction name

— Source/destination format of the instruction operand

— Shorthand notation of the instruction's operation

— Textual description of the instruction's effect

— Specific flag settings affected by the instruction

— Detailed description of the instruction's format, execution time, and addressing mode(s)

— Programming example(s) explaining how to use the instruction

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ADC — Add with Carry

ADC

dst,src

Operation:

dst

ꢄ

dst

+

src

+

c

The source operand, along with the setting of the carry flag, is added to the destination operand

and the sum is stored in the destination. The contents of the source are unaffected. Two's-

complement addition is performed. In multiple precision arithmetic, this instruction permits the

carry from the addition of low-order operands to be carried into the addition of high-order

operands.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result

is of the opposite sign; cleared otherwise.

D: Always cleared to "0".

H: Set if there is a carry from the most significant bit of the low-order four bits of the result;

cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

12

13

r

lr

dst

src

3

6

14

15

R

IR

dst

6

16

R

IM

Examples:

Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register

03H = 0AH:

ADC R1,R2

ꢅ

R1

=

14H, R2

1BH, R2

=

03H

ADC R1,@R2

ADC 01H,02H

ADC 01H,@02H

ADC 01H,#11H

Register 01H

=

24H, register 02H

2BH, register 02H

32H

=

03H

In the first example, destination register R1 contains the value 10H, the carry flag is set to "1",

and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds

03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.

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ADD — Add

ADD

dst,src

Operation:

dst

ꢄ

dst

+

src

The source operand is added to the destination operand and the sum is stored in the destination.

The contents of the source are unaffected. Two's-complement addition is performed.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the

result is of the opposite sign; cleared otherwise.

D: Always cleared to "0".

H: Set if a carry from the low-order nibble occurred.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

02

03

r

lr

dst

src

3

6

04

05

R

IR

dst

6

06

R

IM

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

ADD R1,R2

ꢅ

R1

=

15H, R2

1CH, R2

=

03H

ADD R1,@R2

ADD 01H,02H

ADD 01H,@02H

ADD 01H,#25H

=

Register 01H

=

24H, register 02H

2BH, register 02H

46H

=

03H

In the first example, destination working register R1 contains 12H and the source working register

R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in

register R1.

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AND — Logical AND

AND

dst,src

dst

The source operand is logically ANDed with the destination operand. The result is stored in the

Operation:

ꢄ

dst AND src

destination. The AND operation results in a "1" bit being stored whenever the corresponding bits

in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the

source are unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always cleared to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

52

53

r

lr

dst

src

3

6

54

55

R

IR

dst

6

56

R

IM

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

AND R1,R2

ꢅ

R1

=

02H, R2

=

03H

AND R1,@R2

AND 01H,02H

AND 01H,@02H

AND 01H,#25H

02H, R2 = 03H

Register 01H

=

01H, register 02H

00H, register 02H

21H

=

03H

In the first example, destination working register R1 contains the value 12H and the source

working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source

operand 03H with the destination operand value 12H, leaving the value 02H in register R1.

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BAND — Bit AND

BAND

dst,src.b

BAND

dst.b,src

Operation:

dst(0)

dst(b)

ꢄ

dst(0) AND src(b)

dst(b) AND src(0)

or

ꢄ

The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of

the destination (or source). The resultant bit is stored in the specified bit of the destination. No

other bits of the destination are affected. The source is unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

3

6

67

r0 Rb

dst | b | 0

src | b | 1

3

6

67

Rb

r0

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits,

the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1 = 07H and register 01H = 05H:

BAND R1,01H.1

BAND 01H.1,R1

ꢅ

R1

=

06H, register 01H = 05H

05H, R1 07H

Register 01H

=

In the first example, source register 01H contains the value 05H (00000101B) and destination

working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit

1 value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the

value 06H (00000110B) in register R1.

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BCP — Bit Compare

BCP

dst,src.b

Operation:

dst(0) – src(b)

The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.

The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both

operands are unaffected by the comparison.

Flags:

C: Unaffected.

Z: Set if the two bits are the same; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

3

6

17

r0 Rb

dst | b | 0

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is

three bits, and the LSB address value is one bit in length.

Example:

Given: R1

=

07H and register 01H

R1

=

01H:

BCP R1,01H.1

ꢅ

=

07H, register 01H

=

01H

If destination working register R1 contains the value 07H (00000111B) and the source register

01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of

the source register (01H) and bit zero of the destination register (R1). Because the bit values are

not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).

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BITC — Bit Complement

BITC

dst.b

Operation:

dst(b) ꢄ NOT dst(b)

This instruction complements the specified bit within the destination without affecting any other

bits in the destination.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

2

4

57

rb

dst | b | 0

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'

is three bits, and the LSB address value is one bit in length.

Example:

Given: R1

=

07H

BITC R1.1

ꢅ

R1

=

05H

If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1"

complements bit one of the destination and leaves the value 05H (00000101B) in register R1.

Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is

cleared.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

149

BITR— Bit Reset

BITR

dst.b

Operation:

dst(b)

ꢄ

0

The BITR instruction clears the specified bit within the destination without affecting any other bits

in the destination.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

2

4

77

rb

dst | b | 0

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'

is three bits, and the LSB address value is one bit in length.

Example:

Given: R1

=

07H:

BITR R1.1

ꢅ

R1

=

05H

If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit

one of the destination register R1, leaving the value 05H (00000101B).

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

150

BITS— Bit Set

BITS

dst.b

Operation:

dst(b)

ꢄ

1

The BITS instruction sets the specified bit within the destination without affecting any other bits in

the destination.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

2

4

77

rb

dst | b | 1

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'

is three bits, and the LSB address value is one bit in length.

Example:

Given: R1

=

07H:

BITS R1.3

ꢅ

R1

=

0FH

If working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit

three of the destination register R1 to "1", leaving the value 0FH (00001111B).

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

151

BOR— Bit OR

BOR

dst,src.b

BOR

dst.b,src

Operation:

dst(0)

dst(b)

ꢄ

dst(0) OR src(b)

dst(b) OR src(0)

or

ꢄ

The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the

destination (or the source). The resulting bit value is stored in the specified bit of the destination.

No other bits of the destination are affected. The source is unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

3

6

07

r0 Rb

dst | b | 0

src | b | 1

3

6

07

Rb

r0

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits,

the bit address 'b' is three bits, and the LSB address value is one bit.

Examples:

Given: R1

=

07H and register 01H

=

03H:

BOR R1, 01H.1

BOR 01H.2, R1

ꢅ

R1 = 07H, register 01H = 03H

Register 01H = 07H, R1 = 07H

In the first example, destination working register R1 contains the value 07H (00000111B) and

source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs

bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value

(07H) in working register R1.

In the second example, destination register 01H contains the value 03H (00000011B) and the

source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically

ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H

in register 01H.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

152

BTJRF — Bit Test, Jump Relative on False

BTJRF

dst,src.b

Operation:

If src(b) is a "0", then PC

ꢄ

PC

+

dst

The specified bit within the source operand is tested. If it is a "0", the relative address is added to

the program counter and control passes to the statement whose address is now in the PC;

otherwise, the instruction following the BTJRF instruction is executed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

(Note 1)

opc

dst

3

10

37

RA rb

src | b | 0

NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is

three bits, and the LSB address value is one bit in length.

Example:

Given: R1

=

07H:

BTJRF SKIP,R1.3

ꢅ

PC jumps to SKIP location

If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3"

tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the

memory location pointed to by the SKIP. (Remember that the memory location must be within the

allowed range of + 127 to – 128.)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

153

BTJRT— Bit Test, Jump Relative on True

BTJRT

dst,src.b

Operation:

If src(b) is a "1", then PC

ꢄ

PC

+

dst

The specified bit within the source operand is tested. If it is a "1", the relative address is added to

the program counter and control passes to the statement whose address is now in the PC;

otherwise, the instruction following the BTJRT instruction is executed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

(Note 1)

opc

dst

3

10

37

RA rb

src | b | 1

NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is

three bits, and the LSB address value is one bit in length.

Example:

Given: R1

=

07H:

BTJRT

SKIP,R1.1

If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1"

tests bit one in the source register (R1). Because it is a "1", the relative address is added to the

PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the

memory location must be within the allowed range of + 127 to – 128.)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

154

BXOR— Bit XOR

BXOR

dst,src.b

BXOR

dst.b,src

Operation:

dst(0)

dst(b)

ꢄ

dst(0) XOR src(b)

dst(b) XOR src(0)

or

ꢄ

The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB)

of the destination (or source). The result bit is stored in the specified bit of the destination. No

other bits of the destination are affected. The source is unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

3

6

27

r0 Rb

dst | b | 0

src | b | 1

3

6

27

Rb

r0

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits,

the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1

=

07H (00000111B) and register 01H

=

03H (00000011B):

BXOR R1,01H.1

BXOR 01H.2,R1

ꢅ

R1

=

06H, register 01H

07H, R1

=

03H

07H

Register 01H

=

In the first example, destination working register R1 has the value 07H (00000111B) and source

register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusive-ORs

bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in

bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is

unaffected.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

155

CALL— Call Procedure

CALL

dst

Operation:

SP

@SP

SP

@SP

PC

ꢄ

SP – 1

PCL

SP –1

PCH

dst

The current contents of the program counter are pushed onto the top of the stack. The program

counter value used is the address of the first instruction following the CALL instruction. The

specified destination address is then loaded into the program counter and points to the first

instruction of a procedure. At the end of the procedure the return instruction (RET) can be used

to return to the original program flow. RET pops the top of the stack back into the program

counter.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

3

14

F6

F4

D4

DA

IRR

IA

dst

2

12

14

Examples:

Given: R0

=

35H, R1 = 21H, PC

SP 0000H

(Memory locations 0000H

=

1A47H, and SP

=

0002H:

CALL 3521H ꢅ

=

1AH, 0001H

=

4AH, where

4AH is the address that follows the instruction.)

SP = 0000H (0000H 1AH, 0001H 49H)

SP 0000H (0000H 1AH, 0001H 49H)

CALL @RR0 ꢅ

=

CALL #40H

ꢅ

=

In the first example, if the program counter value is 1A47H and the stack pointer contains the

value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the

stack. The stack pointer now points to memory location 0000H. The PC is then loaded with the

value 3521H, the address of the first instruction in the program sequence to be executed.

If the contents of the program counter and stack pointer are the same as in the first example, the

statement "CALL @RR0" produces the same result except that the 49H is stored in stack

location 0001H (because the two-byte instruction format was used). The PC is then loaded with

the value 3521H, the address of the first instruction in the program sequence to be executed.

Assuming that the contents of the program counter and stack pointer are the same as in the first

example, if program address 0040H contains 35H and program address 0041H contains 21H, the

PS031601-0813

P R E L I M I N A R Y

statement "CALL #40H" produces the same result as in the second example

S3F82NB

Product Specification

156

CCF— Complement Carry Flag

CCF

Operation:

C

ꢄ

NOT

The carry flag (C) is complemented. If C

zero; if C "0", the value of the carry flag is changed to logic one.

C

=

"1", the value of the carry flag is changed to logic

=

Flags:

C: Complemented.

No other flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

EF

Example:

Given: The carry flag

CCF

=

"0":

If the carry flag

=

"0", the CCF instruction complements it in the FLAGS register (0D5H),

changing its value from logic zero to logic one.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

157

CLR— Clear

CLR

dst

Operation:

dst

ꢄ

"0"

The destination location is cleared to "0".

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

B0

B1

R

IR

Examples:

Given: Register 00H

=

4FH, register 01H

=

02H, and register 02H

=

5EH:

CLR

00H

ꢅ

Register 00H

Register 01H

=

00H

02H, register 02H

@01H ꢅ

=

00H

In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H

value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR)

addressing mode to clear the 02H register value to 00H.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

158

COM— Complement

COM

dst

Operation:

dst

ꢄ

NOT dst

The contents of the destination location are complemented (one's complement); all "1s" are

changed to "0s", and vice-versa.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always reset to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

R

opc

dst

2

4

60

61

IR

Examples:

Given: R1

=

07H and register 07H

=

0F1H:

COM R1

ꢅ

R1

=

0F8H

07H, register 07H

COM @R1

=

0EH

In the first example, destination working register R1 contains the value 07H (00000111B). The

statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros,

and vice-versa, leaving the value 0F8H (11111000B).

In the second example, Indirect Register (IR) addressing mode is used to complement the value

of destination register 07H (11110001B), leaving the new value 0EH (00001110B).

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

159

CP— Compare

CP

dst,src

Operation:

dst – src

The source operand is compared to (subtracted from) the destination operand, and the

appropriate flags are set accordingly. The contents of both operands are unaffected by the

comparison.

Flags:

C: Set if a "borrow" occurred (src > dst); cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

A2

A3

r

lr

dst

3

6

A4

A5

R

IR

dst

src

6

A6

R

IM

Examples:

1. Given: R1

CP

=

02H and R2

=

03H:

R1,R2 ꢅ

Set the C and S flags

Destination working register R1 contains the value 02H and source register R2 contains the value

03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value

(destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are

"1".

2. Given: R1 = 05H and R2 = 0AH:

CP

JP

R1,R2

UGE,SKIP

R1

INC

SKIP LD

R3,R1

In this example, destination working register R1 contains the value 05H which is less than the

contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1"

and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1"

executes, the value 06H remains in working register R3.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

160

CPIJE— Compare, Increment, and Jump on Equal

CPIJE

dst,src,RA

Operation:

If dst – src

=

"0", PC

ꢄ

PC

+

RA

Ir

ꢄ

Ir

+

1

The source operand is compared to (subtracted from) the destination operand. If the result is "0",

the relative address is added to the program counter and control passes to the statement whose

address is now in the program counter. Otherwise, the instruction immediately following the

CPIJE instruction is executed. In either case, the source pointer is incremented by one before the

next instruction is executed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src dst

RA

3

12

C2

r

Ir

NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.

Example:

Given: R1

=

02H, R2

=

03H, and register 03H

=

02H:

CPIJE R1,@R2,SKIP ꢅ

R2 04H, PC jumps to SKIP location

=

In this example, working register R1 contains the value 02H, working register R2 the value 03H,

and register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value

02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the

relative address is added to the PC and the PC then jumps to the memory location pointed to by

SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that

the memory location must be within the allowed range of + 127 to – 128.)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

161

CPIJNE— Compare, Increment, and Jump on Non-Equal

CPIJNE

dst,src,RA

Operation:

If dst – src

"0", PC

+ 1

ꢄ

PC

+

RA

Ir

ꢄ

Ir

The source operand is compared to (subtracted from) the destination operand. If the result is not

"0", the relative address is added to the program counter and control passes to the statement

whose address is now in the program counter; otherwise the instruction following the CPIJNE

instruction is executed. In either case the source pointer is incremented by one before the next

instruction.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src dst

RA

3

12

D2

r

Ir

NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.

Example:

Given: R1

=

02H, R2

=

03H, and register 03H

=

04H:

CPIJNER1,@R2,SKIP ꢅ

R2 04H, PC jumps to SKIP location

=

Working register R1 contains the value 02H, working register R2 (the source pointer) the value

03H, and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts

04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal, the

relative address is added to the PC and the PC then jumps to the memory location pointed to by

SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H.

(Remember that the memory location must be within the allowed range of + 127 to – 128.)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

162

DA— Decimal Adjust

DA

dst

Operation:

dst

ꢄ

DA dst

The destination operand is adjusted to form two 4-bit BCD digits following an addition or

subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table

indicates the operation performed. (The operation is undefined if the destination operand was not

the result of a valid addition or subtraction of BCD digits):

Instruction

Carry

Before DA

Bits 4–7

Value (Hex)

H Flag

Before DA

Bits 0–3

Value (Hex)

Number Added

to Byte

Carry

After DA

0

1

0

1

0–9

0–8

0–9

A–F

9–F

A–F

0–2

0–3

0–9

0–8

7–F

6–F

0

1

0

1

0

1

0

1

0

1

0–9

A–F

0–3

0–9

A–F

0–3

0–9

A–F

0–3

0–9

6–F

0–9

6–F

00

06

60

66

60

66

0

1

0

1

ADD

ADC

00

FA

A0

9A

=

– 00

– 06

– 60

– 66

SUB

SBC

Flags:

C: Set if there was a carry from the most significant bit; cleared otherwise (see table).

Z: Set if result is "0"; cleared otherwise.

S: Set if result bit 7 is set; cleared otherwise.

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

40

41

R

IR

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

163

DA— Decimal Adjust

DA

(Continued)

Example:

Given: Working register R0 contains the value 15 (BCD), working register R1 contains

27 (BCD), and address 27H contains 46 (BCD):

ADD

DA

R1,R0

R1

;

C ꢄ "0", H ꢄ "0", Bits 4–7 = 3, bits 0–3 = C, R1 ꢄ 3CH

R1 ꢄ 3CH + 06

If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is

incorrect, however, when the binary representations are added in the destination location using

standard binary arithmetic:

0 0 0 1

+ 0 0 1 0

0 1 0 1

0 1 1 1

15

27

0 0 1 1

1 1 0 0 =

3CH

The DA instruction adjusts this result so that the correct BCD representation is obtained:

0 0 1 1

+ 0 0 0 0

1 1 0 0

0 1 1 0

0 1 0 0

0 0 1 0 =

42

Assuming the same values given above, the statements

SUB

DA

27H,R0 ;

@R1

C ꢄ "0", H ꢄ "0", Bits 4–7 = 3, bits 0–3 = 1

@R1 ꢄ 31–0

;

leave the value 31 (BCD) in address 27H (@R1).

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

164

DEC— Decrement

DEC

dst

Operation:

dst

ꢄ

dst – 1

The contents of the destination operand are decremented by one.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

R

opc

dst

2

4

00

01

IR

Examples:

Given: R1

=

03H and register 03H

=

10H:

0FH

DEC R1

ꢅ

R1

=

02H

DEC @R1

Register 03H

=

In the first example, if working register R1 contains the value 03H, the statement "DEC R1"

decrements the hexadecimal value by one, leaving the value 02H. In the second example, the

statement "DEC @R1" decrements the value 10H contained in the destination register 03H by

one, leaving the value 0FH.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

165

DECW— Decrement Word

DECW

dst

Operation:

dst

ꢄ

dst – 1

The contents of the destination location (which must be an even address) and the operand

following that location are treated as a single 16-bit value that is decremented by one.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

8

80

81

RR

IR

Examples:

Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:

DECW RR0

DECW @R2

ꢅ

R0

=

12H, R1

=

33H

Register 30H

=

0FH, register 31H

=

20H

In the first example, destination register R0 contains the value 12H and register R1 the value

34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word

and decrements the value of R1 by one, leaving the value 33H.

NOTE:

A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW

instruction. To avoid this problem, we recommend that you use DECW as shown in the following

example:

LOOP: DECW RR0

LD

OR

JR

R2,R1

R2,R0

NZ,LOOP

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

166

DI— Disable Interrupts

DI

Operation:

SYM (0)

ꢄ

0

Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all

interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits,

but the CPU will not service them while interrupt processing is disabled.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

8F

Example:

Given: SYM

DI

=

01H:

If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the

register and clears SYM.0 to "0", disabling interrupt processing.

Before changing IMR, interrupt pending and interrupt source control register, be sure DI state.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

167

DIV— Divide (Unsigned)

DIV

dst,src

Operation:

dst

÷

src

dst (UPPER)

dst (LOWER)

ꢄ

REMAINDER

QUOTIENT

The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits)

is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of

8

the destination. When the quotient is ꢇ 2 , the numbers stored in the upper and lower halves of

the destination for quotient and remainder are incorrect. Both operands are treated as unsigned

integers.

Flags:

C: Set if the V flag is set and quotient is between 2⁸and 2⁹–1; cleared otherwise.

Z: Set if divisor or quotient

S: Set if MSB of quotient

=

"0"; cleared otherwise.

"1"; cleared otherwise.

=

V: Set if quotient is

D: Unaffected.

H: Unaffected.

ꢇ

2⁸or if divisor

=

"0"; cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src

dst

3

26/10

94

95

96

RR

R

RR

IR

IM

NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles.

Examples:

Given: R0

=

10H, R1

=

03H, R2

=

40H, register 40H

=

80H:

DIV

RR0,R2

ꢅ

R0

=

03H, R1

=

40H

20H

80H

RR0,@R2

RR0,#20H

In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H

(R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit

RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the

value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination

register RR0 (R0) and the quotient in the lower half (R1).

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

168

DJNZ— Decrement and Jump if Non-Zero

DJNZ

r,dst

Operation:

r

ꢄ

r

–

1

If

r

ꢊ 0, PC

ꢄ

PC

+

dst

The working register being used as a counter is decremented. If the contents of the register are

not logic zero after decrementing, the relative address is added to the program counter and

control passes to the statement whose address is now in the PC. The range of the relative

address is +127 to –128, and the original value of the PC is taken to be the address of the

instruction byte following the DJNZ statement.

NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at

the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

r

|

opc

dst

2

8 (jump taken)

8 (no jump)

rA

RA

r = 0 to F

Example:

Given: R1

=

02H and LOOP is the label of a relative address:

#0C0H

SRP

DJNZ R1,LOOP

DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the

destination operand instead of a numeric relative address value. In the example, working register

R1 contains the value 02H, and LOOP is the label for a relative address.

The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H.

Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative

address specified by the LOOP label.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

169

EI— Enable Interrupts

EI

Operation:

SYM (0)

ꢄ

1

An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to

be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was

set while interrupt processing was disabled (by executing a DI instruction), it will be serviced

when you execute the EI instruction.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

9F

Example:

Given: SYM

EI

=

00H:

If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the

statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for

global interrupt processing.)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

170

ENTER— Enter

ENTER

Operation:

SP

@SP

IP

PC

IP

ꢄ

SP – 2

IP

PC

@IP

IP + 2

This instruction is useful when implementing threaded-code languages. The contents of the

instruction pointer are pushed to the stack. The program counter (PC) value is then written to the

instruction pointer. The program memory word that is pointed to by the instruction pointer is

loaded into the PC, and the instruction pointer is incremented by two.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

14

1F

Example:

The diagram below shows one example of how to use an ENTER statement.

Before

After

Data

Address

IP

Data

Address

IP

0050

0040

0022

0043

0110

0020

Address

Data

1F

Address

40 Enter

Data

1F

PC

SP

40 Enter

PC

SP

41 Address H 01

42 Address L 10

43 Address H

41 Address H 01

42 Address L 10

43 Address H

20

21

22

00

50

IPH

IPL

Data

110 Routine

Memory

22

Data

Stack

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

171

EXIT— Exit

EXIT

Operation:

IP

ꢄ

@SP

SP

@IP

SP

PC

IP

+

2

IP

+

2

This instruction is useful when implementing threaded-code languages. The stack value is

popped and loaded into the instruction pointer. The program memory word that is pointed to by

the instruction pointer is then loaded into the program counter, and the instruction pointer is

incremented by two.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode (Hex)

opc

1

14 (internal stack)

16 (internal stack)

2F

Example:

The diagram below shows one example of how to use an EXIT statement.

Before

After

Data

Address

IP

Data

Address

IP

0050

0040

0022

0052

0060

0022

Address

Data

Address

60

Data

PC

SP

PC

SP

50 PCL old

51 PCH

60

00

Main

140 Exit

2F

20

21

22

00

50

IPH

IPL

Data

Memory

Data

22

Stack

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

172

IDLE— Idle Operation

IDLE

Operation:

The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle

mode can be released by an interrupt request (IRQ) or an external reset operation.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

1

4

6F

–

Example:

The instruction

IDLE

stops the CPU clock but not the system clock.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

173

INC— Increment

INC

dst

Operation:

dst

ꢄ

dst

+

1

The contents of the destination operand are incremented by one.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

|

opc

1

4

rE

r

r = 0 to F

opc

dst

2

4

20

21

R

IR

Examples:

Given: R0

=

1BH, register 00H

=

0CH, and register 1BH

=

0FH:

INC

R0

ꢅ

R0

Register 00H

R0 1BH, register 01H

=

1CH

00H

@R0

=

0DH

=

10H

In the first example, if destination working register R0 contains the value 1BH, the statement "INC

R0" leaves the value 1CH in that same register.

The next example shows the effect an INC instruction has on register 00H, assuming that it

contains the value 0CH.

In the third example, INC is used in Indirect Register (IR) addressing mode to increment the

value of register 1BH from 0FH to 10H.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

174

INCW— Increment Word

INCW

dst

Operation:

dst

ꢄ

dst

+

1

The contents of the destination (which must be an even address) and the byte following that

location are treated as a single 16-bit value that is incremented by one.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

RR

IR

opc

dst

2

8

A0

A1

Examples:

Given: R0

=

1AH, R1

=

02H, register 02H

1AH, R1 = 03H

Register 02H 10H, register 03H

=

0FH, and register 03H

=

0FFH:

INCW RR0

INCW @R1

ꢅ

R0

=

00H

In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H

in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the

value 03H in register R1. In the second example, the statement "INCW @R1" uses Indirect

Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to

00H and register 02H from 0FH to 10H.

NOTE:

A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an

INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the

following example:

LOOP:

INCW

LD

RR0

R2,R1

R2,R0

NZ,LOOP

OR

JR

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

175

IRET— Interrupt Return

IRET

IRET (Normal)

IRET (Fast)

Operation:

FLAGS

ꢄ

SP

@SP

SP

@SP

PC

FLAGS

FIS

ꢋ

IP

ꢄ

0

SP

PC

SP

ꢄ

+

1

FLAGS'

ꢄ

+

2

SYM(0)

ꢄ

1

This instruction is used at the end of an interrupt service routine. It restores the flag register and

the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the

fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast

interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine.

Flags:

All flags are restored to their original settings (that is, the settings before the interrupt occurred).

Format:

IRET

(Normal)

Bytes

Cycles

Opcode (Hex)

opc

1

10 (internal stack)

12 (internal stack)

BF

IRET

(Fast)

Bytes

Cycles

Opcode (Hex)

opc

1

6

BF

Example:

In the figure below, the instruction pointer is initially loaded with 100H in the main program before

interrupts are enabled. When an interrupt occurs, the program counter and instruction pointer are

swapped. This causes the PC to jump to address 100H and the IP to keep the return address.

The last instruction in the service routine normally is a jump to IRET at address FFH. This causes

the instruction pointer to be loaded with 100H "again" and the program counter to jump back to

the main program. Now, the next interrupt can occur and the IP is still correct at 100H.

0H

FFH

IRET

100H

Interrupt

Service

Routine

JP to FFH

FFFFH

NOTE:

In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay

attention to the order of the last two instructions. The IRET cannot be immediately proceeded by

a clearing of the interrupt status (as with a reset of the IPR register).

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

176

JP— Jump

JP

cc,dst

(Conditional)

JP

dst

(Unconditional)

Operation:

If cc is true, PC

ꢄ

dst

The conditional JUMP instruction transfers program control to the destination address if the

condition specified by the condition code (cc) is true; otherwise, the instruction following the JP

instruction is executed. The unconditional JP simply replaces the contents of the PC with the

contents of the specified register pair. Control then passes to the statement addressed by the

PC.

Flags:

No flags are affected.

Format: ⁽¹⁾

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

(2)

cc

|

opc

dst

3

8

ccD

DA

cc = 0 to F

opc

dst

2

8

30

IRR

NOTES:

1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.

2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the

opcode are both four bits.

Examples:

Given: The carry flag (C)

=

"1", register 00

LABEL_W

PC 0120H

=

01H, and register 01

=

20H:

JP

C,LABEL_W

@00H

ꢅ

=

1000H, PC

=

1000H

ꢅ

=

The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement

"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to

that location. Had the carry flag not been set, control would then have passed to the statement

immediately following the JP instruction.

The second example shows an unconditional JP. The statement "JP @00" replaces the

contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

177

JR— Jump Relative

JR

cc,dst

Operation:

If cc is true, PC

ꢄ

PC

+

dst

If the condition specified by the condition code (cc) is true, the relative address is added to the

program counter and control passes to the statement whose address is now in the program

counter; otherwise, the instruction following the JR instruction is executed. (See list of condition

codes).

The range of the relative address is +127, –128, and the original value of the program counter

is taken to be the address of the first instruction byte following the JR statement.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

(1)

dst

cc

|

opc

dst

2

6

ccB

RA

cc = 0 to F

NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each

four bits.

Example:

Given: The carry flag = "1" and LABEL_X

=

1FF7H:

JR C,LABEL_X PC 1FF7H

ꢅ

=

If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will

pass control to the statement whose address is now in the PC. Otherwise, the program

instruction following the JR would be executed.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

178

LD— Load

LD

dst,src

dst

Operation:

ꢄ

src

The contents of the source are loaded into the destination. The source's contents are unaffected.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

dst

src

|

opc

src

dst

|

2

4

rC

r8

r

IM

r

R

|

2

3

4

r9

R

r

r = 0 to F

opc

dst

src

4

C7

D7

r

lr

r

Ir

src

dst

src

6

E4

E5

R

IR

6

E6

D6

R

IM

IR

opc

src

dst

x

3

6

F5

87

97

IR

r

R

x [r]

r

dst

src

|

src

dst

x

x [r]

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

179

LD— Load

LD

(Continued)

Examples:

Given: R0

register 02H

=

01H, R1

=

0AH, register 00H

=

01H, register 01H

0FFH:

=

20H,

02H, LOOP

=

30H, and register 3AH

=

LD

R0,#10H

R0,01H

01H,R0

R1,@R0

@R0,R1

00H,01H

ꢅ

R0 = 10H

R0 = 20H, register 01H = 20H

Register 01H = 01H, R0 = 01H

R1 = 20H, R0 = 01H

R0 = 01H, R1 = 0AH, register 01H = 0AH

Register 00H = 20H, register 01H = 20H

Register 02H = 20H, register 00H = 01H

Register 00H = 0AH

02H,@00H

00H,#0AH

@00H,#10H

@00H,02H

ꢅ

Register 00H = 01H, register 01H = 10H

Register 00H = 01H, register 01H = 02, register 02H = 02H

R0 = 0FFH, R1 = 0AH

R0,#LOOP[R1] ꢅ

#LOOP[R0],R1 ꢅ

Register 31H = 0AH, R0 = 01H, R1 = 0AH

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

180

LDB— Load Bit

LDB

dst,src.b

LDB

dst.b,src

Operation:

dst(0)

dst(b)

ꢄ

src(b)

src(0)

or

ꢄ

The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the

source is loaded into the specified bit of the destination. No other bits of the destination are

affected. The source is unaffected.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

3

6

47

r0 Rb

dst | b | 0

src | b | 1

3

6

47

Rb

r0

NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the bit

address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R0

=

06H and general register 00H

=

05H:

LDB

R0,00H.2

00H.0,R0

ꢅ

R0

=

07H, register 00H

06H, register 00H

=

05H

04H

In the first example, destination working register R0 contains the value 06H and the source

general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the

00H register into bit zero of the R0 register, leaving the value 07H in register R0.

In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit

zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in general

register 00H.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

181

LDC/LDE— Load Memory

LDC/LDE

dst,src

dst

This instruction loads a byte from program or data memory into a working register or vice-versa.

Operation:

ꢄ

src

The source values are unaffected. LDC refers to program memory and LDE to data memory. The

assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number

for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

1.

2.

3.

4.

5.

opc

dst | src

src | dst

dst | src

src | dst

dst | src

2

10

C3

D3

E7

F7

A7

r

Irr

2

3

4

10

12

14

Irr

r

XS

r

XS [rr]

r

XS [rr]

r

XL_L

XL_H

DA_H

XL [rr]

XL_L

DA_L

6.

7.

opc

src | dst

dst | 0000

src | 0000

dst | 0001

src | 0001

4

14

B7

A7

B7

A7

B7

XL [rr]

r

DA

r

8.

DA

r

9.

DA

r

10.

opc

DA

NOTES:

1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.

2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one

byte.

3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two

bytes.

4. The DA and r source values for formats 7 and 8 are used to address program memory; the second

set of values, used in formats 9 and 10, are used to address data memory.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

182

LDC/LDE— Load Memory

LDC/LDE

(Continued)

Examples:

Given: R0

=

11H, R1

=

34H, R2

=

01H, R3

=

04H; Program memory locations

0103H

=

4FH, 0104H

=

1A, 0105H

=

6DH, and 1104H

=

88H. External data memory

locations 0103H

=

5FH, 0104H

=

2AH, 0105H

=

7DH, and 1104H

=

98H:

LDC

R0,@RR2

; R0

ꢄ

=

contents of program memory location 0104H

1AH, R2 01H, R3 04H

=

LDE

R0,@RR2

; R0

ꢄ

=

contents of external data memory location 0104H

2AH, R2 01H, R3 04H

=

LDC ^(note)@RR2,R0

; 11H (contents of R0) is loaded into program memory

; location 0104H (RR2),

; working registers R0, R2, R3

ꢅ

no change

LDE

LDC

LDE

@RR2,R0

; 11H (contents of R0) is loaded into external data memory

; location 0104H (RR2),

; working registers R0, R2, R3

ꢅ

no change

R0,#01H[RR2]

; R0 contents of program memory location 0105H

ꢄ

; (01H + RR2),

; R0

=

6DH, R2

=

01H, R3

=

04H

; R0

ꢄ

contents of external data memory location 0105H

; (01H + RR2), R0

=

7DH, R2 01H, R3 04H

=

LDC ^(note)#01H[RR2],R0

; 11H (contents of R0) is loaded into program memory location

; 0105H (01H + 0104H)

LDE

LDC

LDE

#01H[RR2],R0

; 11H (contents of R0) is loaded into external data memory

; location 0105H (01H + 0104H)

R0,#1000H[RR2] ; R0

ꢄ

contents of program memory location 1104H

88H, R2 01H, R3 04H

; (1000H + 0104H), R0

=

R0,#1000H[RR2] ; R0

ꢄ

contents of external data memory location 1104H

; (1000H + 0104H), R0 98H, R2 01H, R3 04H

=

LDC

88H

R0,1104H

; R0

ꢄ

contents of program memory location 1104H, R0

=

LDE

; R0

ꢄ

=

contents of external data memory location 1104H,

98H

LDC ^(note)1105H,R0

; 11H (contents of R0) is loaded into program memory location

; 1105H, (1105H) 11H

ꢄ

LDE

1105H,R0

; 11H (contents of R0) is loaded into external data memory

; location 1105H, (1105H) 11H

ꢄ

NOTE: These instructions are not supported by masked ROM type devices.

PS031601-0813 P R E L I M I N A R Y

S3F82NB

Product Specification

183

LDCD/LDED— Load Memory and Decrement

LDCD/LDED dst,src

Operation:

dst

rr

ꢄ

src

ꢄ

rr – 1

These instructions are used for user stacks or block transfers of data from program or data

memory to the register file. The address of the memory location is specified by a working register

pair. The contents of the source location are loaded into the destination location. The memory

address is then decremented. The contents of the source are unaffected.

LDCD references program memory and LDED references external data memory. The assembler

makes 'Irr' an even number for program memory and an odd number for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

2

10

E2

r

Irr

Examples:

Given: R6

=

10H, R7

=

33H, R8

=

12H, program memory location 1033H

= 0DDH:

=

0CDH,

and external data memory location 1033H

LDCD

R8,@RR6

; 0CDH (contents of program memory location 1033H) is loaded

; into R8 and RR6 is decremented by one

; R8

=

0CDH, R6

=

10H, R7

=

32H (RR6

ꢄ

RR6 – 1)

LDED

R8,@RR6

; 0DDH (contents of data memory location 1033H) is loaded

; into R8 and RR6 is decremented by one (RR6 RR6 – 1)

; R8 0DDH, R6 10H, R7 32H

ꢄ

=

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

184

LDCI/LDEI— Load Memory and Increment

LDCI/LDEI

dst,src

Operation:

dst

rr

ꢄ

src

rr

ꢄ

+

1

These instructions are used for user stacks or block transfers of data from program or data

memory to the register file. The address of the memory location is specified by a working register

pair. The contents of the source location are loaded into the destination location. The memory

address is then incremented automatically. The contents of the source are unaffected.

LDCI refers to program memory and LDEI refers to external data memory. The assembler makes

'Irr' even for program memory and odd for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

2

10

E3

r

Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and 1034H

= 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:

LDCI

R8,@RR6

; 0CDH (contents of program memory location 1033H) is loaded

; into R8 and RR6 is incremented by one (RR6 RR6 + 1)

; R8 0CDH, R6 10H, R7 34H

ꢄ

=

LDEI

R8,@RR6

; 0DDH (contents of data memory location 1033H) is loaded

; into R8 and RR6 is incremented by one (RR6 RR6 + 1)

; R8 0DDH, R6 10H, R7 34H

ꢄ

=

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

185

LDCPD/LDEPD— Load Memory with Pre-Decrement

LDCPD/

LDEPD

dst,src

Operation:

rr

ꢄ

rr

–

1

dst

ꢄ

src

These instructions are used for block transfers of data from program or data memory from the

register file. The address of the memory location is specified by a working register pair and is first

decremented. The contents of the source location are then loaded into the destination location.

The contents of the source are unaffected.

LDCPD refers to program memory and LDEPD refers to external data memory. The assembler

makes 'Irr' an even number for program memory and an odd number for external data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src | dst

2

14

F2

Irr

r

Examples:

Given: R0

=

77H, R6

=

30H, and R7

=

00H:

LDCPD @RR6,R0

; (RR6 RR6 – 1)

ꢄ

; 77H (contents of R0) is loaded into program memory location

; 2FFFH (3000H – 1H)

; R0

=

77H, R6

=

2FH, R7

=

0FFH

LDEPD @RR6,R0

; (RR6

ꢄ

RR6 – 1)

; 77H (contents of R0) is loaded into external data memory

; location 2FFFH (3000H – 1H)

; R0

=

77H, R6

=

2FH, R7

=

0FFH

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

186

LDCPI/LDEPI— Load Memory with Pre-Increment

LDCPI/

LDEPI

dst,src

Operation:

rr

ꢄ

rr

+

1

dst

ꢄ

src

These instructions are used for block transfers of data from program or data memory from the

register file. The address of the memory location is specified by a working register pair and is first

incremented. The contents of the source location are loaded into the destination location. The

contents of the source are unaffected.

LDCPI refers to program memory and LDEPI refers to external data memory. The assembler

makes 'Irr' an even number for program memory and an odd number for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src | dst

2

14

F3

Irr

r

Examples:

Given: R0

LDCPI

=

7FH, R6

=

21H, and R7

=

0FFH:

@RR6,R0

; (RR6 RR6 + 1)

ꢄ

; 7FH (contents of R0) is loaded into program memory

; location 2200H (21FFH + 1H)

; R0

=

7FH, R6

=

22H, R7

=

00H

LDEPI

@RR6,R0

; (RR6

ꢄ RR6 + 1)

; 7FH (contents of R0) is loaded into external data memory

; location 2200H (21FFH + 1H)

; R0

=

7FH, R6

=

22H, R7

=

00H

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

187

LDW— Load Word

LDW

dst,src

Operation:

dst

ꢄ

src

The contents of the source (a word) are loaded into the destination. The contents of the source

are unaffected.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src

dst

3

8

C4

C5

RR RR

RR

IR

src

4

8

C6

RR

IML

Examples:

Given: R4

register 01H

=

06H, R5

=

1CH, R6

=

05H, R7

=

02H, register 00H

=

1AH,

02H, register 02H

=

03H, and register 03H

=

0FH:

LDW

RR6,RR4

00H,02H

ꢅ

R6

=

06H, R7

=

1CH, R4

=

06H, R5

0FH,

=

1CH

Register 00H

register 02H

=

03H, register 01H

03H, register 03H

=

0FH

LDW

RR2,@R7

ꢅ

R2

Register 04H

R6 12H, R7

Register 02H

=

03H, R3

=

0FH,

03H, register 05H

34H

0FH, register 03H

04H,@01H

RR6,#1234H

02H,#0FEDH

=

0FH

=

0EDH

In the second example, please note that the statement "LDW 00H,02H" loads the contents of

the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in

general register 00H and the value 0FH in register 01H.

The other examples show how to use the LDW instruction with various addressing modes and

formats.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

188

MULT— Multiply (Unsigned)

MULT

dst,src

Operation:

dst

ꢄ

dst ꢀ src

The 8-bit destination operand (even register of the register pair) is multiplied by the source

operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination

address. Both operands are treated as unsigned integers.

Flags:

C: Set if result is ꢌ 255; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if MSB of the result is a "1"; cleared otherwise.

V: Cleared.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

3

22

84

85

86

RR

R

RR

IR

IM

Examples:

Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H:

MULT

00H, 02H

ꢅ

Register 00H = 01H, register 01H = 20H, register 02H = 09H

00H, @01H

00H, #30H

Register 00H = 00H, register 01H = 0C0H

Register 00H = 06H, register 01H = 00H

In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in

the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The

16-bit product, 0120H, is stored in the register pair 00H, 01H.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

189

NEXT— Next

PC

IP

ꢄ

@ IP

IP

ꢄ

+

2

The NEXT instruction is useful when implementing threaded-code languages. The program

memory word that is pointed to by the instruction pointer is loaded into the program counter. The

instruction pointer is then incremented by two.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

10

0F

Example:

The following diagram shows one example of how to use the NEXT instruction.

Before

After

Data

Address

IP

Data

Address

IP

0043

0120

0045

0130

Address

Data

Address

Data

PC

43 Address H 01

44 Address L 10

45 Address H

PC

43 Address H

44 Address L

45 Address H

120 Next

Memory

130 Routine

Memory

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

190

NOP— No Operation

NOP

Operation:

No action is performed when the CPU executes this instruction. Typically, one or more NOPs are

executed in sequence in order to effect a timing delay of variable duration.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

FF

Example:

When the instruction

NOP

is encountered in a program, no operation occurs. Instead, there is a delay in instruction

execution time.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

191

OR— Logical OR

OR

dst,src

Operation:

dst

ꢄ

dst OR src

The source operand is logically ORed with the destination operand and the result is stored in the

destination. The contents of the source are unaffected. The OR operation results in a "1" being

stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is

stored.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always cleared to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

r

opc

dst | src

src

2

4

6

42

43

r

lr

dst

src

3

6

44

45

R

IR

dst

6

46

R

IM

Examples:

Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register

08H = 8AH:

OR

R0,R1

ꢅ

R0

=

3FH, R1

37H, R2

=

2AH

R0,@R2

00H,01H

01H,@00H

00H,#02H

01H, register 01H

=

37H

Register 00H

=

3FH, register 01H

08H, register 01H

0AH

=

37H

0BFH

In the first example, if working register R0 contains the value 15H and register R1 the value 2AH,

the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result

(3FH) in destination register R0.

The other examples show the use of the logical OR instruction with the various addressing

modes and formats.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

192

POP— Pop From Stack

POP

dst

Operation:

dst

SP

ꢄ

@SP

SP

+

1

The contents of the location addressed by the stack pointer are loaded into the destination. The

stack pointer is then incremented by one.

Flags:

No flags affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

8

50

51

R

IR

Examples:

Given: Register 00H

=

01H, register 01H

55H:

=

1BH, SPH (0D8H)

=

00H, SPL (0D9H)

=

0FBH, and stack register 0FBH

=

POP

00H

ꢅ

Register 00H

=

55H, SP

=

00FCH

@00H

=

01H, register 01H

=

55H, SP

=

00FCH

In the first example, general register 00H contains the value 01H. The statement "POP 00H"

loads the contents of location 00FBH (55H) into destination register 00H and then increments the

stack pointer by one. Register 00H then contains the value 55H and the SP points to location

00FCH.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

193

POPUD— Pop User Stack (Decrementing)

POPUD

dst,src

Operation:

dst

IR

ꢄ

src

ꢄ

IR – 1

This instruction is used for user-defined stacks in the register file. The contents of the register file

location addressed by the user stack pointer are loaded into the destination. The user stack

pointer is then decremented.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src

dst

3

8

92

R

IR

Example:

Given: Register 00H

register 02H 70H:

=

42H (user stack pointer register), register 42H

=

6FH, and

=

POPUD 02H,@00H

6FH

ꢅ

Register 00H

=

41H, register 02H

=

6FH, register 42H

=

If general register 00H contains the value 42H and register 42H the value 6FH, the statement

"POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The

user stack pointer is then decremented by one, leaving the value 41H.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

194

POPUI— Pop User Stack (Incrementing)

POPUI

dst,src

Operation:

dst

IR

ꢄ

src

ꢄ

IR + 1

The POPUI instruction is used for user-defined stacks in the register file. The contents of the

register file location addressed by the user stack pointer are loaded into the destination. The user

stack pointer is then incremented.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src

dst

3

8

93

R

IR

Example:

Given: Register 00H

POPUI 02H,@00H

=

01H and register 01H

=

70H:

ꢅ

Register 00H = 02H, register 01H = 70H, register 02H = 70H

If general register 00H contains the value 01H and register 01H the value 70H, the statement

"POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user

stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

195

PUSH— Push To Stack

PUSH

src

Operation:

SP

ꢄ

SP

–

1

@SP

ꢄ

src

A PUSH instruction decrements the stack pointer value and loads the contents of the source (src)

into the location addressed by the decremented stack pointer. The operation then adds the new

value to the top of the stack.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

src

2

8 (internal clock)

8 (external clock)

70

R

8 (internal clock)

8 (external clock)

71

IR

Examples:

Given: Register 40H

=

4FH, register 4FH

Register 40H

=

0AAH, SPH

=

00H, and SPL

=

00H:

PUSH

40H

ꢅ

=

4FH, stack register 0FFH

0FFH

=

4FH,

SPH

=

0FFH, SPL

=

PUSH

@40H

ꢅ

Register 40H

=

4FH, register 4FH

=

0AAH, stack register

= 0FFH

0FFH 0AAH, SPH

=

0FFH, SPL

In the first example, if the stack pointer contains the value 0000H, and general register 40H the

value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It

then loads the contents of register 40H into location 0FFFFH and adds this new value to the top

of the stack.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

196

PUSHUD— Push User Stack (Decrementing)

PUSHUD

dst,src

Operation:

IR

ꢄ

IR – 1

dst

ꢄ src

This instruction is used to address user-defined stacks in the register file. PUSHUD decrements

the user stack pointer and loads the contents of the source into the register addressed by the

decremented stack pointer.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst

src

3

8

82

IR

R

Example:

Given: Register 00H

PUSHUD @00H,01H

=

03H, register 01H

=

05H, and register 02H

=

1AH:

ꢅ

Register 00H = 02H, register 01H = 05H, register 02H = 05H

If the user stack pointer (register 00H, for example) contains the value 03H, the statement

"PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The

01H register value, 05H, is then loaded into the register addressed by the decremented user

stack pointer.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

197

PUSHUI— Push User Stack (Incrementing)

PUSHUI

dst,src

Operation:

IR

ꢄ

IR

src

+

1

dst

ꢄ

This instruction is used for user-defined stacks in the register file. PUSHUI increments the user

stack pointer and then loads the contents of the source into the register location addressed by

the incremented user stack pointer.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst

src

3

8

83

IR

R

Example:

Given: Register 00H

PUSHUI @00H,01H

=

03H, register 01H

=

05H, and register 04H

=

2AH:

ꢅ

Register 00H = 04H, register 01H = 05H, register 04H = 05H

If the user stack pointer (register 00H, for example) contains the value 03H, the statement

"PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H

register value, 05H, is then loaded into the location addressed by the incremented user stack

pointer.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

198

RCF— Reset Carry Flag

RCF

Operation:

C

ꢄ

0

The carry flag is cleared to logic zero, regardless of its previous value.

Flags:

C: Cleared to "0".

No other flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

CF

Example:

Given: C = "1" or "0":

The instruction RCF clears the carry flag (C) to logic zero.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

199

RET— Return

RET

Operation:

PC

SP

ꢄ

@SP

SP

+

2

The RET instruction is normally used to return to the previously executing procedure at the end of

a procedure entered by a CALL instruction. The contents of the location addressed by the stack

pointer are popped into the program counter. The next statement that is executed is the one that

is addressed by the new program counter value.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode (Hex)

opc

1

8 (internal stack)

10 (internal stack)

AF

Example:

Given: SP

=

00FCH, (SP)

PC

=

101AH, and PC

=

1234:

RET

ꢅ

=

101AH, SP

=

00FEH

The statement "RET" pops the contents of stack pointer location 00FCH (10H) into the high byte

of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the

PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to

memory location 00FEH.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

200

RL— Rotate Left

RL

dst

Operation:

C

ꢄ

dst (7)

dst (0) ꢄ dst (7)

dst (n 1)

+

ꢄ

dst (n),

n

=

0–6

The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is

moved to the bit zero (LSB) position and also replaces the carry flag.

7

0

C

Flags:

C: Set if the bit rotated from the most significant bit position (bit 7) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

90

91

R

IR

Examples:

Given: Register 00H

=

0AAH, register 01H

=

02H and register 02H

55H, C "1"

02H, register 02H

=

17H:

RL

00H

ꢅ

Register 00H

Register 01H

=

@01H

ꢅ

=

2EH, C

=

"0"

In the first example, if general register 00H contains the value 0AAH (10101010B), the statement

"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B)

and setting the carry and overflow flags.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

201

RLC— Rotate Left Through Carry

RLC

dst

Operation:

dst (0) ꢂꢄ

C

ꢄ

dst (7)

1) ꢄꢂ dst (n), n

dst (n

+

=

0–6

The contents of the destination operand with the carry flag are rotated left one bit position. The

initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.

7

0

C

Flags:

C: Set if the bit rotated from the most significant bit position (bit 7) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

10

11

R

IR

Examples:

Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":

RLC

00H

ꢅ

Register 00H

Register 01H

=

54H, C

=

"1"

@01H

02H, register 02H

=

2EH, C = "0"

In the first example, if general register 00H has the value 0AAH (10101010B), the statement

"RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag

and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H

(01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

202

RR— Rotate Right

RR

dst

Operation:

C

ꢄ

dst (0)

dst (nꢍꢂꢂꢄ dst (n

dst (7)

ꢄ

+

1), n

=

0–6

The contents of the destination operand are rotated right one bit position. The initial value of bit

zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

7

0

C

Flags:

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

E0

E1

R

IR

Examples:

Given: Register 00H

=

31H, register 01H

Register 00H = 98H, C

Register 01H 02H, register 02H

=

02H, and register 02H

=

17H:

RR

00H

ꢅ

=

"1"

@01H

ꢅ

=

8BH, C

=

"1"

In the first example, if general register 00H contains the value 31H (00110001B), the statement

"RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to

bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also

resets the C flag to "1" and the sign flag and overflow flag are also set to "1".

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

203

RRC— Rotate Right Through Carry

RRC

dst

Operation:

dst (7)

ꢄ

C

ꢄ

dst (0)

dst (n

dst (n)

ꢄ

+

1), n

=

0–6

The contents of the destination operand and the carry flag are rotated right one bit position. The

initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7

(MSB).

7

0

C

Flags:

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".

Z: Set if the result is "0" cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

C0

C1

R

IR

Examples:

Given: Register 00H

=

55H, register 01H

=

02H, register 02H

2AH, C "1"

02H, register 02H

=

17H, and C

=

"0":

RRC

00H

ꢅꢂ

Register 00H

Register 01H

=

@01H

ꢅ

=

0BH, C

=

"1"

In the first example, if general register 00H contains the value 55H (01010101B), the statement

"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1")

replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new

value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both

cleared to "0".

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

204

SB0— Select Bank 0

SB0

Operation:

BANK ꢂꢄ

0

The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero,

selecting bank 0 register addressing in the set 1 area of the register file.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

4F

Example:

The statement

SB0

clears FLAGS.0 to "0", selecting bank 0 register addressing.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

205

SB1— Select Bank 1

SB1

Operation:

BANK ꢄꢂ 1

The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one,

selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not

implemented in some S3C8-series microcontrollers.)

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

5F

Example:

The statement

SB1

sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

206

SBC— Subtract with Carry

SBC

dst,src

Operation:

dst

ꢄ

dst

–

src

–

c

The source operand, along with the current value of the carry flag, is subtracted from the

destination operand and the result is stored in the destination. The contents of the source are

unaffected. Subtraction is performed by adding the two's-complement of the source operand to

the destination operand. In multiple precision arithmetic, this instruction permits the carry

("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of

high-order operands.

Flags:

C: Set if a borrow occurred (src

ꢌ

dst); cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign

of the result is the same as the sign of the source; cleared otherwise.

D: Always set to "1".

H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;

set otherwise, indicating a "borrow".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

32

33

r

lr

dst

3

6

34

35

R

IR

opc

dst

src

=

6

36

R

IM

Examples:

Given: R1

and register 03H

=

10H, R2

=

03H, C

=

"1", register 01H

=

20H, register 02H

=

03H,

0AH:

SBC

R1,R2

ꢅ

R1 = 0CH, R2 = 03H

R1,@R2

R1 = 05H, R2 = 03H, register 03H = 0AH

Register 01H = 1CH, register 02H = 03H

01H,02H

01H,@02H

01H,#8AH

Register 01H = 15H,register 02H = 03H, register 03H = 0AH

Register 01H = 5H; C, S, and V = "1"

In the first example, if working register R1 contains the value 10H and register R2 the value 03H,

the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the

destination (10H) and then stores the result (0CH) in register R1.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

207

SCF— Set Carry Flag

SCF

Operation:

Flags:

C ꢂꢄ

1

The carry flag (C) is set to logic one, regardless of its previous value.

C: Set to "1".

No other flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

DF

Example:

The statement

SCF

sets the carry flag to logic one.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

208

SRA— Shift Right Arithmetic

SRA

dst

Operation:

dst (7)

ꢄ

dst (7)

dst (0)

dst (n

C

ꢄ

dst (n)

ꢄ

+

1), n

=

0–6

An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the

LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit

position 6.

7

6

0

C

Flags:

C: Set if the bit shifted from the LSB position (bit zero) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Always cleared to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

D0

D1

R

IR

Examples:

Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":

SRA

00H

ꢅ

Register 00H

Register 02H

=

0CD, C

=

"0"

@02H

03H, register 03H

=

0DEH, C

=

"0"

In the first example, if general register 00H contains the value 9AH (10011010B), the statement

"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C

flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the

value 0CDH (11001101B) in destination register 00H.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

209

SRP/SRP0/SRP1— Set Register Pointer

SRP

src

SRP0

SRP1

Operation:

If src (1)

=

1 and src (0)

0 and src (0)

=

0 then:

1 then:

0 then:

RP0 (3–7)

RP1 (3–7)

RP0 (4–7)

ꢄ

src (3–7)

src (4–7),

RP0 (3)

ꢄ

0

RP1 (4–7)

RP1 (3)

src (4–7),

1

The source data bits one and zero (LSB) determine whether to write one or both of the register

pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register

pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

src

opc

src

2

4

31

IM

Examples:

The statement

SRP #40H

sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location

0D7H to 48H.

The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to

68H.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

210

STOP— Stop Operation

STOP

Operation:

The STOP instruction stops the both the CPU clock and system clock and causes the

microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers,

peripheral registers, and I/O port control and data registers are retained. Stop mode can be

released by an external reset operation or by external interrupts. For the reset operation, the

RESET pin must be held to Low level until the required oscillation stabilization interval has

elapsed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

1

4

7F

–

Example:

The statement

STOP

halts all microcontroller operations.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

211

SUB— Subtract

SUB

dst,src

Operation:

dst

ꢄ

dst – src

The source operand is subtracted from the destination operand and the result is stored in the

destination. The contents of the source are unaffected. Subtraction is performed by adding the

two's complement of the source operand to the destination operand.

Flags:

C: Set if a "borrow" occurred; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the

sign of the result is of the same as the sign of the source operand; cleared otherwise.

D: Always set to "1".

H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;

set otherwise indicating a "borrow".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst

src

|

2

4

6

22

r

23

r

lr

opc

src

dst

src

3

6

24

25

R

IR

6

26

R

IM

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

SUB

R1,R2

ꢅ

R1

=

0FH, R2

08H, R2

=

03H

R1,@R2

01H,02H

01H,@02H

01H,#90H

01H,#65H

Register 01H

=

1EH, register 02H

17H, register 02H

91H; C, S, and V

=

03H

=

"1"

"1", V

0BCH; C and S

=

"0"

In the first example, if working register R1 contains the value 12H and if register R2 contains the

value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination

value (12H) and stores the result (0FH) in destination register R1.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

212

SWAP— Swap Nibbles

SWAP

dst

Operation:

dst (0

–

3)

ꢋ

dst (4 – 7)

The contents of the lower four bits and upper four bits of the destination operand are swapped.

7

4 3

0

Flags:

C: Undefined.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

F0

F1

R

IR

Examples:

Given: Register 00H

=

3EH, register 02H

=

03H, and register 03H

=

0A4H:

SWAP

00H

ꢅ

Register 00H

Register 02H

= 0E3H

@02H

ꢅ

=

03H, register 03H

=

4AH

In the first example, if general register 00H contains the value 3EH (00111110B), the statement

"SWAP 00H" swaps the lower and upper four bits (nibbles) in the 00H register, leaving the

value 0E3H (11100011B).

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

213

TCM— Test Complement Under Mask

TCM

dst,src

Operation:

(NOT dst) AND src

This instruction tests selected bits in the destination operand for a logic one value. The bits to be

tested are specified by setting a "1" bit in the corresponding position of the source operand

(mask). The TCM statement complements the destination operand, which is then ANDed with the

source mask. The zero (Z) flag can then be checked to determine the result. The destination and

source operands are unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always cleared to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

62

63

r

lr

dst

src

3

6

64

65

R

IR

opc

dst

6

66

R

IM

Examples:

Given: R0

=

0C7H, R1

= 02H, R2

23H:

=

12H, register 00H

=

2BH, register 01H

=

02H, and register 02H

=

TCM

R0,R1

ꢅ

R0

=

0C7H, R1

=

02H, Z

=

"1"

R0,@R1

00H,01H

00H,@01H

02H, register 02H

=

23H, Z

=

"0"

Register 00H

=

2BH, register 01H

=

02H, Z

02H,

=

"1"

Register 00H

register 02H

=

2BH, register 01H

=

23H, Z

2BH, Z

=

"1"

"0"

TCM

00H,#34

ꢅ

Register 00H

=

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1

the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register

for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one

and can be tested to determine the result of the TCM operation.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

214

TM— Test Under Mask

TM

dst,src

Operation:

dst AND src

This instruction tests selected bits in the destination operand for a logic zero value. The bits to be

tested are specified by setting a "1" bit in the corresponding position of the source operand

(mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to

determine the result. The destination and source operands are unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always reset to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

72

73

r

lr

dst

src

3

6

74

75

R

IR

opc

dst

6

76

R

IM

Examples:

Given: R0

=

0C7H, R1

= 02H, R2

23H:

=

18H, register 00H

=

2BH, register 01H

=

02H, and register 02H

=

TM

R0,R1

ꢅ

R0

=

0C7H, R1

=

02H, Z

=

"0"

R0,@R1

00H,01H

00H,@01H

02H, register 02H

=

23H, Z

=

"0"

Register 00H

=

2BH, register 01H

=

02H, Z "0"

=

Register 00H

register 02H

=

2BH, register 01H = 02H,

23H, Z

=

"0"

TM

00H,#54H

ꢅ

Register 00H

=

2BH, Z

=

"1"

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1

the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register

for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic

zero and can be tested to determine the result of the TM operation.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

215

WFI— Wait for Interrupt

WFI

Operation:

The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take

place during this wait state. The WFI status can be released by an internal interrupt, including a

fast interrupt .

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4n

3F

( n

=

1, 2, 3, … )

Example:

The following sample program structure shows the sequence of operations that follow a "WFI"

statement:

Main program

.

EI

(Enable global interrupt)

(Wait for interrupt)

WFI

(Next instruction)

.

Interrupt occurs

Interrupt service routine

.

Clear interrupt flag

IRET

Service routine completed

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

216

XOR— Logical Exclusive OR

XOR

dst,src

Operation:

dst

ꢄ

dst XOR src

The source operand is logically exclusive-ORed with the destination operand and the result is

stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever

the corresponding bits in the operands are different; otherwise, a "0" bit is stored.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always reset to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

B2

B3

r

lr

dst

src

3

6

B4

B5

R

IR

opc

dst

6

B6

R

IM

Examples:

Given: R0

=

0C7H, R1

= 02H, R2

23H:

=

18H, register 00H

=

2BH, register 01H

=

02H, and register 02H

=

XOR

R0,R1

ꢅ

R0

=

0C5H, R1

0E4H, R1

=

02H

02H, register 02H

R0,@R1

00H,01H

00H,@01H

=

23H

Register 00H

=

29H, register 01H

08H, register 01H

=

02H

XOR

23H

02H, register 02H

=

XOR

00H,#54H

ꢅ

Register 00H

=

7FH

In the first example, if working register R0 contains the value 0C7H and if register R1 contains

the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0

value and stores the result (0C5H) in the destination register R0.

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

217

7

CLOCK CIRCUIT

OVERVIEW

The S3F82NB microcontroller has two oscillator circuits: a main clock and a sub clock circuit. The CPU and

peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU

clock frequency of S3F82NB is determined by CLKCON register settings.

SYSTEM CLOCK CIRCUIT

The system clock circuit has the following components:

— External crystal, ceramic resonator, RC oscillation source, or an external clock source

— Oscillator stop and wake-up functions

— Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16)

— System clock control register, CLKCON

— Oscillator control register, OSCCON and STOP control register, STPCON

CPU CLOCK NOTATION

In this document, the following notation is used for descriptions of the CPU clock;

fx: main clock

fxt: sub clock

fxx: selected system clock

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

218

MAIN OSCILLATOR CIRCUITS

SUB OSCILLATOR CIRCUITS

32.768 kHz

XTIN

XIN

XOUT

XTOUT

Figure 7-1. Crystal/Ceramic Oscillator (fX)

Figure 7-4. Crystal Oscillator (fxt)

XIN

XTIN

XOUT

XTOUT

Figure 7-2. External Oscillator (fX)

Figure 7-5. External Oscillator (fxt)

XIN

R

XOUT

Figure 7-3. RC Oscillator (fX)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

219

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:

— In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset

operation or an external interrupt (with RC delay noise filter), and can be released by internal interrupt too

when the sub-system oscillator is running and watch timer is operating with sub-system clock.

— In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers and timer/

counters. Idle mode is released by a reset or by an external or internal interrupt.

Stop Release

INT

Main-System

Oscillator

Circuit

Sub-system

Oscillator

Circuit

fX

f_Xt

Watch Timer

LCD Controller

Selector 1

fXX

Stop

OSCCON.3

OSCCON.0

Stop

OSCCON.2

1/1-1/4096

STOP OSC

inst.

Basic Timer

Frequency

Dividing

Circuit

Timer/Counters 0, 1/A

Watch Timer

LCD Controller

SIO

STPCON

A/D Converter

Comparator

LVR

1/1 1/2 1/8 1/16

Selector 2

CLKCON.4-.3

CPU Clock

IDLE Instruction

Figure 7-6. System Clock Circuit Diagram

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

220

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in the set 1, address D4H. It is read/write addressable and

has the following functions:

— Oscillator frequency divide-by value

After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If

necessary, you can then increase the CPU clock speed fxx/8, fxx/2, or fxx/1.

System Clock Control Register (CLKCON)

D4H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used

(must keep always 0)

Not used

(must keep always 0)

Oscillator IRQ wake-up function bit:

0 = Enable IRQ for main wake-up in power down mode

1 = Disable IRQ for main wake-up in power down mode

Divide-by selection bits for CPU clock frequency:

00 = fXX/16

01 = fXX/8

10 = fXX/2

11 = fXX/1

NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock.

To select faster speed, load the appropriate values to CLKCON.3-.4.

Figure 7-7. System Clock Control Register (CLKCON)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

221

OSCILLATOR CONTROL REGISTER (OSCCON)

The oscillator control register, OSCCON, is located in set 1, bank 0, at address FAH. It is read/write addressable

and has the following functions:

— System clock selection

— Main oscillator control

— Sub oscillator control

OSCCON.0 register settings select Main clock or Sub clock as system clock.

After a reset, Main clock is selected for system clock because the reset value of OSCCON.0 is "0".

The main oscillator can be stopped or run by setting OSCCON.3.

The sub oscillator can be stopped or run by setting OSCCON.2.

Oscillator Control Register (OSCCON)

FAH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

System clock selection bit:

0 = Main oscillator select

1 = Sub oscillator select

Not used for S3F82NB

Sub system oscillator control bit:

0 = Sub oscillator RUN

1 = Sub oscillator STOP

Main system oscillator control bit:

0 = Main oscillator RUN

1 = Main oscillator STOP

Figure 7-8. Oscillator Control Register (OSCCON)

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

222

STOP CONTROL REGISTER (STPCON)

The STOP control register, STPCON, is located in the bank 0 of set1, address F5H. It is read/write addressable

and has the following functions:

— Enable/Disable STOP instruction

After a reset, the STOP instruction is disabled, because the value of STPCON is "other values".

If necessary, you can use the STOP instruction by setting the value of STPCON to "10100101B".

STOP Control Register (STPCON)

F5H, Set 1, bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

STOP Control bits:

Other values = Disable STOP instruction

10100101 = Enable STOP instruction

NOTE:

Before executing the STOP instruction, set the STPCON

register as "10100101b". Otherwise the STOP instruction

will not be executed and reset will be generated.

Figure 7-9. STOP Control Register (STPCON)

ꢁ

ꢀ

PROGRAMMING TIP — How to Use Stop Instruction

This example shows how to go STOP mode when a main clock is selected as the system clock.

LD

STOPCON,#1010010B

; Enable STOP instruction

; Enter STOP mode

STOP

NOP

LD

; Release STOP mode

STOPCON,#00000000B ; Disable STOP instruction

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SWITCHING THE CPU CLOCK

Data loading in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as

the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch

dynamically between main and sub clocks and to modify operating frequencies.

OSCCON.0 selects the main clock (fx) or the sub clock (fxt) for the CPU clock. OSCCON .3 start or stop main

clock oscillation and OSCCON.2 start or stop sub clock oscillation. CLKCON.4–.3 controls the frequency divider

circuit, and divides the selected fxx clock by 1, 2, 8 and 16. If the sub clock (fxt) is selected for system clock, the

CLKCON.4–.3 must be set to “11”.

For example, you are using the default CPU clock (normal operating mode and a main clock of fx/16) and you

want to switch from the fx clock to a sub clock and to stop the main clock. To do this, you need to set CLKCON.4-

.3 to "11", OSCCON.0 to “1”, and OSCCON.3 to “1” by turns. This switches the clock from fx to fxt and stops main

clock oscillation.

The following steps must be taken to switch from a sub clock to the main clock: first, set OSCCON.3 to “0” to

enable main clock oscillation. Then, after a certain number of machine cycles have elapsed, select the main clock

by setting OSCCON.0 to “0”.

ꢁ

ꢀ

PROGRAMMING TIP — Switching the CPU Clock

1. This example shows how to change from the main clock to the sub clock:

MA2SUB OR

LD

CLKCON,#18H

OSCCON,#01H

DLY16

; Non-divided clock for system clock

; Switches to the sub clock

; Delay 16 ms

CALL

OR

RET

OSCCON,#08H

; Stop the main clock oscillation

2. This example shows how to change from sub clock to main clock:

SUB2MA AND

OSCCON,#07H

DLY16

; Start the main clock oscillation

; Delay 16 ms

; Switch to the main clock

CALL

AND

RET

OSCCON,#06H

DLY16

DEL

SRP

LD

#0C0H

R0,#20H

NOP

DJNZ

RET

R0,DEL

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8

RESET and POWER-DOWN

SYSTEM RESET

OVERVIEW

During a power-on reset, the voltage at V_DDgoes to High level and the nRESET pin is forced to Low level. The

nRESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This

procedure brings the S3F82NB into a known operating status.

To allow time for internal CPU clock oscillation to stabilize, the nRESET pin must be held to Low level for a

minimum time interval after the power supply comes within tolerance. The minimum required time of a reset

operation for oscillation stabilization is 1 millisecond.

Whenever a reset occurs during normal operation (that is, when both V_DDand nRESET are High level), the

nRESET pin is forced Low level and the reset operation starts. All system and peripheral control registers are

then reset to their default hardware values

In summary, the following sequence of events occurs during a reset operation:

— All interrupt is disabled.

— The watchdog function (basic timer) is enabled.

— Ports 0-10 and set to input mode, and all pull-up resistors are disabled for the I/O port.

— Peripheral control and data register settings are disabled and reset to their default hardware values.

— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.

— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM

location 0100H (and 0101H) is fetched and executed at normal mode by smart option.

— The reset address at ROM can be changed by Smart Option in the S3F82NB (full-flash device). Refer to "The

Chapter 18. Embedded Flash Memory Interface" for more detailed contents.

NORMAL MODE RESET OPERATION

In normal mode, the Test pin is tied to V_SS. A reset enables access to the 64-Kbyte on-chip ROM. (The external

interface is not automatically configured).

NOTE

To program the duration of the oscillation stabilization interval, you make the appropriate settings to the

basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic

timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can

disable it by writing "1010B" to the upper nibble of BTCON.

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HARDWARE RESET VALUES

Table 8-1, 8-2, 8-3, 8-4 list the reset values for CPU and system registers, peripheral control registers, and

peripheral data registers following a reset operation. The following notation is used to represent reset values:

— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.

— An "x" means that the bit value is undefined after a reset.

— A dash ("–") means that the bit is either not used or not mapped, but read 0 is the bit value.

Table 8-1. S3F82NB Set 1 Register and Values after RESET

Register Name

Mnemonic

Address

Dec Hex

Locations D0H–D2H are not mapped.

Bit Values after RESET

7

6

5

4

3

2

1

0

Basic timer control register

System clock control register

System flags register

Register pointer 0

Register pointer 1

Stack pointer (high byte)

Stack pointer (low byte)

Instruction pointer (high byte)

Instruction pointer (low byte)

Interrupt request register

Interrupt mask register

System mode register

Register page pointer

BTCON

CLKCON

FLAGS

RP0

211

212

213

214

215

216

217

218

219

220

221

222

223

D3H

D4H

D5H

D6H

D7H

D8H

D9H

DAH

DBH

DCH

DDH

DEH

DFH

0

x

1

x

0

x

0

–

x

1

x

0

x

–

0

–

x

0

x

0

x

–

0

x

0

x

0

x

0

x

0

1

x

0

x

0

–

x

–

x

0

x

0

–

0

–

x

0

x

0

–

0

–

x

0

x

0

RP1

SPH

SPL

IPH

IPL

IRQ

IMR

SYM

PP

NOTES:

1. An 'x' means that the bit value is undefined following reset.

2. A dash ('-') means that the bit is neither used nor mapped, but the bit is read as “0”.

Table 8-2. S3F82NB Page15 Register and Values after RESET

Register Name

Mnemonic

Address

Bit Values after RESET

Dec

176

Hex

B0H

7

6

5

4

3

2

1

0

Reset Source Indicating Register

RESETID

Refer to the Page 4-51.

NOTES:

1. An 'x' means that the bit value is undefined following reset.

2. A dash ('–') means that the bit is neither used nor mapped, but the bit is read as “0”.

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Table 8-3. S3F82NB Set 1, Bank 0 Register and Values after RESET

Register Name

Mnemonic Address

Bit Values after RESET

Dec Hex

PG0CON 208 D0H

PG1CON 209 D1H

7

0

–

x

6

0

–

x

5

0

x

4

0

x

3

0

x

2

0

x

1

0

x

0

x

Port Group 0 Control Register

Port Group 1 Control Register

Port 6 Control Register

A/D Converter Data Register (High Byte)

A/D Converter Data Register (Low Byte)

A/D Converter Control Register

Timer 0 Counter Register

Timer 0 Data Register

Timer 0 Control Register

Timer B Counter Register

Timer A Counter Register

Timer B Data Register

Timer A Data Register

Timer B Control Register

Timer 1/A Control Register

Timer Interrupt Pending Register

Timer Interrupt Control Register

Watch Timer Control Register

LCD Control Register

P6CON

210 D2H

ADDATAH 224 E0H

ADDATAL 225 E1H

–

0

1

0

1

0

–

0

–

0

–

0

–

0

1

0

1

0

–

0

–

0

–

0

–

0

1

0

1

0

–

0

–

0

–

0

–

0

1

0

1

–

0

–

0

–

0

–

0

1

0

1

–

0

–

0

–

0

1

0

1

0

–

0

–

0

x

ADCON

T0CNT

226 E2H

227 E3H

228 E4H

229 E5H

230 E6H

231 E7H

232 E8H

233 E9H

234 EAH

235 EBH

0

1

0

1

0

–

0

–

0

1

–

0

1

–

0

–

0

T0DATA

T0CON

TBCNT

TACNT

TBDATA

TADATA

TBCON

TACON

TINTPND 236 ECH

TINTCON 237 EDH

WTCON

LCON

LMOD

238 EEH

239 EFH

240 F0H

LCD Mode Register

Comparator Control Register

Comparator Result Register

SIO Control Register

SIO Data Register

SIO Pre-scaler Register

Flash Memory Sector Address Register (High Byte)

Flash Memory Sector Address Register (Low Byte)

Flash Memory User Programming Enable Register

Flash Memory Control Register

Oscillator Control Register

STOP Control register

CMPCON 241 F1H

CMPREG 242 F2H

SIOCON

SIODATA 244 F4H

SIOPS 245 F5H

243 F3H

FMSECH 246 F6H

FMSECL 247 F7H

FMUSR

FMCON

248 F8H

249 F9H

OSCCON 250 FAH

STPCON 251 FBH

Location FCH is not mapped.

BTCNT 253 FDH

Location FEH is not mapped.

Basic Timer Counter

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

x

Interrupt Priority Register

IPR

255 FFH

NOTES:

1. An 'x' means that the bit value is undefined following reset.

2. A dash ('–') means that the bit is neither used nor mapped, but the bit is read as “0”.

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Table 8-4. S3F82NB Set 1, Bank 1 Register and Values after RESET

Register Name

Mnemonic

Address

Dec Hex

208 D0H

209 D1H

210 D2H

224 E0H

225 E1H

226 E2H

227 E3H

228 E4H

229 E5H

230 E6H

231 E7H

232 E8H

233 E9H

234 EAH

235 EBH

236 ECH

237 EDH

238 EEH

239 EFH

240 F0H

241 F1H

242 F2H

243 F3H

244 F4H

245 F5H

246 F6H

247 F7H

248 F8H

249 F9H

250 FAH

251 FBH

252 FCH

253 FDH

254 FEH

255 FFH

Bit Values after RESET

7

0

–

0

–

0

–

0

6

0

–

0

–

0

–

0

5

0

–

0

–

0

4

0

–

0

–

0

3

0

–

0

–

0

–

0

2

0

–

0

–

0

1

0

–

0

–

0

Port 4 Control Register (High Byte)

Port 4 Control Register (Low Byte)

Port 4 Pull-up Resistor Enable Register

Port 0 Control Register (High Byte)

Port 0 Control Register (Low Byte)

Port 0 Pull-up Resistor Enable Register

Alternative Function Selection Register

Port 1 Control Register (High Byte)

Port 1 Control Register (Low Byte)

Port 1 Pull-up Resistor Enable Register

Port 1 Interrupt Pending Register

Port 1 Interrupt Control Register (High Byte)

Port 1 Interrupt Control Register (Low Byte)

Port 2 Control Register (High Byte)

Port 2 Control Register (Low Byte)

Port 2 Pull-up Resistor Enable Register

Port 3 Pull-up Resistor Enable Register

Port 3 Control Register (High Byte)

Port 3 Control Register (Low Byte)

Port 0 Data Register

P4CONH

P4CONL

P4PUR

P0CONH

P0CONL

P0PUR

AFSEL

P1CONH

P1CONL

P1PUR

P1PND

P1INTH

P1INTL

P2CONH

P2CONL

P2PUR

P3PUR

P3CONH

P3CONL

P0

Port 1 Data Register

Port 2 Data Register

Port 3 Data Register

Port 4 Data Register

Port 5 Data Register

Port 6 Data Register

Port 7 Data Register

Port 8 Data Register

P1

P2

P3

P4

P5

P6

P7

P8

Port 9 Data Register

Port 10 Data Register

P9

P10

Port 5 Interrupt Control Register

Port 5 Interrupt Pending Register

Port 5 Pull-up Resistor Enable Register

Port 5 Control Register (High Byte)

Port 5 Control Register (Low Byte)

P5INT

P5PND

P5PUR

P5CONH

P5CONL

NOTES:

1. An 'x' means that the bit value is undefined following reset.

2. A dash ('–') means that the bit is neither used nor mapped, but the bit is read as “0”.

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POWER-DOWN MODES

STOP MODE

Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all

peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than

3ꢎA. All system functions stop when the clock “freezes”, but data stored in the internal register file is retained.

Stop mode can be released in one of two ways: by a reset or by interrupts, for more details see Figure 7-6.

NOTE

Do not use stop mode if you are using an external clock source because X_INor XT_INinput must be

restricted internally to V_SSto reduce current leakage.

Using nRESET to Release Stop Mode

Stop mode is released when the nRESET signal is released and returns to high level: all system and peripheral

control registers are reset to their default hardware values and the contents of all data registers are retained. A

reset operation automatically selects a slow clock fxx/16 because CLKCON.3 and CLKCON.4 are cleared to

‘00B’. After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization

routine by fetching the program instruction stored in ROM location 0100H (and 0101H)

Using an External Interrupt to Release Stop Mode

External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can

use to release Stop mode in a given situation depends on the microcontroller’s current internal operating mode.

The external interrupts in the S3F82NB interrupt structure that can be used to release Stop mode are:

— External interrupts P1.0–P1.7, P5.4–P5.7 (INT0–INT11)

Please note the following conditions for Stop mode release:

— If you release Stop mode using an external interrupt, the current values in system and peripheral control

registers are unchanged except STPCON register.

— If you use an internal or external interrupt for Stop mode release, you can also program the duration of the

oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before

entering Stop mode.

— When the Stop mode is released by external interrupt, the CLKCON.4 and CLKCON.3 bit-pair setting remains

unchanged and the currently selected clock value is used.

— The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service

routine, the instruction immediately following the one that initiated Stop mode is executed.

Using an Internal Interrupt to Release Stop Mode

Activate any enabled interrupt, causing Stop mode to be released. Other things are same as using external

interrupt.

How to Enter into Stop Mode

Handling STPCON register then writing STOP instruction (keep the order).

LD

STPCON,#10100101B

STOP

NOP

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IDLE MODE

Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some

peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all

peripherals timers remain active. Port pins retain the mode (input or output) they had at the time idle mode was

entered.

There are two ways to release idle mode:

1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents

of all data registers are retained. The reset automatically selects the slow clock fxx/16 because CLKCON.4

and CLKCON.3 are cleared to ‘00B’. If interrupts are masked, a reset is the only way to release idle mode.

2. Activate any enabled interrupt, causing idle mode to be released. When you use an interrupt to release idle

mode, the CLKCON.4 and CLKCON.3 register values remain unchanged, and the currently selected clock

value is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction

immediately following the one that initiated idle mode is executed.

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9

I/O PORTS

OVERVIEW

The S3F82NB microcontroller has eleven bit-programmable I/O ports, P0–P10. The port 6 is a 3-bit port and the

others are 8-bit ports. This gives a total of 83 I/O pins. Each port can be flexibly configured to meet application

design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O

instructions are required.

Table 9-1 gives you a general overview of the S3F82NB I/O port functions.

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Table 9-1. S3F82NB Port Configuration Overview

Configuration Options

Port

0

1-bit programmable I/O port.

Input (P0.0 and P0.1 are Schmitt trigger input) or push-pull, open-drain output mode selected by

software; software assignable pull-ups.

Alternately P0.0–P0.7 can be used as T1CLK/AD0, T0CLK/AD1, T1OUT/T1PWM/T1CAP/AD2,

T0OUT/T0PWM/T0CAP/AD3, AD4–AD7.

1

1-bit programmable I/O port.

Schmitt trigger input or push-pull, open-drain output mode selected by software; software assignable

pull-ups.

P1.0–P1.7 can be used as inputs for external interrupts INT0–INT7 (with noise filter, interrupt enable

and pending control).

The P1.0 is configured as one of the P1.0/INT0 and AV_REFby “Smart option”.

Alternately P1.0–P1.7 can be used as BUZ, SI, SO, SCK.

2

3

4

5

1-bit programmable I/O port.

Input or push-pull, open-drain output mode selected by software; software assignable pull-ups.

Alternatively P2.0-P2.7 can be used as outputs for LCD SEG.

1-bit programmable I/O port.

Input or push-pull, open-drain output mode selected by software; software assignable pull-ups.

Alternatively P3.0-P3.7 can be used as outputs for LCD SEG.

1-bit programmable I/O port.

Input or push-pull, open-drain output mode selected by software; software assignable pull-ups.

Alternatively P4.0-P4.7 can be used as outputs for LCD SEG.

1-bit programmable I/O port.

Input (P5.4–P5.7 are Schmitt trigger input) or push-pull, open-drain output mode selected by

software; software assignable pull-ups.

P5.4–P5.7 can be used as inputs for external interrupts INT8–INT11 (with noise filter, interrupt

enable and pending control).

Alternatively P5.0-P5.7 can be used as outputs for LCD SEG.

6

7

1-bit programmable I/O port.

Schmitt trigger input or push-pull output mode selected by software; software assignable pull-ups.

Alternatively P6.0–P6.2 can be used as CIN0–CIN2.

4-bit programmable I/O port.

Input or push-pull output mode selected by software; software assignable pull-ups.

Alternatively P7.0–P7.7 can be used as outputs for LCD SEG.

8

4-bit programmable I/O port.

Input or push-pull output mode selected by software; software assignable pull-ups.

Alternatively P8.0–P8.7 can be used as outputs for LCD SEG.

9

4-bit programmable I/O port.

Input or push-pull output mode selected by software; software assignable pull-ups.

Alternatively P9.0–P9.7 can be used as outputs for LCD SEG.

10

4-bit programmable I/O port.

Input or push-pull output mode selected by software; software assignable pull-ups.

Alternatively P10.0–P10.7 can be used as outputs for LCD SEG.

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PORT DATA REGISTERS

Table 9-2 gives you an overview of the register locations of all twelve S3F82NB I/O port data registers. Data

registers for ports 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10 have the general format shown in Figure 9-1.

Table 9-2. Port Data Register Summary

Register Name

Port 0 data register

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

Port 10 data register

Mnemonic

P0

Decimal

Hex

F0H

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

F9H

FAH

Location

R/W

0

1

Set 1, Bank 1

P1

P2

2

P3

3

P4

4

P5

5

P6

6

P7

7

P8

8

P9

9

P10

10

S3F82NB I/O Port Data Register Format (n = 0-10)

.7 .6 .5 .4 .3 .2 .1 .0

MSB

LSB

Pn.7 Pn.6 Pn.5 Pn.4 Pn.3 Pn.2 Pn.1 Pn.0

Figure 9-1. S3F82NB I/O Port Data Register Format

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PORT 0

Port 0 is an 8-bit I/O port that can be used for general purpose I/O as A/D converter inputs, AD0-AD7. Port 0 pins

are accessed directly by writing or reading the port 0 data register, P0 at location F0H in Set 1, Bank 1. P0.0–P0.7

can serve as inputs (with or without pull-ups), as outputs (push-pull or open-drain). And you can configure the

following alternative functions:

— Low-byte pins (P0.0–P0.3): AD0/T1CLK, AD1/T0CLK, AD2/T1OUT/T1PWM/T1CAP,

AD3/T0OUT/T0PWM/T0CAP

— High-byte pins (P0.4–P0.7): AD4-AD7

Port 0 Control Register (P0CONH, P0CONL)

Port 0 has two 8-bit control registers: P0CONH for P0.4-P0.7 and P0CONL for P0.0-P0.3. A reset clears the

P0CONH and P0CONL registers to "00H", configuring all pins to input mode. You use control registers settings to

select input or output mode, enable pull-up resistors, select push-pull or open-drain output mode and enable the

alternative functions.

When programming the port, please remember that any alternative peripheral I/O function you configure using the

port 0 control registers must also be enabled in the associated peripheral module.

Port 0 Pull-up Resistor Enable Register (P0PUR)

Using the port 0 pull-up resistor enable register, P0PUR (E2H, set1, bank1), you can configure pull-up resistors to

individual port 0 pins.

Alternative Function Selection Register (AFSEL)

Using the port 0 alternative function selection register, AFSEL (E3H, set1, bank1), you can configure alternative

mode to P0.2 and P0.3. The AD3 or T0OUT/T0PWM outputs depend on AFSEL.1 and the AD2 or

T1OUT/T1PWM outputs depend on AFSEL.0.

Port 0 Control Register, High Byte (P0CONH)

E0H, Set 1, Bank 1, R/W

MSB

LSB

.7

.6

.5

.4

.3

.2

.1

.0

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0CONH bit-pair pin configuration settings:

00

01

10

11

Input mode

Output mode, open-drain

Output mode, push-pull

Alternative function (AD4-AD7)

Figure 9-2. Port 0 High-Byte Control Register (P0CONH)

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Port 0 Control Register, Low Byte (P0CONL)

E1H, Set 1, Bank 1, R/W

MSB

LSB

.7

.6

.5

.4

.3

.2

.1

.0

P0.2/AD2

/T1OUT/T1PWM

/T1CAP

P0.3/AD3

/T0OUT/T0PWM

/T0CAP

P0.1/AD1

/T0CLK

P0.0/AD0

/T1CLK

P0CONL bit-pair pin configuration settings:

00

01

10

11

Input mode (T0CAP, T1CAP), Schmitt trigger input mode (T0CLK, T1CLK)

Output mode, open-drain

Output mode, push-pull

Alternative function (AD0, AD1, AD2/T1OUT/T1PWM, AD3/T0OUT/T0PWM)

NOTE: The P0.2 and P0.3 alternative functions depend on

AFSEL.0 and AFSEL.1, respectively.

Figure 9-3. Port 0 Low-Byte Control Register (P0CONL)

Port 0 Pull-up Resistor Enable Register (P0PUR)

E2H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0

P0PUR bit configuration settings:

0

1

Disable Pull-up Resistor

Enable Pull-up Resistor

NOTE: A pull-up resistor of port 0 is automatically disabled

only when the corresponding pin is selected as

push-pull output or alternative function.

Figure 9-4. Port 0 Pull-up Resistor Enable Register (P0PUR)

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235

Alternative Function Selection Register (AFSEL)

E3H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used for the S3F82NB

P0.3 Alternative mode selection bit:

0

1

Alternative Function (AD3)

Alternative Function (T0OUT/T0PWM)

P0.2 Alternative mode selection bit:

0

1

Alternative Function (AD2)

Alternative Function (T1OUT/T1PWM)

Figure 9-5. Alternative Function Selection Register (AFSEL)

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PORT 1

Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading

the port 1 data register, P1 at location F1H in set 1, bank 1. P1.0–P1.7 can serve as inputs (with or without pull-

ups), as outputs (push-pull or open-drain). P1.0 is configured as one of the P1.0/INT0 and AV

option”. And you can configure the following alternative functions:

by “Smart

REF

— Low-byte pins (P1.0-P1.3): AV

REF

— High-byte pins (P1.4-P1.7): BUZ, SI, SO, SCK

Port 1 Control Register (P1CONH, P1CONL)

Port 1 has two 8-bit control registers: P1CONH for P1.4-P1.7 and P1CONL for P1.0-P1.3. A reset clears the

P1CONH and P1CONL registers to "00H", configuring all pins to input mode. In input mode, three different

selections are available:

— Schmitt trigger input with interrupt generation on falling signal edges.

— Schmitt trigger input with interrupt generation on rising signal edges.

— Schmitt trigger input with interrupt generation on falling/rising signal edges.

When programming the port, please remember that any alternative peripheral I/O function you configure using the

port 1 control registers must also be enabled in the associated peripheral module.

Port 1 Pull-up Resistor Enable Register (P1PUR)

Using the port 1 pull-up resistor enable register, P1PUR (E6H, set1, bank1), you can configure pull-up resistors to

individual port 1 pins.

Port 1 Interrupt Enable and Pending Registers (P1INTH, P1INTL, P1PND)

To process external interrupts at the port 1 pins, the additional control registers are provided: the port 1 interrupt

enable register P1INTH (high byte, E8H, set 1, bank 1), P1INTL (Low byte, E9H, set1, bank1) and the port 1

interrupt pending register P1PND (E7H, set 1, bank 1).

The port 1 interrupt pending register P1PND lets you check for interrupt pending conditions and clear the pending

condition when the interrupt service routine has been initiated. The application program detects interrupt requests

by polling the P1PND register at regular intervals.

When the interrupt enable bit of any port 1 pin is “1”, a rising or falling signal edge at that pin will generate an

interrupt request. The corresponding P1PND bit is then automatically set to “1” and the IRQ level goes low to

signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application

software must the clear the pending condition by writing a “0” to the corresponding P1PND bit.

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Port 1 Control Register, High Byte (P1CONH)

E4H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P1.7/INT7

/SCK

P1.6/INT6

/SO

P1.5/INT5

/SI

P1.4/INT4

/BUZ

P1CONH bit-pair pin configuration settings:

00 Schmitt trigger input mode (SCK, SI)

10

01

Output mode, open-drain

Output mode, push-pull

11 Alternative function (BUZ, SO, SCK, not used for P1.5)

Figure 9-6. Port 1 High-Byte Control Register (P1CONH)

Port 1 Control Register, Low Byte (P1CONL)

E5H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P1.3/INT3

P1.2/INT2

P1.1/INT1

P1.0/INT0

/AVREF

P1CONL bit-pair pin configuration settings:

00 Schmitt trigger input mode

Output mode, open-drain

Output mode, push-pull

10

01

11 Not available

NOTE: Refer to the SMART OPTION for configuring as

one of the P1.0/INT0 and AVREF.

Figure 9-7. Port 1 Low-Byte Control Register (P1CONL)

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Port 1 Pull-up Resistor Enable Register (P1PUR)

E6H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0

P1PUR bit configuration settings:

0

1

Disable Pull-up Resistor

Enable Pull-up Resistor

NOTE: A pull-up resistor of port 1 is automatically disabled

only when the corresponding pin is selected as

push-pull output or alternative function.

Figure 9-8. Port 1 Pull-up Resistor Enable Register (P1PUR)

Port 1 Interrupt Control Register, High Byte (P1INTH)

E8H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

INT7

INT6

INT5

INT4

P1INTH bit-pair pin configuration settings:

00

01

10

11

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

Figure 9-9. Port 1 High-Byte Interrupt Control Register (P1INTH)

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239

Port 1 Interrupt Control Register, Low Byte (P1INTL)

E9H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

INT3

INT2

INT1

INT0

P1INTL bit-pair pin configuration settings:

00

01

10

11

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

Figure 9-10. Port 1 Low-Byte Interrupt Control Register (P1INTL)

Port 1 Interrupt Pending Register (P1PND)

E7H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

PND7 PND6 PND5 PND4 PND3 PND2 PND1 PND0

P1PND bit configuration settings:

0

Interrupt request is not pending,

pending bit clear when write 0

1

Interrupt request is pending

Figure 9-11. Port 1 Interrupt Pending Register (P1PND)

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240

PORT 2

Port 2 is an 8-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading

the port 2 data register, P2 at location F2H in set 1, bank 1. P2.0–P2.7 can serve as inputs (with or without pull-

ups), as outputs (push-pull or open-drain). And they can serve as segment pins for LCD also.

Port 2 Control Register (P2CONH, P2CONL)

Port 2 has two 8-bit control registers: P2CONH for P2.4–P2.7 and P2CONL for P2.0–P2.3. A reset clears the

P2CONH and P2CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to

select input or output mode, enable pull-up resistors, select push-pull or open drain output mode and enable the

alternative functions.

Port 2 Pull-up Resistor Enable Register (P2PUR)

Using the port 2 pull-up resistor enable register, P2PUR (ECH, set1, bank1), you can configure pull-up resistors to

individual port 2 pins.

Port 2 Control Register, High Byte (P2CONH)

EAH, Set 1, Bank 1, R/W

MSB

LSB

.7

.6

.5

.4

.3

.2

.1

.0

P2.7/SEG63 P2.6/SEG62 P2.5/SEG61 P2.4/SEG60

P2CONH bit-pair pin configuration settings:

00

01

10

11

Input mode

Output mode, Open-drain

Output mode, Push-pull

Alternative function (SEG60-SEG63)

Figure 9-12. Port 2 High-Byte Control Register (P2CONH)

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241

Port 2 Control Register, Low Byte (P2CONL)

EBH, Set 1, Bank 1, R/W

MSB

LSB

.7

.6

.5

.4

.3

.2

.1

.0

P2.3/SEG59 P2.2/SEG58 P2.1/SEG57 P2.0/SEG56

P2CONL bit-pair pin configuration settings:

00

01

10

11

Input mode

Output mode, Open-drain

Output mode, Push-pull

Alternative function (SEG56-SEG59)

Figure 9-13. Port 2 Low-Byte Control Register (P2CONL)

Port 2 Pull-up Resistor Enable Register (P2PUR)

ECH, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0

P2PUR bit configuration settings:

0

1

Disable Pull-up Resistor

Enable Pull-up Resistor

NOTE: A pull-up resistor of port 2 is automatically disabled

only when the corresponding pin is selected as

push-pull output or alternative function.

Figure 9-14. Port 2 Pull-up Resistor Enable Register (P2PUR)

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PORT 3

Port 3 is an 8-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading

the port 3 data register, P3 at location F3H in set 1, bank 1. P3.0–P3.7 can serve as inputs (with or without pull-

ups), as outputs (push-pull or open-drain). And they can serve as segment pins for LCD also.

Port 3 Control Register (P3CONH, P3CONL)

Port 3 has two 8-bit control registers: P3CONH for P3.4–P3.7 and P3CONL for P3.0–P3.3. A reset clears the

P3CONH and P3CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to

select input or output mode, enable pull-up resistors, select push-pull or open drain output mode and enable the

alternative functions.

Port 3 Pull-up Resistor Enable Register (P3PUR)

Using the port 3 pull-up resistor enable register, P3PUR (EDH, set1, bank1), you can configure pull-up resistors to

individual port 3 pins.

Port 3 Control Register, High Byte (P3CONH)

EEH, Set 1, Bank 1, R/W

MSB

LSB

.7

.6

.5

.4

.3

.2

.1

.0

P3.7/SEG71 P3.6/SEG70 P3.5/SEG69 P3.4/SEG68

P3CONH bit-pair pin configuration settings:

00

01

10

11

Input mode

Output mode, Open-drain

Output mode, Push-pull

Alternative function (SEG68-SEG71)

Figure 9-15. Port 3 High-Byte Control Register (P3CONH)

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243

Port 3 Control Register, Low Byte (P3CONL)

EFH, Set 1, Bank 1, R/W

MSB

LSB

.7

.6

.5

.4

.3

.2

.1

.0

P3.3/SEG67 P3.2/SEG66 P3.1/SEG65 P3.0/SEG64

P3CONL bit-pair pin configuration settings:

00

01

10

11

Input mode

Output mode, Open-drain

Output mode, Push-pull

Alternative function (SEG64-SEG67)

Figure 9-16. Port 3 Low-Byte Control Register (P3CONL)

Port 3 Pull-up Resistor Enable Register (P3PUR)

EDH, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0

P3PUR bit configuration settings:

0

1

Disable Pull-up Resistor

Enable Pull-up Resistor

NOTE: A pull-up resistor of port 3 is automatically disabled

only when the corresponding pin is selected as

push-pull output or alternative function.

Figure 9-17. Port 3 Pull-up Resistor Enable Register (P3PUR)

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244

PORT 4

Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading

the port 4 data register, P4 at location F4H in set 1, bank 1. P4.0–P4.7 can serve as inputs (with or without pull-

ups), as outputs (push-pull or open-drain). And they can serve as segment pins for LCD also.

Port 4 Control Register (P4CONH, P4CONL)

Port 4 has two 8-bit control registers: P4CONH for P4.4–P4.7 and P4CONL for P4.0–P4.3. A reset clears the

P4CONH and P4CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to

select input or output mode, enable pull-up resistors, select push-pull or open drain output mode and enable the

alternative functions.

Port 4 Pull-up Resistor Enable Register (P4PUR)

Using the port 4 pull-up resistor enable register, P4PUR (D2H, set1, bank1), you can configure pull-up resistors to

individual port 4 pins.

Port 4 Control Register, High Byte (P4CONH)

D0H, Set 1, Bank 1, R/W

MSB

LSB

.7

.6

.5

.4

.3

.2

.1

.0

P4.7/SEG79 P4.6/SEG78 P4.5/SEG77 P4.4/SEG76

P4CONH bit-pair pin configuration settings:

00

01

10

11

Input mode

Output mode, Open-drain

Output mode, Push-pull

Alternative function (SEG76-SEG79)

Figure 9-18. Port 4 High-Byte Control Register (P4CONH)

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245

Port 4 Control Register, Low Byte (P4CONL)

D1H, Set 1, Bank 1, R/W

MSB

LSB

.7

.6

.5

.4

.3

.2

.1

.0

P4.3/SEG75 P4.2/SEG74 P4.1/SEG73 P4.0/SEG72

P4CONL bit-pair pin configuration settings:

00

01

10

11

Input mode

Output mode, Open-drain

Output mode, Push-pull

Alternative function (SEG72-SEG75)

Figure 9-19. Port 4 Low-Byte Control Register (P4CONL)

Port 4 Pull-up Resistor Enable Register (P4PUR)

D2H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0

P4PUR bit configuration settings:

0

1

Disable Pull-up Resistor

Enable Pull-up Resistor

NOTE: A pull-up resistor of port 4 is automatically disabled

only when the corresponding pin is selected as

push-pull output or alternative function.

Figure 9-20. Port 4 Pull-up Resistor Enable Register (P4PUR)

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PORT 5

Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading

the port 5 data register, P5 at location F5H in set 1, bank 1. P5.0–P5.7 can serve as inputs (with or without pull-

ups), as outputs (push-pull or open-drain). And they can serve as segment pins for LCD also. And you can

configure the following alternative functions:

— High-byte pins (P5.4–P5.7): INT8-INT11

Port 5 Control Register (P5CONH, P5CONL)

Port 5 has two 8-bit control registers: P5CONH for P5.4-P5.7 and P5CONL for P5.0-P5.3. A reset clears the

P5CONH and P5CONL registers to "00H", configuring all pins to input mode. In input mode, three different

selections are available:

— Schmitt trigger input with interrupt generation on falling signal edges.

— Schmitt trigger input with interrupt generation on rising signal edges.

— Schmitt trigger input with interrupt generation on falling/rising signal edges.

Port 5 Interrupt Enable and Pending Registers (P5INT, P5PND)

To process external interrupts at the port 5 pins, the additional control registers are provided: the port 5 interrupt

enable register P5INT (FBH, set 1, bank 1) and the port 5 interrupt pending register P5PND (FCH, set 1, bank 1).

The port 5 interrupt pending register P5PND lets you check for interrupt pending conditions and clear the pending

condition when the interrupt service routine has been initiated. The application program detects interrupt requests

by polling the P5PND register at regular intervals.

When the interrupt enable bit of any port 5 pin is “1”, a rising or falling signal edge at that pin will generate an

interrupt request. The corresponding P5PND bit is then automatically set to “1” and the IRQ level goes low to

signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application

software must the clear the pending condition by writing a “0” to the corresponding P5PND bit.

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Port 5 Control Register, High Byte (P5CONH)

FEH, Set 1, Bank 1, R/W

MSB

LSB

.7

.6

.5

.4

.3

.2

.1

.0

P5.7/INT11 P5.6/INT10

/SEG87 /SEG86

P5.5/INT9

/SEG85

P5.4/INT8

/SEG84

P5CONH bit-pair pin configuration settings:

00

01

10

11

Schmitt trigger input mode

Output mode, Open-drain

Output mode, Push-pull

Alternative function (SEG84-SEG87)

Figure 9-21. Port 5 High-Byte Control Register (P5CONH)

Port 5 Control Register, Low Byte (P5CONL)

FFH, Set 1, Bank 1, R/W

MSB

LSB

.7

.6

.5

.4

.3

.2

.1

.0

P5.3/SEG83 P5.2/SEG82 P5.1/SEG81 P5.0/SEG80

P5CONL bit-pair pin configuration settings:

00

01

10

11

Input mode

Output mode, Open-drain

Output mode, Push-pull

Alternative function (SEG80-SEG83)

Figure 9-22. Port 5 Low-Byte Control Register (P5CONL)

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Port 5 Pull-up Resistor Enable Register (P5PUR)

FDH, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0

P5PUR bit configuration settings:

0

1

Disable Pull-up Resistor

Enable Pull-up Resistor

NOTE: A pull-up resistor of port 5 is automatically disabled

only when the corresponding pin is selected as

push-pull output or alternative function.

Figure 9-23. Port 5 Pull-up Resistor Enable Register (P5PUR)

Port 5 Interrupt Control Register (P5INT)

EBH, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

INT11

INT10

INT9

INT8

P5INT bit-pair pin configuration settings:

00

01

10

11

Disable interrupt

Enable interrupt by falling edge

Enable interrupt by rising edge

Enable interrupt by both falling and rising edge

Figure 9-24. Port 5 High-Byte Interrupt Control Register (P5INT)

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249

Port 5 Interrupt Pending Register (P5PND)

FCH, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

PND11 PND10 PND9 PND8 Not used for the S3F82NB

P5PND bit configuration settings:

0

Interrupt request is not pending,

pending bit clear when write 0

1

Interrupt request is pending

Figure 9-25. Port 5 Interrupt Pending Register (P5PND)

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PORT 6

Port 6 is a 3-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading

the port 6 data register, P6 at location F6H in set 1, bank 0. P6.0–P6.2 can serve as inputs (with or without pull-

ups), as push-pull outputs. And you can configure the following alternative functions:

— Pins (P6.0-P6.2): CIN0, CIN1, CIN2

Port 6 Control Register (P6CON)

Port 6 has one 8-bit control register: P6CON for P6.0–P6.2. A reset clears the P6CON register to “00H”,

configuring all pins to input mode. You use control registers settings to select input (with or without pull-ups) or

push-pull output mode and enable the alternative functions.

When programming the port, please remember that any alternative peripheral I/O function you configure using the

port 6 control register must also be enabled in the associated peripheral module.

Port 6 Control Register (P6CON)

D2H, Set 1, Bank 0, R/W

MSB

LSB

.7

.6

.5

.4

.3

.2

.1

.0

Not used for the S3F82NB P6.2/CIN2 P6.1/CIN1

P6.0/CIN0

P6CON bit-pair pin configuration settings:

00

01

10

11

Schmitt trigger input mode

Schmitt trigger input mode, pull-up

Output mode, Push-pull

Alternative function (CIN0-CIN2)

Figure 9-26. Port 6 Control Register (P6CON)

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PORT 7, 8

Port 7 and Port 8 are 8-bit I/O port with nibble configurable pins, respectively. Port 7 and 8 pins are accessed

directly by writing or reading the port 7 and 8 data registers, P7 at location F7H and P8 at location F8H in set 1,

bank 1. P7.0–P7.7 and P8.0–P8.7 can serve as inputs (with or without pull-ups), as push-pull outputs. And they

can serve as segment pins for LCD also.

Port Group 1 Control Register (PG1CON)

Port 6 and 7 have an 8-bit control register: PG1CON.0–.3 for P7.0–P7.7 and PG1CON.4–.7 for P8.0–P8.7. A

reset clears the PG1CON register to “00H”, configuring all pins to input mode.

Port Group 1 Control Register (PG1CON)

D1H, Set 1, Bank 0, R/W

MSB

LSB

.7

.6

.5

.4

.3

.2

.1

.0

P7.0-P7.3

/SEG48-SEG51

/SEG52-SEG55

P7.4-P7.7

P8.0-P8.3

/SEG40-SEG43

P8.4-P8.7

/SEG44-SEG47

PG1CON bit-pair pin configuration settings:

00

01

10

11

Input mode

Input mode, pull-up

Output mode, Push-pull

Alternative function (SEG40-SEG55)

Figure 9-27. Port Group 1 Control Register (PG1CON)

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PORT 9, 10

Port 9 and Port 10 are 8-bit I/O port with nibble configurable pins, respectively. Port 9 and 10 pins are accessed

directly by writing or reading the port 9 and 10 data registers, P9 at location F9H and P10 at location FAH in set 1,

bank 1. P9.0–P9.7 and P10.0–P10.7 can serve as inputs (with or without pull-ups), as push-pull outputs. And they

can serve as segment pins for LCD also.

Port Group 0 Control Register (PG0CON)

Port 9 and 10 have an 8-bit control register: PG0CON.0–.3 for P9.0–P9.7 and PG0CON.4–.7 for P10.0–P10.7. A

reset clears the PG0CON register to “00H”, configuring all pins to input mode.

Port Group 0 Control Register (PG0CON)

D0H, Set 1, Bank 0, R/W

MSB

LSB

.7

.6

.5

.4

.3

.2

.1

.0

P9.0-P9.3

/SEG32-SEG35

/SEG36-SEG39

P9.4-P9.7

P10.0-P10.3

/SEG24-SEG27

P10.4-P10.7

/SEG28-SEG31

PG0CON bit-pair pin configuration settings:

00

01

10

11

Input mode

Input mode, pull-up

Output mode, Push-pull

Alternative function (SEG24-SEG39)

Figure 9-28. Port Group 0 Control Register (PG0CON)

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10 BASIC TIMER

OVERVIEW

S3F82NB has an 8-bit basic timer.

BASIC TIMER (BT)

You can use the basic timer (BT) in two different ways:

— As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction.

— To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.

The functional components of the basic timer block are:

— Clock frequency divider (fxx divided by 4096, 1024, 128, or 16) with multiplexer

— 8-bit basic timer counter, BTCNT (set 1, Bank 0, FDH, read-only)

— Basic timer control register, BTCON (set 1, D3H, read/write)

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BASIC TIMER CONTROL REGISTER (BTCON)

The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer

counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1,

address D3H, and is read/write addressable using Register addressing mode.

A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of

fxx/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register

control bits BTCON.7–BTCON.4.

The 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH), can be cleared at any time during the normal

operation by writing a "1" to BTCON.1. To clear the frequency dividers, write a "1" to BTCON.0.

Basic TImer Control Register (BTCON)

D3H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Divider clear bit:

0 = No effect

1= Clear dvider

Watchdog timer enable bits:

1010B = Disable watchdog function

Other value = Enable watchdog function

Basic timer counter clear bit:

0 = No effect

1= Clear BTCNT

Basic timer input clock selection bits:

00 = fXX/4096

01 = fXX/1024

10 = fXX/128

11 = fXX/16

Figure 10-1. Basic Timer Control Register (BTCON)

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BASIC TIMER FUNCTION DESCRIPTION

Watchdog Timer Function

You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to

any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to

"00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by

the current CLKCON register setting), divided by 4096, as the BT clock.

A reset is generated whenever the basic timer counter overflow occurs. During normal operation, the application

program must prevent the overflow, and the accompanying reset operation, from occurring, To do this, the

BTCNT value must be cleared (by writing a “1” to BTCON.1) at regular intervals.

If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation

will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during the normal

operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always

broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.

Oscillation Stabilization Interval Timer Function

You can also use the basic timer to program a specific oscillation stabilization interval after a reset or when stop

mode has been released by an external interrupt.

In stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts

increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an external interrupt).

When BTCNT.4 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate

the clock signal off to the CPU so that it can resume the normal operation.

In summary, the following events occur when stop mode is released:

1. During the stop mode, a power-on reset or an external interrupt occurs to trigger the Stop mode release and

oscillation starts.

2. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an interrupt is

used to release stop mode, the BTCNT value increases at the rate of the preset clock source.

3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows.

4. When a BTCNT.4 overflow occurs, the normal CPU operation resumes.

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RESET or STOP

Data Bus

Bit 1

Bits 3, 2

Basic Timer Control Register

(Write '1010xxxxB' to Disable)

f

XX/4096

XX/1024

XX/128

XX/16

Clear

8-Bit Up Counter

(BTCNT, Read-Only)

f

XX

DIV

MUX

OVF

RESET

Start the CPU ^(NOTE)

R

Bit 0

NOTE:

During a power-on reset operation, the CPU is idle during the required oscillation

stabilization interval (until bit 4 of the basic timer counter overflows).

Figure 10-2. Basic Timer Block Diagram

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11 8-BIT TIMER 0

8-BIT TIMER 0

OVERVIEW

The 8-bit timer 0 is an 8-bit general-purpose timer/counter. Timer 0 has three operating modes, one of which you

select using the appropriate T0CON setting:

— Interval timer mode (Toggle output at T0OUT pin)

— Capture input mode with a rising or falling edge trigger at the T0CAP pin

— PWM mode (T0PWM)

Timer 0 has the following functional components:

— Clock frequency divider (fxx divided by 1024, 256, 64, 8 or 1) with multiplexer

— External clock input pin (T0CLK)

— 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)

— I/O pins for capture input (T0CAP) or PWM or match output (T0PWM, T0OUT)

— Timer 0 overflow interrupt (IRQ0 vector DCH) and match/capture interrupt (IRQ0 vector DAH) generation

— Timer 0 control register, T0CON (set 1, Bank 0, E5H, read/write)

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TIMER 0 CONTROL REGISTER (T0CON)

You use the timer 0 control register, T0CON, to

— Select the timer 0 operating mode (interval timer, capture mode, or PWM mode)

— Select the timer 0 input clock frequency

— Clear the timer 0 counter, T0CNT

— Enable the timer 0 counting operation

T0CON is located in set 1, Bank 0 at address E5H, and is read/write addressable using Register addressing

mode.

A reset clears T0CON to '00H'. This sets timer 0 to normal interval timer mode, selects an input clock frequency of

fxx/1024, and disable counting operation. You can clear the timer 0 counter at any time during normal operation

by writing a "1" to T0CON.2.

TIMER INTERRUPT CONTROL REGISTER (TINTCON)

You use the timer interrupt control register, TINTCON, to

— Enable the timer 0 overflow interrupt or timer 0 match/capture interrupt

TINTCON is located in set 1, Bank 0 at address EDH, and is read/write addressable using Register addressing

mode.

The timer 0 overflow interrupt (T0OVF) is interrupt level IRQ0 and has the vector address DCH. When a timer 0

overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware

or must be cleared by software.

To enable the timer 0 match/capture interrupt (IRQ0, vector DAH), you must write TINTCON.1 to "1". To detect a

match/capture interrupt pending condition, the application program polls TINTPND.1. When a "1" is detected, a

timer 0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending

condition must be cleared by software by writing a "0" to the timer 0 match/capture interrupt pending bit,

TINTPND.1.

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Timer 0 Control Register (T0CON)

E5H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Timer 0 clock selection bits:

000 = fxx/1024

001 = fxx/256

Not used for the S3F82NB

010 = fxx/64

Timer 0 counter operating enable bit:

0 = DIsable counting operating

1 = Enable counting operating

011 = fxx/8

100 = fxx/1

101 = External clock (T0CLK) falling edge

110 = External clock (T0CLK) rising edge

111 = Not available

Timer 0 counter clear bit:

0 = No effect

1 = Clear the timer 0 counter (when write)

Timer 0 operating mode selection bits:

00 = Interval mode (T0OUT)

01 = Capture mode (capture on rising edge,

Counter running, OVF can occur)

10 = Capture mode (Capture on falling edge,

Counter running, OVF can occur)

11 = PWM mode (OVF and match interrupt can occur)

Figure 11-1. Timer 0 Control Register (T0CON)

Timer Interrupt Control Register (TINTCON)

EDH, Set 1, Bank 0, R/W

LS

B

MSB

.7

.6

.5

.4

.3

.2

.1

.0

Not used for the S3F82NB

Timer 0 overflow interupt

Timer 0 match/capture interupt

Timer 1/A overflow interupt

Timer 1/A match/capture interupt

Timer B match interupt

TINTCON bit configuration settings:

0

1

Disable Interrupt

Enable Interrupt

Figure 11-2. Timer Interrupt Control Register (TINTCON)

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Timer Interrupt Pending Register (TINTPND)

ECH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used for the S3F82NB

Timer 0 overflow interupt pending bit

Timer 0 match/capture interupt pending bit

Timer 1/A overflow interupt pending bit

Timer 1/A match/capture interupt pending bit

Timer B match interupt pending bit

0 = Interrupt request is not pending, pending bit clear when write "0"

1 = Interrupt request is pending

Figure 11-3. Timer Interrupt Pending Register (TINTPND)

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TIMER 0 FUNCTION DESCRIPTION

Timer 0 Interrupts (IRQ0, Vectors DAH and DCH)

The timer 0 can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/capture

interrupt (T0INT). T0OVF is interrupt level IRQ0, vector DCH. T0INT also belongs to interrupt level IRQ0, but is

assigned the separate vector address, DAH.

A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or

should be cleared by software in the interrupt service routine by writing a “0” to the TINTPND.0 interrupt pending

bit. However, the timer 0 match/capture interrupt pending condition must be cleared by the application’s interrupt

service routine by writing a "0" to the TINTPND.1 interrupt pending bit.

Interval Timer Mode

In interval timer mode, a match signal is generated when the counter value is identical to the value written to the

timer 0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector

DAH) and clears the counter.

If, for example, you write the value "10H" to T0DATA, the counter will increment until it reaches “10H”. At this

point, the timer 0 interrupt request is generated, the counter value is reset, and counting resumes. With each

match, the level of the signal at the timer 0 output pin is inverted (see Figure 11-4).

Interrupt Enable/Disable

Capture Signal

TINTCON.1

R (Clear)

CLK

8-Bit Up Counter

8-Bit Comparator

T0INT (IRQ0)

(Match INT)

M

U

X

Match

TINTPND.1

Pending

T0OUT

Timer 0 Buffer Register

Timer 0 Data Register

T0CON.4-.3

Match Signal

T0CON.2

T0OVF

Figure 11-4. Simplified Timer 0 Function Diagram: Interval Timer Mode

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Pulse Width Modulation Mode

Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the

T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the

value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter.

Instead, it runs continuously, overflowing at "FFH", and then continues incrementing from "00H".

Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in

PWM-type applications. Instead, the pulse at the T0PWM pin is held to Low level as long as the reference data

value is less than or equal to ( ꢆ ) the counter value and then the pulse is held to High level for as long as the

data value is greater than ( > ) the counter value. One pulse width is equal to t_CLKꢀ 256 (see Figure 11-5).

TINTCON.0

Interrupt Enable/Disable

TINTCON.1

Capture Signal

T0OVF(IRQ0)

(Overflow INT)

CLK

8-Bit Up Counter

8-Bit Comparator

TINTPND.0

T0INT (IRQ0)

M

U

X

Match

TINTPND.1

Pending

(Match INT)

T0PWM

Output (P0.3)

High level when

data > counter,

Lower level when

data < counter

Timer 0 Buffer Register

Timer 0 Data Register

T0CON.4-.3

Match Signal

T0CON.2

T0OVF

Figure 11-5. Simplified Timer 0 Function Diagram: PWM Mode

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Capture Mode

In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads the current counter

value into the timer 0 data register. You can select rising or falling edges to trigger this operation.

Timer 0 also gives you capture input source: the signal edge at the T0CAP pin. You select the capture input by

setting the values of the timer 0 capture input selection bits in the port 0 control register, P0CONL.7–.6, (set 1,

bank 1, E1H). When P0CONL.7–.6 is "00" the T0CAP input is selected.

Both kinds of timer 0 interrupts can be used in capture mode: the timer 0 overflow interrupt is generated whenever

a counter overflow occurs; the timer 0 match/capture interrupt is generated whenever the counter value is loaded

into the timer 0 data register.

By reading the captured data value in T0DATA, and assuming a specific value for the timer 0 clock frequency, you

can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin (see Figure 11-6).

TINTCON.0

T0OVF(IRQ0)

8-Bit Up Counter

TINTPND.0

CLK

(Overflow INT)

Interrupt Enable/Disable

TINTCON.1

T0INT (IRQ0)

(Capture INT)

M

U

X

T0CAP

TINTPND.1

Pending

Match Signal

T0CON.4-.3

Timer 0 Data Register

Figure 11-6. Simplified Timer 0 Function Diagram: Capture Mode

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BLOCK DIAGRAM

TINTCON.0

T0CON.7-.5

T0OVF

(IRQ0)

OVF

TINTPND.0

Data Bus

8

fXX/1024

fXX/256

fXX/64

fXX/8

T0CON.1

T0CON.2

Clear

M

U

X

8-bit Up-Counter

(Read Only)

fXX/1

R

TINTCON.1

T0CLK

M

U

X

8-bit Comparator

T0INT

(IRQ0)

Match

TINTPND.1

M

U

T0OUT

T0CAP

X

Timer 0 Buffer Register

T0PWM

T0CON.4-.3

Match Signal

T0CON.2

T0OVF

Timer 0 Data Register

8

Data Bus

Figure 11-7. Timer 0 Functional Block Diagram

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12 TIMER 1

OVERVIEW

The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. When TACON.0 is set to "1", it is in one 16-

bit timer mode. When TACON.0 is set to "0", the timer 1 is used as two 8-bit timers.

— One 16-bit timer mode (Timer 1)

— Two 8-bit timers mode (Timer A and B)

ONE 16-BIT TIMERS MODE (TIMER 1)

OVERVIEW

The 16-bit timer 1 is a 16-bit general-purpose timer. Timer 1 has three operating modes, one of which you select

using the appropriate TACON setting:

— Interval timer mode (Toggle output at T1OUT pin)

— Capture input mode with a rising or falling edge trigger at the T1CAP pin

— PWM mode (T1PWM)

Timer 1 has the following functional components:

— Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer

—

External clock input pin (T1CLK)

— 16-bit counter (TACNT, TBCNT), 16-bit comparator, and 16-bit reference data register (TADATA, TBDATA)

— I/O pins for capture input (T1CAP) or PWM or match output (T1PWM, T1OUT)

— Timer 1 overflow interrupt (IRQ1 vector E0H) and match/capture interrupt (IRQ1 vector DEH) generation

— Timer 1 control register, TACON (set 1, bank 0, EBH, read/write)

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TIMER 1 CONTROL REGISTER (TACON)

You use the timer 1 control register, TACON, to

— Enable the timer 1 operating (interval timer, capture mode, or PWM mode)

— Select the timer 1 input clock frequency

— Clear the timer 1 counter, TACNT and TBCNT

— Enable the timer 1 counting operating

TACON is located in set 1, bank 0, at address EBH, and is read/write addressable using register addressing

mode.

A reset clears TACON to "00H". This sets timer 1 to disable interval timer mode, selects an input clock frequency

of fxx/1024, and disable counting operation. You can clear the timer 1 counter at any time during the normal

operation by writing a "1" to TACON.2.

TIMER INTERRUPT CONTROL REGISTER (TINTCON)

You use the timer interrupt control register, TINTCON, to

— Enable the timer 1/A overflow interrupt or timer 1/A match/capture interrupt

TINTCON is located in set 1, Bank 0 at address EDH, and is read/write addressable using Register addressing

mode.

The timer 1 overflow interrupt (T1OVF) is interrupt level IRQ1 and has the vector address E0H. When a timer 1

overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware

or must be cleared by software.

To enable the timer 1 match/capture interrupt (IRQ1, vector DEH), you must write TACON.0 to "1", TACON.1 and

TINTCON.3 to "1". To detect a match/capture interrupt pending condition, the application program polls

TINTPND.3. When a "1" is detected, a timer 1 match or capture interrupt is pending. When the interrupt request

has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 1

match/capture interrupt pending bit, TINTPND.3.

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Timer 1 Control Register (TACON)

EBH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Timer 1 operating enable bit:

Timer 1 clock selection bits:

000 = fxx/1024

001 = fxx/256

0 = Two 8-bit timer mode (Timer A/B)

1 = One 16-bit timer mdoe (Timer 1)

010 = fxx/64

Timer 1 counter operating enable bit:

0 = DIsable counting operating

1 = Enable counting operating

011 = fxx/8

100 = fxx/1

101 = External clock (T1CLK) falling edge

110 = External clock (T1CLK) rising edge

111 = Not available

Timer 1 counter clear bit:

0 = No effect

1 = Clear the timer 1 counter (when write)

Timer 1 operating mode selection bits:

00 = Interval mode (T1OUT)

01 = Capture mode (capture on rising edge,

Counter running, OVF can occur)

10 = Capture mode (Capture on falling edge,

Counter running, OVF can occur)

11 = PWM mode (OVF and match interrupt can occur)

Figure 12-1. Timer 1 Control Register (TACON)

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Timer Interrupt Control Register (TINTCON)

EDH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used for the S3F82NB

Timer 0 overflow interupt

Timer 0 match/capture interupt

Timer 1/A overflow interupt

Timer 1/A match/capture interupt

Timer B match interupt

TINTCON bit configuration settings:

0

1

Disable Interrupt

Enable Interrupt

Figure 12-2. Timer Interrupt Control Register (TINTCON)

Timer Interrupt Pending Register (TINTPND)

ECH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used for the S3F82NB

Timer 0 overflow interupt pending bit

Timer 0 match/capture interupt pending bit

Timer 1/A overflow interupt pending bit

Timer 1/A match/capture interupt pending bit

Timer B match interupt pending bit

0 = Interrupt request is not pending, pending bit clear when write "0"

1 = Interrupt request is pending

Figure 12-3. Timer Interrupt Pending Register (TINTPND)

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TIMER 1 FUNCTION DESCRIPTION

Timer 1 Interrupts (IRQ1, Vectors DEH and E0H)

The timer 1 can generate two interrupts: the timer 1 overflow interrupt (T1OVF), and the timer 1 match/ capture

interrupt (T1INT). T1OVF is belongs to interrupt level IRQ1, vector E0H. T1INT also belongs to interrupt level

IRQ1, but is assigned the separate vector address, DEH.

A timer 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or

should be cleared by software in the interrupt service routine by writing a “0” to the TINTPND.2 interrupt pending

bit. However, the timer 1 match/capture interrupt pending condition must be cleared by the application’s interrupt

service routine by writing a "0" to the TINTPND.3 interrupt pending bit.

Interval Timer Mode

In interval timer mode, a match signal is generated when the counter value is identical to the value written to the

timer 1 reference data register, TBDATA/TADATA. The match signal generates a timer 1 match interrupt (T1INT,

vector DEH) and clears the counter.

If, for example, you write the value "1087H" to TBDATA/TADATA, the counter will increment until it reaches

“1087H”. At this point, the timer 1 interrupt request is generated, the counter value is reset, and counting

resumes. With each match, the level of the signal at the timer 1 output pin is inverted (see Figure 12-4).

Interrupt Enable/Disable

Capture Signal

TINTCON.3

R (Clear)

CLK

16-Bit Up Counter

16-Bit Comparator

T1INT (IRQ1)

(Match INT)

M

U

X

Match

TINTPND.3

Pending

T1OUT

Timer 1 Buffer Register

Timer 1 Data Register

TACON.4-.3

Match Signal

TACON.2

T1OVF

Figure 12-4. Simplified Timer 1 Function Diagram: Interval Timer Mode

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Pulse Width Modulation Mode

Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the

T1PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the

value written to the timer 1 data register. In PWM mode, however, the match signal does not clear the counter.

Instead, it runs continuously, overflowing at "FFFFH", and then continues incrementing from "0000H".

Although you can use the match signal to generate a timer 1 overflow interrupt, interrupts are not typically used in

PWM-type applications. Instead, the pulse at the T1PWM pin is held to Low level as long as the reference data

value is less than or equal to ( ꢆ ) the counter value and then the pulse is held to High level for as long as the data

value is greater than ( > ) the counter value. One pulse width is equal to t_CLKꢀ 65536 (see Figure 12-5).

TINTCON.2

Interrupt Enable/Disable

TINTCON.3

Capture Signal

T1OVF(IRQ1)

(Overflow INT)

CLK

16-Bit Up Counter

16-Bit Comparator

TINTPND.2

T1INT (IRQ1)

M

U

X

Match

TINTPND.3

Pending

(Match INT)

T1PWM

High level when

data > counter,

Lower level when

data < counter

Timer 1 Buffer Register

Timer 1 Data Register

TACON.4-.3

Match Signal

TACON.2

T1OVF

Figure 12-5. Simplified Timer 1 Function Diagram: PWM Mode

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Capture Mode

In capture mode, a signal edge that is detected at the T1CAP pin opens a gate and loads the current counter

value into the timer 1 data register. You can select rising or falling edges to trigger this operation.

Timer 1 also gives you capture input source: the signal edge at the T1CAP pin. You select the capture input by

setting the values of the timer 1 capture input selection bits in the port 1 control register, P0CONL.5–.4, (set 1,

bank 1, E1H). When P0CONL.5–.4 is "00", the T1CAP input is selected.

Both kinds of timer 1 interrupts can be used in capture mode: the timer 1 overflow interrupt is generated whenever

a counter overflow occurs; the timer 1 match/capture interrupt is generated whenever the counter value is loaded

into the timer 1 data register.

By reading the captured data value in TBDATA/TADATA, and assuming a specific value for the timer 1 clock

frequency, you can calculate the pulse width (duration) of the signal that is being input at the T1CAP pin (see

Figure 12-6).

TINTCON.2

T1OVF(IRQ1)

16-Bit Up Counter

TINTPND.2

CLK

(Overflow INT)

Interrupt Enable/Disable

TINTCON.3

T1INT (IRQ1)

(Capture INT)

M

U

X

T1CAP

TINTPND.3

Pending

Match Signal

TACON.4-.3

Timer 1 Data Register

Figure 12-6. Simplified Timer 1 Function Diagram: Capture Mode

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TIMER 1 BLOCK DIAGRAM

TINTCON.2

Pending

TINTPND.2

TACON.7-.5

T1OVF

(IRQ1)

OVF

Data Bus

16

fXX/1024

fXX/256

fXX/64

fXX/8

TACON.1

TACON.2

Clear

M

U

X

16-bit Up-Counter

(Read Only)

(TBCNT/TACNT)

fXX/1

R

TINTCON.3

T1CLK

M

U

X

16-bit Comparator

Pending

TINTPND.3

T1INT

(IRQ1)

Match

M

U

X

Timer 1 Buffer Register

(16-Bit)

T1OUT

T1CAP

T1PWM

TACON.4-.3

Match Signal

TACON.2

T1OVF

Timer 1 Data Register

(TBDATA/TADATA)

16

Data Bus

NOTE: When TACON.0 is "1", 16-bit timer 1.

Figure 12-7. Timer 1 Functional Block Diagram

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TWO 8-BIT TIMERS MODE (TIMER A and B)

OVERVIEW

The 8-bit timer A is an 8-bit general-purpose timer. Timer A has three operating modes, one of which you select

using the appropriate TACON setting:

— Interval timer mode (Toggle output at T1OUT pin)

— Capture input mode with a rising or falling edge trigger at the T1CAP pin

— PWM mode (T1PWM)

Timer A has the following functional components:

— Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer

— External clock input pin (T1CLK)

— 8-bit counter (TACNT), 8-bit comparator, and 8-bit reference data register (TADATA)

— I/O pins for capture input (T1CAP) or PWM or match output (T1PWM, T1OUT)

— Timer A overflow interrupt (IRQ1 vector E0H) and match/capture interrupt (IRQ1 vector DEH) generation

— Timer A control register, TACON (set 1, bank 0, EBH, read/write)

The 8-bit timer B is an 8-bit general-purpose timer. Timer B includes interval timer mode using appropriate

TBCON setting.

Timer B has the following functional components:

— Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer

— 8-bit counter (TBCNT), 8-bit comparator, and 8-bit reference data register (TBDATA)

— Timer B match interrupt (IRQ2, vector E2H) generation

— Timer B control register, TBCON (set 1, bank 0, EAH, read/write)

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TIMER A CONTROL REGISTER (TACON)

You use the timer A control register, TACON, to

— Enable the timer A (interval timer, capture mode, or PWM mode)

— Select the timer A input clock frequency

— Clear the timer A counter, TACNT

— Select the timer A counting operation

TACON is located in set 1, bank 0, at address EBH, and is read/write addressable using register addressing

mode.

A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency

of fxx/1024, and disables counting operation. You can clear the timer A counter at any time during normal

operation by writing a "1" to TACON.2.

TIMER INTERRUPT CONTROL REGISTER (TINTCON)

You use the timer interrupt control register, TINTCON, to

— Enable the timer 1/A overflow interrupt or timer 1/A match/capture interrupt

TINTCON is located in set 1, Bank 0 at address EDH, and is read/write addressable using Register addressing

mode.

The timer A overflow interrupt (T1OVF) is interrupt level IRQ1 and has the vector address E0H. When a timer A

overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware

or must be cleared by software.

To enable the timer A match/capture interrupt (IRQ1, vector DEH), you must write TACON.0 to "0", TACON.1 and

TINTCON.3 to "1". To detect a match/capture interrupt pending condition, the application program polls

TINTPND.3. When a "1" is detected, a timer A match or capture interrupt is pending. When the interrupt request

has been serviced, the pending condition must be cleared by software by writing a "0" to the timer A

match/capture interrupt pending bit, TINTPND.3.

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Timer A Control Register (TACON)

EBH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Timer A operating enable bit:

Timer A clock selection bits:

000 = fxx/1024

001 = fxx/256

0 = Two 8-bit timer mode (Timer A/B)

1 = One 16-bit timer mdoe (Timer 1)

010 = fxx/64

Timer A counter operating enable bit:

0 = DIsable counting operating

1 = Enable counting operating

011 = fxx/8

100 = fxx/1

101 = External clock (T1CLK) falling edge

110 = External clock (T1CLK) rising edge

111 = Not available

Timer A counter clear bit:

0 = No effect

1 = Clear the timer A counter (when write)

Timer A operating mode selection bits:

00 = Interval mode (T1OUT)

01 = Capture mode (capture on rising edge,

Counter running, OVF can occur)

10 = Capture mode (Capture on falling edge,

Counter running, OVF can occur)

11 = PWM mode (OVF and match interrupt can occur)

Figure 12-8. Timer A Control Register (TACON)

Timer Interrupt Control Register (TINTCON)

EDH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used for the S3F82NB

Timer 0 overflow interupt

Timer 0 match/capture interupt

Timer 1/A overflow interupt

Timer 1/A match/capture interupt

Timer B match interupt

TINTCON bit configuration settings:

0

1

Disable Interrupt

Enable Interrupt

Figure 12-9. Timer Interrupt Control Register (TINTCON)

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Timer Interrupt Pending Register (TINTPND)

ECH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used for the S3F82NB

Timer 0 overflow interupt pending bit

Timer 0 match/capture interupt pending bit

Timer 1/A overflow interupt pending bit

Timer 1/A match/capture interupt pending bit

Timer B match interupt pending bit

0 = Interrupt request is not pending, pending bit clear when write "0"

1 = Interrupt request is pending

Figure 12-10. Timer Interrupt Pending Register (TINTPND)

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TIMER A FUNCTION DESCRIPTION

Timer A Interrupts (IRQ1, Vectors DEH and E0H)

The timer A can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/capture

interrupt (TAINT). TAOVF is interrupt level IRQ1, vector E0H. TAINT also belongs to interrupt level IRQ1, but is

assigned the separate vector address, DEH.

A timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or

should be cleared by software in the interrupt service routine by writing a “0” to the TINTPND.2 interrupt pending

bit. However, the timer A match/capture interrupt pending condition must be cleared by the application’s interrupt

service routine by writing a "0" to the TINTPND.3 interrupt pending bit.

Interval Timer Mode

In interval timer mode, a match signal is generated when the counter value is identical to the value written to the

timer A reference data register, TADATA. The match signal generates a timer A match interrupt (TAINT, vector

DEH) and clears the counter.

If, for example, you write the value "10H" to TADATA, "0" to TACON.0, and 06H to TACON, the counter will

increment until it reaches “10H”. At this point, the timer A interrupt request is generated, the counter value is

reset, and counting resumes. With each match, the level of the signal at the timer A output pin is inverted (see

Figure 12-11).

Interrupt Enable/Disable

Capture Signal

TINTCON.3

R (Clear)

CLK

8-Bit Up Counter

8-Bit Comparator

TAINT (IRQ1)

(Match INT)

M

U

X

Match

TINTPND.3

Pending

T1OUT

Timer A Buffer Register

Timer A Data Register

TACON.4-.3

Match Signal

TACON.2

TAOVF

Figure 12-11. Simplified Timer A Function Diagram: Interval Timer Mode

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Pulse Width Modulation Mode

Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the

T1PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the

value written to the timer A data register. In PWM mode, however, the match signal does not clear the counter.

Instead, it runs continuously, overflowing at "FFH", and then continues incrementing from "00H".

Although you can use the match signal to generate a timer A overflow interrupt, interrupts are not typically used in

PWM-type applications. Instead, the pulse at the T1PWM pin is held to Low level as long as the reference data

value is less than or equal to ( ꢆ ) the counter value and then the pulse is held to High level for as long as the data

value is greater than ( > ) the counter value. One pulse width is equal to t_CLKꢀ 256 (see Figure 12-12).

TINTCON.2

Interrupt Enable/Disable

TINTCON.3

Capture Signal

TAOVF(IRQ1)

(Overflow INT)

CLK

8-Bit Up Counter

8-Bit Comparator

TINTPND.2

TAINT (IRQ1)

M

U

X

Match

TINTPND.3

Pending

(Match INT)

T1PWM

High level when

data > counter,

Lower level when

data < counter

Timer A Buffer Register

Timer A Data Register

TACON.4-.3

Match Signal

TACON.2

TAOVF

Figure 12-12. Simplified Timer A Function Diagram: PWM Mode

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Capture Mode

In capture mode, a signal edge that is detected at the T1CAP pin opens a gate and loads the current counter

value into the timer A data register. You can select rising or falling edges to trigger this operation.

Timer A also gives you capture input source: the signal edge at the T1CAP pin. You select the capture input by

setting the values of the timer A capture input selection bits in the port 0 control register, P0CONL.5–.4, (set 1,

bank 1, E1H). When P0CONL.5–.4 is "00" the T1CAP input is selected.

Both kinds of timer A interrupts can be used in capture mode: the timer A overflow interrupt is generated

whenever a counter overflow occurs; the timer A match/capture interrupt is generated whenever the counter value

is loaded into the timer A data register.

By reading the captured data value in TADATA, and assuming a specific value for the timer A clock frequency,

you can calculate the pulse width (duration) of the signal that is being input at the T1CAP pin (see Figure 12-13).

TINTCON.2

TAOVF(IRQ1)

8-Bit Up Counter

TINTPND.2

CLK

(Overflow INT)

Interrupt Enable/Disable

TINTCON.3

TAINT (IRQ1)

(Capture INT)

M

U

X

T1CAP

TINTPND.3

Pending

Match Signal

TACON.4-.3

Timer A Data Register

Figure 12-13. Simplified Timer A Function Diagram: Capture Mode

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TIMER A BLOCK DIAGRAM

TINTCON.2

Pending

TINTPND.2

TACON.7-.5

TAOVF

(IRQ1)

OVF

Data Bus

8

fXX/1024

fXX/256

fXX/64

fXX/8

TACON.1

TACON.2

Clear

M

U

X

8-bit Up-Counter

(Read Only)

(TACNT)

fXX/1

R

TINTCON.3

T1CLK

M

U

X

8-bit Comparator

Pending

TINTPND.3

TAINT

(IRQ1)

Match

M

U

X

T1OUT

T1PWM

T1CAP

Timer A Buffer Register

TACON.4-.3

Match Signal

TACON.2

TAOVF

Timer A Data Register

(TADATA)

8

Data Bus

NOTE: When TACON.0 is "0", two 8-bit timer A/B.

Figure 12-14. Timer A Functional Block Diagram

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TIMER B CONTROL REGISTER (TBCON)

You use the timer B control register, TBCON, to

— Enable the timer B operating (interval timer)

— Select the timer B input clock frequency

— Clear the timer B counter, TBCNT

— Select the timer B counting operation

TBCON are located in set 1, bank 0, at address EAH, and is read/write addressable using register addressing

mode.

A reset clears TBCON to "00H". This sets timer B to disable interval timer mode, selects an input clock frequency

of fxx/1024, and disables counting operation. You can clear the timer B counter at any time during normal

operation by writing a "1" to TBCON.2.

TIMER INTERRUPT CONTROL REGISTER (TINTCON)

You use the timer interrupt control register, TINTCON, to

— Enable the timer B match interrupt

TINTCON is located in set 1, Bank 0 at address EDH, and is read/write addressable using Register addressing

mode.

To enable the timer B match interrupt (IRQ2, vector E2H), you must write TACON.0 to "0", TBCON.1 and

TINTCON.4 to "1". To detect a match interrupt pending condition, the application program polls TINTPND.4.

When a "1" is detected, a timer B match interrupt is pending. When the interrupt request has been serviced, the

pending condition must be cleared by software by writing a "0" to the timer B match interrupt pending bit,

TINTPND.4.

TIMER B FUNCTION DESCRIPTION

Interval Timer Function

The timer B module can generate an interrupt: the timer B match interrupt (TBINT). TBINT belongs to the interrupt

level IRQ2 and is assigned a separate vector address, E2H.

The TBINT pending condition should be cleared by software after they are serviced.

In interval timer mode, a match signal is generated when the counter value is identical to the values written to the

TB reference data registers, TBDATA. The match signal generates corresponding match interrupt (TBINT, vector

E2H) and clears the counter.

If, for example, you write the value 10H to TBDATA, "0" to TACON.0, and 06H to TBCON, the counter will

increment until it reaches 10H. At this point, the TB interrupt request is generated, the counter value is reset, and

counting resumes.

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282

Timer B Control Register (TBCON)

EAH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used for the S3F82NB

Timer B clock selection bits:

000 = fxx/1024

001 = fxx/256

Timer B counter operating enable bit:

0 = DIsable counting operating

1 = Enable counting operating

010 = fxx/64

011 = fxx/8

100 = fxx/1

Others = Not available

Timer B counter clear bit:

0 = No effect

1 = Clear the timer B counter (when write)

Not used for the S3F82NB

Figure 12-15. Timer B Control Register (TBCON)

Timer Interrupt Control Register (TINTCON)

EDH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used for the S3F82NB

Timer 0 overflow interupt

Timer 0 match/capture interupt

Timer 1/A overflow interupt

Timer 1/A match/capture interupt

Timer B match interupt

TINTCON bit configuration settings:

0

1

Disable Interrupt

Enable Interrupt

Figure 12-16. Timer Interrupt Control Register (TINTCON)

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Timer Interrupt Pending Register (TINTPND)

ECH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used for the S3F82NB

Timer 0 overflow interupt pending bit

Timer 0 match/capture interupt pending bit

Timer 1/A overflow interupt pending bit

Timer 1/A match/capture interupt pending bit

Timer B match interupt pending bit

0 = Interrupt request is not pending, pending bit clear when write "0"

1 = Interrupt request is pending

Figure 12-17. Timer Interrupt Pending Register (TINTPND)

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284

TIMER B BLOCK DIAGRAM

TBCON.7-.5

Data BUS

8

TBCON.1

TBCON.2

fxx/1024

fxx/256

fxx/64

fxx/8

MUX

8-Bit Up Counter

(Read-Only)

(TBCNT)

Clear

R

fxx/1

TINTCON.4

Pending

TINTPND.4

TBINT

(IRQ2)

8-Bit Comparator

Match

Timer B Buffer Register

Match signal

TBCON.2

Timer B Data Register

(Read-Only)

(TBDATA)

8

Data BUS

NOTE: When TACON.0 is "0", two 8-bit timer A/B.

Figure 12-18. Timer B Function Block Diagram

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13 WATCH TIMER

OVERVIEW

Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To

start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1".

And if you want to service watch timer overflow interrupt (IRQ4, vector E6H), then set the WTCON.6 to “1”.

The watch timer overflow interrupt pending condition (WTCON.0) must be cleared by software in the application’s

interrupt service routine by means of writing a "0" to the WTCON.0 interrupt pending bit.

After the watch timer starts and elapses a time, the watch timer interrupt pending bit (WTCON.0) is automatically

set to "1", and interrupt requests commence in 3.91 ms, 0.125, 0.25 and 0.5-second intervals by setting Watch

timer speed selection bits (WTCON.3–.2).

The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to BUZ output pin for Buzzer. By

setting WTCON.3 and WTCON.2 to "11b", the watch timer will function in high-speed mode, generating an

interrupt every 3.91 ms. High-speed mode is useful for timing events for program debugging sequences.

The watch timer supplies the clock frequency for the LCD controller (f_LCD). Therefore, if the watch timer is

disabled, the LCD controller does not operate.

Watch timer has the following functional components:

— Real Time and Watch-Time Measurement

— Using a Main Clock Source or Sub clock

— Clock Source Generation for LCD Controller (f_LCD

)

— I/O pin for Buzzer Output Frequency Generator (BUZ)

— Timing Tests in High-Speed Mode

— Watch timer overflow interrupt (IRQ4, vector E6H) generation

— Watch timer control register, WTCON (set 1, bank 0, EEH, read/write)

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WATCH TIMER CONTROL REGISTER (WTCON)

The watch timer control register, WTCON is used to select the watch timer interrupt time and Buzzer signal, to

enable or disable the watch timer function. It is located in set 1, bank 0 at address EEH, and is read/write

addressable using register addressing mode.

A reset clears WTCON to "00H". This disable the watch timer.

So, if you want to use the watch timer, you must write appropriate value to WTCON.

Watch Timer Control Register (WTCON)

EEH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Watch timer interrupt pending bit:

0 = Interrupt request is not pending

(Clear pending bit when write"0")

1 = Interrupt request is pending

Watch timer clock selection bit:

0 = Select main clock divided by 2⁷(fx/128)

1 = Select sub clock (fxt)

Watch timer INT Enable/Disable bit:

0 = Disable watch timer INT

1 = Enable watch timer INT

Watch timer Enable/Disable bit:

0 = Disable watch timer

(Clear frequency dividing circuits)

1 = Enable watch timer

Buzzer signal selection bits:

00 = 0.5 kHz

Watch timer speed selection bits:

00 = Set watch timer interrupt to 0.5 s

01 = Set watch timer interrupt to 0.25 s

10 = Set watch timer interrupt to 0.125 s

11 = Set watch timer interrupt to 3.91 ms

01 = 1 kHz

10 = 2 kHz

11 = 4 kHz

Figure 13-1. Watch Timer Control Register (WTCON)

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WATCH TIMER CIRCUIT DIAGRAM

WTCON.7

WTCON.6

BUZ

WT INT

Enable

WTCON.6

WTCON.5

WTCON.4

MUX

WTINT

(IRQ4)

8

fw/64 (0.5 kHz)

fw/32 (1 kHz)

fw/16 (2 kHz)

fw/8 (4 kHz)

WTCON.3

WTCON.2

Enable/Disable

Selector

Circuit

WTCON.1

WTCON.0

(Pending Bit)

0.5sec

0.25sec

0.125sec

3.91msec

Frequency

Dividing

Circuit

fw

Clock

Selector

32.768 kHz

f

LCD = 4096 Hz

fx = Main clock (where fx = 4.19 MHz)

fxt = Sub clock (32.768 kHz)

fxt

fx/128

fw = Watch timer frequency

Figure 13-2. Watch Timer Circuit Diagram

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14 LCD CONTROLLER/DRIVER

OVERVIEW

The S3F82NB microcontroller can directly drive an up-to-1280-dot (80 segments x 16 commons) LCD panel. Its

LCD block has the following components:

— LCD controller/driver

— Display RAM (F00H–FAFH) for storing display data in page 15

— 8 common/segment output pins (COM8/SEG0–COM15/SEG7)

— 80 segment output pins (SEG8–SEG87)

— 8 common output pins (COM0–COM7)

— Five LCD operating power supply pins (V_LC0–V_LC4

— V_LC0pin for controlling the driver and bias voltage

— LCD contrast control circuit by software (16 steps)

)

The LCD control register, LCON, is used to turn the LCD display on and off, select frame frequency, LCD duty

and bias. The LCD mode control register, LMOD, is used to control LCD bias voltage by 16 steps. Data written to

the LCD display RAM can be automatically transferred to the segment signal pins without any program control.

When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even in the main clock

stop or idle modes.

VLC0-VLC4

5

COM0-COM7

8

LCD

Controller/Driver

COM8-COM15

/SEG0-SEG7

8

SEG8-SEG87

80

Figure 14-1. LCD Function Diagram

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LCD CIRCUIT DIAGRAM

SEG87/P5.7

SEG72/P4.0

SEG64/P3.0

SEG56/P2.0

SEG48/P7.0

SEG40/P8.0

SEG32/P9.0

Port

Latch

SEG/Port

Driver

SEG24/P10.0

SEG23

SEG8

LCD

Display RAM

(F00H-FAFH)

COM15/SEG7

COM8/SEG0

COM7

COM/Port

Driver

f^LCD

COM0

Timing

Controller

LCON

LMOD

VLC0

VLC1

VLC2

VLC3

VLC4

LCD

Voltage

Control

Contrast

Controller

Figure 14-2. LCD Circuit Diagram

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LCD RAM ADDRESS AREA

RAM addresses of 00H - AFH page 15 are used as LCD data memory. These locations can be addressed by 1-

bit or 8-bit instructions. When the bit value of a display segment is "1", the LCD display is turned on; When the bit

value is "0", the display is turned off.

Display RAM data are sent out through the segment pins, SEG0–SEG87, using the direct memory access (DMA)

method that is synchronized with the f_LCDsignal. RAM addresses in this location that are not used for LCD

display can be allocated to general-purpose use.

COM

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

Bit

.0

.1

.2

.3

.4

.5

.6

.7

.0

.1

.2

.3

.4

.5

.6

.7

SEG0

F00H

SEG1

F02H

SEG2

F04H

SEG3

F06H

SEG4

F08H

SEG5

F0AH

SEG85 SEG86 SEG87

FAAH

FACH

FAEH

F01H

F03H

F05H

F07H

F09H

F0BH

FABH

FADH

FAFH

Figure 14-3. LCD Display Data RAM Organization

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291

LCD CONTROL REGISTER (LCON)

A LCON is located in set1, bank0 at address EFH, and is read/write addressable using register addressing mode.

It has the following control functions.

— LCD duty and bias selection

— LCD clock selection

— LCD display control

The LCON register is used to turn the LCD display on/off, to select duty and bias and select LCD clock. A reset

clears the LCON registers to "00H", configuring turns off the LCD display, select 1/8 duty and 1/4 bias and select

256Hz for LCD clock.

The LCD clock signal determines the frequency of COM signal scanning of each segment output. This is also

referred as the LCD frame frequency. Since the LCD clock is generated by watch timer clock (fw). The watch

timer should be enabled when the LCD display is turned on.

NOTE: The clock and duty for LCD controller/driver is automatically initialized by hardware, whenever LCON register data

value is re-write. So, the LCON register don’t re-write frequently.

LCD Control Register (LCON)

EFH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

LCD output control bit:

0 = Display off

LCD clock selection bits:

000 = fw/2⁷(256 Hz)

001 = fw/2⁶(512 Hz)

010 = fw/2⁵(1024 Hz)

011 = fw/2⁴(2048 Hz)

100 = fw/2³(4096 Hz)

Others = Not available

1 = Display on

Not used for the S3F82NB

LCD duty selection bit:

0 = 1/8 duty

1 = 1/16 duty

LCD bias selection bit:

0 = 1/4 bias

1 = 1/5 bias

Figure 14-4. LCD Control Register (LCON)

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LCD MODE CONTROL REGISTER (LMOD)

A LMOD is located in set 1, bank 0 at address F0H, and is read/write addressable using Register addressing

mode. It has the following control functions.

— LCD contrast control circuit by software (16 steps)

The LMOD register is used to control the LCD contrast up to 16 step contrast level. A reset clears the LMOD

registers to "00H", configuring select 1/16 step contrast level and disable LCD contrast control.

You can’t control LCD contrast by software when the VLCD voltage is supplied by external voltage source. Only

when you use internal VDD for VLCD voltage, you can control LCD contrast by software.

LCD Mode Control Register (LMOD)

F0H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used for the S3F82NB

LCD contrast level control bits:

0000 = 1/16 step (The dimmest level)

0001 = 2/16 step

LCD contrast enabel/disable selection bit:

0 = Disable LCD contrast control

1 = Enabel LCD contrast control

0010 = 3/16 step

1111 = 16/16 step (The brightest level)

(VLCD = VDD x (n+17)/32, where n = 0 - 15)

Figure 14-5. LCD Mode Control Register (LMOD)

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LCD VOLTAGE DIVIDING RESISTOR

1/5 bias

1/4 bias

VDD

LCON.0

Contrast

Controller

LCON.0

Contrast

Controller

"0"

"1"

"0"

"1"

16 steps of voltage

LMOD.3=0

V

LC0

VLC0

V

LC1

LC2

LC3

LC4

VLC1

VLC2

VLC3

VLC4

VLCD

VSS

Application With Contrast Control

VDD

LCON.0

Contrast

Controller

16 steps of voltage

"0"

"1"

LMOD.3=1

VLC0

V

LCD = VDD x (n+17)/32

n = 0, 1, 2, .........., 15

VLC1

VLC2

VLC3

VLC4

VLCD

VSS

Figure 14-6. LCD Voltage Dividing Resistor Connection

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COMMON (COM) SIGNALS

The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.

— In 1/16 duty mode, COM0-COM15 (SEG8–SEG87) pins are selected.

— In 1/8 duty mode, COM0-COM7 (SEG0–SEG87) pins are selected.

SEGMENT (SEG) SIGNALS

The 88 LCD segment signal pins are connected to corresponding display RAM locations at page 15. Bits of the

display RAM are synchronized with the common signal output pins.

When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin.

When the display bit is "0", a 'no-select' signal to the corresponding segment pin.

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COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

0

1

2

3

15 0

1

2

3

15

VLC0

VSS

FR

1 Frame

VLC0

VLC1

VLC2

VLC3

VLC4

VSS

COM0

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

VLC0

VLC1

VLC2

VLC3

VLC4

VSS

S S S S S

E E E E E

G G G G G

COM1

COM2

SEG8

8

9

1

0

1

2

VLC0

VLC1

VLC2

VLC3

VLC4

VSS

VLC0

VLC1

VLC2

VLC3

VLC4

VSS

Figure 14-7. LCD Signal Waveforms (1/16 Duty, 1/5 Bias)

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0

1

2

3

15

0

1

2

3

15

VLC0

VSS

FR

1 Frame

VLC0

VLC1

VLC2

VLC3

VLC4

VSS

SEG9

VLC0

VLC1

VLC2

VLC3

VLC4

0V

SEG8-COM0

-VLC4

-VLC3

-VLC2

-VLC1

-VLC0

VLC0

VLC1

VLC2

VLC3

VLC4

0V

SEG9-COM0

-VLC4

-VLC3

-VLC2

-VLC1

-VLC0

Figure 14-7. LCD Signal Waveforms (1/16 Duty, 1/5 Bias) (Continued)

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COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

0

1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

VLC0

VSS

FR

1 Frame

VLC0

S S S S S

E E E E E

G G G G G

0 1 2 3 4

VLC1

VLC2 (VLC3)

VLC4

COM0

VSS

VLC0

VLC1

COM1

COM2

SEG0

VLC2 (VLC3)

VLC4

VSS

VLC0

VLC1

VLC2 (VLC3)

VLC4

VSS

VLC0

VLC1

VLC2 (VLC3)

VLC4

VSS

VLC0

VLC1

VLC2 (VLC3)

VLC4

SEG0-COM0

0V

-VLC4

-VLC2 (-VLC3)

-VLC1

-VLC0

Figure 14-8. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)

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298

0

1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

VLC0

VSS

FR

1 Frame

VLC0

VLC1

SEG1

VLC2(VLC3)

VLC4

VSS

VLC0

VLC1

VLC2(VLC3)

VLC4

SEG1-COM0

0V

-VLC4

-VLC2(-VLC3)

-VLC1

-VLC0

Figure 14-8. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) (Continued)

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299

15 10-BIT ANALOG-TO-DIGITAL CONVERTER

OVERVIEW

The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at

one of the eight input channels to equivalent 10-bit digital values. The analog input level must lie between the

AV_REFand AV_SSvalues. The A/D converter has the following components:

— Analog comparator with successive approximation logic

— D/A converter logic (resistor string type)

— ADC control register (ADCON)

— Eight multiplexed analog data input pins (AD0–AD7)

— 10-bit A/D conversion data output register (ADDATAH/L)

— 8-bit digital input port (Alternately, I/O port)

— AV_REFand V_SSpins

FUNCTION DESCRIPTION

To initiate an analog-to-digital conversion procedure, at the first you must set ADCEN signal for ADC input enable

at port 0, the pin set with alternative function can be used for ADC analog input. And you write the channel

selection data in the A/D converter control register ADCON.4–.6 to select one of the eight analog input pins

(AD0–7) and set the conversion start or disable bit, ADCON.0. The read-write ADCON register is located in set 1,

bank 0 at address E2H. The pins which are not used for ADC can be used for normal I/O.

During a normal conversion, ADC logic initially sets the successive approximation register to 200H (the

approximate half-way point of an 10-bit register). This register is then updated automatically during each

conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time.

You can dynamically select different channels by manipulating the channel selection bit value (ADCON.6–.4) in

the ADCON register. To start the A/D conversion, you should set the start bit, ADCON.0. When a conversion is

completed, ADCON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the

ADDATAH/L register where it can be read. The A/D converter then enters an idle state. Remember to read the

contents of ADDATAH/L before another conversion starts. Otherwise, the previous result will be overwritten by

the next conversion result.

NOTE

Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the

analog level at the AD0–AD7 input pins during a conversion procedure be kept to an absolute minimum.

Any change in the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or

IDLE mode in conversion process, there will be a leakage current path in A/D block. You must use STOP

or IDLE mode after ADC operation is finished.

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CONVERSION TIMING

The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D

conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for

conversion clock with an 8 MHz fxx clock frequency, one clock cycle is 1 us. Each bit conversion requires 4

clocks, the conversion rate is calculated as follows:

4 clocks/bit

ꢀ

10 bits + set-up time = 50 clocks, 50 clock ꢀ 1us = 50 ꢎs at 1 MHz

A/D CONVERTER CONTROL REGISTER (ADCON)

The A/D converter control register, ADCON, is located at address E2H in set1, bank 0. It has three functions:

— Analog input pin selection (ADCON.6–.4)

— End-of-conversion status detection (ADCON.3)

— ADC clock selection (ADCON.2–.1)

— A/D operation start or disable (ADCON.0)

After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog input

pins (AD0–AD7) can be selected dynamically by manipulating the ADCON.4–6 bits. And the pins not used for

analog input can be used for normal I/O function.

A/D Converter Control Register (ADCON)

E2H, Set1, Bank 0, R/W (EOC bit is read-only)

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Always logic "0"

Start or disable bit:

0 = Disable operation

1 = Start operation

A/D input pin selection bits:

Clock Selection bit:

0 0 = fxx/16

0 1 = fxx/8

1 0 = fxx/4

1 1 = fxx/1

0 0 0 = AD0

0 0 1 = AD1

0 1 0 = AD2

0 1 1 = AD3

1 0 0 = AD4

1 0 1 = AD5

1 1 0 = AD6

1 1 1 = AD7

End-of-conversion bit:

0 = Conversion not complete

1 = Conversion complete

Figure 15-1. A/D Converter Control Register (ADCON)

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A/D Converter Data Register, High Byte (ADDATAH)

E0H, Set 1, Bank 0, Read Only

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

A/D Converter Data Register, Low Byte (ADDATAL)

E1H, Set1, Bank 0, Read Only

.1

.0

Figure 15-2. A/D Converter Data Register (ADDATAH/L)

INTERNAL REFERENCE VOLTAGE LEVELS

In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input

level must remain within the range AV_SSto AV_REF(usually, AV_{REF DD,}AV_{SS SS}).

V

ꢆ

ꢏ

Different reference voltage levels are generated internally along the resistor tree during the analog conversion

process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 AV_REF

.

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302

BLOCK DIAGRAM

ADCON.2-.1

ADCON.6-.4

(Select one input pin of the assigned pins)

To ADCON.3

(EOC Flag)

Clock

Selector

ADCON.0

(AD/C Enable)

M

Analog

Comparator

Successive

Approximation

Logic & Register

-

Input Pins

AD0-AD7

(P0.0-P0.7)

U

X

.

+

ADCON.0

(AD/C Enable)

Upper 8-bit is loaded to

A/D Conversion

Data Register

P0CONH/L

(Assign Pins to ADC Input)

Conversion

Result

(ADDATAH/L)

AVREF

10-bit D/A

Converter

AVSS(VSS)

Figure 15-3. A/D Converter Functional Block Diagram

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DD

V

Reference

Voltage

Input

REF

AV

+

-

C

103

10 ꢎF

REF

(AV

ꢆ VDD

)

DD

V

Analog

Input Pin

AD0-AD7

C

101

S3F82NB

AVSS(VSS

)

Figure 15-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy

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16 SERIAL I/O INTERFACE

OVERVIEW

Serial I/O module, SIO can interface with various types of external device that require serial data transfer. The

components of each SIO function block are:

— 8-bit control register (SIOCON)

— Clock selector logic

— 8-bit data buffer (SIODATA)

— 8-bit pre-scaler (SIOPS)

— 3-bit serial clock counter

— Serial data I/O pins (SI, SO)

— Serial clock input/output pins (SCK)

The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control

register settings. To ensure flexible data transmission rates, you can select an internal or external clock source.

PROGRAMMING PROCEDURE

To program the SIO modules, follow these basic steps:

1. Configure the I/O pins at port (SO, SCK, SI) by loading the appropriate value to the P6CONH register if

necessary.

2. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this

operation, SIOCON.2 must be set to "1" to enable the data shifter.

3. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON.1) to "1".

4. When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift

operation starts.

5. When the shift operation (transmit/receive) is completed, the SIO pending bit (SIOCON.0) is set to "1" and an

SIO interrupt request is generated.

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SIO CONTROL REGISTER (SIOCON)

The control register for serial I/O interface module, SIOCON, is located at F3H in set 1, bank 0. It has the control

settings for SIO module.

— Clock source selection (internal or external) for shift clock

— Interrupt enable

— Edge selection for shift operation

— Clear 3-bit counter and start shift operation

— Shift operation (transmit) enable

— Mode selection (transmit/receive or receive-only)

— Data direction selection (MSB first or LSB first)

A reset clears the SIOCON value to "00H". This configures the corresponding module with an internal clock

source at the SCK, selects receive-only operating mode, and clears the 3-bit counter. The data shift operation

and the interrupt are disabled. The selected data direction is MSB-first.

Serial I/O Module Control Register (SIOCON)

F3H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

SIO interrupt pending bit:

0 = No interrupt pending

0 = Clear pending condition

(when write)

SIO shift clock selection bit:

0 = Internal clock (P.S Clock)

1 = External clock (SCK)

1 = Interrupt is pending

Data direction control bit:

0 = MSB-first mode

1 = LSB-first mode

SIO interrupt enable bit:

0 = Disable SIO interrupt

1 = Enable SIO interrupt

SIO mode selection bit:

0 = Receive only mode

1 = Transmit/receive mode

SIO shift operation enable bit:

0 = Disable shifter and clock counter

1 = Enable shifter and clock counter

Shift clock edge selection bit:

0 = TX at falling edges, Rx at rising edges

1 = TX at rising edges, Rx at falling edges

SIO counter clear and shift start bit:

0 = No action

1 = Clear 3-bit counter and start shifting

Figure 16-1. Serial I/O Module Control Registers (SIOCON)

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SIO PRE-SCALER REGISTER (SIOPS)

The control register for serial I/O interface module, SIOPS, is located at F5H in set 1, bank 0.

The value stored in the SIO pre-scaler register, SIOPS, lets you determine the SIO clock rate (baud rate) as

follows:

Baud rate = Input clock (fxx/4)/(Pre-scaler value + 1), or SCK input clock, where the input clock is fxx/4

SIO Pre-scaler Register (SIOPS)

F5H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Baud rate = (fxx/4)/(SIOPS +1)

Figure 16-2. SIO Pre-scaler Register (SIOPS)

BLOCK DIAGRAM

SIO INT

3-Bit Counter

SIOCON.0

Pending

IRQ3

Clear

CLK

SIOCON.1

(Interrupt Enable)

SIOCON.3

SIOCON.7

SIOCON.4

(Edge Select)

SIOCON.2

(Shift Enable)

SIOCON.5

(Mode Select)

M

U

X

SCK

SIOPS (F5H, bank 0)

8-bit P.S. 1/2

CLK

8-Bit SIO Shift Buffer

SO

(SIODATA, F4H, bank 0)

fxx/2

SIOCON.6

(LSB/MSB First

Mode Select)

8

SI

Data Bus

Figure 16-3. SIO Functional Block Diagram

P R E L I M I N A R Y

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307

SERIAL I/O TIMING DIAGRAM

SCK

SI

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

SO

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

Transmit

Complete

IRQ4

Set SIOCON.3

Figure 16-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)

SCK

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

SI

SO

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

Transmit

Complete

IRQ4

Set SIOCON.3

Figure 16-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)

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17 COMPARATOR

OVERVIEW

P6.0, P6.1 and P6.2 can be used as an analog input port for a comparator. The reference voltage for the

4-channel comparator can be supplied either internally or externally at P6.2. When an internal reference voltage

is used, four channels (P6.0-P6.2) are used for analog inputs and the internal reference voltage is varied in 16

levels. If an external reference voltage is input at P6.2, the other P6.0 and P6.1 pins are used for analog input.

When a conversion is completed, the result is saved in the comparison result register CMPREG. The initial values

of the CMPREG are undefined and the comparator operation is disabled by a RESET. The comparator module

has the following components:

— Comparator

— Internal reference voltage generator (4-bit resolution)

— External reference voltage source at P6.2

— Comparator mode register (CMPCON)

— Comparator result register (CMPREG)

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COMPARATOR CONTROL REGISTER (CMPCON)

The comparator mode register CMPCON is an 8-bit register that is used to select operation mode of the

comparator. It is located in set 1, bank 0 at address F1H, and is read/write addressable using register addressing

mode.

A reset clears CMPCON to "00H". This disable the comparator, selects conversion time of 8 x 2⁵/fx, the P6.0-

P6.2 (CIN0-CIN2) can be used analog input. CMPCON.6 bit controls conversion timer while CMPCON.7 bit

enables or disables comparator operation to reduce power consumption. Based on the CMPCON.5 bit setting, an

internal or an external reference voltage is input for the comparator, as follows:

When CMPCON.5 is set to logic “0”:

— A reference voltage is selected by the CMPCON.0 to CMPCON.3 bit settings.

— P6.0-P6.2 (CIN0-CIN2) are used as analog input pins.

— The internal digital to analog converter generates 16 reference voltages.

— The comparator can detect 150-mV differences between the reference voltage and the analog input voltages.

— Comparator results are written into bit0-bit2 of the comparison result register (CMPREG)

When CMPCON.5 is set to logic “1”:

— A external reference voltage is supplied from P6.2/CIN2.

— P6.0 and P6.1 (CIN0-CIN1) are used as the analog input pins.

— The internal digital to analog converter generates 16 reference voltages.

— The comparator can detect 150-mV differences between the reference voltage and the analog input voltages.

— Bit0 and bit1 in the CMPREG register contain the results.

Comparator Control Register

F1H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Comparator enable bit:

0 = Disable comparator

1 = Enable comparator

Reference Voltage Selection bits:

Selected VREF = VDD X (N+0.5)/16, N = 0 to 15

Not used, But you must keep "0"

External/Internal reference selection bit:

0 = Internal reference, CIN0-CIN2; analog input

1 = CIN2; External reference, CIN0-CIN1; analog input

Conversion time selection bit:

0 = 8 X 2⁵/fx

1 = 8 X 2⁴/fx

Figure 17-1. Comparator Control Register (CMPCON)

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BLOCK DIAGRAM

Comparison

P6.0/CIN0

+

-

Result

MUX

3

P6.1/CIN1

P6.2/CIN2

Register

(CMPREG)

VREF

(External)

MUX

VDD

CMPCON.7

CMPCON.6

CMPCON.5

0

CMPCON.3

CMPCON.2

CMPCON.1

CMPCON.0

VREF

(Internal)

1/2R

R

MUX

1/2R

NOTE: The comparison result of CIN0, CIN1 and CIN2 are respectively

stored in CMPREG.0, CMPREG.1 and CMPREG.2.

Figure 17-2. Comparator Circuit Diagram

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COMPARATOR OPERATION

The comparator compares analog voltage input at CIN0-CIN2 with an external or internal reference voltage

(VREF) that is selected by the CMPCON register. The result is written to the comparison result register CMPREG

at address F2H, set 1, bank 0.

The comparison result at internal reference is calculated as follows:

If “1” Analog input voltage ˻ VREF + 150mV

If “0” Analog input voltage ˺ VREF - 150mV

To obtain a comparison result, the data must be read out from the CMPREG register after VREF is updated by

changing the CMPCON value after a conversion time has elapsed.

Comparsion Time

(CMPCLK x8)

Comparator Clock

(CMPCLK, fx/16, fx/32)

Comparsion

End

Comparsion

Start

Analog Input

Voltage (CIN0-CIN2)

Reference

Voltage (VREF)

Comparison

Result (CMPREG)

1

0

Invalid

Valid

Invalid

Figure 17-3. Conversion Characteristics

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ꢁ

PROGRAMMING TIP — Programming the Comparator

The following code converts the analog voltage input at the CIN0-CIN2 pins into 3-bit digital code:

LD

R0,#0FH

CMPCON,#0CXH

; Analog input selection (CIN0-CIN2)

; X = 0 – F, comparator enable

; internal reference, conversion time (8 x 2⁵/fx)

WAIT0

WAIT1

LD

R2,#02H

R1,R0

R3,#10H

WAIT2

NOP

DJNZ

R3,WAIT2

LD

R0,CMPREG

; Read the result

NOP

DJNZ

CP

R2,WAIT1

R0,R1

JR

NE,WAIT0

SB1

LD

P2,R0

; Output the result from port 2

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18 EMBEDDED FLASH MEMORY INTERFACE

OVERVIEW

The S3F82NB has an on-chip flash memory internally instead of masked ROM. The flash memory is accessed by

'LDC' instruction and the type of sector erase and a byte programmable flash, a user can program the data in a

flash memory area any time you want. The S3F82NB's embedded 64K-bytes memory has two operating features

as below:

— User Program Mode

— Tool Program Mode: Refer to the chapter 21. S3F82NB FLASH MCU.

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USER PROGRAM MODE

This mode supports sector erase, byte programming, byte read and one protection mode (Hard lock protection).

The read protection mode is available only in Tool Program mode. So in order to make a chip into read protection,

you need to select a read protection option when you program an initial your code to a chip by using Tool

Program mode by using a programming tool.

The S3F82NB has the pumping circuit internally; therefore, 12.5V into V_PP(Test) pin is not needed. To program a

flash memory in this mode several control registers will be used. There are four kind functions – programming,

reading, sector erase and hard lock protection

NOTES

1. The user program mode cannot be used when the CPU operates with the subsystem clock.

2. Be sure to execute the DI instruction before starting user program mode. The user program mode

checks the interrupt request register (IRQ). If an interrupt request is generated, user program mode

is stopped.

3. User program mode is also stopped by an interrupt request that is masked even in the DI status.

To prevent this, Be disable the interrupt by using the each peripheral interrupt enable bit.

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315

FLASH MEMORY CONTROL REGISTERS (User Program Mode)

Flash Memory Control Register

FMCON register is available only in user program mode to select the Flash Memory operation mode; sector

erase, byte programming, and to make the flash memory into a hard lock protection.

Flash Memory Control Register (FMCON)

F9H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Flash operation start bit:

0 = Operation stop

Flash memory mode selection bits:

0101 = Programming mode

1010 = Sector erase mode

0110 = Hard lock mode

1 = Operation start

(This bit will be cleared automatically

just after the corresponding operation

completed).

others = Not available

Sector erase status bit:

0 = Success sector erase

1 = Fail sector erase

Not used for S3F82NB

Figure 18-1. Flash Memory Control Register (FMCON)

The bit0 of FMCON register (FMCON.0) is a start bit for Erase and Hard Lock operation mode. Therefore,

operation of Erase and Hard Lock mode is activated when you set FMCON.0 to "1". Also you should wait a time

of Erase (Sector erase) or Hard lock to complete it's operation before a byte programming or a byte read of same

sector area by using "LDC" instruction. When you read or program a byte data from or into flash memory, this bit

is not needed to manipulate.

The sector erase status bit is read only. Even if IMR bits are “0”, the interrupt is serviced during the operation of

"Sector erase", when the each peripheral interrupt enable bit is set “1” and interrupt pending bit is set “1”. If an

interrupt is requested during the operation of "Sector erase", the operation of "Sector erase" is discontinued, and

the interrupt is served by CPU. Therefore, the sector erase status bit should be checked after executing "Sector

erase". The "sector erase" operation is success if the bit is logic "0", and is failure if the bit is logic "1".

NOTE

When the ID code, "A5H", is written to the FMUSR register. A mode of sector erase, user program, and

hard lock may be executed unfortunately. So, it should be careful of the above situation.

PS031601-0813

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S3F82NB

Product Specification

316

Flash Memory User Programming Enable Register

The FMUSR register is used for a safety operation of the flash memory. This register will protect undesired erase

or program operation from malfunctioning of CPU caused by an electrical noise.

After reset, the user-programming mode is disabled, because the value of FMUSR is "00000000B" by reset

operation. If necessary to operate the flash memory, you can use the user programming mode by setting the

value of FMUSR to "10100101B". The other value of "10100101b", User Program mode is disabled.

Flash Memory User Programming Enable Register (FMUSR)

F8H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Flash memory user programming enable bits:

10100101: Enable user programming mode

Other values: Disable user programming mode

Figure 18-2. Flash Memory User Programming Enable Register (FMUSR)

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S3F82NB

Product Specification

317

Flash Memory Sector Address Registers

There are two sector address registers for addressing a sector to be erased. The FMSECL (Flash Memory Sector

Address Register Low Byte) indicates the low byte of sector address and FMSECH (Flash Memory Sector

Address Register High Byte) indicates the high byte of sector address.

The FMSECH is needed for S3F82NB because it has 512 sectors, respectively. One sector consists of 128-

bytes. Each sector's address starts XX00H or XX80H that is a base address of sector is XX00H or XX80H. So

FMSECL register 6-0 don't mean whether the value is '1' or '0'. We recommend that the simplest way is to load

sector base address into FMSECH and FMSECL register.

When programming the flash memory, you should write data after loading sector base address located in the

target address to write data into FMSECH and FMSECL register. If the next operation is also to write data, you

should check whether next address is located in the same sector or not. In case of other sectors, you must load

sector address to FMSECH and FMSECL register according to the sector.

Flash Memory Sector Address Register (FMSECH)

F6H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Flash Memory Setor Address (High Byte)

NOTE:

The high-byte flash memory sector address pointer

value is the higher eight bits of the 16-bit pointer address.

Figure 18-3. Flash Memory Sector Address Register High Byte (FMSECH)

Flash Memory Sector Address Register (FMSECL)

F7H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Don't care

Flash Memory Sector Address (Low Byte)

NOTE:

The low-byte flash memory sector address pointer

value is the lower eight bits of the 16-bit pointer address.

Figure 18-4. Flash Memory Sector Address Register Low Byte (FMSECL)

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S3F82NB

Product Specification

318

ISP^TM(ON-BOARD PROGRAMMING) SECTOR

ISP^TMsectors located in program memory area can store On Board Program software (Boot program code for

upgrading application code by interfacing with I/O port pin). The ISP^TMsectors can not be erased or programmed

by LDC instruction for the safety of On Board Program software.

The ISP sectors are available only when the ISP enable/disable bit is set 0, that is, enable ISP at the Smart

Option. If you don't like to use ISP sector, this area can be used as a normal program memory (can be erased or

programmed by LDC instruction) by setting ISP disable bit ("1") at the Smart Option. Even if ISP sector is

selected, ISP sector can be erased or programmed in the Tool Program mode, by Serial programming tools.

The size of ISP sector can be varied by settings of Smart Option. You can choose appropriate ISP sector size

according to the size of On Board Program software.

(Decimal)

65,535

(HEX)

FFFFH

64K-bytes

Internal Program

Memory Area

8FFH

FFH

Available

ISP Sector Area

255

0

Interrupt Vector Area

Smart Option Area

3FH

3CH

00H

Byte

Figure 18-5. Program Memory Address Space

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P R E L I M I N A R Y

S3F82NB

Product Specification

319

Table 18-1. ISP Sector Size

Smart Option(003EH) ISP Size Selection Bit

Area of ISP Sector

ISP Sector Size

Bit 2

Bit 1

Bit 0

1

0

x

0

1

x

0

1

0

1

–

0

100H – 1FFH (256 Byte)

100H – 2FFH (512 Byte)

100H – 4FFH (1024 Byte)

100H – 8FFH (2048 Byte)

256 Bytes

512 Bytes

1024 Bytes

2048 Bytes

NOTE: The area of the ISP sector selected by Smart Option bit (003EH.2 – 003EH.0) can not be erased and programmed

by LDC instruction in User Program mode.

ISP RESET VECTOR AND ISP SECTOR SIZE

If you use ISP sectors by setting the ISP Enable/Disable bit to "0" and the Reset Vector Selection bit to “0” at the

Smart Option, you can choose the reset vector address of CPU as shown in Table 18-2 by setting the ISP Reset

Vector Address Selection bits.

Table 18-2. Reset Vector Address

Smart Option (003EH)

ISP Reset Vector Address Selection Bit

Reset Vector

Address After POR

Usable Area for

ISP Sector

ISP Sector Size

Bit 7

Bit 6

Bit 5

1

0

x

0

1

x

0

1

0

1

0100H

0200H

0300H

0500H

0900H

–

100H – 1FFH

100H – 2FFH

100H – 4FFH

100H – 8FFH

256 Bytes

512 Bytes

1024 Bytes

2048 Bytes

NOTE: The selection of the ISP reset vector address by Smart Option (003EH.7 – 003EH.5) is not dependent of the

selection of ISP sector size by Smart Option (003EH.2 – 003EH.0).

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P R E L I M I N A R Y

S3F82NB

Product Specification

320

SECTOR ERASE

User can erase a flash memory partially by using sector erase function only in User Program Mode. The only unit

of flash memory to be erased and programmed in User Program Mode is called sector.

The program memory of S3F82NB is divided into 512 sectors for unit of erase and programming, respectively.

Every sector has all 128-byte sizes of program memory areas. So each sector should be erased first to program a

new data (byte) into a sector.

Minimum 10ms delay time for erase is required after setting sector address and triggering erase start bit

(FMCON.0). Sector Erase is not supported in Tool Program Modes (MDS mode tool or Programming tool).

FFFFH

Sector 511

(128 byte)

FF7FH

Sector 510

(128 byte)

FEFFH

3FFFH

Sector 127

(128 byte)

3F7FH

05FFH

Sector 11

(128 byte)

057FH

Sector 10

(128 byte)

0500H

04FFH

Sector 0-9

(128 byte x 10)

0000H

S3F82NB

Figure 18-6. Sector Configurations in User Program Mode

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S3F82NB

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321

The Sector Erase Procedure in User Program Mode

1.

If the procedure of Sector Erase needs to be stopped by any interrupt, set the appropriately bit of Interrupt

Mask Enable Register (IMR) and the appropriately peripheral interrupt enable bit. Otherwise clear all bits of

Interrupt Mask Enable Register (IMR) and all peripheral interrupt enable bits.

2.

3.

4.

5.

6.

7.

Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”.

Set Flash Memory Sector Address Register (FMSECH/ FMSECL).

Check user’s ID code (written by user)

Set Flash Memory Control Register (FMCON) to “10100001B”.

Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”.

Check the “Sector erase status bit” whether “Sector erase” is success or not.

ꢁ

ꢀ

PROGRAMMING TIP — Sector Erase

ꢈ

SB0

reErase:

LD

FMUSR,Temp0

; User Program mode enable

; Temp0 = #0A5H

; Temp0 variable is must be setting another routine

LD

CP

FMSECH,#10H

FMSECL,#00H

; Set sector address (1000H–107FH)

UserID_Code,#User_value ; Check user’s ID code (written by user)

; User_value is any value by user

JR

LD

NE,Not_ID_Code

FMCON,Temp1

; If not equal, jump to Not_ID_Code

; Start sector erase

; Temp1 = #0A1H

; Temp1 variable is must be setting another routine

; Dummy Instruction, This instruction must be needed

; User Program mode disable

; Check “Sector erase status bit”

; Jump to reErase if fail

NOP

LD

FMUSR,#0

FMCON,#00001000B

NZ,reErase

TM

JR

ꢈ

Not_ID_Code:

SB0

LD

FMUSR,#0

FMCON,#0

; User Program mode disable

; Sector erase mode disable

ꢈ

NOTE: In case of Flash User Mode, the Tmep0~Temp1’s data values are must be setting another routine.

Temp0~Temp(n) variables are should be defined by user.

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P R E L I M I N A R Y

S3F82NB

Product Specification

322

PROGRAMMING

A flash memory is programmed in one byte unit after sector erase. And for programming safety's sake, must set

FMSECH and FMSECL to flash memory sector value.

The write operation of programming starts by 'LDC' instruction.

You can write until 128 byte, because this flash sector's limit is 128 byte.

So, if you written 128 byte, must reset FMSECH and FMSECL.

The Program Procedure in User Program Mode

1. Must erase sector before programming.

2. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”.

3. Set Flash Memory Sector Register (FMSECH, FMSECL) to sector value of write address.

4. Load a flash memory upper address into upper register of pair working register.

5. Load a flash memory lower address into lower register of pair working register.

6. Load a transmission data into a working register.

7. Check user’s ID code (written by user)

8. Set Flash Memory Control Register (FMCON) to “01010001B”.

9. Load transmission data to flash memory location area on ‘LDC’ instruction by indirectly addressing mode

10. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”.

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S3F82NB

Product Specification

323

ꢁ

ꢀ

PROGRAMMING TIP — Programming

ꢈ

SB0

LD

FMUSR,Temp0

; User Program mode enable

; Temp0 = #0A5H

; Temp0 variable is must be setting another routine

LD

CP

FMSECH,#17H

FMSECL,#80H

R2,#17H

; Set sector address (1780H-17FFH)

; Set a ROM address in the same sector 1780H–17FFH

R3,#84H

R4,#78H

; Temporary data

UserID_Code,#User_value ; Check user’s ID code (written by user)

; User_value is any value by user

JR

LD

NE,Not_ID_Code

FMCON,Temp1

; If not equal, jump to Not_ID_Code

; Start program

; Temp1 = #51H

; Temp1 variable is must be setting another routine

; Write the data to a address of same sector(1784H)

; Dummy Instruction, This instruction must be needed

; User Program mode disable

LDC

NOP

LD

@RR2,R4

FMUSR,#0

ꢈ

Not_ID_Code:

SB0

LD

FMUSR,#0

FMCON,#0

; User Program mode disable

; Programming mode disable

ꢈ

NOTE: In case of Flash User Mode, the Tmep0~Temp1’s data values are must be setting another routine.

Temp0~Temp(n) variables are should be defined by user.

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S3F82NB

Product Specification

324

READING

The read operation of programming starts by ‘LDC’ instruction.

The Reading Procedure in User Program Mode

1.

2.

3.

Load a flash memory upper address into upper register of pair working register.

Load a flash memory lower address into lower register of pair working register.

Load receive data from flash memory location area on ‘LDC’ instruction by indirectly addressing mode

ꢁ

ꢀ

PROGRAMMING TIP — Reading

ꢈ

LD

R2,#3H

R3,#0

; Load flash memory upper address

; to upper of pair working register

; Load flash memory lower address

; to lower pair working register

; Read data from flash memory location

; (Between 300H and 3FFH)

LD

LOOP:

LDC

R0,@RR2

INC

CP

JP

R3

R3,#0H

NZ,LOOP

ꢈ

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P R E L I M I N A R Y

S3F82NB

Product Specification

325

HARD LOCK PROTECTION

User can set Hard Lock Protection by write ‘0110’ in FMCON.7-4. If this function is enabled, the user cannot write

or erase the data in a flash memory area. This protection can be released by the chip erase execution (in the tool

program mode).

In terms of user program mode, the procedure of setting Hard Lock Protection is following that. Whereas in tool

mode the manufacturer of serial tool writer could support Hardware Protection. Please refer to the manual of

serial program writer tool provided by the manufacturer.

The Hard Lock Protection Procedure in User Program Mode

1. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”.

2. Check user’s ID code (written by user)

3. Set Flash Memory Control Register (FMCON) to “01100001B”.

4. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”.

ꢁ

ꢀ

PROGRAMMING TIP — Hard Lock Protection

ꢈ

SB0

LD

FMUSR,Temp0

; User Program mode enable

; Temp0 = #0A5H

; Temp0 variable is must be setting another routine

CP

UserID_Code,#User_value ; Check user’s ID code (written by user)

; User_value is any value by user

NE,Not_ID_Code

FMCON,Temp1

JR

LD

; If not equal, jump to Not_ID_Code

; Hard Lock mode set & start

; Temp1 = #61H

; Temp1 variable is must be setting another routine

; Dummy Instruction, This instruction must be needed

; User Program mode disable

NOP

LD

FMUSR,#0

ꢈ

Not_ID_Code:

SB0

LD

FMUSR,#0

FMCON,#0

; User Program mode disable

; Hard Lock Protection mode disable

ꢈ

NOTE: In case of Flash User Mode, the Tmep0~Temp1’s data values are must be setting another routine.

PS031601-0813 P R E L I M I N A R Y

Temp0~Temp(n) variables are should be defined by user.

S3F82NB

Product Specification

326

19 ELECTRICAL DATA

OVERVIEW

In this chapter, S3F82NB electrical characteristics are presented in tables and graphs. The information is

arranged in the following order:

— Absolute maximum ratings

— Input/output capacitance

— D.C. electrical characteristics

— A.C. electrical characteristics

— Oscillation characteristics

— Oscillation stabilization time

— Data retention supply voltage in stop mode

— LVR timing characteristics

— A/D converter electrical characteristics

— Serial I/O timing characteristics

— Comparator electrical characteristics

— LCD contrast controller electrical characteristics

— Internal Flash ROM electrical characteristics

— Operating voltage range

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S3F82NB

Product Specification

327

Table 19-1. Absolute Maximum Ratings

ꢃ

(T_A= 25 C)

Parameter

Symbol

Conditions

Rating

Unit

V_DD

Supply voltage

Input voltage

–

– 0.3 to + 6.5

V

V_I

– 0.3 to V_DD+ 0.3

Ports 0-10

V_O

I_OH

Output voltage

Output current high

–

One I/O pin active

All I/O pins active

One I/O pin active

Total pin current for ports

–

– 15

mA

– 60

I_OL

Output current low

+ 30 (Peak value)

+ 100 (Peak value)

– 40 to + 85

ꢃ

C

T_A

Operating temperature

Storage temperature

T_STG

–

– 65 to + 150

Table 19-2. D.C. Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

ꢃ

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_DD

f

Operating voltage

1.8

–

5.5

V

x = 0.4–4.2 MHz, xt = 32.768 kHz

2.2

–

5.5

V_DD

x = 0.4–12.0 MHz

V_IH1

V_IH2

All input pins except V_{IH2, 3}

0.7V_DD

0.8V_DD

Input high voltage

Input low voltage

P0.0-P0.1, P1, P5.4-P5.7, P6,

nRESET

V_IH3

V_IL1

V_IL2

X_IN

X

XT XT

OUT

V_DD–0.1

–

V_DD

,

IN

OUT

All input pins except V_{IL2, 3}

0.3V_DD

0.2V_DD

–

P0.0-P0.1, P1, P5.4-P5.7, P6,

nRESET

V_IL3

X_IN

X XT XT

, ,

OUT IN OUT

0.1

,

PS031601-0813

P R E L I M I N A R Y

S3F82NB

Product Specification

328

Table 19-2. D.C. Electrical Characteristics (Continued)

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

ꢃ

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_OH

V_DD= 4.5V to 5.5V

V_DD–1.0

Output high voltage

–

V

I_OH= –1mA

All output ports

V_OL

V_DD= 4.5V to 5.5V

Output low voltage

–

2.0

I_OL= 15mA

All output ports

V_DD= 1.8V to 5.5V

0.4

3

I_OL= 1.6mA

I_LIH1

I_LIH2

I_LIL1

V_IN= V_DD

All input pins except I

Input high leakage

current

–

ꢎA

LIH2

V_IN= V_DD

X_IN, X_OUT, XT_IN, XT_OUT

20

–3

V_IN= 0 V

Input low leakage

current

All input pins except for

nRESET, I_LIL2

I_LIL2

V_IN= 0 V

–20

X_IN, X_OUT, XT_IN, XT_OUT

I_LOH

I_LOL

R_LCD

R_OSC1

R_OSC2

R_L1

V_OUT= V_DD

All output pins

V_OUT= 0 V

All output pins

ꢃ

Output high

–

3

–3

leakage current

Output low leakage

current

LCD voltage

dividing resistor

40

420

60

850

80

kꢐ

T = 25 C

A

ꢃ

Oscillator feed

back resistors

1700

V_DD= 5 V, T_A= 25 C

X_IN= V_DD, X_OUT= 0 V

ꢃ

2200

25

4500

50

9000

100

150

400

700

V_DD= 5 V, T_A= 25 C

XT_IN= V_DD, XT_OUT= 0 V

V_IN= 0 V; V_DD= 5 V

Pull-up resistor

ꢃ

T_A= 25 C, Ports 0–10

V_IN= 0 V; V_DD= 3 V

50

100

250

500

ꢃ

T_A= 25 C, Ports 0–10

R_L2

V_IN= 0 V; V_DD= 5 V

150

300

ꢃ

T_A= 25 C, nRESET

V_IN= 0 V; V_DD= 3 V

ꢃ

T_A= 25 C, nRESET

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S3F82NB

Product Specification

329

Table 19-2. D.C. Electrical Characteristics (Continued)

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

ꢃ

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_LC1

V_DD= 2.4V to 5.5V, 1/5 Bias

LCD clock = 0Hz, V_LC0= V_DD

0.8V_DD–0.2

0.8V_DD

0.6V_DD

0.4V_DD

0.2V_DD

0.8V_DD+0.2

Middle output

voltage ^(note)

V

V_LC2

V_LC3

V_LC4

V_DC

0.6V_DD–0.2

0.4V_DD–0.2

0.2V_DD–0.2

0.6V_DD+0.2

0.4V_DD+0.2

0.2V_DD+0.2

|V_LCD– COMi|

Voltage drop

(i = 0 – 15)

120

–15 ꢎA per common pin

–15 ꢎA per segment pin

–

mV

|V_LCD– SEGx|

V_DS

120

–

Voltage drop

(x = 0 – 87)

NOTE: It is middle output voltage when the V

and V

pin are connected.

DD

LC0

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S3F82NB

Product Specification

330

Table 19-2. D.C. Electrical Characteristics (Concluded)

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

ꢃ

Parameter

Supply current ⁽¹⁾

Symbol

Conditions

Run mode:

Min

Typ

Max

Unit

(2)

2.2

4.0

12.0 MHz

4.2 MHz

–

mA

I_DD1

V

_DD= 5.0V

Crystal oscillator

C1 = C2 = 22pF

1.2

2.0

V_DD= 3.0V

Idle mode:

0.8

1.3

1.5

2.3

4.2 MHz

(2)

12.0 MHz

–

I_DD2

V

_DD= 5.0V

Crystal oscillator

C1 = C2 = 22pF

0.8

1.5

4.2 MHz

V_DD= 3.0V

0.4

0.8

4.2 MHz

(3)

65.0

100.0

Sub Operating mode:

_DD= 3.0V

32kHz crystal oscillator

–

ꢎA

I_DD3

V

(3)

6.0

0.3

15.0

6.0

Sub Idle mode:

I_DD4

V_DD= 3.0V

32kHz crystal oscillator

(4)

Stop mode: V_DD= 5.0V

–

I_DD5

NOTES:

1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, the

LVR block, and external output current loads.

2.

3.

4.

I

and I

include a power consumption of sub clock oscillation.

DD1

DD2

I

and I are the current when the main clock oscillation stops and the sub clock is used.

DD4

DD3

I

is the current when the main and sub clock oscillation stops.

DD5

5. Every value in this table is measured when bits 4-3 of the system clock control register (CLKCON.4–.3) is

set to 11B.

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S3F82NB

Product Specification

331

Table 19-3. A.C. Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

ꢃ

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

t_INTH, t_INTL

All interrupt, V_DD= 5 V

Interrupt input high, low

width

(P1.0-P1.7, P5.4-P5.7)

500

–

ns

t_RSL

Input, V_DD= 5 V

nRESET input low width

10

–

ꢎs

NOTE: If width of interrupt or reset pulse is greater than min. value, pulse is always recognized as valid pulse.

t

INTL

tINTH

External

Interrupt

0.8 VDD

0.2 VDD

Figure 19-1. Input Timing for External Interrupts

t

RSL

nRESET

0.2 VDD

Figure 19-2. Input Timing for nRESET

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S3F82NB

Product Specification

332

Table 19-4. Input/Output Capacitance

ꢃ

(T_A= – 40 C to + 85 C, V_DD= 0 V )

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

C_IN

Input

capacitance

f = 1 MHz; unmeasured pins

are returned to V_SS

–

10

pF

C_OUT

C_IO

Output

capacitance

I/O capacitance

Table 19-5. Data Retention Supply Voltage in Stop Mode

ꢃ

(T_A= – 40 C to + 85 C)

Parameter

Symbol

V_DDDR

Conditions

Min

Typ

Max

Unit

Data retention

supply voltage

1.8

–

5.5

V

ꢃ

I_DDDR

Data retention

supply current

–

1

ꢎA

Stop mode, T_A= 25 C

_DDDR= 1.8V

Disable LVR block

V

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S3F82NB

Product Specification

333

nRESET

Occurs

Oscillation

Stabilization

Time

Stop Mode

Normal

Operating Mode

Data Retention Mode

VDD

VDDDR

Execution of

STOP Instrction

nRESET

0.8 VDD

tWAIT

0.2 VDD

NOTE:

tWAIT is the same as 4096 x 16 x 1/fxx.

Figure 19-3. Stop Mode Release Timing Initiated by nRESET

Oscillation

Stabillization TIme

IDLE Mode

Stop Mode

VDD

Data Retention Mode

VDDDR

Normal

Operation Mode

Execution of

STOP Instruction

Interrupt

0.2VDD

tWAIT

NOTE:

tWAIT is the same as 16 x 1/fBT. (fBT is basic timer clock selected)

Figure 19-4. Stop Mode Release Timing Initiated by Interrupts

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Table 19-6. A/D Converter Electrical Characteristics

(T = – 40 C to + 85 ꢃC, V_DD= 2.7 V to 5.5 V)

ꢃ

A

Parameter

Resolution

Symbol

Conditions

Min

–

Typ

10

–

Max

–

Unit

–

bit

Total accuracy

–

LSB

ꢑ3

ꢑ2

ꢑ1

V_DD= 5.120 V

_SS= 0 V

CPU clock = 12.0 MHz

Integral linearity error

ILE

DLE

–

V

Differential linearity

error

–

Offset error of top

EOT

EOB

T_CON

ꢑ1

–

ꢑ3

–

Offset error of bottom

Conversion time ⁽¹⁾

Analog input voltage

–

25

V_SS

2

ꢎS

V

V_IAN

R_AN

AV_REF

–

Analog input

impedance

1000

Mꢐ

AV_REF

V_DD

Analog reference

voltage

–

1.8

–

V

I_ADIN

I_ADC

V_DD= 5.0 V

Analog input current

–

10

1.5

500

ꢎA

mA

nA

Analog block current ⁽²⁾

0.5

100

V_DD= 5.0 V

When power down mode

NOTES:

1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends.

2. is an operating current during A/D converter.

I

ADC

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Table 19-7. Synchronous SIO Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

ꢃ

Parameter

SCK Cycle time

Symbol

t_KCY

Conditions

Min

Typ

Max

Unit

External SCK source

1,000

–

ns

Internal SCK source

External SCK source

1,000

500

t_KH, t_KL

SCK high, low width

t

_KCY/2-50

Internal SCK source

External SCK source

t_SIK

SI setup time to SCK high

SI hold time to SCK high

Output delay for SCK to SO

250

Internal SCK source

External SCK source

250

400

t_KSI

Internal SCK source

External SCK source

400

–

t_KSO

300

250

Internal SCK source

tKCY

tKL

tKH

SCK

0.8 VDD

0.2 VDD

tSIK

tKSI

0.8 VDD

0.2 VDD

SI

Input Data

tKSO

SO

Output Data

Figure 19-5. Serial Data Transfer Timing

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Table 19-8. Low Voltage Reset Electrical Characteristics

(T = – 40 ꢃC to + 85 ꢃC, V_DD= 1.8 V to 5.5 V)

A

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

V_LVR

Voltage of LVR

–

1.9

2.0

2.1

V

V_DDvoltage rising time

V_DDvoltage off time

t_R

–

10

0.5

–

ꢎS

S

t_OFF

Hysteresis LVR

–

10

30

100

60

mV

ꢎA

୞V

I_LVR

V_DD= 3.0 V

Current consumption

–

NOTE: The current of LVR circuit is consumed when LVR is enabled by “Smart Option”.

t

OFF

t

R

0.9VDD

0.1VDD

V

DD

Figure 19-6. LVR (Low Voltage Reset) Timing

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Table 19-9. Comparator Converter Electrical Characteristics

(T = – 40 ꢃC to + 85 ꢃC, V_DD= 4.0 V to 5.5 V)

A

Parameter

Symbol

Condition

Min

Typ

Max

Unit

V_DD

Input voltage range

–

0

–

V

V_REF

V_CIN

V_DD

Reference voltage range

Input voltage accuracy

–

0

–

V

8 x 2⁵/fx, @0.4 ~ 12.0 MHz

8 x 2⁴/fx, @0.4 ~ 6.0 MHz

–

mV

ꢑ150

I

_CIN, I_REF

Input leakage current

– 3

–

3

ꢎA

Table 19-10. LCD Contrast Controller Electrical Characteristics

(T = – 40 ꢃC to + 85 ꢃC, V_DD= 4.5 V to 5.5 V)

A

Parameter

Symbol

–

Condition

Min

–

Typ

–

Max

4

Unit

Bits

mV

Resolution

Linearity

–

R_LIN

V_DD= 5.0 V

–

ꢑ150

V_LC0

V_LPP

V_LC0= V_DD= 5.0 V

LMOD = #F8H

Max output voltage

4.9

–

V

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Table 19-11. Main Oscillator Characteristics

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

ꢃ

Oscillator

Clock Configuration

Parameter

Test Condition Min

Typ

Max Units

C1

Crystal

Main oscillation

frequency

2.2 V – 5.5 V

0.4

–

12.0

MHz

XIN

1.8 V – 5.5 V

0.4

–

4.2

XOUT

C1

Ceramic

Oscillator

Main oscillation

frequency

2.2 V – 5.5 V

1.8 V – 5.5 V

0.4

–

12.0

4.2

X

IN

XOUT

X_INinput frequency

Frequency

External

Clock

2.2 V – 5.5 V

1.8 V – 5.5 V

0.4

–

12.0

4.2

X

IN

XOUT

RC

Oscillator

3.0 V

5.0 V

0.4

–

1

2

MHz

XIN

R

XOUT

Table 19-12. Sub Oscillation Characteristics

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

ꢃ

Oscillator

Clock Configuration

Parameter

Test

Condition

Min

Typ

Max Units

Crystal

Sub oscillation

frequency

1.8 V – 5.5 V

–

32.768

–

kHz

C1

XTIN

C2

XTOUT

XT_INinput

frequency

External

clock

1.8 V – 5.5 V

32

–

100

XTIN

XTOUT

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Table 19-13. Main Oscillation Stabilization Time

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Oscillator Test Condition

Crystal

ꢃ

Min

–

Typ

–

Max

40

Unit

ms

fx > 1 MHz

Oscillation stabilization occurs when V_DDis

Ceramic

–

10

ms

equal to the minimum oscillator voltage range.

X_INinput high and low width (t_XH, t_XL)

External clock

62.5

–

1250

ns

1/fx

t

XL

tXH

XIN

V

DD - 0.1V

0.1V

Figure 19-7. Clock Timing Measurement at X_IN

Table 19-14. Sub Oscillation Stabilization Time

ꢃ

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Oscillator Test Condition

Crystal

External clock

Min

–

Typ

–

Max

10

Unit

s

–

XT_INinput high and low width (t_XTH, t_XTL

)

5

–

15

ꢎs

1/fxt

t

XTL

tXTH

XTIN

V

DD - 0.1V

0.1V

Figure 19-8. Clock Timing Measurement at XT_IN

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Instruction Clock

3.0MHz

Main oscillation frequency

12.0 MHz

1.05 MHz

4.2 MHz

0.5 MHz

100 kHz

2.0 MHz

400 kHz

3

4

5

1.8V

2.2V

5.5V

Supply Voltage (V)

CPU Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)

Figure 19-9. Operating Voltage Range

Table 19-15. Internal Flash ROM Electrical Characteristics

ꢃ

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Ftp

Conditions

Min

20

32

4

Typ

25

50

8

Max

30

Unit

Programming Time ⁽¹⁾

Chip Erasing Time ⁽²⁾

Sector Erasing Time ⁽³⁾

Read frequency

–

ꢎs

ms

Ftp1

Ftp2

f_R

70

12

ms

–

12

10,000⁽⁴⁾

MHz

Times

FN_WE

Number of Writing/Erasing

–

NOTES:

1. The Programming time is the time during which one byte (8-bit) is programmed.

2. The Chip erasing time is the time during which all 64K byte block is erased.

3. The Sector erasing time is the time during which all 128 byte block is erased.

4. The Chip erasing is available in Tool Program Mode only.

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NOTES

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20 MECHANICAL DATA

OVERVIEW

The S3F82NB microcontroller is currently available in 128-pin-QFP package.

22.00ꢂꢑꢂ0.30

0-8

20.00 ꢑꢂ0.20

+ 0.10

- 0.05

0.15

0.10 MAX

128-QFP-1420

#128

+ 0.10

- 0.05

#1

0.20

0.05 MIN

0.50

(0.75)

0.10 MAX

2.10 ꢑꢂ0.10

2.40 MAX

0.10 MAX

0.50ꢂꢑꢂ0.20

NOTE: Dimensions are in millimeters.

Figure 20-1. Package Dimensions (128-QFP-1420)

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21 S3F82NB FLASH MCU

OVERVIEW

The S3F82NB single-chip CMOS microcontroller is the Flash MCU. It has an on-chip Flash MCU ROM. The Flash

ROM is accessed by serial data format.

NOTE

This chapter is about the Tool Program Mode of Flash MCU. If you want to know the User Program

Mode, refer to the chapter 18. Embedded Flash Memory Interface.

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COM9/SEG1

1

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

P10.4/SEG28

P10.5/SEG29

P10.6/SEG30

P10.7/SEG31

P9.0/SEG32

P9.1/SEG33

P9.2/SEG34

P9.3/SEG35

P9.4/SEG36

P9.5/SEG37

P9.6/SEG38

P9.7/SEG39

P8.0/SEG40

P8.1/SEG41

P8.2/SEG42

P8.3/SEG43

P8.4/SEG44

P8.5/SEG45

P8.6/SEG46

P8.7/SEG47

P7.0/SEG48

P7.1/SEG49

P7.2/SEG50

P7.3/SEG51

P7.4/SEG52

P7.5/SEG53

P7.6/SEG54

P7.7/SEG55

P2.0/SEG56

P2.1/SEG57

P2.2/SEG58

P2.3/SEG59

P2.4/SEG60

P2.5/SEG61

P2.6/SEG62

P2.7/SEG63

P3.0/SEG64

P3.1/SEG65

COM8/SEG0

2

COM7

3

COM6

4

COM5

5

COM4

6

COM3

7

COM2

8

COM1

9

COM0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

VLC4

VLC3

VLC2

VLC1

VLC0

P1.7/SCK/INT7

P1.6/SO/INT6

SDAT/P1.5/SI/INT5

SCLK/P1.4/BUZ/INT4

VDD/VDD

S3F82NB

128-QFP-1420

VSS/VSS

XOUT

XIN

VPP/TEST

XTIN

XTOUT

nRESET/nRESET

P1.3/INT3

P1.2/INT2

P1.1/INT1

P1.0/AVREF/INT0

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/T0OUT/T0PWM/T0CAP/AD3

P0.2/T1OUT/T1PWM/T1CAP/AD2

P0.1/T0CLK/AD1

Figure 21-1. S3F82NB Pin Assignments (100-QFP-1420)

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Table 21-1. Descriptions of Pins Used to Read/Write the Flash ROM

Main Chip

Pin Name

P1.5

During Programming

I/O

Pin Name

Pin No.

Function

SDAT

18

I/O

Serial data pin. Output port when reading and

input port when writing. Can be assigned as a

Input/push-pull output port.

P1.4

SCLK

V_PP

19

24

I/O

I

Serial clock pin. Input only pin.

Tool mode selection when TEST/ V_PPpin sets

TEST

Logic value ‘1’. If user uses the flash writer tool

mode (ex.spw2+ etc..), user should be connected

TEST/ V_PPpin to V_DD. (S3F82NB supplies high

voltage 12.5V by internal high voltage generation

circuit.)

nRESET

V_DD, V_SS

nRESET

V_DD, V_SS

27

I

Chip Initialization

Power supply pin for logic circuit. V_DDshould be

tied to 5.0V during programming.

20, 21

ꢁꢂ

Test Pin Voltage

The TEST pin on socket board for MTP writer must be connected to V_DD(5.0V) with RC delay as the figure

21-2 (only when SPW 2+ and GW-pro2 are used to). The TEST pin on socket board must not be connected

Vpp (12.5V) which is generated from MTP Writer. So the specific socket board for S3F82NB must be used,

when writing or erasing using MTP writer.

VDD

R (330ȳ)

}

ww

C (0.1uF)

Figure 21-2. RC Delay Circuit

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ON BOARD WRITING

The S3F82NB needs only 6 signal lines including V_DDand V_SSpins for writing internal flash memory with serial

protocol. Therefore the on-board writing is possible if the writing signal lines are considered when the PCB of

application board is designed.

Circuit Design Guide

At the flash writing, the writing tool needs 6 signal lines that are V_SS, V_DD, nRESET, TEST, SDAT and SCLK.

When you design the PCB circuits, you should consider the usage of these signal lines for the on-board writing.

In case of TEST pin, normally test pin is connected to V_SSbut in writing mode the programming these two cases,

a resistor should be inserted between the TEST pin and V_SS. The nRESET, SDAT and SCLK should be treated

under the same consideration.

Please be careful to design the related circuit of these signal pins because rising/falling timing of V_PP, SCLK and

SDAT is very important for proper programming.

G

R

SCLK

SCLK(I/O)

SDAT(I/O)

nRESET

To Application circuit

SDAT

nRESET

VPP

V

PP(TEST)

C VPP

C nRESET

V

DD

V

PP

SDAT

SCLK

V

SS

VDD

nRESET

C nRESET and C VPP are used to

improve the noise effect.

GND

SPW-uni,GW-uni, AS-pro, US-pro

NOTE: If writer tool is the SPW 2+ and GW-pro2, reference to the page 21-3.

Figure 21-3. PCB Design Guide for on Board Programming

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Reference Table for Connection

Table 21-2. Reference Table for Connection

Pin Name

I/O mode

in Applications

Resistor

(need)

Required value

R_Vppis 10 Kohm ~ 50 Kohm.

VPP (TEST)

nRESET

Input

Yes

C_Vppis 0.01uF ~ 0.02uF.

R_nRESETis 2 Kohm ~ 5 Kohm.

C_nRESETis 0.01uF ~ 0.02uF.

R_SDATis 2 Kohm ~ 5 Kohm.

ꢁꢂ

Input

Output

Input

Yes

No^(NOTE)

Yes

SDAT(I/O)

SCLK(I/O)

R_SCLKis 2 Kohm ~ 5 Kohm.

ꢁꢂ

Output

No^(NOTE)

NOTES:

1. In on-board writing mode, very high-speed signal will be provided to pin SCLK and SDAT. And it will cause

some damages to the application circuits connected to SCLK or SDAT port if the application circuit is designed

as high speed response such as relay control circuit. If possible, the I/O configuration of SDAT, SCLK pins had

better be set to input mode.

2. The value of R, C in this table is recommended value. It varies with circuit of system.

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22 DEVELOPMENT TOOLS

OVERVIEW

Samsung provides a powerful and easy-to-use development support system on a turnkey basis. The development

support system is composed of a host system, debugging tools, and supporting software. For a host system, any

standard computer that employs Win95/98/2000/XP as its operating system can be used. A sophisticated

debugging tool is provided both in hardware and software: the powerful in-circuit emulator, OPENice-i500 and SK-

1200, for the S3C7-, S3C9-, and S3C8- microcontroller families. Samsung also offers supporting software that

includes, debugger, an assembler, and a program for setting options.

TARGET BOARDS

Target boards are available for all the S3C8/S3F8-series microcontrollers. All the required target system cables

and adapters are included on the device-specific target board. TB82NB is a specific target board for the

development of application systems using S3F82NB.

PROGRAMMING SOCKET ADAPTER

When you program S3F82NB’s flash memory by using an emulator or OTP/MTP writer, you need a specific

programming socket adapter for S3F82NB.

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IBM-PC AT or Compatible

Emulator [SK-1200 (RS-232, USB)

RS-232C/USB

or OPENice i-500 (RS-232) ]

Target

Application

System

OTP/MTP Writer Block

RAM Break/Display Block

Probe

Adapter

Trace/Timer Block

SAM8 Base Block

TB82NB

Target

Board

POD

EVAChip

Power Supply Block

Figure 22-1. Emulator Product Configuration

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TB82NB TARGET BOARD

The TB82NB target board can be used for development of the S3F82NB microcontroller.

The TB82NB target board is operated as target CPU with Emulator (SK-1200, OPENice-i500)).

TB82NB

In-Circuit Emulator

To User_VCC

(SK-1200, OPENice-i500)

Off

On

IDLE

STOP

RESET

U2

7411

J1

JP2

Y1

(sub-clock)

VDD

AVREF

J2

VCC

CN4

4

25

CN6

J101

J102

(TB Mode Selection)

Main Mode

1

2

65

66

Eva Mode

50

1

60

200

208 QFP

S3E82N0

EVA Chip

1

160

100

JP1

110

150

(Smart Option Source)

External

TP1

63

Smart Option Selection

64 127

128

Internal

"0"

ON

1

SW1

6

2

3

7

8

4

5

9

10

"1"

Figure 22-2. TB82NB Target Board Configuration

NOTE: The symbol ‘ ‘ marks start point of jumper signals.

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Table 22-1. Components of TB82NB

Symbols

Usage

100-pin connector

64-pin connector

Description

J2

Connection between emulator and TB82NB target board.

J101, J102

Connection between target board and user application

system

RESET

Push button

Generation low active reset signal to S3F82NB EVA-chip

External power connector for TB82NB

VDD, GND

STOP, IDLE LED

POWER connector

STOP/IDLE Display

Indicate the status of STOP or IDLE of S3F82NB EVA-chip

on TB82NB target board

CN1

CN6

Flash serial programming

TB Mode Selection

Signal points for programming Flash ROM by external

programmer. Don’t use this one in user mode.

Selection of EVA/MAIN-chip mode

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Table 22-2. Setting of the Jumper in TB82NB

1-2 Connection

JP#

Description

2-3 Connection

Default

Setting

CN4

AVREF power source

VDD

User power

Join 2-3

You should activate AVREF on the TB82NB by setting the

related TP1.

TP1

P1.0/INT0 or AVREF selection

TP1 should be used P1.0/INT0 normally. If user wants to use

the AVREF, user should be connected to VSS.

CN6

JP2

Target board mode selection

Clock source selection

H: MAIN-Mode

L: EVA-Mode

Join 2-3

When using the internal clock source which is generated from

Emulator, join connector 2-3 and 4-5 pin. If user wants to use

the external clock source like a crystal, user should change the

jumper setting from 1-2 to 5-6 and connect J1 to an external

clock source.

Emulator

2-3

4-5

J1

External clock source

Connecting points for external clock source

JP1

Smart option source selection

The Smart Option is selected The Smart Option is selected

by external smart option switch by internal smart option area

Join 1-2

(SW1)

(003EH–0003FH of ROM). But

this selection is not available.

SW1

CN1

Smart option selection

The Smart Option can be selected by this switch when the

Smart Option source is selected by external. The B2–B0 are

comparable to the 003EH.2–.0. The B7–B5 are comparable to

the 003EH.7–.5. The B8 is comparable to the 003FH.0.

The B4–B3 and B9 are not connected. The TP1 is comparable

to the 003FH.7. Refer to the page 2-3.

Header for flash serial

programming signals

To program an internal flash, connect the signals with flash

writer tool.

Target System is supplied V_DD

Target Board is supplied V_DD

from user System.

To

User_Vcc

Target Board is not supplied

_DDfrom user System.

Join 2-3

V

ꢈ

IDLE LED

This LED is ON when the evaluation chip (S3E82N0) is in idle mode.

STOP LED

This LED is ON when the evaluation chip (S3E82N0) is in stop mode

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J101

COM9/SEG1

COM7

1

2

4

COM8/SEG0

COM6

3

COM5

5

6

COM4

COM3

7

8

COM2

COM1

9

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

COM0

VLC4

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

VLC3

VLC2

VLC1

VLC0

P1.7/INT7/SCK

P1.5/INT5/SI

VDD

P1.6/INT6/SO

P1.4/INT4/BUZ

VSS

N.C

nRESET

P1.3/INT3

P1.1/INT1

P0.7/AD7

P0.5/AD5

P1.2/INT2

P1.0/INT0/AVREF

P0.6/AD6

P0.4/AD4

P0.3/AD3/T0OUT/T0PWM/T0CAP

P0.1/AD1/T0CLK

P6.2/CIN2

P0.2/T1OUT/T1PWM/T1CAP/AD2

P0.0/T1CLK/AD0

P6.1/CIN1

P6.0/CIN0

P5.7/INT11/SEG87

P5.5/INT9/SEG85

P5.3/SEG83

P5.1/SEG81

P4.7/SEG79

P4.5/SEG77

P4.3/SEG75

P4.1/SEG73

P3.7/SEG71

P3.5/SEG69

P3.3/SEG67

P5.6/INT10/SEG86

P5.4/INT8/SEG84

P5.2/SEG82

P5.0/SEG80

P4.6/SEG78

P4.4/SEG76

P4.2/SEG74

P4.0/SEG72

P3.6/SEG70

P3.4/SEG68

P3.2/SEG66

Figure 22-3. 64-Pin Connectors (J101, J102) for TB82NB

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P R E L I M I N A R Y

S3F82NB

Product Specification

354

J102

P3.1/SEG65

P2.7/SEG63

P2.5/SEG61

P2.3/SEG59

P2.1/SEG57

P7.7/SEG55

P7.5/SEG53

P7.3/SEG51

P7.1/SEG49

P8.7/SEG47

P8.5/SEG45

P8.3/SEG43

P8.1/SEG41

P9.7/SEG39

P9.5/SEG37

P9.3/SEG35

P9.1/SEG33

P10.7/SEG31

P10.5/SEG29

P10.3/SEG27

P10.1/SEG25

SEG23

1

2

4

P3.0/SEG64

P2.6/SEG62

P2.4/SEG60

P2.2/SEG58

P2.0/SEG56

P7.6/SEG54

P7.4/SEG52

P7.2/SEG50

P7.0/SEG48

P8.6/SEG46

P8.4/SEG44

P8.2/SEG42

P8.0/SEG40

P9.6/SEG38

P9.4/SEG36

P9.2/SEG34

P9.0/SEG32

P10.6/SEG30

P10.4/SEG28

P10.2/SEG26

P10.0/SEG24

SEG22

3

5

6

7

8

9

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

COM15/SEG7

COM13/SEG5

COM11/SEG3

COM14/SEG6

COM12/SEG4

COM10/SEG2

Figure 22-3. 64-Pin Connectors (J101, J102) for TB82NB (Continued)

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P R E L I M I N A R Y

S3F82NB

Product Specification

355

Target Board

Target System

J102

J101

J102

1

2

65 66

1

2

Target Cable for 64-Pin

Connector

63 64 127 128

127 128 63 64

Figure 22-4. S3F82NB Cables for 128-QFP Package

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P R E L I M I N A R Y

S3F82NB

Product Specification

356

THIRD PARTIES FOR DEVELOPMENT TOOLS

SAMSUNG provides a complete line of development tools for SAMSUNG's microcontroller. With long experience

in developing MCU systems, our third parties are leading companies in the tool's technology. SAMSUNG In-circuit

emulator solution covers a wide range of capabilities and prices, from a low cost ICE to a complete system with

an OTP/MTP programmer.

In-Circuit Emulator for SAM8 family

ꢈ

OPENice-i500

SmartKit SK-1200

OTP/MTP Programmer

ꢈ

SPW-uni

GW-uni

AS-pro

US-pro

Development Tools Suppliers

Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting

development tools.

8-bit In-Circuit Emulator

OPENice - i500

AIJI System

ꢈ

TEL: 82-31-223-6611

FAX: 82-331-223-6613

E-mail : openice@aijisystem.com

URL : http://www.aijisystem.com

SK-1200

Seminix

ꢈ

TEL: 82-2-539-7891

FAX: 82-2-539-7819

E-mail: sales@seminix.com

URL: http://www.seminix.com

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P R E L I M I N A R Y

S3F82NB

Product Specification

357

OTP/MTP PROGRAMMER (WRITER)

SEMINIX

SPW-uni

Single OTP/ MTP/FLASH Programmer

ꢈ

TEL: 82-2-539-7891

FAX: 82-2-539-7819.

E-mail:

sales@seminix.com

URL:

ꢈ

Download/Upload and data edit function

PC-based operation with USB port

Full function regarding OTP/MTP/FLASH MCU

programmer

ꢈ

http://www.seminix.com

(Read, Program, Verify, Blank, Protection..)

Fast programming speed (4Kbyte/sec)

Support all of SAMSUNG OTP/MTP/FLASH MCU

devices

ꢈ

Low-cost

NOR Flash memory (SST, Samsung…)

NAND Flash memory (SLC)

New devices will be supported just by adding

device files or upgrading the software.

SEMINIX

GW-uni

ꢈ

TEL: 82-2-539-7891

Gang Programmer for OTP/MTP/FLASH MCU

FAX: 82-2-539-7819.

E-mail:

ꢈ

8 devices programming at one time

Download/Upload and data edit function

PC-based operation with USB port

Full function regarding OTP/MTP/FLASH MCU

programmer

sales@seminix.com

URL:

ꢈ

http://www.seminix.com

(Read, Program, Verify, Blank, Protection..)

Fast programming speed (4Kbyte/sec)

Support all of SAMSUNG OTP/MTP/FLASH MCU

devices

ꢈ

Low-cost

NOR Flash memory (SST, Samsung…)

NAND Flash memory (SLC)

New devices will be supported just by adding

device files or upgrading the software.

ꢈ

Will be developed in March, 2008.

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P R E L I M I N A R Y

S3F82NB

Product Specification

358

OTP/MTP PROGRAMMER (WRITER) (Continued)

SEMINIX

AS-pro

ꢈ

TEL: 82-2-539-7891

FAX: 82-2-539-7819.

E-mail:

sales@seminix.com

URL:

On-board programmer for Samsung Flash MCU

ꢈ

Portable & Stand alone Samsung

OTP/MTP/FLASH Programmer for After Service

Small size and Light for the portable use

ꢈ

ꢈ Support all of SAMSUNG OTP/MTP/FLASH

http://www.seminix.com

devices

ꢈ

HEX file download via USB port from PC

Very fast program and verify time

( OTP:2Kbytes per second, MTP:10Kbytes per

second)

ꢈ

Internal large buffer memory (118M Bytes)

Driver software run under various O/S

(Windows 95/98/2000/XP)

ꢈ

Full function regarding OTP/MTP programmer

(Read, Program, Verify, Blank, Protection..)

Two kind of Power Supplies

(User system power or USB power adapter)

Support Firmware upgrade

SEMINIX

US-pro

Portable Samsung OTP/MTP/FLASH Programmer

ꢈ

TEL: 82-2-539-7891

ꢈ Portable Samsung OTP/MTP/FLASH Programmer

ꢈ Small size and Light for the portable use

ꢈ Support all of SAMSUNG OTP/MTP/FLASH

devices

ꢈ Convenient USB connection to any IBM compatible

PC or Laptop computers.

FAX: 82-2-539-7819.

E-mail:

sales@seminix.com

URL:

ꢈ

http://www.seminix.com

ꢈ Operated by USB power of PC

ꢈ PC-based menu-drive software for simple operation

ꢈ

Very fast program and verify time

( OTP:2Kbytes per second, MTP:10Kbytes per

second)

ꢈ Support Samsung standard Hex or Intel Hex format

ꢈ

Driver software run under various O/S

(Windows 95/98/2000/XP)

Full function regarding OTP/MTP programmer

(Read, Program, Verify, Blank, Protection..)

Support Firmware upgrade

SEMINIX

Flash writing adapter board

ꢈ

TEL: 82-2-539-7891

ꢈ

Specific flash writing socket only for S3F82NB

FAX: 82-2-539-7819.

E-mail:

- 128QFP

sales@seminix.com

URL:

ꢈ

http://www.seminix.com

PS031601-0813

P R E L I M I N A R Y


型号：	S3F82NB
厂家：	ZILOG, INC.
描述：	S3 Family 8-Bit Microcontrollers S3系列8位微控制器微控制器
文件：	总361页 (文件大小：1471K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S3F82NB [ZILOG]

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