ZXFV4583N16TA [ZETEX]

SYNC SEPARATOR WITH VARIABLE FILTER; 带可变滤波器同步分离器


型号：	ZXFV4583N16TA
厂家：	ZETEX SEMICONDUCTORS
描述：	SYNC SEPARATOR WITH VARIABLE FILTER 带可变滤波器同步分离器商用集成电路光电二极管 LTE
文件：	总14页 (文件大小：213K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ZXFV4583

SYNC SEPARATOR WITH VARIABLE FILTER

DEVICE DESCRIPTION

FEATURES AND BENEFITS

The ZXFV4583 provides the ability to separate out

video synchronization signals for a wide variety of TV

and CRT display system s, standard and non-standard.

•

PAL, NTSC, SECAM

Variable filter for optim al accuracy

Sync outputs: com posite, horizontal, vertical, back

porch, odd/even

Flexibility arises from the use of just three external

resistors to adapt to each application. One resistor

controls a fully integrated internal color carrier filter

with variable bandwidth. This filter avoids disturbance

from the color carrier, perm itting accurate threshold

slicing for tim ing extraction.

•

No-signal detector

On chip sam ple / hold capacitors

+5V single supply

Default vertical output where there are no

serration pulses

A second resistor controls the voltage threshold for

loss of signal detection after a tim e-out interval. The

third resistor controls the tim ing functions.

•

Pin and layout com patible with part EL4583 in

SO16N surface m ount package

APPLICATIONS

DC restoration for displays is facilitated by the Back

Porch synch output, which can be used to drive an

external circuit to clam p the blanking voltage to a fixed

level.

•

Digital im age capture

Video input system s requiring separation of

picture tim ing

ORDERING INFORMATION

•

Video distribution

Part Number

Container

Increment

500

CCTV surveillance

ZXFV4583N16TA

ZXFV4583N16TC

Re e l 7″

Digital m ultim edia

Re e l 13″

2500

Tim ing for black level clam p

CONNECTION DIAGRAM

ISSUE 3 - NOVEMBER 2003

S E M IC O N D U C T O R S

ZXFV4583

ABSOLUTE MAXIMUM RATINGS

Supply voltage V_CC

-0.5V to +7V

Inputs to ground*

-0.5V to V_CC+0.5V

Operating tem perature range

Storage

-40ЊC to 85ЊC

-65ЊC to +150ЊC

T_{J MAX}150ЊC**

Operating am bient junction tem perature

**The therm al resistance from the sem iconductor die to am bient is typically 120ЊC/W when the SO16 package is

m ounted on a PCB in free air. The power dissipation of the device when loaded m ust be designed to keep the

device junction tem perature below T_{J MAX.}

*During power-up and power-down, these voltage ratings require that signals be applied only when the power

supply is connected.

ELECTRICAL CHARACTERISTICS

V_CC= 5V, R_SET= 681k⍀, R_FILT= 22k⍀, R_NOSIG= 82k⍀, T_{am b}= 25ЊC unless otherwise stated.

Test level:

P = 100% production test

C = Characterized only

PARAMETER

CONDITIONS

TES T

MIN

TYP MAX UNIT

DC Ch a ra ct e ris t ics

S u p p ly cu rre n t

4.5

1.35

6.5

1.5

m A

Cla m p vo lta g e a t FILTIN

Dis ch a rg e cu rre n t a t FILTIN

Cla m p ch a rg e cu rre n t a t FILTIN

Cla m p vo lta g e a t FVIDIN

Dis ch a rg e cu rre n t a t FVIDIN

Cla m p ch a rg e cu rre n t a t FVIDIN

Pin 4 u n lo a d e d

1.2

Pin 4, Vin = 2V p k-p k

Pin 4, n o s ig n a l

␮A

m A

Pin 4, Vin = 1V p k-p k

Pin 8 u n lo a d e d

1.2

1.35

1.5

Pin 8, Vin = 2V p k-p k

Pin 8, n o s ig n a l

␮〈

m A

Pin 8, Vin = 1V p k-p k

vo lta g e , p in 12

vo lta g e , p in 1

1.5

0.35

1.5

1.75

0.5

2.5

0.35

S ET

FILT

0.65

3.5

0.8

RNOS IG cu rre n t, p in 2

␮A

Lo g ic o u tp u t lo w vo lta g e , V

= 1.6m A

ISSUE 3 - NOVEMBER 2003

S E M IC O N D U C T O R S

ZXFV4583

ELECTRICAL CHARACTERISTICS (Cont.)

= 5V, R

= 681k⍀, R

= 22k⍀, R

= 82k⍀, T

= 25ЊC unless otherwise stated.

am b

SET

FILT

NOSIG

PARAMETER

AC Ch a ra ct e ris t ics

CONDITIONS

TES T MIN TYP MAX

UNIT

FILTIN fu n ctio n in p u t vo lta g e ra n g e

Filte r vo lta g e g a in

PAL/NTS C

0.5

4.9

V p k-p k

d B

FILTIN to FILOUT

5.7

6.5

Filte r a tte n u a tio n

4.4MHz fo r PAL,

3.6MHz fo r NTS C

d B

S lice le ve l

Vin = 1V p k-p k

40 50

n s

␮s

n s

␮s

n s

␮s

CS YNC p ro p . De la y, t

VS YNC d e la y

Re la tive to p in 4 in p u t

250 400

250

VS YNC p u ls e w id th , t

(PAL)

165

VS YNC

(NTS C)

195

VS YNC d e fa u lt d e la y, t

HS YNC d e la y

3.8

2.7

250

VS D

HS YNC p u ls e w id th , t

6.2

HS YNC

BKPCH d e la y, t

Re la tive to p in 4 in p u t

250 400

3.7 4.7

BKPCH p u ls e w id th , t

Note:

In order to avoid coupling between high speed logic output signals and analog inputs, the test circuit

layout uses connections from the logic output pins routed away from the analog pins. In the application,

sim ilar care in the layout is required, keeping resistors R

, R

NOSIG

and R close to their respective

FILT

SET

pins, in particular routing signal CSYNC away from pins 1, 2 and 12.

ISSUE 3 - NOVEMBER 2003

S E M IC O N D U C T O R S

ZXFV4583

CONNECTIONS

PIN No . PIN NAME

TYPE

FUNCTION

Co n tro ls th e in p u t co lo r ca rrie r filte r ch a ra cte ris tic. An e xte rn a l

Re s is to r

co n tro l

re s is to r R

S m a lle r R

co n n e cte d fro m th is p in to 0V s e ts th e b a n d w id th .

FILT

g ive s in cre a s e d b a n d w id th . S e e th e d e ta ile d o p e ra tin g

d e s crip tio n b e lo w .

Co n tro ls th e n o -s ig n a l d e te cto r le ve l. An e xte rn a l re s is to r R

NOS IG

co n n e cte d fro m th is p in to 0V s e ts th e th re s h o ld vo lta g e le ve l,

a cco rd in g to th e e q u a tio n

Re s is to r

co n tro l

NOS IG

= 0.75 R

/ R

PMIN

NOS IG S ET

w h e re V

is th e m in im u m d e te cte d s yn c p u ls e a m p litu d e a t p in 4

PMIN

a n d R

is th e re s is to r va lu e a t p in 12.

S ET

Co m p o s ite s yn c lo g ic o u tp u t. In clu d e s a ll s yn c p u ls e s d e rive d fro m

th e in p u t vid e o .

CS YNC

FILTIN

Lo g ic o u t

An a lo g in

In p u t to co lo r ca rrie r filte r. Th is is th e m a in a n a lo g (u n filte re d )

co m p o s ite vid e o in p u t u s e d w h e n co lo r ca rrie r filte rin g is re q u ire d . A

vo lta g e cla m p circu it a n d a d a p tive cu rre n t s o u rce a re a ls o in clu d e d

a t th is n o d e . S e e th e d e ta ile d o p e ra tin g d e s crip tio n . Wh e n th e filte r

is n o t u s e d , th is p in m u s t b e le ft o p e n circu it.

Ve rtica l s yn c o u tp u t. Th is is a n a ctive lo w p u ls e co m m e n cin g o n th e

firs t ve rtica l s yn c p u ls e tra ilin g (ris in g ) e d g e a n d e n d in g n e a r th e

s e co n d n e xt e q u a lizin g p u ls e . S e e tim in g d ia g ra m .

VS YNC

OVD

Lo g ic o u t

Gro u n d

Pro vid e s g ro u n d re tu rn p a th fo r in te rn a l lo g ic o u tp u t b u ffe r circu its .

No rm a lly co n n e cte d e xte rn a lly to a co m m o n PCB g ro u n d p la n e .

An a lo g o u tp u t s ig n a l fro m co lo r ca rrie r filte r. Th e filte r vo lta g e g a in

is n o m in a lly 2. Th is o u tp u t is n o rm a lly ca p a cito r-co u p le d to p in 8.

FILTOUT An a lo g o u t

In p u t fo r filte re d a n a lo g vid e o s ig n a l in p u t. Th is is th e d ire ct in p u t

to th e s a m p le /h o ld a n d s yn c s licin g co m p a ra to r p ro vid in g th e lo g ic

tim in g e d g e s . Th is in p u t is n o rm a lly co u p le d via a n e xte rn a l

ca p a cito r fro m FILTOUT, p in 7. It m a y b e u s e d a s th e s ig n a l in p u t

w h e re th e co lo r ca rrie r filte r is n o t re q u ire d . In clu d e s a cla m p

s im ila r th a t o f p in 4.

FVIDIN

An a lo g in

An a lo g o u tp u t, a p o s itive vo lta g e typ ica lly e q u a l to tw ice th e

(n e g a tive ) p e a k s yn c p u ls e a m p litu d e if th e filte r is u s e d .

VLEV

An a lo g o u t

Lo g ic o u t

Lo g ic o u tp u t, w h ich g o e s h ig h a fte r a tim e -o u t d e la y w h e n n o s ig n a l

is p re s e n t. Th e th re s h o ld le ve l is co n tro lle d a t p in 2.

NOS IG

Bu rs t o r Ba ck Po rch lo g ic o u tp u t, a n a ctive lo w m o n o s ta b le p u ls e

trig g e re d fro m ris in g co m p o s ite s yn c p u ls e e d g e s . Th e w id th is s e t

b y R

to o ve rla p m o s t o f th e s te a d y p a rt o f th e b a ck p o rch ,

S ET

BKPCH

Lo g ic o u t

a s s u m in g th e co lo r ca rrie r b u rs t h a s b e e n a tte n u a te d s u fficie n tly b y

filte rin g . Th is p u ls e is th e n s u ita b le fo r co n tro llin g a n e xte rn a l b la ck

le ve l cla m p in g circu it. S e e th e tim in g d ia g ra m .

Co n tro ls th e tim in g in te rva l o f th e s a m p le /h o ld circu it a n d th e

m o n o s ta b le in te rva l fo r th e s yn c o u tp u ts a cco rd in g to th e

Re s is to r

co n tro l

a p p lica tio n . An e xte rn a l re s is to r, R

co n n e cte d fro m th is p in to 0V

S ET

e s ta b lis h e s th e tim in g p a ra m e te r, to w h ich th e s e tim e s a re s ca le d

to g e th e r. S e e th e d e ta ile d o p e ra tin g d e s crip tio n .

Od d fie ld lo g ic o u tp u t. Hig h d u rin g a n o d d n u m b e re d fie ld , lo w

d u rin g e ve n . Th is o u tp u t is tim e d w ith th e s ta rt o f th e VS YNC p u ls e .

ODDFLD

V+

Lo g ic o u t

Po w e r in Po w e r s u p p ly in p u t, +5V.

Ho rizo n ta l s yn c lo g ic o u tp u t. Mo n o s ta b le o u tp u t d e rive d fro m

CS YNC fa llin g e d g e s , it a ch ie ve s a s te a d y s tre a m o f 5µs p u ls e s . Th e

h a lf lin e e ve n ts d u rin g th e fie ld b la n kin g in te rva l a re e lim in a te d . S e e

tim in g d ia g ra m .

HS YNC

Lo g ic o u t

ISSUE 3 - NOVEMBER 2003

S E M IC O N D U C T O R S

ZXFV4583

DETAILED DESCRIPTION

Introduction

This device includes all the functions required to separate

out the critical timing points of most types of video signal.

A sam ple-and-hold process is used to establish

accurately the 50% point of the sync pulse. The input is

also filtered to avoid the effect of the color carrier. The

filter is coupled externally. The following paragraphs

give a simplified description of the signal processing.

The vertical sync output VSYNC is derived from the

Field pulse group. Where there are short equalization

pulses in the standard system s, these short pulses are

ignored. Essentially, a pulse width discrim inator

circuit senses the first of the Field pulses, as they are

wider than those of the rest of the sequence. The

trailing edge of the first negative-going Fram e Pulse

(i.e. the rising edge of the first “serration” pulse)

triggers the VSYNC output. In system s with a fram e

interval with no serration pulses, a vertical sync output

is provided after a default delay as in Figure 4. Also

provided is an ODDFLD logic output, which is high

during an odd-num bered field and low during an even

one.

Color carrier filter

This low-pass filter provides adjustable attenuation of

the color carrier with low distortion of the rem aining

sync pulses so as to ensure accurate tim ing of the

extracted logic outputs. The control is via an external

re s is to r R_FILTco n n e cte d fro m p in 1 to g ro u n d .

_FILT=22k⍀ g ive s co rn e r fre q u e n cy o f ∼1.3MHz

c o r r e s p o n d in g t o ~1 2 d B a t t e n u a t io n

3.58MHz.(Co rn e r fre q . Pro p o rtio n a l to 1/R_FILT

The horizontal sync HSYNC is a m onostable output

d e rive d fro m th e le a d in g (fa llin g ) e d g e o f th e

com posite sync. The pulse width is about 5 µs. Also,

during the Field blanking sequence, the additional

half-line pulses are rem oved by a tim ing circuit with a

pulse interval discrim ination function controlled by

m inim um value 18k⍀). A graph shows how the

bandwidth varies with the resistor value.

_SET. R_SETis norm ally set to 681k⍀ for standard PAL or

NTSC tim ings. Consequently the scan rate is inversely

proportional to R_SET

Clam ping circuits

Clam ping circuits are use to lim it the signal swing

excursion after AC coupling at both the input to the

filter, FILTIN and the tim ing extractor input, FVIDIN. In

each case, the sync tip level is m aintained at a value of

nom inally 1.35V.

The Back Porch m onostable output BKPCH is initiated

from the trailing edge of the com posite sync. The pulse

is active low and the width is set according to R_SET

Sync tim ing extraction circuits

Loss-of-Signal detector

The waveform s are depicted in Tim ing Diagram s,

Figure 1 for PAL (625 lines) and Figure 2 for NTSC (525

lines). Sam ple-and-hold circuits are used to obtain

tim e-delayed voltage values of the sync tip and the

back porch. The sam ple gates are controlled by a

com parator sensing the video input relative to a

threshold at a fixed offset above the sync tip clam p

level. The sam pled voltages are com bined in a

potential divider to derive the m ean voltage (50%

am plitude), which is used as the sync pulse threshold.

A second com parator then provides CSYNC, the logic

version of the com posite sync signal. This is delayed

s lig h tly a s s h o w n in Fig u re 3. Th e tim e d e la y

com prises that of the input filter and also the sm aller

delay of the com parator and logic. The tim ing of the

s a m p le h o ld a n d o th e r tim e p a ra m e te rs a re a ll

controlled together in unison by the external resistor

Loss of signal is indicated by a logic high level at the

output NOSIG. The decision threshold is set by an

external resistor R_NOSIGconnected from pin 2 to

ground. R_NOSIG=100k⍀ gives a shut off threshold of

∼250m V of sync am plitude at FVIDIN or ~130m V on

FILTIN (Threshold proportional to R_NOSIG, m inim um

value 82k⍀) The table of connections above gives the

equation used to determ ine a suitable resistor value. A

waiting tim e of nom inally 600 µs occurs before the loss

of signal is flagged.

R_SET. A 1% resistor tolerance is recom m ended. The

sync tip voltage level from the sam ple-and-hold is

buffered and provided as an analog output, VLEV.

ISSUE 3 - NOVEMBER 2003

S E M IC O N D U C T O R S

ZXFV4583

FRAME 1

FIELD BLANKING

VIDEO INPUT

621

624

620

622

623

625

CSYNC OUTPUT

VSYNC OUTPUT

HSYNC OUTPUT

BACK PORCH OUTPUT, BKPCH

SEE FIGURE 3 FOR DETAIL

Figure 1: PAL 625 TIMING DIAGRAM

VIDEO INPUT

524

523

525

CSYNC OUTPUT

VSYNC OUTPUT

HSYNC OUTPUT

BACK PORCH OUTPUT, BKPCH

Figure 2: NTSC TIMING DIAGRAM

ISSUE 3 - NOVEMBER 2003

S E M IC O N D U C T O R S

ZXFV4583

FVIDIN VIDEO INPUT

50%

t_CS

CSYNC OUTPUT

t_BD

BKPCH OUTPUT

t_B

Figure 3: SYNC SLICING & OUTPUT DETAIL

LINE PERIOD

FVIDIN VIDEO INPUT

VSD

VSYNC OUTPUT

Figure 4: VERTICAL SYNC DEFAULT

ISSUE 3 - NOVEMBER 2003

S E M IC O N D U C T O R S

ZXFV4583

TYPICAL CHARACTERISTICS

ISSUE 3 - NOVEMBER 2003

S E M IC O N D U C T O R S

ZXFV4583

TYPICAL CHARACTERISTICS (Cont.)

ISSUE 3 - NOVEMBER 2003

S E M IC O N D U C T O R S

ZXFV4583

APPLICATIONS INFORMATION

General guidance

Parts List

The ZXFV4583 is a high speed m ixed analog/digital

s ig n a l p r o c e s s in g c o m p o n e n t r e q u ir in g t h e

appropriate care in the layout of the application printed

circuit board. A continuous ground plane construction

is preferred. Suitable power supply decoupling

suggested includes a 100nF leadless ceram ic capacitor

close to the power supply connection at pin 14.

QTY

CCTREF

VALUE

DES CRIPTION

Re s is t o rs , s u rfa ce m o u n t

51⍀

22k⍀

82k⍀

681k⍀

2.2k⍀

1k⍀

0805

In order to avoid coupling between high speed logic

output signals and analog inputs, the test circuit layout

uses connections from the logic output pins routed

away from the analog pins. In the application, sim ilar

R5, R12

R6, R7, R8

care in the layout is required, keeping resistors, R_FILT

130⍀

33⍀

_NOSIG, and R_SETclose to their respective pins, in

R10

particular routing signal CSYNC away from pins 1, 2

and 12.

R11

24⍀

Ca p a cit o rs , s u rfa ce m o u n t

Evaluation circuit

C1, C2,

C3, C5, C6

100n F ce ra m ic X7R 50V 0805

An evaluation circuit is available, designed to provide

dem onstration of the ZXFV4583 function using 50 ⍀

test instrum ents. The schem atic diagram is shown in

Figure 5 and the printed circuit layout is shown in

Figures 6, 7 and 8. The circuit includes the Zetex

ZXFV4089 DC Restoration Circuit, which is described in

the data sheet for that part. The ZXFV4089 uses the

Back Porch output from the ZXFV4583 in order to

co n tro l a n d s ta b ilize th e b la ck le ve l o f a vid e o

waveform .

1n F

ceram ic NPO 50V 0805

ce ra m ic X7R 50V 0805

10n F

ta n ta lu m e le c 16V

s ize C

C8, C9

10␮F

In t e g ra t e d circu it s

ZXFV4583N16 - Ze te x

ZXFV4089N8 - Ze te x

BNC con n e ctor so cke ts a llo w co nn e ction of the

a n a lo g v id e o a n d o u t p u t t o la b o r a t o r y t e s t

instrum ents via 50 ⍀ BNC cables. The circuit can be

adapted for 75 ⍀ use. The output circuit includes a

resistor m atching circuit to present a load of 150 ⍀ to

the am plifier and sim ultaneously provide 50 ⍀ output

im pedance. The attenuation of this m atching circuit is

15.45 dB. As the am plifier is configured for a voltage

gain of 2, the overall gain in a 50 ⍀ system is:

Mis ce lla n e o u s

S o cke t BNC PCB

s tra ig h t fla n g e e .g .

Tyco B35N14H999X99

J 1, J 2

J 3

Te rm in a l b lo ck 3-w a y

IMO 20.501/3S B

He a d e r 8 w a y s in g le

ro w 2.54m m , Ha rw in

M20-9990805

PL1

PL2

6 - 15.45 = -9.45 dB.

Header 8 way double

row 2.54m m , Harwin M

The synchronized logic outputs are brought to a header

for exam ination using oscilloscope probes. A set of

jum per links allow the selection of operation with or

without the built in color carrier filter. The selection is

depicted on the board itself.

TP1, TP2,

TP3

Te s t te rm in a l, W.

Hu g h e s 200-207

J u m p e r Lin k, Ha rw in

M7567-05

LK1, LK2

ISSUE 3 - NOVEMBER 2003

S E M IC O N D U C T O R S

ZXFV4583

Figure 5: Evaluation circuit board schem atic

ISSUE 3 - NOVEMBER 2003

S E M IC O N D U C T O R S

ZXFV4583

Figure 6: Evaluation circuit layout: Top side

Figure 7: Evaluation circuit layout: Bottom side (view ed through board)

ISSUE 3 - NOVEMBER 2003

S E M IC O N D U C T O R S

ZXFV4583

Figure 8: Evaluation circuit layout: Com ponent layout

ISSUE 3 - NOVEMBER 2003

S E M IC O N D U C T O R S

ZXFV4583

PACKAGE OUTLINE

⍜

Pin1

Seating Plane

Millim e t e rs

In ch e s

DIM

MIN

MAX

MIN

MAX

1.35

0.10

0.33

0.19

9.80

3.80

1.75

0.053

0.004

0.013

0.008

0.386

0.150

0.069

0.25

0.51

0.010

0.020

0.25

10.00

4.00

0.010

0.394

0.157

1.27BS C

0.050BS C

0.228

5.80

0.25

0.40

0°

6.20

0.50

1.27

8°

0.244

0.020

0.050

8°

0.010

0.016

0°

⍜

Conform s to J EDEC MS-012AC Iss C (SO16N)

Europe

Am ericas

Asia Pacific

Zetex plc

Zetex Gm bH

Zetex Inc

Zetex (Asia) Ltd

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Chadderton

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United Kingdom

Telephone (44) 161 622 4444

Fax: (44) 161 622 4446

hq@zetex.com

Kwai Fong

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Telephone: (852) 26100 611

Fax: (852) 24250 494

asia.sales@zetex.com

Germ any

USA

Telefon: (49) 89 45 49 49 0

Fax: (49) 89 45 49 49 49

europe.sales@zetex.com

Telephone: (1) 631 360 2222

Fax: (1) 631 360 8222

usa.sales@zetex.com

These offices are supported by agents and distributors in m ajor countries world-wide.

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for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned. The Com pany

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ISSUE 3 - NOVEMBER 2003

S E M IC O N D U C T O R S

ZXFV4583N16TA [ZETEX]

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