PSA1905A [ZCOMM]

LOW COST - HIGH PERFORMANCE PHASE LOCKED LOOP; 低成本 - 高性能锁相环


型号：	PSA1905A
厂家：	Z-COMMUNICATIONS, INC
描述：	LOW COST - HIGH PERFORMANCE PHASE LOCKED LOOP 低成本 - 高性能锁相环
文件：	总2页 (文件大小：76K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PSA1905A

9939 Via Pasar • San Diego, CA 92126

TEL (858) 621-2700 FAX (858) 621-2722

PHASE LOCKED LOOP

Rev A1

PHASE NOISE (1 Hz BW, typical)

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

FEATURES

• Frequency Range: 1875

1935

MHz

• Step Size:

100

KHz

•

- Style Package

PLL-24

APPLICATIONS

• Telecommunications

• Satellite

100

1000

10000

100000

Telemetry

•

VALUE

1875 - 1935

UNITS

MHz

PERFORMANCE SPECIFICATIONS

Frequency Range

-106

dBc/Hz

dBc

Phase Noise @ 10 kHz offset (1 Hz BW, typ.)

Harmonic Suppression (2nd, typ.)

Sideband Spurs (typ.)

-10

-65

dBc

Power Output

1.5±3.5

dBm

Load Impedance

Step Size

Ω

100

KHz

5000

Charge Pump Output Current

Switching Speed (typ., adjacent channel)

Startup Lock Time (typ.)

µΑ

mSec

°C

-30 to 85

Operating Temperature Range

Package Style

PLL-24

POWER SUPPLY REQUIREMENTS

Supply Voltage (Vcc, nom.)

Vdc

Supply Current (Icc, typ.)

All specifications are typical unless otherwise noted and subject to change without notice.

APPLICATION NOTES

• AN-107 : How to Solder Z-COMM VCOs / PLLs

• AN-200 : Mounting and Grounding of Z-COMM PLLs

• AN-201 : PLL Fundamentals

AN-202 : PLL Functional Description

NOTES:

Reference Oscillator Signal: 5 MHz<f_osc<100 MHz

Frequency Synthesizer: National Semiconductor - ADF4106

Page 1

LOW COST - HIGH PERFORMANCE

PHASE LOCKED LOOP

PSA1905A

PAGE 2

VCO TUNING CURVE, typ.

1 9 8 5

1 9 6 5

1 9 4 5

1 9 2 5

1 9 0 5

1 8 8 5

1 8 6 5

1 8 4 5

1 8 2 5

°c

-40

0 . 5

1 . 5

2 . 5

3 . 5

4 . 5

TUNING VOLTAGE (Vdc)

VCO POWER CURVE, typ.

4 . 5

3 . 5

2 . 5

°c

1 . 5

0 . 5

1 8 4 1 1 8 5 5 1 8 6 8 1 8 8 0 1 8 9 2 1 9 0 5 1 9 1 7 1 9 3 0 1 9 4 3 1 9 5 7

FREQUENCY (MHz)

PHYSICAL DIMENSIONS

The inside radius of all 24 half holes at the perimeter of

the board are plated to provide a surface for the

attachment of the PLL Module to the PCB. 16 pads are

for grounding, 8 pads are for signal interface.

The surface of the shield is tin-plated and may be

soldered to. The shield’s base metal is cold-rolled steel.

The ground plane on the bottom side is ground and

attaches to a ground track on the top side of the board

as well as to the shield.

SIDE VIEW

-.025

.000

24 23

22 21 20

PIN 1

.153

.238

.323

.408

.493

.578

.663

Unless otherwise noted all dimensions are in inches.

Unless otherwise noted all tolerances are as follows:

.xxx = ± .010.

BOTTOM

TOP

SEE DETAIL A

P1 RF OUTPUT

P2-4 GROUND

P5 REFERENCE OSCILLATOR INPUT

.816

.841

10 11

P6 GROUND

P7 CLOCK

SEE DETAIL B

P8 DATA

P9 GROUND

P10 LOAD ENABLE

P11 GROUND

P12 LOCK DETECT

P13 VCC

.055

.015

.030

P14 GROUND

P15 GROUND

P16 GROUND

P17 NO CONNECTION

P18-24 GROUND

DETAIL

(TYP)

(8 PLACES)

TABS RANGE:

SEE NOTE 5

DETAIL A

Page 2

Printed in the U.S.A.

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