ZL50233QC [ZARLINK]
4 Channel Voice Echo Cancellor; 4通道语音回声抵消器
| 型号： | ZL50233QC |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | 4 Channel Voice Echo Cancellor |
| 文件： | 总37页 (文件大小：607K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL50233
4 Channel Voice Echo Cancellor
Data Sheet
March 2003
Features
•
Independent multiple channels of echo
Ordering Information
cancellation; from 4 channels of 64ms to 2
channels of 128ms with the ability to mix
channels at 128ms or 64ms in any combination
ZL50233/QCC 100-Pin LQFP
ZL50233/GDC 208-Ball LBGA
•
•
•
•
•
•
Independent Power Down mode for each group of
2 channels for power management
-40°C to +85°C
Fully compliant to ITU-T G.165, G.168 (2000) and
(2002) specifications
•
•
Protection against narrow band signal divergence
and instability in high echo environments
Passed AT&T voice quality testing for carrier
grade echo cancellers.
0 dB to -12 dB level adjusters (3 dB steps) at all
signal ports
Compatible to ST-BUS and GCI interfaces with
2Mb/s serial PCM data
•
•
•
Offset nulling of all PCM channels
10 MHz or 20 MHz master clock operation
PCM coding, µ/A-Law ITU-T G.711 or sign
magnitude
3.3 V I/O pads and 1.8V Logic core operation with
5-Volt tolerant inputs
Per channel Fax/Modem G.164 2100Hz or G.165
2100Hz phase reversal Tone Disable
•
•
IEEE-1149.1 (JTAG) Test Access Port
•
•
•
•
•
Per channel echo canceller parameters control
Transparent data transfer and mute
ZL50232, ZL50233, ZL50234 and ZL50235 have
same pinouts in both LQFP and LBGA packages
Fast reconvergence on echo path changes
Fully programmable convergence speeds
Applications
•
•
Voice over IP network gateways
Voice over ATM, Frame Relay
Patented Advanced Non-Linear Processor with
high quality subjective performance
V
V
V
DD1 (3.3V)
DD2 (1.8V)
ODE
SS
Rin
Sin
Rout
Sout
Parallel
to
Serial
Serial
to
Parallel
Echo Canceller Pool
Group 0
ECA/ECB
Group 1
ECA/ECB
MCLK
Fsel
Note:
Refer to Figure 4
for Echo Canceller
block diagram
PLL
C4i
F0i
RESET
Timing
Unit
Microprocessor Interface
Test Port
DS CS R/W A10-A0 DTA D7-D0 IRQ TMS TDI TDO TCK TRST
Figure 1 - ZL50233 Device Overview
1
ZL50233
Data Sheet
•
T1/E1/J1 multichannel echo cancellation
Wireless base stations
•
•
•
Echo Canceller pools
DCME, satellite and multiplexer system
Description
The ZL50233 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation
conforming to ITU-T G.168 requirements. The ZL50233 architecture contains 2 groups of two echo cancellers (ECA
and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds
echo cancellation. This provides 4 channels of 64 milliseconds to 2 channels of 128 milliseconds echo cancellation
or any combination of the two configurations. The ZL50233 supports ITU-T G.165 and G.164 tone disable
requirements.
TMS
TDI
TDO
TCK
VSS
TRSTB
NC
NC
NC
IC0
IC0
IC0
IC0
VSS
RESETB
IRQB
IC0
IC0
DS
IC0
ZL50233 QC
CS
IC0
R/W
VDD2
(100 pin LQFP)
DTA
C4ib
Foib
Rin
VDD2
D0
D1
Sin
D2
VSS
D3
Rout
Sout
ODE
D4
VSS
NC
D5
D6
D7
V
= 1.8V
V
= 3.3V
DD2
DD1
NC
NC
NC
NC
NC
NC
Figure 2 - 100 Pin LQFP
2
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
A
V
IC0
V
V
IC0
V
Sout
V
IC0
V
IC0
V
V
V
SS
SS
SS
c4i
DD1
SS
DD1
SS
SS
SS
SS
NC
B
C
D
E
F
V
IC0
V
IC0
V
V
V
V
V
V
V
SS
Rin
Rout
Sin
ODE
DD1
SS
SS
SS
DD1
SS
SS
F0i
IC0
IC0
IC0
IC0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
DD1
SS
DD2
SS
DD1
SS
DD1
SS
SS
SS
SS
NC
NC
NC
V
V
V
V
V
V
V
V
V
V
V
A10
DD1
SS
DD1
DD2
DD1
SS
DD1
SS
DD1
SS
SS
DD1
V
V
V
V
IC0
A9
A8
NC
NC
NC
NC
SS
SS
DD1
SS
V
V
IC0
ZL50233GD
V
NC
V
SS
DD1
DD1
DD1
V
V
V
V
V
V
V
V
NC
A7
A6
MCLK
Fsel
DD2
DD2
SS
SS
SS
SS
SS
SS
G
H
J
V
V
V
V
NC
V
V
V
V
V
V
V
V
V
V
SS
DD1
DD2
DD1
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
IC0
NC
NC
NC
NC
A5
A4
DD1
DD2
DD1
IC0 PLLVSSPLLVDD
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
K
L
NC
A3
NC
V
SS
V
V
DD1
V
NC
SS
DD1
V
V
TDI
TMS
A2
A1
A0
V
V
V
SS
DD1
DD1
SS
SS
M
N
V
V
V
DD1
V
V
V
V
V
V
DD1
V
V
V
V
V
SS
TDO TRST
SS
SS
SS
DD1
DD1
DD2
DD2
SS
DD1
DD1
SS
SS
V
TCK
V
SS
V
V
V
V
V
V
V
V
V
V
V
SS
V
V
V
DD1
SS
SS
DD1
SS
DD1
SS
SS
SS
SS
DD1
P
R
V
V
V
IC0
V
VDD1
V
RESET
R/W
DTA
DD1
IRQ
D4
DS
D5
CS
D6
DD1
DD1
DD1
SS
SS
SS
V
V
V
V
V
V
V
V
SS
SS
SS
DD1
SS
SS
DD1
SS
D0
D1
D2
D3
D7
T
- A1 corner is identified by metallized markings.
1
Figure 3 - 208 Ball LBGA
Zarlink Semiconductor Inc.
3
ZL50233
Data Sheet
Pin Description
PIN #
PIN
Name
Description
100 PIN
LQFP
208-Ball LBGA
V
A1, A3,A7,A11, A13,
5, 18, 32, Ground.
SS
A15, A16, B2, B6, B8, 42, 56, 69,
B12, B14, B15, B16, C3,
C5, C7, C9, C11, C12,
C13, C14, C16, D4, D8,
D10, D12, D13, E3, E4,
E14, F13, G3, G4, G7,
G8, G9, G10, H7, H8,
H9, H10, H13, H14, J7,
J8, J9, J10, K7, K8, K9,
K10, K13, K14, L3, L4,
M13, M14, M15, N3, N4,
N5, N7, N9, N11, N13,
P2, P3, P5, P7, P9,P11,
P13, P14, R2, R14,
81, 98
R15, R16, T1, T3, T7,
T10, T14, T16
V
A5, A9, B10, C4, C8, 27, 48, 77, Positive Power Supply V
. Nominally 3.3 Volt.
DD1
DD1
B4, C10, D3, D5, D7,
D9, D11, D14, E13, F3,
F4, F14, H3, H4, J13,
J14, L13, L14, M3, M4,
N6, N8, N10, N14, N15,
P4, P6, P8, P10, P15,
R4, R6, R8, R10, R12,
T5, T12
100
V
C6, D6, J3, J4, N12,
P12, G13, G14
14, 37, 64, Positive Power Supply V
. Nominally 1.8Volts.
DD2
DD2
91
IC0
E15, F15, A12, A10, A6, 7, 41, 43, Internal Connection. These pins must be connected to VSS for
A2, B1, B3, C1, C2, D2, 65, 66, 67, normal operation.
E2, J2, K2, R1
68, 70, 71,
72, 86, 87,
88, 93, 94
NC
A14, C15, D1, D15, E1, 24, 25, 26, No connection. These pins must be left open for normal
F1, G1, G15, H1, H15, 44, 45, 46, operation.
J1, J15, K1,
K15,L1,L15,F2,L2
47, 49, 51,
52, 53, 54,
55, 73, 74,
75, 76, 78,
79, 80, 82,
83, 84, 85,
89, 99, 50
Interrupt Request (Open Drain Output). This output goes low
when an interrupt occurs in any channel. IRQ returns high when
all the interrupts have been read from the Interrupt FIFO
Register. A pull-up resistor (1K typical) is required at this output.
R9
9
IRQ
4
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
Pin Description (continued)
PIN #
PIN
Name
Description
100 PIN
LQFP
208-Ball LBGA
R11
R13
R5
10
11
12
13
Data Strobe (Input). This active low input works in conjunction
with CS to enable the read and write operations.
DS
CS
Chip Select (Input). This active low input is used by a
microprocessor to activate the microprocessor port.
Read/Write (Input). This input controls the direction of the data
bus lines (D7-D0) during a microprocessor access.
R/W
DTA
R7
Data Transfer Acknowledgment (Open Drain Output). This
active low output indicates that a data bus transfer is completed.
A pull-up resistor (1K typical) is required at this output.
D0..D7
T2,T4,T6,T8,T9,T11, 15, 16, 17, Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit
T13,T15
19, 20, 21, bidirectional data bus of the microprocessor port.
22, 23
A0..A10 P16,N16,M16,L16,K16, 28, 29, 30, Address A0 to A10 (Input). These inputs provide the A10 - A0
J16,H16,G16,F16,E16, 31, 33, 34, address lines to the internal registers.
D16
35, 36, 38,
39, 40
ODE
B13
57
Output Drive Enable (Input). This input pin is logically AND’d
with the ODE bit-6 of the Main Control Register. When both ODE
bit and ODE input pin are high, the Rout and Sout ST-BUS
outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the Rout
and Sout ST-BUS outputs are high impedance.
Sout
Rout
Sin
A8
B9
58
59
60
61
62
Send PCM Signal Output (Output). Port 1 TDM data output
streams. Sout pin outputs serial TDM data streams at 2.048 Mb/s
with 4 channels per stream.
Receive PCM Signal Output (Output). Port 2 TDM data output
streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s
with 4 channels per stream.
B11
B7
Send PCM Signal Input (Input). Port 2 TDM data input streams.
Sin pin receives serial TDM data streams at 2.048 Mb/s with 4
channels per stream.
Rin
Receive PCM Signal Input (Input). Port 1 TDM data input
streams. Rin pin receives serial TDM data streams at 2.048 Mb/s
with 4 channels per stream.
B5
Frame Pulse (Input). This input accepts and automatically
identifies frame synchronization signals formatted according to
ST-BUS or GCI interface specifications.
F0i
A4
G2
63
90
Serial Clock (Input). 4.096 MHz serial clock for shifting data
in/out on the serial streams (Rin, Sin, Rout, Sout).
C4i
MCLK
Master Clock (Input). Nominal 10MHz or 20MHz Master Clock
input. May be connected to an asynchronous (relative to frame
signal) clock source.
Zarlink Semiconductor Inc.
5
ZL50233
Data Sheet
Pin Description (continued)
PIN #
PIN
Name
Description
100 PIN
LQFP
208-Ball LBGA
Fsel
H2
K3
92
Frequency select (Input). This input selects the Master Clock
frequency operation. When Fsel pin is low, nominal 20 MHz
Master Clock input must be applied. When Fsel pin is high,
nominal 10 MHz Master Clock input must be applied.
PLLVss1
PLLVss2
97, 95
PLL Ground. Must be connected to V
SS
PLLV
K4
96
1
PLL Power Supply. Must be connected to V
= 1.8V
DD2
DD
TMS
M2
Test Mode Select (3.3V Input). JTAG signal that controls the
state transitions of the TAP controller. This pin is pulled high by
an internal pull-up when not driven.
TDI
M1
N1
2
3
Test Serial Data In (3.3V Input). JTAG serial test instructions
and data are shifted in on this pin. This pin is pulled high by an
internal pull-up when not driven.
TDO
Test Serial Data Out (Output). JTAG serial data is output on this
pin on the falling edge of TCK. This pin is held in high impedance
state when JTAG scan is not enabled.
TCK
P1
N2
4
6
Test Clock (3.3V Input). Provides the clock to the JTAG test
logic.
Test Reset (3.3V Input). Asynchronously initializes the JTAG
TAP controller by putting it in the Test-Logic-Reset state. This pin
should be pulsed low on power-up or held low, to ensure that the
ZL50233 is in the normal functional mode. This pin is pulled by
an internal pull-down when not driven.
TRST
R3
8
Device Reset (Schmitt Trigger Input). An active low resets the
device and puts the ZL50233 into a low-power stand-by mode.
When the RESET pin is returned to logic high and a clock is
applied to the MCLK pin, the device will automatically execute
initialization routines, which preset all the Control and Status
Registers to their default power-up values.
RESET
1.0 Device Overview
The ZL50233 architecture contains 4 echo cancellers divided into 2 groups. Each group has two echo cancellers,
Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or Back-to-
Back configurations. In Normal configuration, a group of echo cancellers provides two channels of 64ms echo
cancellation, which run independently on different channels. In Extended Delay configuration, a group of echo
cancellers achieves 128ms of echo cancellation by cascading the two echo cancellers (A & B). In Back-to-Back
configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both
directions in a single channel, providing full-duplex 64ms echo cancellation.
6
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
Each echo canceller contains the following main elements (see Figure 4).
•
•
•
Adaptive Filter for estimating the echo channel
Subtractor for cancelling the echo
Double-Talk detector for disabling the filter adaptation during periods of double-talk
•
•
•
Path Change detector for fast reconvergence on major echo path changes
Instability Detector to combat instability in very low ERL environments
Patented Advanced Non-Linear Processor for suppression of residual echo, with comfort noise injection
Disable Tone Detectors for detecting valid disable tones at send and receive path inputs
Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals
Offset Null filters for removing the DC component in PCM channels
•
•
•
•
•
•
0 to -12dB level adjusters at all signal ports
Parallel controller interface compatible with Motorola microcontrollers
PCM encoder/decoder compatible with µ/A-Law ITU-T G.711 or Sign-Magnitude coding
Each echo canceller in the ZL50233 has four functional states: Mute, Bypass, Disable Adaptation and Enable
Adaptation. These are explained in the section entitled Echo Canceller Functional States.
0 to -12dB
Level Adjust
Non-Linear
Processor
0 to -12dB
Level Adjust
Offset
Null
Linear/
/A-Law
µ
/A-Law/
Sin
(channel N)
Σ
Sout
(channel N)
µ
Linear
-
Microprocessor
Disable Tone
Detector
MuteS
Interface
Double - Talk
Detector
Path Change
Detector
Instability
Detector
Disable Tone
Detector
Narrow-Band
Detector
MuteR
Offset
Null
Linear/
/A-Law
0 to -12dB
Level Adjust
µ
/A-Law/
0 to -12dB
Level Adjust
Rout
(channel N)
Rin
µ
Linear
(channel N)
Echo Canceller (N), where 0 < N < 3
Programmable Bypass
Figure 4 - Functional Block Diagram
1.1 Adaptive Filter
The adaptive filter adapts to the echo path and generates an estimate of the echo signal. This echo estimate is then
subtracted from Sin. For each group of echo cancellers, the adaptive filter is a 1024 tap FIR adaptive filter which is
divided into two sections. Each section contains 512 taps providing 64ms of echo estimation. In Normal
configuration, the first section is dedicated to channel A and the second section to channel B. In Extended Delay
configuration, both sections are cascaded to provide 128ms of echo estimation in channel A. In Back-to Back
configuration, the first section is used in the receive direction and the second section is used in the transmit
direction for the same channel.
Zarlink Semiconductor Inc.
7
ZL50233
Data Sheet
1.2 Double-Talk Detector
Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously.
When this happens, it is necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter
coefficients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller
continues to cancel echo using the previous converged echo profile. A double-talk condition exists whenever the
relative signal levels of Rin (Lrin) and Sin (Lsin) meet the following condition:
Lsin > Lrin + 20log (DTDT)
10
where DTDT is the Double-Talk Detection Threshold. Lsin and Lrin are signal levels expressed in dBm0.
A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo
return. During these periods, the adaptation process is slowed down but it is not halted. The slow convergence
speed is set using the Slow sub-register in Control Register 4. During slow convergence, the adaptation speed is
Slow
reduced by a factor of 2
relative to normal convergence for non-zero values of Slow. If Slow equals zero,
adaptation is halted completely.
In the G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk
Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to achieve additional guardband, the
DTDT is set internally to 0.5625 (-5 dB).
In some applications the return loss can be higher or lower than 6 dB. The ZL50233 allows the user to change the
detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value
into the DTDT register.
The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:
DTDT
= hex(DTDT
* 32768)
(hex)
(dec)
where 0 < DTDT(dec) < 1
Example:
For DTDT = 0.5625 (-5 dB), the
hexadecimal value becomes
hex(0.5625 * 32768) = 4800
hex
1.3 Path Change Detector
Integrated into the ZL50233 is a Path Change Detector. This permits fast reconvergence when a major change
occurs in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence
is achieved, but at a much slower speed.
The Path Change Detector is activated by setting the PathDet bit in Control Register 3 to “1”. An optional path
clearing feature can be enabled by setting the PathClr bit in Control Register 3 to “1”. With path clearing turned on,
the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon detection
of a major path change.
8
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
1.4 Non-Linear Processor (NLP)
After echo cancellation, there is always a small amount of residual echo which may still be audible. The ZL50233
uses Zarlink’s patented Advanced NLP to remove residual echo signals which have a level lower than the
Adaptive Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin)
reference signal as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR).
TSUP can be calculated by the following equation:
TSUP = Lrin + 20log (NLPTHR)
10
where NLPTHR is the Non-Linear Processor Threshold register value and Lrin is the relative power level expressed
in dBm0. The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the
following equation:
NLPTHR
= hex(NLPTHR
* 32768)
(dec)
(hex)
where 0 < NLPTHR(dec) < 1
When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual signal
by an additional 30 dB. To prevent a perceived decrease in background noise due to the activation of the NLP, a
spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This keeps the
perceived noise level constant. Consequently, the user does not hear the activation and de-activation of the NLP.
The NLP processor can be disabled by setting the NLPDis bit to “1” in Control Register 2.
The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register 1. It should be noted
that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled.
The patented Advanced NLP provides a number of new and improved features over the original NLP found in
previous generation devices. Differences between the Advanced NLP and the original NLP are summarized in
Table 1.
Advanced
Original NLP
Feature
Register or Bit(s)
NLP Default
Value
Default Value
NLP Selection
NLPSel (Control Register 3)
NLRun1 (Control Register 3)
NLRun2 (Control Register 3)
InjCtrl (Control Register 3)
1
1
1
1
0 (feature
not supported)
Reject uncanceled echo as noise
Reject double-talk as noise
0 (feature
not supported)
0 (feature
not supported)
Noise level estimator ramping scheme
0 (feature
not supported)
Noise level ramping rate
Noise level scaling
NLInc (Noise Control)
Noise Scaling
5(hex)
C(hex)
16(hex)
74(hex)
Table 1 - Comparison of NLP Types
The NLPSel bit in Control Register 3 selects which NLP is used. A “1” will select the Advanced NLP, “0” selects the
original NLP. ( See page 23 for Control Register 3 bit description)
The Advanced NLP uses a new noise ramping scheme to quickly and more accurately estimate the background
noise level. The noise ramping method of the original NLP can also be used. The InjCtrl bit in Control Register 3
selects the ramping scheme.
Zarlink Semiconductor Inc.
9
ZL50233
Data Sheet
The NLInc sub-register in Noise Control is used to set the ramping speed. When InjCtrl = 1 (such as with the
Advanced NLP), a lower value will give faster ramping. When InjCtrl = 0 (such as with the original NLP), a higher
value will give faster ramping. NLInc is a 4-bit value, so only values from 0 to F(hex) are valid.
The Noise Scaling register can be used to adjust the relative volume of the comfort noise. Lowering this value will
scale the injected noise level down, conversely, raising the value will scale the comfort noise up. Due to differences
in the noise estimator operation, the Advanced NLP requires a different scaling value than the original NLP.
IMPORTANT NOTE: NLInc and the Noise Scaling register have been pre-programmed with G.168 compliant
values. Changing these values may result in undesirable comfort noise performance!
The Advanced NLP also contains safeguards to prevent double-talk and uncancelled echo from being mistaken for
background noise. These features were not present in the original NLP. They can be disabled by setting the
NLRun1 and NLRun2 bits in Control Register 3 to “0”.
1.5 Disable Tone Detector
The G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz (±21Hz) sine
wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees (± 25 degrees) every
450 ms (±25 ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the
Tone Detector will trigger.
The G.164 recommendation defines the disable tone as a 2100 Hz (+21 Hz) sine wave with a power level between
0 to -31 dBm0. If the disable tone is present for a minimum of 400 ms, with or without phase reversal, the Tone
Detector will trigger.
The ZL50233 has two Tone Detectors per channels (for a total of 8) in order to monitor the occurrence of a valid
disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic
high and an interrupt is generated (i.e. IRQ pin low). Refer to Figure 5 and to the Interrupts section.
Tone Detector
Tone Detector
Rin
Sin
ECA
Status reg
TD bit
Echo Canceller
A
B
Tone Detector
Tone Detector
Rin
Sin
ECB
Status reg
TD bit
Echo Canceller
Figure 5 - Disable Tone Detection
Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to
maintain Tone Detector status (i.e. TD bit high). The Tone Detector status will only release (i.e. TD bit low) if the
signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the
frequency range of 700 Hz to 3400 Hz, for at least 400 ms. Whenever a Tone Detector releases, an interrupt is
generated (i.e. IRQ pin low).
The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2 on a per
channel basis. When the PHDis bit is set to “1”, G.164 tone disable requirements are selected.
In response to a valid disable tone, the echo canceller must be switched from the Enable Adaptation state to the
Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors
internally control the switching between Enable Adaptation and Bypass states. The automatic mode is activated by
setting the AutoTD bit in Control Register 2 to high. In external mode, an external controller is needed to service the
10
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
interrupts and poll the TD bits in the Status Registers. Following the detection of a disable tone (TD bit high) on a
given channel, the external controller must switch the echo canceller from Enable Adaptation to Bypass state.
1.6 Instability Detector
In systems with very low echo channel return loss (ERL), there may be enough feedback in the loop to cause
stability problems in the adaptive filter. This instability can result in variable pitched ringing or oscillation. Should this
ringing occur, the Instability Detector will activate and suppress the oscillations.
The Instability Detector is activated by setting the RingClr bit in Control Register 3 to “1”.
1.7 Narrow Band Signal Detector (NBSD)
Single or dual frequency tones (i.e. DTMF tones) present in the receive input (Rin) of the echo canceller for a
prolonged period of time may cause the Adaptive Filter to diverge. The Narrow Band Signal Detector (NBSD) is
designed to prevent this by detecting single or dual tones of arbitrary frequency, phase, and amplitude. When narrow
band signals are detected, adaptation is halted but the echo canceller continues to cancel echo.
The NBSD will be active regardless of the Echo Canceller functional state. However the NBSD can be disabled by
setting the NBDis bit to “1” in Control Register 2.
1.8 Offset Null Filter
Adaptive filters in general do not operate properly when a DC offset is present at any input. To remove the DC
component, the ZL50233 incorporates Offset Null filters in both Rin and Sin inputs.
The offset null filters can be disabled by setting the HPFDis bit to “1” in Control Register 2.
1.9 Adjustable Level Pads
The ZL50233 provides adjustable level pads at Rin, Rout, Sin and Sout. This setup allows signal strength to be
adjusted both inside and outside the echo path. Each signal level may be independently scaled with anywhere from
0 to -12 dB level, in 3 dB steps. Level values are set using the Gains register.
CAUTION: Gain adjustment can help interface the ZL50233 to a particular system in order to provide optimum echo
cancellation, but it can also degrade performance if not done carefully. Excessive loss may cause low signal levels
and slow convergence. Exercise great care when adjusting these values.
The -12 dB PAD bit in Control Register 1 is still supported as a legacy feature. Setting this bit will provide 12 dB of
attenuation at Rin, and override the values in the Gains register.
1.10 ITU-T G.168 Compliance
The ZL50233 has been certified G.168 (1997), (2000) and (2002) compliant in all 64 ms cancellation modes
(i.e. Normal and Back-to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester.
The ZL50233 has also been tested for G.168 compliance and all voice quality tests at AT&T Labs. The ZL50233
was classified as “carrier grade” echo canceller.
Zarlink Semiconductor Inc.
11
ZL50233
Data Sheet
2.0 Device Configuration
The ZL50233 architecture contains 4 echo cancellers divided into 2 groups. Each group has two echo cancellers
which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB)). They can be set in
three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figures 6, 7, and 8.
2.1 Normal Configuration
In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in
Figure 6, providing 64 milliseconds of echo cancellation in two channels simultaneously.
channel A
Sout
Sin
+
-
echo
path A
Adaptive
Filter (64ms)
channel A
Rout
Rin
PORT2
PORT1
ECA
channel B
+
-
echo
path B
Adaptive
Filter (64ms)
channel B
ECB
Figure 6 - Normal Device Configuration (64ms)
2.2 Back-to-Back Configuration
In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming
from both directions in a single channel providing full-duplex 64ms echo cancellation. See Figure 7. This
configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB
contains zero code. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo
cancellation is required.
Sout
+
Sin
-
echo
path
Adaptive
Filter (64ms)
echo
path
Adaptive
Filter (64ms)
-
+
Rout
Rin
PORT1
PORT2
ECA
ECB
Figure 7 - Back-to-Back Device Configuration (64ms)
12
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
Back-to-Back configuration is selected by writing a “1” into the BBM bit of Control Register 1 for both Echo
Canceller A and Echo Canceller B for a given group of echo canceller. Table 4 shows the 2 groups of 2 cancellers
that can be configured into Back-to-Back.
Examples of Back-to-Back configuration include positioning one group of echo cancellers between a codec and a
transmission device or between two codecs for echo control on analog trunks.
2.3 Extended Delay configuration
In this configuration, the two echo cancellers from the same group are internally cascaded into one 128
milliseconds echo canceller. See Figure 8. This configuration uses only one timeslot on PORT1 and PORT2 and
the second timeslot normally associated with ECB contains quiet code.
channel A
Sin
+
Sout
-
echo
path A
Adaptive Filter
(128 ms)
channel A
Rout
Rin
PORT2
PORT1
ECA
Figure 8 - Extended Delay Configuration (128ms)
Extended Delay configuration is selected by writing a “1” into the ExtDl bit in Echo Canceller A, Control Register 1.
For a given group, only Echo Canceller A, Control Register 1, has the ExtDl bit. For Echo Canceller B Control
Register 1, Bit 0 must always be set to zero.
Table 4 shows the 2 groups of 2 cancellers that can each be configured into 64ms or 128ms echo tail capacity.
3.0 Echo Canceller Functional States
Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation.
3.1 Mute
In Normal and in Extended Delay configurations, writing a “1” into the MuteR bit replaces Rin with quiet code which
is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with
quiet code.
SIGN/
MAGNITUDE
µ-Law
CCITT (G.711)
LINEAR
16 bits
µ-Law
FF
A-Law
D5
2’s complement
A-Law
+Zero
0000
80
hex
hex
hex
hex
(quiet code)
Table 2 - Quiet PCM Code Assignment
Zarlink Semiconductor Inc.
13
ZL50233
Data Sheet
In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes
quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2,
causes quiet code to be transmitted on Sout.
In Extended Delay and in Back-to-Back configurations, MuteR and MuteS bits of Echo Canceller B must always be
“0”. Refer to Figure 4 and to Control Register 2 for bit description.
3.2 Bypass
The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is
selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame
(125 µs) in order to properly clear the filter.
3.3 Disable Adaptation
When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The
adaptation process is halted, however, the echo canceller continues to cancel echo.
3.4 Enable Adaptation
In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller
to model the echo return path characteristics in order to cancel echo. This is the normal operating state.
The echo canceller functions are selected in Control Register 1 and Control Register 2 through four control bits:
MuteS, MuteR, Bypass and AdaptDis. Refer to the Registers Description for details.
4.0 ZL50233 Throughput Delay
The throughput delay of the ZL50233 varies according to the device configuration. For all device configurations, Rin
to Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout and
Sin to Sout paths have a delay of two frames.
5.0 Serial PCM I/O channels
There are two sets of TDM I/O streams, each with channels numbered from 0 to 31. One set of input streams is for
Receive (Rin) channels, and the other set of input streams is for Send (Sin) channels. Likewise, one set of output
streams is for Rout PCM channels, and the other set is for Sout channels. See Figure 9 for channel allocation.
The arrangement and connection of PCM channels to each echo canceller is a 2 port I/O configuration for each set
of PCM Send and Receive channels, as illustrated in Figure 9.
5.1 Serial Data Interface Timing
The ZL50233 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz.
The input and output data rate of the ST-BUS and GCI bus is 2.048 Mb/s.
The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The ZL50233 automatically detects the
presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling
edge of the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of
the way into the bit cell (See Figure 12). In GCI format, every second rising edge of the C4i clock marks the bit
boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 13).
14
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
125 µsec
F0i
ST-BUS
15.625 µsec
F0i
GCI interface
Active
Channels
Rin/Sin
Rout/Sout
0 1 2
3
Disabled Channels with Random Data
Note: Refer to Figure 12 and Figure 13 for timing details.
Figure 9 - ST-BUS and GCI Interface Channel Assignment for 2Mb/s Data Streams
Base
Address +
Base
Echo Canceller A
Echo Canceller B
Address +
MS
LS
MS
LS
Byte
Byte
Byte
Byte
-
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
Control Reg 1
Control Reg 2
Status Reg
-
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
Control Reg 1
Control Reg 2
Status Reg
-
-
-
-
-
-
Reserved
Reserved
-
Flat Delay Reg
Reserved
-
Flat Delay Reg
Reserved
-
-
-
Decay Step Size Reg
Decay Step Number
Control Reg 3
Control Reg 4
Noise Scaling
Noise Control
Rin Peak Detect Reg
Sin Peak Detect Reg
Error Peak Detect Reg
Reserved
-
Decay Step Size Reg
Decay Step Number
Control Reg 3
Control Reg 4
Noise Scaling
Noise Control
Rin Peak Detect Reg
Sin Peak Detect Reg
Error Peak Detect Reg
Reserved
-
-
-
-
-
-
-
-
-
-
0Dh
0Fh
11h
13h
15h
17h
19h
1Bh
1Dh
1Fh
2Dh
2Fh
31h
33h
35h
37h
39h
3Bh
3Dh
3Fh
DTDT Reg
DTDT Reg
Reserved
Reserved
NLPTHR
NLPTHR
Step Size, MU
Gains
Step Size, MU
Gains
Reserved
Reserved
Table 3 - Memory Mapping of Per Channel Control and Status Registers
Zarlink Semiconductor Inc.
15
ZL50233
Data Sheet
6.0 Memory Mapped Control and Status registers
Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual
ported memory is mapped into segments on a “per channel” basis to monitor and control each individual echo
canceller and associated PCM channels. For example, in Normal configuration, echo canceller #3 makes use of
Echo Canceller B from group 2. It occupies the internal address space from 060
channel #3 on all serial PCM I/O streams.
to 07F
and interfaces to PCM
hex
hex
As illustrated in Table 3, the “per channel” registers provide independent control and status bits for each echo
canceller. Figure 10 shows the memory map of the control/status register blocks for all echo cancellers.
When Extended Delay or Back-to-Back configuration is selected, Control Register 1 of ECA and ECB and Control
Register 2 of the selected group of echo cancellers require special care. Refer to the Register description section.
Table 4 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended
Delay or Back-to-Back.
6.1 Normal Configuration
For a given group (group 0 to 1), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B,
channels 2 and 3 are active.
Group
Channels
0
1
0, 1
2, 3
Table 4 - Group and Channel allocation
6.2 Extended Delay Configuration
For a given group (group 0 or 1), only one PCM I/O channel is active (Echo Canceller A) and the other channel
carries quiet code. For example, group 0, Echo Canceller A (Channel 0) will be active and Echo Canceller B
(Channel 1) will carry quiet code.
6.3 Back-to-Back Configuration
For a given group (group 0 or 1), only one PCM I/O channel is active (Echo Canceller A) and the other channel
carries quiet code. For example, group 1, Echo Canceller A (Channel 2) will be active and Echo Canceller B
(Channel 3) will carry quiet code.
0000h --> 001Fh
0020h --> 003Fh
Channel 0, ECA Ctrl/Stat Registers
Channel 1, ECB Ctrl/Stat Registers
Group 0
Echo
Cancellers
Registers
0040h --> 005Fh
0060h --> 007Fh
Channel 2, ECA Ctrl/Stat Registers
Channel 3, ECB Ctrl/Stat Registers
Group 1
Echo
Cancellers
Registers
0400h --> 0407h
0410h
Main Control Registers <7:0>
Interrupt FIFO Register
Test Register
0411h
0412h ---> FFFFh
Reserved Test Register
Figure 10 - Memory Mapping
16
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
6.4 Power Up Sequence
On power up, the RESET pin must be held low for 100 µs. Forcing the RESET pin low will put the ZL50233 in power
down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated. The 8
Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero.
When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500 µs for the PLL to
lock. C4i and F0i can be active during this period. Once the PLL has locked, the user must power up the 2 groups
of echo cancellers individually, by writing a “1” into the PWUP bit in each group of echo canceller’s Main Control
Register.
For each group of echo cancellers, when the PWUP bit toggles from zero to one, echo cancellers A and B execute
their initialization routine. The initialization routine sets their registers, Base Address+00
to Base Address+3F
,
hex
hex
to the default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization
routine to execute properly.
Once the initialization routine is executed, the user can set the per channel Control Registers, Base Address+00
hex
to Base Address+3F , for the specific application.
hex
6.5 Power management
Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their
respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are
bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section
for description.
The typical power consumption can be calculated with the following equation:
P
= 9 * Nb_of_groups + 3.6, in mW
C
where 0 ≤ Nb_of_groups ≤ 2.
6.6 Call Initialization
To ensure fast initial convergence on a new call, it is important to clear the Adaptive Filter. This is done by putting
the echo canceller in bypass mode for at least one frame (125 µs) and then enabling adaptation.
Since the Narrow Band Detector is “ON” regardless of the functional state of Echo Canceller it is recommended that
the Echo cancellers are reset before any call progress tones are applied.
6.7 Interrupts
The ZL50233 provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone
Disable is detected and released.
Although the ZL50233 may be configured to react automatically to tone disable status on any input PCM voice
channels, the user may want for the external HOST processor to respond to Tone Disable information in an
appropriate application-specific manner.
Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt
when a Tone Disable releases.
Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory
containing the channel number of the echo canceller that has generated the interrupt.
All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this
FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will
toggle low for each pending interrupt.
Zarlink Semiconductor Inc.
17
ZL50233
Data Sheet
After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel
Status Register can be read from internal memory to determine the cause of the interrupt (see Table 3 for address
mapping of Status register). The TD bit indicates the presence of a Tone Disable.
The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the ZL50233. To provide more flexibility, the
MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<3:0> allow Tone Disable to be masked or
unmasked from generating an interrupt on a per channel basis. Refer to the Registers Description section.
7.0 JTAG Support
The ZL50233 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a
design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is
controlled by an Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only.
7.1 Test Access Port (TAP)
The TAP provides access to many test functions of the ZL50233. It consists of four input pins and one output pin.
The following pins are found on the TAP.
•
•
•
Test Clock Input (TCK)
The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus
remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrent with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test
operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to
V
when it is not driven from an external source.
DD1
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to V
when it is not driven from an external source.
DD1
•
•
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDO. The data from the TDO is clocked on the
falling edge of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is
set to a high impedance state.
Test Reset (TRST)
This pin is used to reset the JTAG scan structure. This pin is internally pulled to V
.
SS
7.2 Instruction Register
In accordance with the IEEE 1149.1 standard, the ZL50233 uses public instructions. The JTAG Interface contains a
3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP
Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to
select the test data register that will operate while the instruction is current, and to define the serial test data register
path, which is used to shift data between TDI and TDO during data register scanning.
18
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
7.3 Test Data Registers
As specified in IEEE 1149.1, the ZL50233 JTAG Interface contains three test data registers:
•
Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path
around the boundary of the ZL50233 core logic.
•
•
Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO.
Device Identification register
The Device Identification register provides access to the following encoded information:
device version number, part number and manufacturer's name.
8.0 Register Description
Echo Canceller A (ECA): Control Register 1
Power-up 00
R/W Address: 00
+ Base Address
hex
hex
Bit 7
Reset
Bit 6
INJDis
Bit 5
BBM
Bit 4
PAD
Bit 3
Bypass
Bit 2
AdpDis
Bit 1
0
Bit 0
ExtDI
Functional Description of Register Bits
Reset
When high, the power-up initialization is executed. This presets all register bits including this bit
and clears the Adaptive Filter coefficients.
INJDis
BBM
When high, the noise injection process is disabled. When low noise injection is enabled.
When high, the Back to Back configuration is enabled. When low, the Normal configuration is
enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time. Always
set both BBM bits of the two echo cancellers (Control Register 1) of the same group to the same
logic value to avoid conflict.
PAD
When high, 12dB of attenuation is inserted into the Rin to Rout path. When low, the Gains register
controls the signal levels.
Bypass
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive Filter
coefficients are set to zero and the filter adaptation is stopped. When low, output data on both
Sout and Rout is a function of the echo canceller algorithm.
AdpDis
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
0
ExtDl
When high, Echo Cancellers A and B of the same group are internally cascaded into one 128ms
echo canceller. When low, Echo Cancellers A and B of the same group operate independently.
Zarlink Semiconductor Inc.
19
ZL50233
Data Sheet
Echo Canceller B (ECB): Control Register 1
Power-up 02
R/W Address: 20
+ Base Address
hex
hex
Bit 7
Reset
Bit 6
INJDis
Bit 5
BBM
Bit 4
PAD
Bit 3
Bypass
Bit 2
AdpDis
Bit 1
1
Bit 0
0
Functional Description of Register Bits
Reset
When high, the power-up initialization is executed which presets all register bits including this bit
and clears the Adaptive Filter coefficients.
INJDis
BBM
When high, the noise injection process is disabled. When low, noise injection is enabled.
When high, the Back to Back configuration is enabled. When low, the Normal configuration is
enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time. Always
set both BBM bits of the two echo cancellers (Control Register 1) of the same group to the same
logic value to avoid conflict.
PAD
When high, 12dB of attenuation is inserted into the Rin to Rout path. When low, the Gains register
controls the signal levels.
Bypass
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive Filter
coefficients are set to zero and the filter adaptation is stopped. When low, output data on both
Sout and Rout is a function of the echo canceller algorithm.
AdpDis
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
Control Register 1 (Echo Canceller B) Bit 0 is a reserved bit and should be written “0”.
1
0
R/W Address:
hex
ECA: Control Register 2
01
21
+ Base Address
Power-up
00
hex
R/W Address:
+ Base Address
ECB: Control Register 2
hex
Bit 7
TDis
Bit 6
PHDis
Bit 5
NLPDis
Bit 4
AutoTD
Bit 3
NBDis
Bit 2
HPFDis
Bit 1
MuteS
Bit 0
MuteR
Functional Description of Register Bits
TDis
When high, tone detection is disabled. When low, tone detection is enabled. When both Echo
Cancellers A and B TDis bits are high, Tone Disable processors are disabled entirely and are put
into Power Down mode.
PHDis
When high, the tone detectors will trigger upon the presence of a 2100 Hz tone regardless of the
presence/absence of periodic phase reversals. When low, the tone detectors will trigger only upon
the presence of a 2100 Hz tone with periodic phase reversals.
NLPDis
AutoTD
When high, the non-linear processor is disabled. When low, the non-linear processors function
normally. Useful for G.165 conformance testing.
When high, the echo canceller puts itself in Bypass mode when the tone detectors detect the
presence of 2100 Hz tone. See PHDis for qualification of 2100 Hz tones.
When low, the echo canceller algorithm will remain operational regardless of the state of the 2100
Hz tone detectors.
NBDis
HPFDis
When high, the narrow-band detector is disabled. When low, the narrow-band detector is enabled.
When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths. When low,
the offset nulling filters are active and will remove DC offsets on PCM input signals.
When high, data on Sout is muted to quiet code. When low, Sout carries active code.
When high, data on Rout is muted to quiet code. When low, Rout carries active code.
MuteS
MuteR
Note: In order to correctly write to Control Register 1 and 2 of ECB, it is necessary to write the data twice to the register, one
immediately after another. The two writes must be separated by at least 350ns and no more than 20us.
20
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
R/W Address:
+ Base Address
ECA: Status Register
ECB: Status Register
02
22
hex
Power-up
00
hex
R/W Address:
+ Base Address
hex
Bit 7
Reserve
Bit 6
TD
Bit 5
DTDet
Bit 4
Reserve
Bit 3
Reserve
Bit 2
Reserve
Bit 1
TDG
Bit 0
NB
Functional Description of Register Bits
Reserve
TD
Reserved bit.
Logic high indicates the presence of a 2100Hz tone.
DTDet
Logic high indicates the presence of a double-talk condition.
Reserve
Reserved bit.
Reserve
Reserve
TDG
Reserved bit.
Reserved bit.
Tone detection status bit gated with the AutoTD bit. (Control Register 2)
Logic high indicates that AutoTD has been enabled and the tone detector has detected the
presence of a 2100Hz tone.
NB
Logic high indicates the presence of a narrow-band signal on Rin.
R/W Address:
hex
ECA: Flat Delay Register (FD)
04
24
+ Base Address
Power-up
00
hex
R/W Address:
+ Base Address
ECB: Flat Delay Register (FD)
hex
Bit 7
FD7
Bit 6
FD6
Bit 5
FD5
Bit 4
FD4
Bit 3
FD3
Bit 2
FD2
Bit 1
FD1
Bit 0
FD0
R/W Address:
+ Base Address
ECA: Decay Step Size Register (NS)
ECB: Decay Step Size Register (NS)
07
hex
Power-up
00
hex
R/W Address:
27 + Base Address
hex
Bit 7
NS7
Bit 6
NS6
Bit 5
NS5
Bit 4
NS4
Bit 3
NS3
Bit 2
NS2
Bit 1
NS1
Bit 0
NS0
R/W Address:
+ Base Address
ECA: Decay Step Size Control Register (NS)
ECB: Decay Step Size Control Register (NS)
06
26
hex
Power-up
00
hex
R/W Address:
+ Base Address
hex
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
SSC2
Bit 1
SSC1
Bit 0
SSC0
Note: Bits marked with “0” are reserved bits and should be written “0”
Zarlink Semiconductor Inc.
21
ZL50233
Data Sheet
Amplitude of MU
FIR Filter Length (512 or 1024 taps)
1.0
Step Size (SS)
Flat Delay (FD
)
7-0
-16
2
Time
Number of Steps (NS
)
7-0
Figure 11 - The MU Profile
9.0 Functional Description of Register Bits
The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS
adaptation step-size (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the
performance of the echo canceller to be optimized for specific applications. For example, if the characteristic of the
echo response is known to have a flat delay of several milliseconds and a roughly exponential decay of the echo
impulse response, then the MU profile can be programmed to approximate this expected impulse response thereby
improving the convergence characteristics of the Adaptive Filter. Note that in the following register descriptions, one
tap is equivalent to 125µs (64ms/512 taps).
-16
FD
Flat Delay: This register defines the flat delay of the MU profile, (i.e., where the MU value is 2 ). The
7-0
-16
delay is defined as FD x 8 taps. For example; If FD = 5, then MU=2 for the first 40 taps of the
7-0
7-0
echo canceller FIR filter. The valid range of FD is: 0 ≤ FD ≤ 64 in normal mode and 0 ≤ FD ≤ 128
7-0
7-0
7-0
in extended-delay mode. The default value of FD is zero.
7-0
SSC
Decay Step Size Control: This register controls the step size (SS) to be used during the exponential
2-0
decay of MU. The decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR
SSC
filter, where SS = 4 x2
2-0. For example; If SSC = 4, then MU is reduced by a factor of 2 every 64
2-0
taps of the FIR filter. The default value of SSC is 04
.
hex
2-0
NS
Decay Step Number: This register defines the number of steps to be used for the decay of MU where
each step has a period of SS taps (see SSC ). The start of the exponential decay is defined as: Filter
7-0
2-0
SSC2-0
Length (512 or 1024) - [Decay Step Number (NS ) x Step Size (SS)] where SS = 4 x2
.
7-0
For example; If NS =4 and SSC =4, then the exponential decay start value is 512 - [NS x SS] =
7-0
2-0
7-0
4
512 - [4 x (4x2 )] = 256 taps for a filter length of 512 taps.
22
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
R/W Address:
+ Base Address
ECA: Control Register 3
ECB: Control Register 3
08
28
hex
Power-up
FB
hex
R/W Address:
+ Base Address
hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NLRun2
InjCtrl
NLRun1
RingClr
Reserve
PathClr
PathDet
NLPSel
Functional Description of Register Bits
NLRun2
When high, the comfort noise level estimator actively rejects double-talk as being background
noise. When low, the noise level estimator makes no such distinction.
Selects which noise ramping scheme is used. See Table below.
InjCtrl
NLRun1
When high, the comfort noise level estimator actively rejects uncancelled echo as being
background noise. When low, the noise level estimator makes no such distinction.
RingClr
When high, the instability detector is activated. When low, the instability detector is disabled.
Reserve
PathClr
Reserved bit. Must always be set to one for normal operation.
When high, the current echo channel estimate will be cleared and the echo canceller will enter fast
convergence mode upon detection of a path change. When low, the echo canceller will keep the
current path estimate but revert to fast convergence mode upon detection of a path change. Note:
this bit is ignored if PathDet is low.
PathDet
NLPSel
When high, the path change detector is activated. When low, the path change detector is disabled.
When high, the Advanced NLP is selected. When low, the original NLP is selected. See Table 1 on
page 9.
R/W Address:
hex
ECA: Control Register 4
09
29
+ Base Address
Power-up
54hex
R/W Address:
+ Base Address
ECB: Control Register 4
hex
Bit 7
0
Bit 6
SD2
Bit 5
SD1
Bit 4
SD0
Bit 3
0
Bit 2
Slow2
Bit 1
Slow1
Bit 0
Slow0
Functional Description of Register Bits
0
Must be set to zero.
These three bits (SD2,SD1,SD0) control how long the echo canceller remains in a fast
SupDec
convergence state following a path change, Reset or Bypass operation. A value of zero will keep
the echo canceller in fast convergence indefinitely.
0
Must be set to zero.
Slow
Slow convergence mode speed adjustment.(Bits Slow2, Slow1,Slow0)
For Slow = 1, 2, ..., 7, slow convergence speed is reduced by a factor of 2
normal adaptation.
Slow
as compared to
Flow Slow = 0, no adaptation occurs during slow convergence.
Zarlink Semiconductor Inc.
23
ZL50233
Data Sheet
R/W Address:
+ Base Address
ECA: Noise Scaling (NS)
ECB: Noise Scaling (NS)
Power-up
16
0A
2A
hex
hex
R/W Address:
+ Base Address
hex
Bit 7
NS7
Bit 6
NS6
Bit 5
NS5
Bit 4
NS4
Bit 3
NS3
Bit 2
NS2
Bit 1
NS1
Bit 0
NS0
Functional Description of Register Bits
This register is used to scale the comfort noise up or down. Larger values will increase the relative level of
comfort noise. The default value of 16 will provide G.168 compliance with the Advanced NLP. A value of 74
hex
hex
is recommended if the original NLP is used.
R/W Address:
+ Base Address
ECA: Noise Control
ECB: Noise Control
0B
2B
hex
Power-up
45
hex
R/W Address:
+ Base Address
hex
Bit 7
Reserve
Bit 6
Reserve
Bit 5
Reserve
Bit 4
Reserve
Bit 3
NLInc3
Bit 2
NLInc2
Bit 1
NLInc1
Bit 0
NLInc0
Functional Description of Register Bits
Reserved bits. Must be set to 4 for normal operation.
Noise level estimator ramping rate. When InjCtrl = 1, a lower value will give faster ramping.
When InjCtrl = 0, a higher value will give faster ramping. The default value of 5 will provide
Reserve
NLInc
hex
hex
G.168 compliance with InjCtrl = 1. A value of C
is recommended if InjCtrl = 0.
hex
R/W Address:
+ Base Address
ECA: Rin Peak Detect Register 2 (RP)
ECB: Rin Peak Detect Register 2 (RP)
0D
2D
hex
Power-up
N/A
R/W Address:
+ Base Address
hex
Bit 7
RP15
Bit 6
RP14
Bit 5
RP13
Bit 4
RP12
Bit 3
RP11
Bit 2
RP10
Bit 1
RP9
Bit 0
RP8
Power-up
N/A
ECA: Rin Peak Detect Register 1 (RP)
ECB: Rin Peak Detect Register 1 (RP)
R/W Address:
+ Base Address
R/W Address:
0C
2C
hex
+ Base Address
hex
Bit 7
RP7
Bit 6
RP6
Bit 5
RP5
Bit 4
RP4
Bit 3
RP3
Bit 2
RP2
Bit 1
RP1
Bit 0
RP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the receive in (Rin) peak signal level. The information is
in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high
byte is in Register 2 and the low byte is in Register 1.
24
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
R/W Address:
+ Base Address
ECA: Sin Peak Detect Register 2 (SP)
ECB: Sin Peak Detect Register 2 (SP)
0F
2F
hex
Power-up
N/A
R/W Address:
+ Base Address
hex
Bit 7
SP15
Bit 6
SP14
Bit 5
SP13
Bit 4
SP12
Bit 3
SP11
Bit 2
SP10
Bit 1
SP9
Bit 0
SP8
Power-up
N/A
ECA: Sin Peak Detect Register 1 (SP)
ECB: Sin Peak Detect Register 1 (SP)
R/W Address:
+ Base Address
R/W Address:
0E
2E
hex
+ Base Address
hex
Bit 7
SP7
Bit 6
SP6
Bit 5
SP5
Bit 4
SP4
Bit 3
SP3
Bit 2
SP2
Bit 1
SP1
Bit 0
SP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the send in (Sin) peak signal level. The information is in
16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte
is in Register 2 and the low byte is in Register 1.
R/W Address:
hex
ECA: Error Peak Detect Register 2 (EP)
11
31
+ Base Address
Power-up
N/A
R/W Address:
ECB: Error Peak Detect Register 2 (EP)
+ Base Address
hex
Bit 7
EP15
Bit 6
EP14
Bit 5
EP13
Bit 4
EP12
Bit 3
EP11
Bit 2
EP10
Bit 1
EP9
Bit 0
EP8
R/W Address:
+ Base Address
ECA: Error Peak Detect Register 1 (EP)
ECB: Error Peak Detect Register 1 (EP)
10
30
hex
Power-up
N/A
R/W Address:
+ Base Address
hex
Bit 7
EP7
Bit 6
EP6
Bit 5
EP5
Bit 4
EP4
Bit 3
EP3
Bit 2
EP2
Bit 1
EP1
Bit 0
EP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the error signal peak level. The information is in 16-bit
2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in
Register 2 and the low byte is in Register 1.
Zarlink Semiconductor Inc.
25
ZL50233
Data Sheet
R/W Address:
+ Base Address
ECA: Double-Talk Detection Threshold Register 2
ECB: Double-Talk Detection Threshold Register 2
15
35
hex
Power-up
48
hex
R/W Address:
+ Base Address
hex
Bit 7
Bit 6
Bit 5
DTDT13
Bit 4
DTDT12
Bit 3
DTDT11
Bit 2
DTDT10
Bit 1
DTDT9
Bit 0
DTDT8
DTDT15 DTDT14
R/W Address:
hex
ECA: Double-Talk Detection Threshold Register 1
ECB: Double-Talk Detection Threshold Register 1
14
34
+ Base Address
Power-up
00
hex
R/W Address:
+ Base Address
hex
Bit 7
DTDT7
Bit 6
DTDT6
Bit 5
DTDT5
Bit 4
DTDT4
Bit 3
DTDT3
Bit 2
DTDT2
Bit 1
DTDT1
Bit 0
DTDT0
Functional Description of Register Bits
This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s
complement linear value defaults to 4800 = 0.5625 or -5 dB. The maximum value is 7FFF
= 0.9999 or 0
hex
hex
dB. The high byte is in Register 2 and the low byte is in Register 1.
ECA: Non-Linear Processor Threshold Register 2
(NLPTHR)
R/W Address:
+ Base Address
19
39
hex
Power-up
0C
hex
ECB: Non-Linear Processor Threshold Register 2
(NLPTHR)
R/W Address:
+ Base Address
hex
Bit 7
NLP15
Bit 6
NLP14
Bit 5
NLP13
Bit 4
NLP12
Bit 3
NLP11
Bit 2
NLP10
Bit 1
NLP9
Bit 0
NLP8
ECA: Non-Linear Processor Threshold Register 1
(NLPTHR)
R/W Address:
+ Base Address
18
38
hex
Power-up
E0
ECB: Non-Linear Processor Threshold Register 1
(NLPTHR)
hex
R/W Address:
+ Base Address
hex
Bit 7
NLP7
Bit 6
NLP6
Bit 5
NLP5
Bit 4
NLP4
Bit 3
NLP3
Bit 2
NLP2
Bit 1
NLP1
Bit 0
NLP0
Functional Description of Register Bits
This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit
2’s complement linear value defaults to 0CE0 = 0.1 or -20.0dB. The maximum value is 7FFF = 0.9999 or 0
hex
hex
dB. The high byte is in Register 2 and the low byte is in Register 1.
26
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
R/W Address:
+ Base Address
ECA: Adaptation Step Size Register 2 (MU)
ECB: Adaptation Step Size Register 2 (MU)
1B
3B
hex
Power-up
40
hex
R/W Address:
+ Base Address
hex
Bit 7
MU15
Bit 6
MU14
Bit 5
MU13
Bit 4
MU12
Bit 3
MU11
Bit 2
MU10
Bit 1
MU9
Bit 0
MU8
R/W Address:
+ Base Address
ECA: Adaptation Step Size Register 1 (MU)
ECB: Adaptation Step Size Register 1 (MU)
1A
3A
hex
Power-up
00
hex
R/W Address:
+ Base Address
hex
Bit 7
MU7
Bit 6
MU6
Bit 5
MU5
Bit 4
MU4
Bit 3
MU3
Bit 2
MU2
Bit 1
MU1
Bit 0
MU0
Functional Description of Register Bits
This register allows the user to program the level of MU. MU is a 16 bit 2’s complement value which defaults to
4000 = 1.0 The maximum value is 7FFF
or 1.9999 decimal. The high byte is in Register 2 and the low byte
hex
hex
is in Register 1.
R/W Address:
hex
ECA: Gains Register 2
ECB: Gains Register 2
1D
3D
+ Base Address
Power-up
44
hex
R/W Address:
+ Base Address
hex
Bit 7
0
Bit 6
Rin2
Bit 5
Rin1
Bit 4
Rin0
Bit 3
0
Bit 2
Rout2
Bit 1
Rout1
Bit 0
Rout0
R/W Address:
+ Base Address
ECA: Gains Register 1
ECB: Gains Register 1
1C
3C
hex
Power-up
44
hex
R/W Address:
+ Base Address
hex
Bit 7
0
Bit 6
Sin2
Bit 5
Sin1
Bit 4
Sin0
Bit 3
0
Bit 2
Sout2
Bit 1
Sout1
Bit 0
Sout0
Functional Description of Register Bits
This register is used to select gain values on RIN, ROUT, SIN and SOUT. Gains has the following structure:
RIN ROUT SIN SOUT
Gains = 0xxx 0xxx 0xxx 0xxx
= 0100 0100 0100 0100 (4444 ) default
hex
Gains is split into four groups of four bits. Each group maps to a different signal port (as indicated above), and
has three gain bits. The following table indicates how these gain bits are used:
Bit2 Bit1 Bit0
Gain Level
0 dB (default)
-3 dB
-6 dB
-9 dB
1
0
1
1
0
0
0
1
0
1
0
0
0
0
0
-12 dB
Note that the -12 dB PAD bit in Control Register 1 provides 12 dB of attenuation in the Rin to Rout path, and will
override the settings in Gains.
Zarlink Semiconductor Inc.
27
ZL50233
Data Sheet
Main Control Register 0 (EC Group 0)
R/W Address: 400
Power-up 00
hex
hex
Bit 7
WR_all
Bit 6
ODE
Bit 5
MIRQ
Bit 4
MTDBI
Bit 3
MTDAI
Bit 2
Format
Bit 1
Law
Bit 0
PWUP
Functional Description of Register Bits
Write all control bit: When high, Group 0 and 1 Echo Cancellers Registers are mapped into
0000 to 0003F which is Group 0 address mapping. Useful to initialize the 2 Groups of Echo
Cancellers as per Group 0. When low, address mapping is per Figure 10. Note: Only the Main
Control Register 0 has the WR_all bit
WR_all
ODE
hex
hex
Output Data Enable: This control bit is logically AND’d with the ODE input pin. When both ODE bit
and ODE input pin are high, the Rout and Sout outputs are enabled. When the ODE bit is low or
the ODE input pin is low, the Rout and Sout outputs are high impedance. Note: Only the Main
Control Register 0 has the ODE bit.
Mask Interrupt: When high, all the interrupts from the Tone Detectors output are masked. The Tone
Detectors operate as specified in their Echo Canceller B, Control Register 2.
When low, the Tone Detectors Interrupts are active.
MIRQ
Note: Only the Main Control Register 0 has the MIRQ bit.
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control
Register 2. When low, the Tone Detector B Interrupt is active.
MTDBI
MTDAI
Format
Law
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control
Register 2. When low, the Tone Detector A Interrupt is active.
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept ITU-T
(G.711) PCM code. When low, both Echo Cancellers A and B for a given group, accept sign-
magnitude PCM code.
A/µ Law: When high, both Echo Cancellers A and B for a given group, accept A-Law companded
PCM code. When low, both Echo Cancellers A and B for a given group, accept µ-Law companded
PCM code.
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are
active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed
in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout
and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the
echo canceller A and B execute their initialization routine which presets their registers, Base
PWUP
Address+00
to Base Address+3F , to default power up value and clears the Adaptive Filter
hex
hex
coefficients. Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for their
specific application.
28
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
Main Control Register 1 (EC Group 1)
Power-up 00hex
R/W Address: 401
hex
Bit 7
Unused
Bit 6
Unused
Bit 5
Unused
Bit 4
MTDBI
Bit 3
MTDAI
Bit 2
Format
Bit 1
Law
Bit 0
PWUP
Functional Description of Register Bits
Unused
MTDBI
Unused Bits.
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller
B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2.
When low, the Tone Detector B Interrupt is active.
MTDAI
Format
Law
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller
A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2.
When low, the Tone Detector A Interrupt is active.
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select ITU-T (G.711)
PCM code. When low, both Echo Cancellers A and B for a given group, select sign-magnitude PCM
code.
A/µ Law: When high, both Echo Cancellers A and B for a given group, select A-Law companded
PCM code. When low, both Echo Cancellers A and B for a given group, select µ-Law companded
PCM code.
PWUP
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are
active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed
in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout
and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the
echo cancellers A and B execute their initialization routine which presets their registers, Base
Address+00
to Base Address+3F , to default Reset Value and clears the Adaptive Filter
hex
hex
coefficients. Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for their specific
application.
Interrupt FIFO Register
Power-up 00hex
R/W Address: 410
hex
Bit 7
IRQ
Bit 6
Unused
Bit 5
Unused
Bit 4
I4
Bit 3
I3
Bit 2
I2
Bit 1
I1
Bit 0
I0
Functional Description of Register Bits
IRQ
Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register is
read. Logic Low indicates that no interrupt is pending and the FIFO is empty.
Unused bit.
Unused
Unused
I<4:0>
Unused bit.
I<4:0> binary code indicates the channel number at which a Tone Detector state change has
occurred. Note: Whenever a Tone Disable is detected or released, an interrupt is generated.
Zarlink Semiconductor Inc.
29
ZL50233
Data Sheet
Absolute Maximum Ratings*
Parameter
I/O Supply Voltage (V
Symbol
Min
Max
Units
1
2
3
4
5
6
7
)
V
-0.5
-0.5
5.0
2.5
V
V
DD1
DD_IO
Core Supply Voltage (V
)
V
DD_CORE
DD2
Input Voltage
V
V
V
V
- 0.5
V
+0.5
V
V
I3
I5
o
SS
SS
DD1
Input Voltage on any 5V Tolerant I/O pins
Continuous Current at digital outputs
Package power dissipation
- 0.3
7.0
I
20
2
mA
W
P
T
D
Storage temperature
-55
150
°C
S
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
.
Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated
‡
Characteristics
Operating Temperature
I/O Supply Voltage (VDD_IO
Core Supply Voltage (VDD_CORE
Sym
Min
Typ
Max
Units
1
2
3
4
5
6
TOP
VDD1
VDD2
VIH3
VIH5
VIL
-40
3.0
1.6
+85
3.6
2.0
°C
V
)
3.3
1.8
)
V
Input High Voltage on 3.3V tolerant I/O
Input High Voltage on 5V tolerant I/O pins
Input Low Voltage
0.7V
V
V
DD1
DD1
DD1
0.7V
5.5
0.3V
V
V
DD1
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing
DC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated.
ss
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
Static Supply Current
I
250
µA RESET = 0
CC
1
IDD_IO (V
= 3.3V)
I
5
mA All 4 channels active
DD1
DD_IO
IDD_CORE (V
= 1.8V)
I
13
40
mA All 4 channels active
DD2
DD_CORE
2
3
4
5
Power Consumption
Input High Voltage
Input Low Voltage
P
mW All 4 channels active
C
I
N
P
U
T
S
V
0.7V
V
V
IH
DD1
V
0.3V
DD1
IL
Input Leakage
Input Leakage on Pullup
Input Leakage on Pulldown
I /I
10
-55
65
µA VIN=V to V
or 5.5V
IH IL
SS
DD1
I
I
-30
30
µA VIN=V
µA VIN=V
LU
LD
SS
DD1
See Note 1
6
7
Input Pin Capacitance
Output High Voltage
C
10
pF
V
I
O
U
T
P
U
T
V
0.8V
I
I
= 12 mA
= 12 mA
OH
DD1
OH
8
Output Low Voltage
V
0.4
10
10
V
OL
OZ
OL
9
High Impedance Leakage
Output Pin Capacitance
I
µA VIN=V to 5.5V
SS
S
10
C
pF
O
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, V =3.3V and are for design aid only: not guaranteed and not subject to production testing.
DD1
* Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (VIN).
30
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
AC Electrical Characteristics† - Timing Parameter Measurement Voltage Levels
- Voltages are with respect to ground (V ) unless otherwise stated.
ss
Characteristics
CMOS Threshold
Sym
Level
Units
Conditions
1
2
3
V
0.5V
V
V
V
TT
DD1
DD1
DD1
CMOS Rise/Fall Threshold Voltage High
CMOS Rise/Fall Threshold Voltage Low
V
0.7V
0.3V
HM
V
LM
† Characteristics are over recommended operating conditions unless otherwise stated
AC Electrical Characteristics† - Frame Pulse and C4i
‡
Characteristic
Sym
Min
Typ
Max
Units
Notes
tFPW
1
2
3
Frame pulse width (ST-BUS, GCI)
20
2*
tCP-20
ns
tFPS
Frame Pulse Setup time before
C4i falling (ST-BUS or GCI)
10
10
122
122
150
150
ns
ns
tFPH
Frame Pulse Hold Time from C4i
falling (ST-BUS or GCI)
tCP
tCH
tCL
t , t
4
5
6
7
190
85
244
300
150
150
10
ns
ns
ns
ns
C4i Period
C4i Pulse Width High
C4i Pulse Width Low
C4i Rise/Fall Time
85
r
f
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, V = 3.3V and for design aid only: not guaranteed and not subject to production testing
DD1
AC Electrical Characteristics† - Serial Streams for ST-BUS and GCI Backplanes
‡
Characteristic
Rin/Sin Set-up Time
Sym
Min
Typ
Max
Units
Test Conditions
tSIS
tSIH
1
2
3
10
10
ns
ns
ns
Rin/Sin Hold Time
tSOD
Rout/Sout Delay
- Active to Active
60
30
CL=150pF
4
Output Data Enable (ODE)
Delay
tODE
ns
CL=150pF, RL=1K
See Note 1
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, V = 3.3V and for design aid only: not guaranteed and not subject to production testing
DD1
* Note1: High Impedance is measured by pulling to the appropriate rail with R , with timing corrected to cancel time taken to discharge C .
L
L
Zarlink Semiconductor Inc.
31
ZL50233
Data Sheet
AC Electrical Characteristics† - Master Clock - Voltages are with respect to ground (V ). unless otherwise stated.
SS
‡
Characteristic
Sym
Min
Typ
Max
Units
Notes
1
Master Clock Frequency,
- Fsel = 0
- Fsel = 1
fMCF0
fMCF1
19.0
9.5
20.0
10.0
21.0
10.5
MHz
MHz
tMCL
tMCH
2
3
Master Clock Low
Master Clock High
20
20
ns
ns
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, V = 3.3V and for design aid only: not guaranteed and not subject to production testing
DD1
AC Electrical Characteristics† - Motorola Non-Multiplexed Bus Mode
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
t
0
ns
CSS
1
2
3
4
5
6
7
8
9
CS setup from DS falling
R/W setup from DS falling
Address setup from DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
Data delay on read
t
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RWS
t
ADS
CSH
RWH
t
t
t
ADH
DDR
DHR
DSW
DHW
t
79
15
t
3
0
0
Data hold on read
t
Data setup on write
t
10 Data hold on write
11 Acknowledgment delay
12 Acknowledgment hold time
13 IRQ delay
t
80
8
AKD
AKH
t
0
t
20
65
IRD
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, V
= 3.3V and for design aid only: not guaranteed and not subject to production testing
DD1
32
Zarlink Semiconductor Inc.
Data Sheet
ZL50233
t
FPW
F0i
C4i
V
TT
t
t
CH
t
t
t
t
CP
FPS
r
FPH
CL
V
V
HM
TT
V
LM
t
t
SOD
f
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
Rout/Sout
V
TT
t
t
SIS
SIH
Rin/Sin
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
V
TT
Figure 12 - ST-BUS Timing at 2.048 Mb/s
t
FPW
F0i
C4i
V
TT
t
t
CH
t
t
t
CP
FPS
t
FPH
CL
r
V
V
V
HM
TT
LM
t
SOD
t
f
Bit 0, Channel 0
Bit 1, Channel 0
Bit 2, Channel 0
Bit 2, Channel 0
Sout/Rout
Sin/Rin
V
TT
t
t
SIS
SIH
Bit 0, Channel 0
Bit 1, Channel 0
V
TT
Figure 13 - GCI Interface Timing at 2.048 Mb/s
V
TT
ODE
t
t
ODE
ODE
V
Valid Data
Sout/Rout
HiZ
HiZ
TT
Figure 14 - Output Driver Enable (ODE)
Zarlink Semiconductor Inc.
33
ZL50233
Data Sheet
t
MCH
V
MCLK
TT
t
MCL
Figure 15 - Master Clock
V
DS
CS
TT
t
t
CSS
CSH
V
TT
t
t
RWH
RWS
V
R/W
TT
TT
t
t
ADS
ADH
V
VALID ADDRESS
A0-A10
t
t
DHR
DDR
V
V
VALID READ DATA
t
D0-D7
READ
TT
t
DSW
DHW
VALID WRITE DATA
D0-D7
WRITE
TT
t
t
AKD
AKH
V
V
DTA
IRQ
TT
t
IRD
TT
Figure 16 - Motorola Non-Multiplexed Bus Timing
34
Zarlink Semiconductor Inc.
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application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may
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2
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
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