ZL50117_06 [ZARLINK]
32, 64 and 128 Channel CESoP Processors; 32，64和128个信道的CESoP处理器
| 型号： | ZL50117_06 |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | 32, 64 and 128 Channel CESoP Processors |
| 文件： | 总95页 (文件大小：1211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL50115/16/17/18/19/20
32, 64 and 128 Channel CESoP
Processors
Data Sheet
February 2006
Features
Ordering Information
General
ZL50115GAG
ZL50116GAG
ZL50117GAG
ZL50118GAG
ZL50119GAG
ZL50120GAG
324 Ball PBGA
324 Ball PBGA
324 Ball PBGA
324 Ball PBGA
324 Ball PBGA
324 Ball PBGA
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
•
Circuit Emulation Services over Packet (CESoP)
transport for MPLS, IP and Ethernet networks
•
On chip timing & synchronization recovery across
a packet network
ZL50115GAG2 324 Ball PBGA** trays, bake & dry pack
ZL50116GAG2 324 Ball PBGA** trays, bake & dry pack
ZL50117GAG2 324 Ball PBGA** trays, bake & dry pack
ZL50118GAG2 324 Ball PBGA** trays, bake & dry pack
ZL50119GAG2 324 Ball PBGA** trays, bake & dry pack
ZL50120GAG2 324 Ball PBGA** trays, bake & dry pack
•
•
•
On chip dual reference Stratum 3 DPLL
Grooming capability for Nx64 Kbps trunking
Fully compatible with Zarlink's ZL50110, ZL50111
and ZL50114 CESoP processors
**Pb Free Tin/Silver/Copper
-40°C to +85°C
Circuit Emulation Services
•
•
Up to 128 bi-directional 64 Kbps channels
Direct connection to LIUs, framers, backplanes
•
•
Complies with ITU-T recommendation Y.1413
Complies with IETF PWE3 draft standards
CESoPSN and SAToP
Customer Side Packet Interfaces
100 Mbps MII Fast Ethernet (ZL50118/19/20 only)
(may also be used as a second provider side packet
•
•
•
Complies with CESoP Implementation
Agreements from MEF 8 and MFA 8.0.0
•
Structured, synchronous CESoP with clock
interface)
recovery
Unstructured, asynchronous CESoP with integral
per-stream clock recovery
Provider Side Packet Interfaces
•
100 Mbps MII Fast Ethernet or 1000 Mbps
GMII/TBI Gigabit Ethernet
Customer Side TDM Interfaces
•
•
Up to 4 T1/E1, 1 J2, 1 T3/E3, or 1 STS-1 ports
H.110, H-MVIP, ST-BUS backplane
Multi-Protocol
Packet
TDM
Interface
Dual
Packet
Interface
MAC
Processing
Engine
(LIU, Framer, Backplane)
PW, RTP, UDP,
IPv4, IPv6, MPLS,
ECID, VLAN, User
Defined, Others
Per Port DCO for
Clock Recovery
(MII, GMII, TBI)
On Chip Packet Memory
(Jitter Buffer Compensation for 128 ms of Packet Delay Variation)
Dual Reference
Stratum 3 DPLL
Host Processor
Interface
JTAG
32-bit Motorola compatible
DMA for signaling packets
Figure 1 - ZL50115/16/17/18/19/20 High Level Overview
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL50115/16/17/18/19/20
Data Sheet
System Interfaces
•
•
Flexible 32 bit Motorola host interface
On-chip packet memory with jitter buffer compensation for over 128 ms of packet delay variation
Packet Processing Functions
•
Flexible, multi-protocol packet encapsulation including IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T Y.1413, IETF
CESoPSN, IETF SAToP and user programmable
•
•
•
•
•
Packet re-sequencing to allow lost packet detection and re-ordering
Four classes of service with programmable priority mechanisms (WFQ and SP) using egress queues
Programmable classification of incoming packets at layers 2 through 5
Wire speed processing of all packets regardless of classification providing low latency
Supports up to 128 separate CESoP connections across the Packet Switched Network
Applications
•
Circuit Emulation Services over Packet Networks
•
•
•
•
•
•
Leased Line support over packet networks
TDM over Cable
TDM over WiFi (802.11x)
TDM over WiMAX (802.16)
Fibre To The Premises G/E-PON
Layer 2 VPN services
•
•
Customer-premise and Provider Edge Routers and Switches
Ethernet and IP based IADs
2
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
1.0 Changes Summary
The following table captures the changes from the July 2005 issue.
Page
Item
Change
38, 39
Section 4.5 and Section 4.6.2
Added external pull-up/pull-down resistor
recommendations for SYSTEM_RST,
SYSTEM_DEBUG, JTAG_TRST, JTAG_TCK.
The following table captures the changes from the April 2005 issue.
Page
Item
Change
Added Section 6.3 SYSTEM_CLK Considerations.
49
Section 6.3
The following table captures the changes from the January 2005 issue.
Page
Item
Change
Clarified data sheet to indicate ZL5011x supports clock
recovery in both synchronous and asynchronous modes
of operation.
84
84
Figure 42
Figure 43
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to
conform with default MPC8260. Polarity of CPU_DREQ
and CPU_SDACK remains programmable through API.
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to
conform with default MPC8260. Polarity of CPU_DREQ
and CPU_SDACK remains programmable through API.
The following table captures the changes from the November 2004 issue.
Page
Item
Change
38
Section 4.6.1
Added 5 kohm pulldown recommendation to GPIO
signals.
3
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
2.0 Device Line Up
There are three products within the ZL5011x family, with capacities as shown in Table 1.
Product
Number
Provider Side
Customer Side
TDM Interface
1 T1 or 1 E1 stream or
Packet Interface
Packet Interface
ZL50115
ZL50116
ZL50117
ZL50118
ZL50119
ZL50120
100 Mbps MII or
None
1 MVIP/ST-BUS stream at 2.048 Mbps or
1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps
(Maximum of 32 DS0 or Nx64 kbps channels)
1000 Mbps GMII/TBI
2 T1 or 2 E1 streams or
100 Mbps MII or
None
2 MVIP/ST-BUS streams at 2.048 Mbps or
1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps
(Maximum of 64 DS0 or Nx64 kbps channels)
1000 Mbps GMII/TBI
4 T1 or 4 E1 streams or
100 Mbps MII or
None
1 J2, 1 T3, 1 E3 or 1 STS-1 stream or
4 MVIP/ST-BUS streams at 2.048 Mbps or
1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps
1000 Mbps GMII/TBI
1 T1 or 1 E1 stream or
100 Mbps MII or
100 Mbps MII
100 Mbps MII
100 Mbps MII
1 MVIP/ST-BUS stream at 2.048 Mbps or
1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps
(Maximum of 32 DS0 or Nx64 kbps channels)
1000 Mbps GMII/TBI
2 T1 or 2 E1 streams or
100 Mbps MII or
2 MVIP/ST-BUS streams at 2.048 Mbps or
1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps
(Maximum of 64 DS0 or Nx64 kbps channels)
1000 Mbps GMII/TBI
4 T1 or 4 E1 streams or
100 Mbps MII or
1 J2, 1 T3, 1 E3 or 1 STS-1 stream or
4 MVIP/ST-BUS streams at 2.048 Mbps or
1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps
1000 Mbps GMII/TBI
Table 1 - Capacity of Devices in the ZL50115/16/17/18/19/20 Family
4
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
2.0 Description
The ZL5011x family (ZL50115, ZL50116, ZL50117, ZL50118, ZL50119, ZL50120) of CESoP processors are highly
functional TDM to Packet bridging devices. The ZL5011x provides both structured and unstructured circuit
emulation services (CESoP) for T1 and E1 streams across a packet network based on MPLS, IP or Ethernet. The
ZL50117/20 also supports unstructured J2, T3, E3 and STS-1.
The circuit emulation features in the ZL5011x family comply with the ITU Recommendation Y.1413, as well as the
Implementation Agreements for CESoP from the Metro Ethernet Forum (MEF 8) and the MPLS and Frame Relay
Alliance (MFA 8.0.0). The ZL5011x also complies with the standards currently being developed within the IETF's
PWE3 working group, listed below.
•
•
Structure-Agnostic TDM over Packet (SAToP) - draft-ietf-pwe3-satop
Structure-aware TDM Circuit Emulation Service over Packet Switched Network (CESoPSN) -
draft-ietf-pwe3-cesopsn
The ZL50118/19/20 provides a customer side 100 Mbps MII port to aggregate data traffic with voice traffic to the
provider side 1000 Mbps GMII/TBI port, thereby eliminating the need for an external Ethernet switch.
The ZL5011x incorporates a range of powerful clock recovery mechanisms for each TDM stream, allowing the
frequency of the source clock to be faithfully generated at the destination, enabling greater system performance
and quality. Timing is carried using RTP or similar protocols, and both adaptive and differential clock recovery
schemes are included, allowing the customer to choose the correct scheme for the application. An externally
supplied clock may also be used to drive the TDM interface of the ZL5011x.
The ZL5011x incur very low latency for the data flow, thereby increasing QoS when carrying voice services across
the Packet Switched Network. Voice, when carried using CESoP, which typically has latencies of less than 10 ms,
does not require expensive processing such as compression and echo cancellation.
The ZL5011x are cost effective devices aimed at the low density applications such as customer premise routers,
IADs, ePON termination and Broadband DLCs. For network systems, the ZL5011x is fully compatible and
interoperable with the ZL50110/11/14 family.
The ZL5011x is capable of assembling user-defined packets of TDM traffic from the TDM interface and transmitting
them out the packet interfaces using a variety of protocols. The ZL5011x supports a range of different packet
switched networks, including Ethernet VLANs, IP (both versions 4 and 6) and MPLS. The devices also supports
four different classes of service on packet egress, allowing priority treatment of TDM-based traffic. This can be used
to help minimize latency variation in the TDM data.
Packets received from the packet interfaces are parsed to determine the egress destination, and are appropriately
queued to the TDM interface, they can also be forwarded to the host interface, or back toward the packet interface.
Packets queued to the TDM interface can be re-ordered based on sequence number, and lost packets filled in to
maintain timing integrity.
The ZL5011x includes on-chip memory sufficient for all applications, thereby reducing system costs, board area,
power, and design complexity.
A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor.
This system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI
that will run on a Windows PC.
5
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
Table of Contents
1.0 Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.0 Device Line Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.0 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.0 Physical Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.0 External Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.1 TDM stream connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.2 TDM Signals common to ZL50115/16/17/18/19/20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2 PAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3 Packet Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.4 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5 System Function Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.6 Test Facilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.6.1 Administration, Control and Test Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.6.2 JTAG Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.7 Miscellaneous Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.8 Power and Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.9 Internal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.10 No Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.11 Device ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.0 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1 Leased Line Provision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2 Remote Concentrator Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3 FTTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.4 Wireless - WiFi or WiMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.5 Digital Loop Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.6 Integrated Access Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2 Data and Control Flows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3 SYSTEM_CLK Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.4 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.4.1 TDM Interface Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.4.2 Structured TDM Port Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.4.3 TDM Clock Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.4.3.1 Synchronous TDM Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.4.3.2 Asynchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.5 Payload Assembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.5.1 Structured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.5.1.1 Payload Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.5.2 Unstructured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.6 Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.7 Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.8 Packet Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.9 TDM Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.10 Ethernet Traffic Aggregation (ZL50118/19/20 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.0 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.1 Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.2 Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.0 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
Table of Contents
8.2 Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.3 Host Packet Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.4 Loss of Service (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.5 Power Up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.6 JTAG Interface and Board Level Test Features.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.7 External Component Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.8 Miscellaneous Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.9 Test Modes Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.9.1.1 System Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.9.1.2 System Tri-State Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.9.2 Test Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.9.3 System Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.9.4 System Tri-state Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.0 DPLL Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1.1 Locking Mode (normal operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1.3 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1.4 Powerdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.2 Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.3 Locking Mode Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.4 Locking Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.5 Locking Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.6 Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.7 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.7.1 Acceptance of Input Wander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.7.2 Intrinsic Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.7.3 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.7.4 Jitter Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.8 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.0 Memory Map and Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.0 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.0 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.1 TDM Interface Timing - ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.1.1 ST-BUS Slave Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.1.2 ST-BUS Master Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.2 TDM Interface Timing - H.110 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.3 TDM Interface Timing - H-MVIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.4 TDM LIU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.5 PAC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.6 Packet Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.6.1 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.6.2 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
12.6.3 GMII Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.6.4 GMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.6.5 TBI Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.6.6 Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
12.7 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
12.8 System Function Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
12.9 JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
13.0 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
Table of Contents
14.0 Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
14.1 High Speed Clock & Data Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
14.1.1 GMAC Interface - Special Considerations During Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.1.2 TDM Interface - Special Considerations During Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.1.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.2 CPU TA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
15.0 Reference Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
15.1 External Standards/Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
15.2 Zarlink Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
16.0 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
List of Figures
Figure 1 - ZL50115/16/17/18/19/20 High Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL50115 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3 - ZL50116 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4 - ZL50117 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5 - ZL50118 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6 - ZL50119 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7 - ZL50120 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8 - Leased Line Services Over a Circuit Emulation Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 9 - Remote Concentrator Unit using CESoP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 10 - EPON using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 11 - Wi-Fi and WiMAX using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 12 - Digital Loop Carrier using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 13 - Integrated Access Device Using CESoP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 14 - ZL50115/16/17/18/19/20 Family Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 15 - ZL50115/16/17/18/19/20 Data and Control Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 16 - Synchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 17 - ZL50115/16/17/18/19/20 Packet Format - Structured Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 18 - Channel Order for Packet Formation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 19 - ZL50115/16/17/18/19/20 Packet Format - Unstructured Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 20 - Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 21 - Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 22 - Powering Up the ZL5011x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 23 - Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 24 - Jitter Transfer Function - Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 25 - TDM ST-BUS Slave Mode Timing at 8.192 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 26 - TDM ST-BUS Slave Mode Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 27 - TDM Bus Master Mode Timing at 8.192 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 28 - TDM Bus Master Mode Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 29 - H.110 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 30 - TDM - H-MVIP Timing Diagram for 16 MHz Clock (8.192 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 31 - TDM-LIU Structured Transmission/Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 32 - MII Transmit Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 33 - MII Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 34 - GMII Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 35 - GMII Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 36 - TBI Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 37 - TBI Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 38 - Management Interface Timing for Ethernet Port - Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 39 - Management Interface Timing for Ethernet Port - Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 40 - CPU Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 41 - CPU Write - MPC8260. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 42 - CPU DMA Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 43 - CPU DMA Write - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 44 - JTAG Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 45 - JTAG Clock and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 46 - ZL50115/16/17/18/19/20 Power Consumption Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 47 - CPU_TA Board Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
9
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
List of Tables
Table 1 - Capacity of Devices in the ZL50115/16/17/18/19/20 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2 - ZL50115/16/17/18/19/20 Ball Signal Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3 - TDM Interface Stream Pin Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 4 - TDM Interface Common Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 5 - PAC Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6 - Packet Interface Signal Mapping - MII to GMII/TBI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7 - MII Management Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8 - MII Port 0 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9 - MII Port 1 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10 - CPU Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11 - System Function Interface Package Ball Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 12 - Administration/Control Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13 - JTAG Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 14 - Miscellaneous Inputs Package Ball Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15 - Power and Ground Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16 - Internal Connections Package Ball Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 17 - Miscellaneous Inputs Package Ball Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18 - Device ID Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 19 - Standard Device Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 20 - TDM Services Offered by the ZL50115/16/17/18/19/20 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 21 - Some of the TDM Port Formats Accepted by the ZL50115/16/17/18/19/20 Family . . . . . . . . . . . . . . . 50
Table 22 - DMA Maximum Bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 23 - Test Mode Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 24 - DPLL Input Reference Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 25 - TDM ST-BUS Master Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 26 - TDM H.110 Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 27 - TDM H-MVIP Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 28 - TDM - LIU Structured Transmission/Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 29 - PAC Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 30 - MII Transmit Timing - 100 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 31 - MII Receive Timing - 100 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 32 - GMII Transmit Timing - 1000 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 33 - GMII Receive Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 34 - TBI Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 35 - MAC Management Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 36 - CPU Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 37 - System Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 38 - JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
3.0 Physical Specification
The ZL5011x will be packaged in a PBGA device.
Features:
•
•
•
•
•
•
Body Size:
23 mm x 23 mm (typ)
324
Ball Count:
Ball Pitch:
Ball Matrix:
1.00 mm (typ)
22 x 22
Ball Diameter:
Total Package Thickness:
0.60 mm (typ)
2.03 mm (typ)
11
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
ZL50115 Package view from TOP side. Note that ball A1 is non-chamfered corner.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
VDD_IO
NC
M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_C M0_TXEN DEVICE_ID CPU_DATA[CPU_DATA[GND
LK [4] 28] 24]
CPU_DATA[GND
23]
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_SDACVDD_IO
19]
12]
9]
8]
7]
K1
A
B
C
D
E
NC
NC
NC
NC
NC
VDD_IO
GND
GND
NC
NC
NC
NC
M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER GND
M0_TXD[5] M0_TXD[3] M0_TXD[2] NC
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[GND
27] 22] 20] 13]
VDD_IO
CPU_TA
VDD_IO
NC
NC
NC
M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] VDD_IO
VDD_IO
CPU_DATA[NC
31]
CPU_DATA[CPU_DATA[VDD_IO
29] 26]
GND
CPU_DRE
Q1
NC
VDD_IO
NC
M0_RXER VDD_IO
M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR VDD_IO
M0_ACTIV VDD_COR VDD_IO
E_LED
CPU_DATA[CPU_ADDRCPU_DATA[
25] 23] 6]
E
K
E
E
E
M0_GIGABINC
T_LED
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[
30] 21] 15] 14]
NC
DEVICE_ID VDD_COR
[1]
VDD_COR CPU_DATA[CPU_DATA[CPU_DATA[
E
E
18]
17]
16]
F
M_MDIO DEVICE_ID M0_LINKU VDD_IO
VDD_IO
CPU_IREQ CPU_DATA[CPU_DATA[
11] 0]
[0]
P_LED
1
G
H
J
M_MDC
NC
GND
NC
VDD_COR
E
CPU_DATA[CPU_DATA[CPU_DATA[IC
10] 1] 4]
NC
NC
NC
NC
VDD_COR
E
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_COR CPU_DATA[CPU_DATA[CPU_IREQ
E
5]
3]
0
NC
VDD_IO
GND
CPU_DATA[C
2]
CPU_DRE
Q0
K
L
GND
NC
AUX_CLKOAUX_CLKI VDD_COR
E
CPU_CLK GND
CPU_SDACIC_VDD_IO
K2
NC
NC
VDD_IO
GND
CPU_TS_A CPU_WE CPU_OE
LE
M
N
P
NC
NC
NC
VDD_COR
E
VDD_IO
CPU_ADD CPU_CS CPU_ADDR
R[22]
[19]
NC
GND
NC
VDD_IO
VDD_COR
E
VDD_COR CPU_ADD CPU_ADDRCPU_ADDR
E
R[17]
18]
[21]
NC
TDM_CLKI[ NC
0]
GND
CPU_ADD CPU_ADDRCPU_ADDR
R[11]
13]
[20]
R
T
NC
NC
TDM_FRMI VDD_IO
_REF
VDD_IO
VDD_IO
CPU_ADDRCPU_ADDR
14] [16]
TDM_STI[0]VDD_IO
GND
TDM_CLKi
S
VDD_COR JTAG_TMS CPU_ADDRCPU_ADDR
15] [12]
E
U
V
TDM_STO[ TDM_CLKOTDM_CLKOTDM_CLKi
DEVICE_ID JTAG_TCK CPU_ADDRCPU_ADDR
3] 10] [9]
0]
[0]
_REF
P
IC
TDM_CLKI TDM_FRM VDD_IO
VDD_IO
IC
VDD_COR VDD_IO
E
VDD_IO
IC
VDD_COR PLL_SEC IC_GND
E
GND
IC
SYSTEM_CVDD_COR GPIO[9]
VDD_IO
GPIO[15] DEVICE_ID VDD_IO
[2]
JTAG_TDO CPU_ADDRCPU_ADDR
_REF
O_REF
LK
E
4]
[8]
W
Y
IC
GND
VDD_IO
IC
VDD_COR IC
E
PLL_PRI IC
C_GND
GND
GND
GPIO[8]
GPIO[7]
GPIO[14] TEST_MODJTAG_TRS C_GND
E[1]
VDD_IO
GND
GND
CPU_ADDR
[7]
T
IC
VDD_IO
IC
GND
IC
VDD_IO
IC
VDD_IO
GND
IC
IC
GND
IC
A1VDD_PL IC
L1
IC
SYSTEM_DSYSTEM_RGPIO[1]
GPIO[2]
GPIO[12] TEST_MODJTAG_TDI C_GND
E[0]
VDD_IO
CPU_ADDR
[6]
EBUG
ST
AA
AB
VDD_IO
IC
GPIO[0]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10] GPIO[11] GPIO[13] TEST_MODIC_GND
E[2]
CPU_ADD CPU_ADD CPU_ADDRVDD_IO
R[2] R[3] 5]
Figure 2 - ZL50115 Package View and Ball Positions
12
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
ZL50116 Package view from TOP side. Note that ball A1 is non-chamfered corner.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
VDD_IO
NC
M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_C M0_TXEN DEVICE_ID CPU_DATA[CPU_DATA[GND
LK [4] 28] 24]
CPU_DATA[GND
23]
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_SDACVDD_IO
19]
12]
9]
8]
7]
K1
A
B
C
D
E
NC
NC
NC
NC
NC
VDD_IO
GND
GND
NC
NC
NC
NC
M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER GND
M0_TXD[5] M0_TXD[3] M0_TXD[2] NC
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[GND
27] 22] 20] 13]
VDD_IO
CPU_TA
VDD_IO
NC
NC
NC
M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] VDD_IO
VDD_IO
CPU_DATA[NC
31]
CPU_DATA[CPU_DATA[VDD_IO
29] 26]
GND
CPU_DRE
Q1
NC
VDD_IO
NC
M0_RXER VDD_IO
M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR VDD_IO
M0_ACTIV VDD_COR VDD_IO
E_LED
CPU_DATA[CPU_ADDRCPU_DATA[
25] 23] 6]
E
K
E
E
E
M0_GIGABINC
T_LED
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[
30] 21] 15] 14]
NC
DEVICE_ID VDD_COR
[1]
VDD_COR CPU_DATA[CPU_DATA[CPU_DATA[
E
E
18]
17]
16]
F
M_MDIO DEVICE_ID M0_LINKU VDD_IO
VDD_IO
CPU_IREQ CPU_DATA[CPU_DATA[
11] 0]
[0]
P_LED
1
G
H
J
M_MDC
NC
GND
NC
VDD_COR
E
CPU_DATA[CPU_DATA[CPU_DATA[IC
10] 1] 4]
NC
NC
NC
NC
VDD_COR
E
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_COR CPU_DATA[CPU_DATA[CPU_IREQ
E
5]
3]
0
NC
VDD_IO
GND
CPU_DATA[C
2]
CPU_DRE
Q0
K
L
GND
NC
AUX_CLKOAUX_CLKI VDD_COR
E
CPU_CLK GND
CPU_SDACIC_VDD_IO
K2
NC
NC
VDD_IO
GND
CPU_TS_A CPU_WE CPU_OE
LE
M
N
P
NC
NC
NC
VDD_COR
E
VDD_IO
CPU_ADD CPU_CS CPU_ADDR
R[22]
[19]
NC
GND
VDD_IO
VDD_COR
E
VDD_COR CPU_ADD CPU_ADDRCPU_ADDR
E
R[17]
18]
[21]
NC
TDM_STI[1]TDM_CLKI[ TDM_STO[
0] 1]
GND
CPU_ADD CPU_ADDRCPU_ADDR
R[11]
13]
[20]
R
T
TDM_CLKI[ TDM_CLKOTDM_FRMI VDD_IO
VDD_IO
VDD_IO
CPU_ADDRCPU_ADDR
14] [16]
1]
[1]
_REF
TDM_STI[0]VDD_IO
GND
TDM_CLKi
S
VDD_COR JTAG_TMS CPU_ADDRCPU_ADDR
15] [12]
E
U
V
TDM_STO[ TDM_CLKOTDM_CLKOTDM_CLKi
DEVICE_ID JTAG_TCK CPU_ADDRCPU_ADDR
3] 10] [9]
0]
[0]
_REF
P
IC
TDM_CLKI TDM_FRM VDD_IO
VDD_IO
IC
VDD_COR VDD_IO
E
VDD_IO
IC
VDD_COR PLL_SEC IC_GND
E
GND
IC
SYSTEM_CVDD_COR GPIO[9]
VDD_IO
GPIO[15] DEVICE_ID VDD_IO
[2]
JTAG_TDO CPU_ADDRCPU_ADDR
_REF
O_REF
LK
E
4]
[8]
W
Y
IC
GND
VDD_IO
IC
VDD_COR IC
E
PLL_PRI IC
C_GND
GND
GND
GPIO[8]
GPIO[7]
GPIO[14] TEST_MODJTAG_TRS C_GND
E[1]
VDD_IO
GND
GND
CPU_ADDR
[7]
T
IC
VDD_IO
IC
GND
IC
VDD_IO
IC
VDD_IO
GND
IC
IC
GND
IC
A1VDD_PL IC
L1
IC
SYSTEM_DSYSTEM_RGPIO[1]
GPIO[2]
GPIO[12] TEST_MODJTAG_TDI C_GND
E[0]
VDD_IO
CPU_ADDR
[6]
EBUG
ST
AA
AB
VDD_IO
IC
GPIO[0]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10] GPIO[11] GPIO[13] TEST_MODIC_GND
E[2]
CPU_ADD CPU_ADD CPU_ADDRVDD_IO
R[2] R[3] 5]
Figure 3 - ZL50116 Package View and Ball Positions
13
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
ZL50117 Package view from TOP side. Note that ball A1 is non-chamfered corner.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
VDD_IO
NC
M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_C M0_TXEN DEVICE_ID CPU_DATA[CPU_DATA[GND
LK [4] 28] 24]
CPU_DATA[GND
23]
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_SDACVDD_IO
19]
12]
9]
8]
7]
K1
A
B
C
D
E
NC
NC
NC
NC
NC
VDD_IO
GND
GND
NC
NC
NC
NC
M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER GND
M0_TXD[5] M0_TXD[3] M0_TXD[2] NC
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[GND
27] 22] 20] 13]
VDD_IO
CPU_TA
VDD_IO
NC
NC
NC
M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] VDD_IO
VDD_IO
CPU_DATA[NC
31]
CPU_DATA[CPU_DATA[VDD_IO
29] 26]
GND
CPU_DRE
Q1
NC
VDD_IO
NC
M0_RXER VDD_IO
M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR VDD_IO
M0_ACTIV VDD_COR VDD_IO
E_LED
CPU_DATA[CPU_ADDRCPU_DATA[
25] 23] 6]
E
K
E
E
E
M0_GIGABINC
T_LED
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[
30] 21] 15] 14]
NC
DEVICE_ID VDD_COR
[1]
VDD_COR CPU_DATA[CPU_DATA[CPU_DATA[
E
E
18]
17]
16]
F
M_MDIO DEVICE_ID M0_LINKU VDD_IO
VDD_IO
CPU_IREQ CPU_DATA[CPU_DATA[
11] 0]
[0]
P_LED
1
G
H
J
M_MDC
NC
GND
NC
VDD_COR
E
CPU_DATA[CPU_DATA[CPU_DATA[IC
10] 1] 4]
NC
NC
NC
NC
VDD_COR
E
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_COR CPU_DATA[CPU_DATA[CPU_IREQ
E
5]
3]
0
NC
VDD_IO
GND
CPU_DATA[C
2]
CPU_DRE
Q0
K
L
GND
AUX_CLKOAUX_CLKI VDD_COR
E
CPU_CLK GND
CPU_SDACIC_VDD_IO
K2
TDM_CLKI[ TDM_STO[ TDM_STI[3]VDD_IO
3] 3]
GND
CPU_TS_A CPU_WE CPU_OE
LE
M
N
P
TDM_STO[ TDM_CLKOTDM_STI[2]VDD_COR
VDD_IO
CPU_ADD CPU_CS CPU_ADDR
2]
[3]
E
R[22]
[19]
TDM_CLKI[ GND
2]
VDD_IO
VDD_COR
E
VDD_COR CPU_ADD CPU_ADDRCPU_ADDR
E
R[17]
18]
[21]
TDM_CLKOTDM_STI[1]TDM_CLKI[ TDM_STO[
[2] 0] 1]
GND
CPU_ADD CPU_ADDRCPU_ADDR
R[11]
13]
[20]
R
T
TDM_CLKI[ TDM_CLKOTDM_FRMI VDD_IO
VDD_IO
VDD_IO
CPU_ADDRCPU_ADDR
14] [16]
1]
[1]
_REF
TDM_STI[0]VDD_IO
GND
TDM_CLKi
S
VDD_COR JTAG_TMS CPU_ADDRCPU_ADDR
15] [12]
E
U
V
TDM_STO[ TDM_CLKOTDM_CLKOTDM_CLKi
DEVICE_ID JTAG_TCK CPU_ADDRCPU_ADDR
3] 10] [9]
0]
[0]
_REF
P
IC
TDM_CLKI TDM_FRM VDD_IO
VDD_IO
IC
VDD_COR VDD_IO
E
VDD_IO
IC
VDD_COR PLL_SEC IC_GND
E
GND
IC
SYSTEM_CVDD_COR GPIO[9]
VDD_IO
GPIO[15] DEVICE_ID VDD_IO
[2]
JTAG_TDO CPU_ADDRCPU_ADDR
_REF
O_REF
LK
E
4]
[8]
W
Y
IC
GND
VDD_IO
IC
VDD_COR IC
E
PLL_PRI IC
C_GND
GND
GND
GPIO[8]
GPIO[7]
GPIO[14] TEST_MODJTAG_TRS C_GND
E[1]
VDD_IO
GND
GND
CPU_ADDR
[7]
T
IC
VDD_IO
IC
GND
IC
VDD_IO
IC
VDD_IO
GND
IC
IC
GND
IC
A1VDD_PL IC
L1
IC
SYSTEM_DSYSTEM_RGPIO[1]
GPIO[2]
GPIO[12] TEST_MODJTAG_TDI C_GND
E[0]
VDD_IO
CPU_ADDR
[6]
EBUG
ST
AA
AB
VDD_IO
IC
GPIO[0]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10] GPIO[11] GPIO[13] TEST_MODIC_GND
E[2]
CPU_ADD CPU_ADD CPU_ADDRVDD_IO
R[2] R[3] 5]
Figure 4 - ZL50117 Package View and Ball Positions
14
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
ZL50118 Package view from TOP side. Note that ball A1 is non-chamfered corner.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
VDD_IO M1_TXEN M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_C M0_TXEN DEVICE_IDCPU_DATA[CPU_DATA[
GND
CPU_DATA[
23]
GND
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_SDAC VDD_IO
LK
[4]
28]
24]
19]
12]
9]
8]
7]
K1
A
B
C
D
E
M1_TXD[2] VDD_IO
GND
M1_TXD[0] M1_TXD[1] M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER
GND
M0_TXD[5] M0_TXD[3] M0_TXD[2] M1_ACTIV CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[
E_LED 27] 22] 20] 13]
GND
VDD_IO
CPU_TA
M1_TXD[3]
GND
VDD_IO M1_RXCLK M1_COL M1_TXER M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] VDD_IO
VDD_IO CPU_DATA[ M1_LINKU CPU_DATA[CPU_DATA[ VDD_IO
31] P_LED 29] 26]
GND
CPU_DRE
Q1
M1_RXD[1] M1_RXD[0] M1_RXD[2] VDD_IO M1_RXDV M0_RXER VDD_IO M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR VDD_IO M0_ACTIV VDD_COR VDD_IO CPU_DATA[CPU_ADDRCPU_DATA[
E
K
E
E
E_LED
E
25]
[23]
6]
M1_RXD[3] M0_GIGABI M1_TXCLK M1_RXER
T_LED
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[
30] 21] 15] 14]
NC
M1_CRS DEVICE_ID VDD_COR
[1]
VDD_COR CPU_DATA[CPU_DATA[CPU_DATA[
18] 17] 16]
E
E
F
M_MDIO DEVICE_ID M0_LINKU VDD_IO
VDD_IO CPU_IREQ CPU_DATA[CPU_DATA[
[0]
P_LED
1
11]
0]
G
H
J
M_MDC
NC
GND
NC
VDD_COR
E
CPU_DATA[CPU_DATA[CPU_DATA[
10] 1] 4]
IC
NC
NC
NC
NC
VDD_COR
E
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_COR CPU_DATA[CPU_DATA[ CPU_IREQ
E
5]
3]
0
NC
VDD_IO
GND
CPU_DATA[
2]
IC
CPU_DRE
Q0
K
L
GND
NC
AUX_CLKO AUX_CLKI VDD_COR
E
CPU_CLK
GND
GND
CPU_SDAC IC_VDD_IO
K2
NC
NC
NC
NC
VDD_IO
CPU_TS_A CPU_WE CPU_OE
LE
M
N
P
NC
VDD_COR
E
VDD_IO CPU_ADD CPU_CS CPU_ADDR
R[22] [19]
NC
GND
NC
VDD_IO VDD_COR
E
VDD_COR CPU_ADD CPU_ADDRCPU_ADDR
E
R[17]
[18]
[21]
NC
TDM_CLKI[
0]
NC
GND
CPU_ADD CPU_ADDRCPU_ADDR
R[11] [13] [20]
R
T
NC
NC
TDM_FRMI VDD_IO
_REF
VDD_IO
VDD_IO CPU_ADDRCPU_ADDR
[14] [16]
TDM_STI[0] VDD_IO
GND
TDM_CLKi
S
VDD_COR JTAG_TMS CPU_ADDRCPU_ADDR
[15] [12]
E
U
V
TDM_STO[ TDM_CLKOTDM_CLKO TDM_CLKi
DEVICE_ID JTAG_TCK CPU_ADDRCPU_ADDR
[3] [10] [9]
0]
[0]
_REF
P
IC
TDM_CLKI TDM_FRM VDD_IO
VDD_IO VDD_COR VDD_IO
E
VDD_IO VDD_COR PLL_SEC IC_GND
E
GND
IC
SYSTEM_C VDD_COR GPIO[9]
VDD_IO
GPIO[15] DEVICE_ID VDD_IO JTAG_TDO CPU_ADDRCPU_ADDR
_REF
O_REF
LK
E
[2]
[4]
[8]
W
Y
IC
IC
GND
VDD_IO
IC
VDD_IO
IC
IC
VDD_COR
E
IC
GND
IC
IC
PLL_PRI
IC
IC
IC
IC_GND
GND
GND
GPIO[8]
GPIO[7]
GPIO[14] TEST_MOD JTAG_TRS IC_GND
E[1]
VDD_IO
GND
GND
CPU_ADDR
[7]
T
VDD_IO
IC
GND
IC
VDD_IO
GND
IC
IC
A1VDD_PL
L1
SYSTEM_DSYSTEM_R GPIO[1]
EBUG
GPIO[2]
GPIO[12] TEST_MOD JTAG_TDI IC_GND
E[0]
VDD_IO CPU_ADDR
[6]
ST
AA
AB
VDD_IO
IC
GPIO[0]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10] GPIO[11] GPIO[13] TEST_MOD IC_GND CPU_ADD CPU_ADD CPU_ADDR VDD_IO
E[2] R[2] R[3] [5]
Figure 5 - ZL50118 Package View and Ball Positions
15
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
ZL50119 Package view from TOP side. Note that ball A1 is non-chamfered corner.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
VDD_IO M1_TXEN M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_C M0_TXEN DEVICE_IDCPU_DATA[CPU_DATA[
GND
CPU_DATA[
23]
GND
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_SDAC VDD_IO
LK
[4]
28]
24]
19]
12]
9]
8]
7]
K1
A
B
C
D
E
M1_TXD[2] VDD_IO
GND
M1_TXD[0] M1_TXD[1] M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER
GND
M0_TXD[5] M0_TXD[3] M0_TXD[2] M1_ACTIV CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[
E_LED 27] 22] 20] 13]
GND
VDD_IO
CPU_TA
M1_TXD[3]
GND
VDD_IO M1_RXCLK M1_COL M1_TXER M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] VDD_IO
VDD_IO CPU_DATA[ M1_LINKU CPU_DATA[CPU_DATA[ VDD_IO
31] P_LED 29] 26]
GND
CPU_DRE
Q1
M1_RXD[1] M1_RXD[0] M1_RXD[2] VDD_IO M1_RXDV M0_RXER VDD_IO M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR VDD_IO M0_ACTIV VDD_COR VDD_IO CPU_DATA[CPU_ADDRCPU_DATA[
E
K
E
E
E_LED
E
25]
[23]
6]
M1_RXD[3] M0_GIGABI M1_TXCLK M1_RXER
T_LED
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[
30] 21] 15] 14]
NC
M1_CRS DEVICE_ID VDD_COR
[1]
VDD_COR CPU_DATA[CPU_DATA[CPU_DATA[
18] 17] 16]
E
E
F
M_MDIO DEVICE_ID M0_LINKU VDD_IO
VDD_IO CPU_IREQ CPU_DATA[CPU_DATA[
[0]
P_LED
1
11]
0]
G
H
J
M_MDC
NC
GND
NC
VDD_COR
E
CPU_DATA[CPU_DATA[CPU_DATA[
10] 1] 4]
IC
NC
NC
NC
NC
VDD_COR
E
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_COR CPU_DATA[CPU_DATA[ CPU_IREQ
E
5]
3]
0
NC
VDD_IO
GND
CPU_DATA[
2]
IC
CPU_DRE
Q0
K
L
GND
NC
AUX_CLKO AUX_CLKI VDD_COR
E
CPU_CLK
GND
GND
CPU_SDAC IC_VDD_IO
K2
NC
NC
NC
NC
VDD_IO
CPU_TS_A CPU_WE CPU_OE
LE
M
N
P
NC
VDD_COR
E
VDD_IO CPU_ADD CPU_CS CPU_ADDR
R[22] [19]
NC
GND
VDD_IO VDD_COR
E
VDD_COR CPU_ADD CPU_ADDRCPU_ADDR
E
R[17]
[18]
[21]
NC
TDM_STI[1] TDM_CLKI[ TDM_STO[
0] 1]
GND
CPU_ADD CPU_ADDRCPU_ADDR
R[11] [13] [20]
R
T
TDM_CLKI[TDM_CLKO TDM_FRMI VDD_IO
VDD_IO
VDD_IO CPU_ADDRCPU_ADDR
[14] [16]
1]
[1]
_REF
TDM_STI[0] VDD_IO
GND
TDM_CLKi
S
VDD_COR JTAG_TMS CPU_ADDRCPU_ADDR
[15] [12]
E
U
V
TDM_STO[ TDM_CLKOTDM_CLKO TDM_CLKi
DEVICE_ID JTAG_TCK CPU_ADDRCPU_ADDR
[3] [10] [9]
0]
[0]
_REF
P
IC
TDM_CLKI TDM_FRM VDD_IO
VDD_IO VDD_COR VDD_IO
E
VDD_IO VDD_COR PLL_SEC IC_GND
E
GND
IC
SYSTEM_C VDD_COR GPIO[9]
VDD_IO
GPIO[15] DEVICE_ID VDD_IO JTAG_TDO CPU_ADDRCPU_ADDR
_REF
O_REF
LK
E
[2]
[4]
[8]
W
Y
IC
IC
GND
VDD_IO
IC
VDD_IO
IC
IC
VDD_COR
E
IC
GND
IC
IC
PLL_PRI
IC
IC
IC
IC_GND
GND
GND
GPIO[8]
GPIO[7]
GPIO[14] TEST_MOD JTAG_TRS IC_GND
E[1]
VDD_IO
GND
GND
CPU_ADDR
[7]
T
VDD_IO
IC
GND
IC
VDD_IO
GND
IC
IC
A1VDD_PL
L1
SYSTEM_DSYSTEM_R GPIO[1]
GPIO[2]
GPIO[12] TEST_MOD JTAG_TDI IC_GND
E[0]
VDD_IO CPU_ADDR
[6]
EBUG
ST
AA
AB
VDD_IO
IC
GPIO[0]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10] GPIO[11] GPIO[13] TEST_MOD IC_GND CPU_ADD CPU_ADD CPU_ADDR VDD_IO
E[2] R[2] R[3] [5]
Figure 6 - ZL50119 Package View and Ball Positions
16
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
ZL50120 Package view from TOP side. Note that ball A1 is non-chamfered corner.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
VDD_IO M1_TXEN M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_C M0_TXEN DEVICE_IDCPU_DATA[CPU_DATA[
GND
CPU_DATA[
23]
GND
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_SDAC VDD_IO
LK
[4]
28]
24]
19]
12]
9]
8]
7]
K1
A
B
C
D
E
M1_TXD[2] VDD_IO
GND
M1_TXD[0] M1_TXD[1] M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER
GND
M0_TXD[5] M0_TXD[3] M0_TXD[2] M1_ACTIV CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[
E_LED 27] 22] 20] 13]
GND
VDD_IO
CPU_TA
M1_TXD[3]
GND
VDD_IO M1_RXCLK M1_COL M1_TXER M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] VDD_IO
VDD_IO CPU_DATA[ M1_LINKU CPU_DATA[CPU_DATA[ VDD_IO
31] P_LED 29] 26]
GND
CPU_DRE
Q1
M1_RXD[1] M1_RXD[0] M1_RXD[2] VDD_IO M1_RXDV M0_RXER VDD_IO M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR VDD_IO M0_ACTIV VDD_COR VDD_IO CPU_DATA[CPU_ADDRCPU_DATA[
E
K
E
E
E_LED
E
25]
[23]
6]
M1_RXD[3] M0_GIGABI M1_TXCLK M1_RXER
T_LED
CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[
30] 21] 15] 14]
NC
M1_CRS DEVICE_ID VDD_COR
[1]
VDD_COR CPU_DATA[CPU_DATA[CPU_DATA[
18] 17] 16]
E
E
F
M_MDIO DEVICE_ID M0_LINKU VDD_IO
VDD_IO CPU_IREQ CPU_DATA[CPU_DATA[
[0]
P_LED
1
11]
0]
G
H
J
M_MDC
NC
GND
NC
VDD_COR
E
CPU_DATA[CPU_DATA[CPU_DATA[
10] 1] 4]
IC
NC
NC
NC
NC
VDD_COR
E
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_COR CPU_DATA[CPU_DATA[ CPU_IREQ
E
5]
3]
0
NC
VDD_IO
GND
CPU_DATA[
2]
IC
CPU_DRE
Q0
K
L
GND
AUX_CLKO AUX_CLKI VDD_COR
E
CPU_CLK
GND
GND
CPU_SDAC IC_VDD_IO
K2
TDM_CLKI[ TDM_STO[ TDM_STI[3] VDD_IO
3] 3]
CPU_TS_A CPU_WE CPU_OE
LE
M
N
P
TDM_STO[ TDM_CLKOTDM_STI[2] VDD_COR
VDD_IO CPU_ADD CPU_CS CPU_ADDR
R[22] [19]
2]
[3]
E
TDM_CLKI[
2]
GND
VDD_IO VDD_COR
E
VDD_COR CPU_ADD CPU_ADDRCPU_ADDR
E
R[17]
[18]
[21]
TDM_CLKOTDM_STI[1] TDM_CLKI[ TDM_STO[
[2] 0] 1]
GND
CPU_ADD CPU_ADDRCPU_ADDR
R[11] [13] [20]
R
T
TDM_CLKI[TDM_CLKO TDM_FRMI VDD_IO
VDD_IO
VDD_IO CPU_ADDRCPU_ADDR
[14] [16]
1]
[1]
_REF
TDM_STI[0] VDD_IO
GND
TDM_CLKi
S
VDD_COR JTAG_TMS CPU_ADDRCPU_ADDR
[15] [12]
E
U
V
TDM_STO[ TDM_CLKOTDM_CLKO TDM_CLKi
DEVICE_ID JTAG_TCK CPU_ADDRCPU_ADDR
[3] [10] [9]
0]
[0]
_REF
P
IC
TDM_CLKI TDM_FRM VDD_IO
VDD_IO VDD_COR VDD_IO
E
VDD_IO VDD_COR PLL_SEC IC_GND
E
GND
IC
SYSTEM_C VDD_COR GPIO[9]
VDD_IO
GPIO[15] DEVICE_ID VDD_IO JTAG_TDO CPU_ADDRCPU_ADDR
_REF
O_REF
LK
E
[2]
[4]
[8]
W
Y
IC
IC
GND
VDD_IO
IC
VDD_IO
IC
IC
VDD_COR
E
IC
GND
IC
IC
PLL_PRI
IC
IC
IC
IC_GND
GND
GND
GPIO[8]
GPIO[7]
GPIO[14] TEST_MOD JTAG_TRS IC_GND
E[1]
VDD_IO
GND
GND
CPU_ADDR
[7]
T
VDD_IO
IC
GND
IC
VDD_IO
GND
IC
IC
A1VDD_PL
L1
SYSTEM_DSYSTEM_R GPIO[1]
GPIO[2]
GPIO[12] TEST_MOD JTAG_TDI IC_GND
E[0]
VDD_IO CPU_ADDR
[6]
EBUG
ST
AA
AB
VDD_IO
IC
GPIO[0]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10] GPIO[11] GPIO[13] TEST_MOD IC_GND CPU_ADD CPU_ADD CPU_ADDR VDD_IO
E[2] R[2] R[3] [5]
Figure 7 - ZL50120 Package View and Ball Positions
17
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
ZL50115
ZL50116
ZL50117
ZL50118
ZL50119
ZL50120
Ball #
Variant
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
A1
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
All
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A2
DEVICE_ID[4]
CPU_DATA[28]
CPU_DATA[24]
GND
DEVICE_ID[4]
CPU_DATA[28]
CPU_DATA[24]
GND
DEVICE_ID[4]
CPU_DATA[28]
CPU_DATA[24]
GND
DEVICE_ID[4]
CPU_DATA[28]
CPU_DATA[24]
GND
DEVICE_ID[4]
CPU_DATA[28]
CPU_DATA[24]
GND
DEVICE_ID[4]
CPU_DATA[28]
CPU_DATA[24]
GND
All
All
All
All
CPU_DATA[23]
GND
CPU_DATA[23]
GND
CPU_DATA[23]
GND
CPU_DATA[23]
GND
CPU_DATA[23]
GND
CPU_DATA[23]
GND
All
All
CPU_DATA[19]
CPU_DATA[12]
CPU_DATA[9]
CPU_DATA[8]
CPU_DATA[7]
CPU_SDACK1
VDD_IO
CPU_DATA[19]
CPU_DATA[12]
CPU_DATA[9]
CPU_DATA[8]
CPU_DATA[7]
CPU_SDACK1
VDD_IO
CPU_DATA[19]
CPU_DATA[12]
CPU_DATA[9]
CPU_DATA[8]
CPU_DATA[7]
CPU_SDACK1
VDD_IO
CPU_DATA[19]
CPU_DATA[12]
CPU_DATA[9]
CPU_DATA[8]
CPU_DATA[7]
CPU_SDACK1
VDD_IO
CPU_DATA[19]
CPU_DATA[12]
CPU_DATA[9]
CPU_DATA[8]
CPU_DATA[7]
CPU_SDACK1
VDD_IO
CPU_DATA[19]
CPU_DATA[12]
CPU_DATA[9]
CPU_DATA[8]
CPU_DATA[7]
CPU_SDACK1
VDD_IO
All
All
All
All
All
All
All
NC
NC
NC
M1_TXEN
M1_TXEN
M1_TXEN
ZL50118/19/20
A3
M0_TXCLK
M0_RXD[7]
M0_RXD[6]
M0_RXD[4]
M0_COL
M0_TXCLK
M0_RXD[7]
M0_RXD[6]
M0_RXD[4]
M0_COL
M0_TXCLK
M0_RXD[7]
M0_RXD[6]
M0_RXD[4]
M0_COL
M0_TXCLK
M0_RXD[7]
M0_RXD[6]
M0_RXD[4]
M0_COL
M0_TXCLK
M0_RXD[7]
M0_RXD[6]
M0_RXD[4]
M0_COL
M0_TXCLK
M0_RXD[7]
M0_RXD[6]
M0_RXD[4]
M0_COL
All
A4
All
A5
All
A6
All
A7
All
A8
M0_GTX_CLK
M0_TXEN
NC
M0_GTX_CLK
M0_TXEN
NC
M0_GTX_CLK
M0_TXEN
NC
M0_GTX_CLK
M0_TXEN
M0_GTX_CLK
M0_TXEN
M0_GTX_CLK
M0_TXEN
All
A9
All
B1
M1_TXD[2]
M0_TXER
M1_TXD[2]
M0_TXER
M1_TXD[2]
M0_TXER
ZL50118/19/20
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B2
M0_TXER
GND
M0_TXER
GND
M0_TXER
GND
All
GND
GND
GND
All
M0_TXD[5]
M0_TXD[3]
M0_TXD[2]
NC
M0_TXD[5]
M0_TXD[3]
M0_TXD[2]
NC
M0_TXD[5]
M0_TXD[3]
M0_TXD[2]
NC
M0_TXD[5]
M0_TXD[3]
M0_TXD[2]
M1_ACTIVE_LED
CPU_DATA[27]
CPU_DATA[22]
CPU_DATA[20]
CPU_DATA[13]
GND
M0_TXD[5]
M0_TXD[3]
M0_TXD[2]
M1_ACTIVE_LED
CPU_DATA[27]
CPU_DATA[22]
CPU_DATA[20]
CPU_DATA[13]
GND
M0_TXD[5]
M0_TXD[3]
M0_TXD[2]
M1_ACTIVE_LED
CPU_DATA[27]
CPU_DATA[22]
CPU_DATA[20]
CPU_DATA[13]
GND
All
All
All
ZL50118/19/20
CPU_DATA[27]
CPU_DATA[22]
CPU_DATA[20]
CPU_DATA[13]
GND
CPU_DATA[27]
CPU_DATA[22]
CPU_DATA[20]
CPU_DATA[13]
GND
CPU_DATA[27]
CPU_DATA[22]
CPU_DATA[20]
CPU_DATA[13]
GND
All
All
All
All
All
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
All
CPU_TA
CPU_TA
CPU_TA
CPU_TA
CPU_TA
CPU_TA
All
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
All
B3
GND
GND
GND
GND
GND
GND
All
B4
NC
NC
NC
M1_TXD[0]
M1_TXD[1]
M0_CRS
M1_TXD[0]
M1_TXD[1]
M0_CRS
M1_TXD[0]
M1_TXD[1]
M0_CRS
ZL50118/19/20
B5
NC
NC
NC
ZL50118/19/20
B6
M0_CRS
M0_CRS
M0_CRS
All
All
All
B7
M0_RXD[0]
M0_RBC1
M0_RXD[0]
M0_RBC1
M0_RXD[0]
M0_RBC1
M0_RXD[0]
M0_RBC1
M0_RXD[0]
M0_RBC1
M0_RXD[0]
M0_RBC1
B8
Table 2 - ZL50115/16/17/18/19/20 Ball Signal Assignment
18
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
ZL50115
ZL50116
ZL50117
ZL50118
ZL50119
ZL50120
Ball #
Variant
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
B9
M0_RBC0
NC
M0_RBC0
NC
M0_RBC0
NC
M0_RBC0
M0_RBC0
M0_RBC0
All
C1
M1_TXD[3]
M0_RXCLK
M0_TXD[7]
M0_TXD[4]
M0_TXD[0]
VDD_IO
M1_TXD[3]
M0_RXCLK
M0_TXD[7]
M0_TXD[4]
M0_TXD[0]
VDD_IO
M1_TXD[3]
M0_RXCLK
M0_TXD[7]
M0_TXD[4]
M0_TXD[0]
VDD_IO
ZL50118/19/20
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C2
M0_RXCLK
M0_TXD[7]
M0_TXD[4]
M0_TXD[0]
VDD_IO
M0_RXCLK
M0_TXD[7]
M0_TXD[4]
M0_TXD[0]
VDD_IO
M0_RXCLK
M0_TXD[7]
M0_TXD[4]
M0_TXD[0]
VDD_IO
All
All
All
All
All
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
All
CPU_DATA[31]
NC
CPU_DATA[31]
NC
CPU_DATA[31]
NC
CPU_DATA[31]
M1_LINKUP_LED
CPU_DATA[29]
CPU_DATA[26]
VDD_IO
CPU_DATA[31]
M1_LINKUP_LED
CPU_DATA[29]
CPU_DATA[26]
VDD_IO
CPU_DATA[31]
M1_LINKUP_LED
CPU_DATA[29]
CPU_DATA[26]
VDD_IO
All
ZL50118/19/20
CPU_DATA[29]
CPU_DATA[26]
VDD_IO
CPU_DATA[29]
CPU_DATA[26]
VDD_IO
CPU_DATA[29]
CPU_DATA[26]
VDD_IO
All
All
All
GND
GND
GND
GND
GND
GND
All
CPU_DREQ1
GND
CPU_DREQ1
GND
CPU_DREQ1
GND
CPU_DREQ1
GND
CPU_DREQ1
GND
CPU_DREQ1
GND
All
All
C3
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
All
C4
NC
NC
NC
M1_RXCLK
M1_COL
M1_RXCLK
M1_COL
M1_RXCLK
M1_COL
ZL50118/19/20
C5
NC
NC
NC
ZL50118/19/20
C6
NC
NC
NC
M1_TXER
M1_TXER
M1_TXER
ZL50118/19/20
C7
M0_RXDV
M0_RXD[3]
M0_RXD[1]
NC
M0_RXDV
M0_RXD[3]
M0_RXD[1]
NC
M0_RXDV
M0_RXD[3]
M0_RXD[1]
NC
M0_RXDV
M0_RXD[3]
M0_RXD[1]
M1_RXD[1]
M0_RXD[2]
M0_REFCLK
M0_TXD[6]
M0_TXD[1]
VDD_CORE
VDD_CORE
VDD_IO
M0_RXDV
M0_RXD[3]
M0_RXD[1]
M1_RXD[1]
M0_RXD[2]
M0_REFCLK
M0_TXD[6]
M0_TXD[1]
VDD_CORE
VDD_CORE
VDD_IO
M0_RXDV
M0_RXD[3]
M0_RXD[1]
M1_RXD[1]
M0_RXD[2]
M0_REFCLK
M0_TXD[6]
M0_TXD[1]
VDD_CORE
VDD_CORE
VDD_IO
All
C8
All
C9
All
D1
ZL50118/19/20
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D2
M0_RXD[2]
M0_REFCLK
M0_TXD[6]
M0_TXD[1]
VDD_CORE
VDD_CORE
VDD_IO
M0_RXD[2]
M0_REFCLK
M0_TXD[6]
M0_TXD[1]
VDD_CORE
VDD_CORE
VDD_IO
M0_RXD[2]
M0_REFCLK
M0_TXD[6]
M0_TXD[1]
VDD_CORE
VDD_CORE
VDD_IO
All
All
All
All
All
All
All
M0_ACTIVE_LED
VDD_CORE
VDD_IO
M0_ACTIVE_LED
VDD_CORE
VDD_IO
M0_ACTIVE_LED
VDD_CORE
VDD_IO
M0_ACTIVE_LED
VDD_CORE
VDD_IO
M0_ACTIVE_LED
VDD_CORE
VDD_IO
M0_ACTIVE_LED
VDD_CORE
VDD_IO
All
All
All
CPU_DATA[25]
CPU_ADDR[23]
CPU_DATA[6]
NC
CPU_DATA[25]
CPU_ADDR[23]
CPU_DATA[6]
NC
CPU_DATA[25]
CPU_ADDR[23]
CPU_DATA[6]
NC
CPU_DATA[25]
CPU_ADDR[23]
CPU_DATA[6]
M1_RXD[0]
M1_RXD[2]
VDD_IO
CPU_DATA[25]
CPU_ADDR[23]
CPU_DATA[6]
M1_RXD[0]
M1_RXD[2]
VDD_IO
CPU_DATA[25]
CPU_ADDR[23]
CPU_DATA[6]
M1_RXD[0]
M1_RXD[2]
VDD_IO
All
All
All
ZL50118/19/20
D3
NC
NC
NC
ZL50118/19/20
D4
VDD_IO
VDD_IO
VDD_IO
All
D5
NC
NC
NC
M1_RXDV
M0_RXER
VDD_IO
M1_RXDV
M0_RXER
VDD_IO
M1_RXDV
M0_RXER
VDD_IO
ZL50118/19/20
D6
M0_RXER
VDD_IO
M0_RXER
VDD_IO
M0_RXER
VDD_IO
All
All
D7
Table 2 - ZL50115/16/17/18/19/20 Ball Signal Assignment (continued)
19
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
ZL50115
ZL50116
ZL50117
ZL50118
ZL50119
ZL50120
Ball #
Variant
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
D8
M0_RXD[5]
VDD_CORE
NC
M0_RXD[5]
VDD_CORE
NC
M0_RXD[5]
VDD_CORE
NC
M0_RXD[5]
VDD_CORE
M1_RXD[3]
CPU_DATA[30]
CPU_DATA[21]
CPU_DATA[15]
CPU_DATA[14]
M0_GIGABIT_LED
M1_TXCLK
M1_RXER
NC
M0_RXD[5]
VDD_CORE
M1_RXD[3]
CPU_DATA[30]
CPU_DATA[21]
CPU_DATA[15]
CPU_DATA[14]
M0_GIGABIT_LED
M1_TXCLK
M1_RXER
NC
M0_RXD[5]
VDD_CORE
M1_RXD[3]
CPU_DATA[30]
CPU_DATA[21]
CPU_DATA[15]
CPU_DATA[14]
M0_GIGABIT_LED
M1_TXCLK
M1_RXER
NC
All
D9
All
E1
ZL50118/19/20
E19
E20
E21
E22
E2
CPU_DATA[30]
CPU_DATA[21]
CPU_DATA[15]
CPU_DATA[14]
M0_GIGABIT_LED
NC
CPU_DATA[30]
CPU_DATA[21]
CPU_DATA[15]
CPU_DATA[14]
M0_GIGABIT_LED
NC
CPU_DATA[30]
CPU_DATA[21]
CPU_DATA[15]
CPU_DATA[14]
M0_GIGABIT_LED
NC
All
All
All
All
All
E3
ZL50118/19/20
E4
NC
NC
NC
ZL50118/19/20
F1
NC
NC
NC
All
F19
F20
F21
F22
F2
VDD_CORE
CPU_DATA[18]
CPU_DATA[17]
CPU_DATA[16]
NC
VDD_CORE
CPU_DATA[18]
CPU_DATA[17]
CPU_DATA[16]
NC
VDD_CORE
CPU_DATA[18]
CPU_DATA[17]
CPU_DATA[16]
NC
VDD_CORE
CPU_DATA[18]
CPU_DATA[17]
CPU_DATA[16]
M1_CRS
VDD_CORE
CPU_DATA[18]
CPU_DATA[17]
CPU_DATA[16]
M1_CRS
VDD_CORE
CPU_DATA[18]
CPU_DATA[17]
CPU_DATA[16]
M1_CRS
All
All
All
All
ZL50118/19/20
F3
DEVICE_ID[1]
VDD_CORE
M_MDIO
DEVICE_ID[1]
VDD_CORE
M_MDIO
DEVICE_ID[1]
VDD_CORE
M_MDIO
DEVICE_ID[1]
VDD_CORE
M_MDIO
DEVICE_ID[1]
VDD_CORE
M_MDIO
DEVICE_ID[1]
VDD_CORE
M_MDIO
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
F4
G1
G19
G20
G21
G22
G2
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
CPU_IREQ1
CPU_DATA[11]
CPU_DATA[0]
DEVICE_ID[0]
M0_LINKUP_LED
VDD_IO
CPU_IREQ1
CPU_DATA[11]
CPU_DATA[0]
DEVICE_ID[0]
M0_LINKUP_LED
VDD_IO
CPU_IREQ1
CPU_DATA[11]
CPU_DATA[0]
DEVICE_ID[0]
M0_LINKUP_LED
VDD_IO
CPU_IREQ1
CPU_DATA[11]
CPU_DATA[0]
DEVICE_ID[0]
M0_LINKUP_LED
VDD_IO
CPU_IREQ1
CPU_DATA[11]
CPU_DATA[0]
DEVICE_ID[0]
M0_LINKUP_LED
VDD_IO
CPU_IREQ1
CPU_DATA[11]
CPU_DATA[0]
DEVICE_ID[0]
M0_LINKUP_LED
VDD_IO
G3
G4
H1
M_MDC
M_MDC
M_MDC
M_MDC
M_MDC
M_MDC
H19
H20
H21
H22
H2
CPU_DATA[10]
CPU_DATA[1]
CPU_DATA[4]
IC
CPU_DATA[10]
CPU_DATA[1]
CPU_DATA[4]
IC
CPU_DATA[10]
CPU_DATA[1]
CPU_DATA[4]
IC
CPU_DATA[10]
CPU_DATA[1]
CPU_DATA[4]
IC
CPU_DATA[10]
CPU_DATA[1]
CPU_DATA[4]
IC
CPU_DATA[10]
CPU_DATA[1]
CPU_DATA[4]
IC
GND
GND
GND
GND
GND
GND
H3
NC
NC
NC
NC
NC
NC
H4
VDD_CORE
NC
VDD_CORE
NC
VDD_CORE
NC
VDD_CORE
NC
VDD_CORE
NC
VDD_CORE
NC
J1
J10
J11
J12
J13
J14
J19
J20
J21
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_CORE
CPU_DATA[5]
CPU_DATA[3]
VDD_CORE
CPU_DATA[5]
CPU_DATA[3]
VDD_CORE
CPU_DATA[5]
CPU_DATA[3]
VDD_CORE
CPU_DATA[5]
CPU_DATA[3]
VDD_CORE
CPU_DATA[5]
CPU_DATA[3]
VDD_CORE
CPU_DATA[5]
CPU_DATA[3]
Table 2 - ZL50115/16/17/18/19/20 Ball Signal Assignment (continued)
20
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
ZL50115
ZL50116
ZL50117
ZL50118
ZL50119
ZL50120
Ball #
Variant
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
J22
J2
CPU_IREQ0
NC
CPU_IREQ0
NC
CPU_IREQ0
NC
CPU_IREQ0
NC
CPU_IREQ0
NC
CPU_IREQ0
NC
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
ZL50117/20
All
All
All
All
All
All
All
All
All
J3
NC
NC
NC
NC
NC
NC
J4
VDD_CORE
GND
VDD_CORE
GND
VDD_CORE
GND
VDD_CORE
GND
VDD_CORE
GND
VDD_CORE
GND
J9
K1
NC
NC
NC
NC
NC
NC
K10
K11
K12
K13
K14
K19
K20
K21
K22
K2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CPU_DATA[2]
IC
CPU_DATA[2]
IC
CPU_DATA[2]
IC
CPU_DATA[2]
IC
CPU_DATA[2]
IC
CPU_DATA[2]
IC
CPU_DREQ0
NC
CPU_DREQ0
NC
CPU_DREQ0
NC
CPU_DREQ0
NC
CPU_DREQ0
NC
CPU_DREQ0
NC
K3
NC
NC
NC
NC
NC
NC
K4
VDD_IO
GND
VDD_IO
GND
VDD_IO
GND
VDD_IO
GND
VDD_IO
GND
VDD_IO
GND
K9
L1
GND
GND
GND
GND
GND
GND
L10
L11
L12
L13
L14
L19
L20
L21
L22
L2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CPU_CLK
GND
CPU_CLK
GND
CPU_CLK
GND
CPU_CLK
GND
CPU_CLK
GND
CPU_CLK
GND
CPU_SDACK2
IC_VDD_IO
AUX_CLKO
AUX_CLKI
VDD_CORE
GND
CPU_SDACK2
IC_VDD_IO
AUX_CLKO
AUX_CLKI
VDD_CORE
GND
CPU_SDACK2
IC_VDD_IO
AUX_CLKO
AUX_CLKI
VDD_CORE
GND
CPU_SDACK2
IC_VDD_IO
AUX_CLKO
AUX_CLKI
VDD_CORE
GND
CPU_SDACK2
IC_VDD_IO
AUX_CLKO
AUX_CLKI
VDD_CORE
GND
CPU_SDACK2
IC_VDD_IO
AUX_CLKO
AUX_CLKI
VDD_CORE
GND
L3
L4
L9
M1
NC
NC
TDM_CLKI[3]
GND
NC
NC
TDM_CLKI[3]
GND
M10
M11
M12
M13
M14
M19
M20
M21
M22
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CPU_TS_ALE
CPU_WE
CPU_OE
CPU_TS_ALE
CPU_WE
CPU_OE
CPU_TS_ALE
CPU_WE
CPU_OE
CPU_TS_ALE
CPU_WE
CPU_OE
CPU_TS_ALE
CPU_WE
CPU_OE
CPU_TS_ALE
CPU_WE
CPU_OE
Table 2 - ZL50115/16/17/18/19/20 Ball Signal Assignment (continued)
21
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
ZL50115
ZL50116
ZL50117
ZL50118
ZL50119
ZL50120
Ball #
Variant
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
M2
NC
NC
TDM_STO[3]
TDM_STI[3]
VDD_IO
NC
NC
TDM_STO[3]
TDM_STI[3]
VDD_IO
ZL50117/20
M3
NC
NC
NC
NC
ZL50117/20
M4
VDD_IO
GND
VDD_IO
GND
VDD_IO
GND
VDD_IO
GND
All
M9
GND
GND
All
N1
NC
NC
TDM_STO[2]
GND
NC
NC
TDM_STO[2]
GND
ZL50117/20
N10
N11
N12
N13
N14
N19
N20
N21
N22
N2
GND
GND
GND
GND
All
GND
GND
GND
GND
GND
GND
All
GND
GND
GND
GND
GND
GND
All
GND
GND
GND
GND
GND
GND
All
GND
GND
GND
GND
GND
GND
All
VDD_IO
CPU_ADDR[22]
CPU_CS
CPU_ADDR[19]
NC
VDD_IO
CPU_ADDR[22]
CPU_CS
CPU_ADDR[19]
NC
VDD_IO
VDD_IO
CPU_ADDR[22]
CPU_CS
CPU_ADDR[19]
NC
VDD_IO
CPU_ADDR[22]
CPU_CS
CPU_ADDR[19]
NC
VDD_IO
All
CPU_ADDR[22]
CPU_CS
CPU_ADDR[22]
CPU_CS
All
All
CPU_ADDR[19]
TDM_CLKO[3]
TDM_STI[2]
VDD_CORE
GND
CPU_ADDR[19]
TDM_CLKO[3]
TDM_STI[2]
VDD_CORE
GND
All
ZL50117/20
N3
NC
NC
NC
NC
ZL50117/20
N4
VDD_CORE
GND
VDD_CORE
GND
VDD_CORE
GND
VDD_CORE
GND
All
N9
All
P1
NC
NC
TDM_CLKI[2]
GND
NC
NC
TDM_CLKI[2]
GND
ZL50117/20
P10
P11
P12
P13
P14
P19
P20
P21
P22
P2
GND
GND
GND
GND
All
GND
GND
GND
GND
GND
GND
All
GND
GND
GND
GND
GND
GND
All
GND
GND
GND
GND
GND
GND
All
GND
GND
GND
GND
GND
GND
All
VDD_CORE
CPU_ADDR[17]
CPU_ADDR[18]
CPU_ADDR[21]
GND
VDD_CORE
CPU_ADDR[17]
CPU_ADDR[18]
CPU_ADDR[21]
GND
VDD_CORE
CPU_ADDR[17]
CPU_ADDR[18]
CPU_ADDR[21]
GND
VDD_CORE
CPU_ADDR[17]
CPU_ADDR[18]
CPU_ADDR[21]
GND
VDD_CORE
CPU_ADDR[17]
CPU_ADDR[18]
CPU_ADDR[21]
GND
VDD_CORE
CPU_ADDR[17]
CPU_ADDR[18]
CPU_ADDR[21]
GND
All
All
All
All
All
P3
VDD_IO
VDD_CORE
GND
VDD_IO
VDD_CORE
GND
VDD_IO
VDD_IO
VDD_CORE
GND
VDD_IO
VDD_CORE
GND
VDD_IO
All
P4
VDD_CORE
GND
VDD_CORE
GND
All
P9
All
R1
NC
NC
TDM_CLKO[2]
GND
NC
NC
TDM_CLKO[2]
GND
ZL50117/20
R19
R20
R21
R22
R2
GND
GND
GND
GND
All
CPU_ADDR[11]
CPU_ADDR[13]
CPU_ADDR[20]
NC
CPU_ADDR[11]
CPU_ADDR[13]
CPU_ADDR[20]
TDM_STI[1]
TDM_CLKI[0]
TDM_STO[1]
TDM_CLKI[1]
VDD_IO
VDD_IO
CPU_ADDR[11]
CPU_ADDR[13]
CPU_ADDR[20]
TDM_STI[1]
TDM_CLKI[0]
TDM_STO[1]
TDM_CLKI[1]
VDD_IO
CPU_ADDR[11]
CPU_ADDR[13]
CPU_ADDR[20]
NC
CPU_ADDR[11]
CPU_ADDR[13]
CPU_ADDR[20]
TDM_STI[1]
TDM_CLKI[0]
TDM_STO[1]
TDM_CLKI[1]
VDD_IO
VDD_IO
CPU_ADDR[11]
CPU_ADDR[13]
CPU_ADDR[20]
TDM_STI[1]
TDM_CLKI[0]
TDM_STO[1]
TDM_CLKI[1]
VDD_IO
All
All
All
ZL50116/17/19/20
R3
TDM_CLKI[0]
NC
TDM_CLKI[0]
NC
All
R4
ZL50116/17/19/20
T1
NC
NC
ZL50116/17/19/20
T19
T20
VDD_IO
VDD_IO
VDD_IO
VDD_IO
All
All
VDD_IO
VDD_IO
Table 2 - ZL50115/16/17/18/19/20 Ball Signal Assignment (continued)
22
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
ZL50115
ZL50116
ZL50117
ZL50118
ZL50119
ZL50120
Ball #
Variant
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
T21
T22
T2
CPU_ADDR[14]
CPU_ADDR[16]
NC
CPU_ADDR[14]
CPU_ADDR[16]
TDM_CLKO[1]
TDM_FRMI_REF
VDD_IO
CPU_ADDR[14]
CPU_ADDR[16]
TDM_CLKO[1]
TDM_FRMI_REF
VDD_IO
CPU_ADDR[14]
CPU_ADDR[16]
NC
CPU_ADDR[14]
CPU_ADDR[16]
TDM_CLKO[1]
TDM_FRMI_REF
VDD_IO
CPU_ADDR[14]
CPU_ADDR[16]
TDM_CLKO[1]
TDM_FRMI_REF
VDD_IO
All
All
ZL50116/17/19/20
T3
TDM_FRMI_REF
VDD_IO
TDM_FRMI_REF
VDD_IO
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
T4
U1
TDM_STI[0]
VDD_CORE
JTAG_TMS
CPU_ADDR[15]
CPU_ADDR[12]
VDD_IO
TDM_STI[0]
VDD_CORE
JTAG_TMS
CPU_ADDR[15]
CPU_ADDR[12]
VDD_IO
TDM_STI[0]
VDD_CORE
JTAG_TMS
CPU_ADDR[15]
CPU_ADDR[12]
VDD_IO
TDM_STI[0]
VDD_CORE
JTAG_TMS
CPU_ADDR[15]
CPU_ADDR[12]
VDD_IO
TDM_STI[0]
VDD_CORE
JTAG_TMS
CPU_ADDR[15]
CPU_ADDR[12]
VDD_IO
TDM_STI[0]
VDD_CORE
JTAG_TMS
CPU_ADDR[15]
CPU_ADDR[12]
VDD_IO
U19
U20
U21
U22
U2
U3
GND
GND
GND
GND
GND
GND
U4
TDM_CLKiS
TDM_STO[0]
DEVICE_ID[3]
JTAG_TCK
CPU_ADDR[10]
CPU_ADDR[9]
TDM_CLKO[0]
TDM_CLKO_REF
TDM_CLKiP
IC
TDM_CLKiS
TDM_STO[0]
DEVICE_ID[3]
JTAG_TCK
CPU_ADDR[10]
CPU_ADDR[9]
TDM_CLKO[0]
TDM_CLKO_REF
TDM_CLKiP
IC
TDM_CLKiS
TDM_STO[0]
DEVICE_ID[3]
JTAG_TCK
CPU_ADDR[10]
CPU_ADDR[9]
TDM_CLKO[0]
TDM_CLKO_REF
TDM_CLKiP
IC
TDM_CLKiS
TDM_STO[0]
DEVICE_ID[3]
JTAG_TCK
CPU_ADDR[10]
CPU_ADDR[9]
TDM_CLKO[0]
TDM_CLKO_REF
TDM_CLKiP
IC
TDM_CLKiS
TDM_STO[0]
DEVICE_ID[3]
JTAG_TCK
CPU_ADDR[10]
CPU_ADDR[9]
TDM_CLKO[0]
TDM_CLKO_REF
TDM_CLKiP
IC
TDM_CLKiS
TDM_STO[0]
DEVICE_ID[3]
JTAG_TCK
CPU_ADDR[10]
CPU_ADDR[9]
TDM_CLKO[0]
TDM_CLKO_REF
TDM_CLKiP
IC
V1
V19
V20
V21
V22
V2
V3
V4
W1
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W2
PLL_SEC
PLL_SEC
PLL_SEC
PLL_SEC
PLL_SEC
PLL_SEC
IC_GND
IC_GND
IC_GND
IC_GND
IC_GND
IC_GND
GND
GND
GND
GND
GND
GND
SYSTEM_CLK
VDD_CORE
GPIO[9]
SYSTEM_CLK
VDD_CORE
GPIO[9]
SYSTEM_CLK
VDD_CORE
GPIO[9]
SYSTEM_CLK
VDD_CORE
GPIO[9]
SYSTEM_CLK
VDD_CORE
GPIO[9]
SYSTEM_CLK
VDD_CORE
GPIO[9]
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
GPIO[15]
GPIO[15]
GPIO[15]
GPIO[15]
GPIO[15]
GPIO[15]
DEVICE_ID[2]
VDD_IO
DEVICE_ID[2]
VDD_IO
DEVICE_ID[2]
VDD_IO
DEVICE_ID[2]
VDD_IO
DEVICE_ID[2]
VDD_IO
DEVICE_ID[2]
VDD_IO
JTAG_TDO
CPU_ADDR[4]
CPU_ADDR[8]
TDM_CLKI_REF
TDM_FRMO_REF
VDD_IO
JTAG_TDO
CPU_ADDR[4]
CPU_ADDR[8]
TDM_CLKI_REF
TDM_FRMO_REF
VDD_IO
JTAG_TDO
CPU_ADDR[4]
CPU_ADDR[8]
TDM_CLKI_REF
TDM_FRMO_REF
VDD_IO
JTAG_TDO
CPU_ADDR[4]
CPU_ADDR[8]
TDM_CLKI_REF
TDM_FRMO_REF
VDD_IO
JTAG_TDO
CPU_ADDR[4]
CPU_ADDR[8]
TDM_CLKI_REF
TDM_FRMO_REF
VDD_IO
JTAG_TDO
CPU_ADDR[4]
CPU_ADDR[8]
TDM_CLKI_REF
TDM_FRMO_REF
VDD_IO
W3
W4
W5
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
W6
VDD_CORE
VDD_IO
VDD_CORE
VDD_IO
VDD_CORE
VDD_IO
VDD_CORE
VDD_IO
VDD_CORE
VDD_IO
VDD_CORE
VDD_IO
W7
W8
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
W9
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
Table 2 - ZL50115/16/17/18/19/20 Ball Signal Assignment (continued)
23
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
ZL50115
ZL50116
ZL50117
ZL50118
ZL50119
ZL50120
Ball #
Variant
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
Y1
IC
IC
IC
IC
IC
IC
IC
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
Y10
Y11
IC
IC
IC
IC
IC
IC_GND
IC
IC_GND
IC
IC_GND
IC
IC_GND
IC
IC_GND
IC
IC_GND
IC
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GPIO[8]
GPIO[14]
TEST_MODE[1]
JTAG_TRST
IC_GND
VDD_IO
GND
GPIO[8]
GPIO[14]
TEST_MODE[1]
JTAG_TRST
IC_GND
VDD_IO
GND
GPIO[8]
GPIO[14]
TEST_MODE[1]
JTAG_TRST
IC_GND
VDD_IO
GND
GPIO[8]
GPIO[14]
TEST_MODE[1]
JTAG_TRST
IC_GND
VDD_IO
GND
GPIO[8]
GPIO[14]
TEST_MODE[1]
JTAG_TRST
IC_GND
VDD_IO
GND
GPIO[8]
GPIO[14]
TEST_MODE[1]
JTAG_TRST
IC_GND
VDD_IO
GND
CPU_ADDR[7]
GND
CPU_ADDR[7]
GND
CPU_ADDR[7]
GND
CPU_ADDR[7]
GND
CPU_ADDR[7]
GND
CPU_ADDR[7]
GND
Y3
VDD_IO
IC
VDD_IO
IC
VDD_IO
IC
VDD_IO
IC
VDD_IO
IC
VDD_IO
IC
Y4
Y5
IC
IC
IC
IC
IC
IC
Y6
VDD_CORE
IC
VDD_CORE
IC
VDD_CORE
IC
VDD_CORE
IC
VDD_CORE
IC
VDD_CORE
IC
Y7
Y8
IC
IC
IC
IC
IC
IC
Y9
PLL_PRI
IC
PLL_PRI
IC
PLL_PRI
IC
PLL_PRI
IC
PLL_PRI
IC
PLL_PRI
IC
AA1
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA2
AA3
AA4
AA5
AA6
AA7
AA8
IC
IC
IC
IC
IC
IC
SYSTEM_DEBUG
SYSTEM_RST
GPIO[1]
GPIO[2]
GPIO[7]
GPIO[12]
TEST_MODE[0]
JTAG_TDI
IC_GND
GND
SYSTEM_DEBUG
SYSTEM_RST
GPIO[1]
GPIO[2]
GPIO[7]
GPIO[12]
TEST_MODE[0]
JTAG_TDI
IC_GND
GND
SYSTEM_DEBUG
SYSTEM_RST
GPIO[1]
GPIO[2]
GPIO[7]
GPIO[12]
TEST_MODE[0]
JTAG_TDI
IC_GND
GND
SYSTEM_DEBUG
SYSTEM_RST
GPIO[1]
GPIO[2]
GPIO[7]
GPIO[12]
TEST_MODE[0]
JTAG_TDI
IC_GND
GND
SYSTEM_DEBUG
SYSTEM_RST
GPIO[1]
GPIO[2]
GPIO[7]
GPIO[12]
TEST_MODE[0]
JTAG_TDI
IC_GND
GND
SYSTEM_DEBUG
SYSTEM_RST
GPIO[1]
GPIO[2]
GPIO[7]
GPIO[12]
TEST_MODE[0]
JTAG_TDI
IC_GND
GND
VDD_IO
CPU_ADDR[6]
VDD_IO
GND
VDD_IO
CPU_ADDR[6]
VDD_IO
GND
VDD_IO
CPU_ADDR[6]
VDD_IO
GND
VDD_IO
CPU_ADDR[6]
VDD_IO
GND
VDD_IO
CPU_ADDR[6]
VDD_IO
GND
VDD_IO
CPU_ADDR[6]
VDD_IO
GND
VDD_IO
VDD_IO
IC
VDD_IO
VDD_IO
IC
VDD_IO
VDD_IO
IC
VDD_IO
VDD_IO
IC
VDD_IO
VDD_IO
IC
VDD_IO
VDD_IO
IC
GND
GND
GND
GND
GND
GND
A1VDD_PLL1
A1VDD_PLL1
A1VDD_PLL1
A1VDD_PLL1
A1VDD_PLL1
A1VDD_PLL1
Table 2 - ZL50115/16/17/18/19/20 Ball Signal Assignment (continued)
24
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
ZL50115
ZL50116
ZL50117
ZL50118
ZL50119
ZL50120
Ball #
Variant
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
Signal Name
AA9
IC
IC
IC
IC
IC
IC
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
AB1
VDD_IO
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10]
GPIO[11]
GPIO[13]
TEST_MODE[2]
IC_GND
CPU_ADDR[2]
CPU_ADDR[3]
CPU_ADDR[5]
VDD_IO
IC
VDD_IO
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10]
GPIO[11]
GPIO[13]
TEST_MODE[2]
IC_GND
CPU_ADDR[2]
CPU_ADDR[3]
CPU_ADDR[5]
VDD_IO
IC
VDD_IO
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10]
GPIO[11]
GPIO[13]
TEST_MODE[2]
IC_GND
CPU_ADDR[2]
CPU_ADDR[3]
CPU_ADDR[5]
VDD_IO
IC
VDD_IO
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10]
GPIO[11]
GPIO[13]
TEST_MODE[2]
IC_GND
CPU_ADDR[2]
CPU_ADDR[3]
CPU_ADDR[5]
VDD_IO
IC
VDD_IO
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10]
GPIO[11]
GPIO[13]
TEST_MODE[2]
IC_GND
CPU_ADDR[2]
CPU_ADDR[3]
CPU_ADDR[5]
VDD_IO
IC
VDD_IO
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[10]
GPIO[11]
GPIO[13]
TEST_MODE[2]
IC_GND
CPU_ADDR[2]
CPU_ADDR[3]
CPU_ADDR[5]
VDD_IO
IC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB2
AB3
IC
IC
IC
IC
IC
IC
AB4
IC
IC
IC
IC
IC
IC
AB5
GND
GND
GND
GND
GND
GND
AB6
IC
IC
IC
IC
IC
IC
AB7
IC
IC
IC
IC
IC
IC
AB8
IC
IC
IC
IC
IC
IC
AB9
GPIO[0]
GPIO[0]
GPIO[0]
GPIO[0]
GPIO[0]
GPIO[0]
Table 2 - ZL50115/16/17/18/19/20 Ball Signal Assignment (continued)
NC - Not Connected - leave open circuit.
IC - Internally Connected - leave open circuit.
IC_GND - Internally Connected - tie to ground
IC_VDD_IO - Internally Connected - tie to VDD_IO
25
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
4.0 External Interface Description
The following key applies to all tables:
I
Input
O
D
U
T
Output
Internal 100 kΩ pull-down resistor present
Internal 100 kΩ pull-up resistor present
Tri-state Output
4.1 TDM Interface
All TDM Interface signals are 5 V tolerant.
All TDM Interface outputs are high impedance while System Reset is LOW.
All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be
safely left unconnected if not used.
4.1.1 TDM stream connections
There are three interfaces possible among the ZL5011x.
The ZL50117/20 supports four TDM ports [3:0] at 2 Mbps, or one TDM port [0] at 8 Mbps or one unstructured TDM
port [0] for J2/E3/T3/STS-1.
The ZL50116/19 supports two TDM ports [1:0] at 2 Mbps, or one TDM port [0] at 8 Mbps (up to 64 DS0).
The ZL50115/18 supports one TDM port [0] at 2 Mbps, or one TDM port [0] at 8 Mbps (up to 32 DS0)
Signal
I/O
Package Balls
Description
TDM_STi[3:0]
I D [3]
[2]
M3
N3
R2
U1
TDM port serial data input streams. For
different standards these pins are given
different identities:
[1]
[0]
ST-BUS: TDM_STi[3:0]
H.110: TDM_D[3:0]
H-MVIP: TDM_HDS[3:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
stream [0] is used. Stream [0] is used for
unstructured J2, T3/E3 or STS-1 on the
ZL50117/20.
Table 3 - TDM Interface Stream Pin Definition
26
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
Signal
I/O
Package Balls
Description
TDM_STo[3:0]
OT [3]
M2
N1
R4
V1
TDM port serial data output streams. For
different standards these pins are given
different identities:
[2]
[1]
[0]
ST-BUS: TDM_STo[3:0]
H.110:
TDM_D[3:0]
H-MVIP: TDM_HDS[3:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
stream [0] is used. Stream [0] is used for
unstructured J2, T3/E3 or STS-1 on the
ZL50117/20.
TDM_CLKi[3:0]
TDM_CLKo[3:0]
Note: Speed modes:
I D [3]
[2]
M1
P1
T1
R3
TDM port clock inputs programmable as
active high or low. Can accept frequencies of
1.544 MHz, 2.048 MHz, 4.096 MHz,
8.192 MHz, 6.312 MHz or 16.384 MHz
depending on standard used. At 8.192 Mbps
only stream [0] is used. Stream [0] is used
for unstructured J2, T3/E3 or STS-1 on the
ZL50117/20.
[1]
[0]
OT [3]
N2
R1
T2
V2
TDM port clock outputs. Will generate
1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz or 16.384 MHz
depending on standard used. At 8.192 Mbps
only stream [0] is used. Stream [0] is used
for unstructured J2, T3/E3 or STS-1 on the
ZL50117/20.
[2]
[1]
[0]
Table 3 - TDM Interface Stream Pin Definition
2.048 Mbps - 32 channels per stream.
8.192 Mbps - 128 channels per stream.
J2 - 98 channels per stream
E3 - 537 channels per stream
T3 - 699 channels per stream
Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left
unconnected if not used.
27
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
4.1.2 TDM Signals common to ZL50115/16/17/18/19/20
Signal
I/O
Package Balls
Description
TDM_CLKi_REF
I D W2
TDM port reference clock input for
backplane operation
TDM_CLKo_REF
TDM_FRMi_REF
O
V3
TDM port reference clock output for
backplane operation
I D T3
TDM port reference frame input. For
different standards this pin is given a
different identity:
ST-BUS: TDM_F0i
H.110:
TDM_FRAME
H-MVIP: TDM_F0
Signal is normally active low, but can be
active high depending on standard.
Indicates the start of a TDM frame by
pulsing every 125 µs. Normally will straddle
rising edge or falling edge of clock pulse,
depending on standard and clock frequency.
TDM_FRMo_REF
O
W3
TDM port reference frame output. For
different standards this pin is given a
different identity:
ST-BUS: TDM_F0o
H.110:
TDM_FRAME
H-MVIP: TDM_F0
Signal is normally active low, but can be
active high depending on standard.
Indicates the start of a TDM frame by
pulsing every 125 µs. Normally will straddle
rising edge or falling edge of clock pulse,
depending on standard and clock frequency.
AUX_CLKI
I D L3
OT L2
Auxiliary clock input. Typically connected to
AUX_CLKO.
AUX_CLKO
Auxiliary clock output. Typically connected
to AUX_CLKI.
Table 4 - TDM Interface Common Pin Definition
28
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
4.2 PAC Interface
All PAC Interface signals are 5 V tolerant.
All PAC Interface outputs are high impedance while System Reset is LOW.
Signal
I/O
Package Balls
Description
TDM_CLKiP
I D V4
Primary reference clock input. Should be
driven by external clock source to provide
locking reference to internal / optional
external DPLL in TDM master mode. Also
provides PRS clock for RTP timestamps in
synchronous modes.
Acceptable frequency range: 8 kHz -
34.368 MHz.
TDM_CLKiS
PLL_PRI
I D U4
OT Y9
Secondary reference clock input. Backup
external reference for automatic switch-over
in case of failure of TDM_CLKiP source.
Primary reference output to optional
external DPLL.
Multiplexed & frequency divided reference
output for support of optional external DPLL.
Expected frequency range:
8 kHz - 16.384 MHz.
PLL_SEC
OT W10
Secondary reference output to optional
external DPLL Multiplexed & frequency
divided reference output for support of
optional external DPLL.
Expected frequency range:
8 kHz - 16.384 MHz.
Table 5 - PAC Interface Package Ball Definition
29
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
4.3 Packet Interfaces
For the ZL50118/19/20 variants the packet interface is capable of either 2 MII interfaces, or 1 MII and 1 GMII
interfaces, or 1 MII and 1 TBI (1000 Mbps) interfaces. The TBI interface is a PCS interface supported by an
integrated 1000BASE-X PCS module. The ZL50118/19/20 supports Port 0 and Port 1.
For the ZL50115/16/17 variants the packet interface is capable of 1 MII or 1 GMII or 1 TBI (1000 Mbps) interface.
The TBI interface is a PCS interface supported by an integrated 1000BASE-X PCS module. The ZL50115/16/17
supports Port 0.
Data for all three types of packet switching is based on Specification IEEE Std. 802.3 - 2000. Only Port 0 has the
1000 Mbps capability necessary for the GMII/TBI interface.
Table 6 maps the signal pins used in the MII interface to those used in the GMII and TBI interface. Table 7 shows all
the pins and their related package ball, but is based on the GMII/MII configuration.
All Packet Interface signals are 5V tolerant, and all outputs are high impedance while System Reset is LOW.
MII
GMII
TBI (PCS)
Mn_LINKUP_LED
Mn_ACTIVE_LED
-
Mn_LINKUP_LED
Mn_ACTIVE_LED
Mn_GIGABIT_LED
Mn_REFCLK
Mn_RXCLK
Mn_COL
Mn_LINKUP_LED
Mn_ACTIVE_LED
Mn_GIGABIT_LED
Mn_REFCLK
Mn_RBC0
-
Mn_RXCLK
Mn_COL
Mn_RBC1
Mn_RXD[3:0]
Mn_RXDV
Mn_RXER
Mn_CRS
Mn_TXCLK
Mn_TXD[3:0]
Mn_TXEN
Mn_TXER
-
Mn_RXD[7:0]
Mn_RXDV
Mn_RXD[7:0]
Mn_RXD[8]
Mn_RXER
Mn_RXD[9]
Mn_CRS
Mn_Signal_Detect
-
-
Mn_TXD[7:0]
Mn_TXEN
Mn_TXD[7:0]
Mn_TXD[8]
Mn_TXER
Mn_TXD[9]
Mn_GTX_CLK
Mn_GTX_CLK
Table 6 - Packet Interface Signal Mapping - MII to GMII/TBI
Note: Mn can be either M0 or M1 for ZL5011x variants.
30
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
Signal
M_MDC
I/O
Package Balls
Description
O
H1
MII management data clock. Common for all
four MII ports. It has a minimum period of
400 ns (maximum freq. 2.5 MHz), and is
independent of the TXCLK and RXCLK.
M_MDIO
ID/ G1
OT
MII management data I/O. Common for all
four MII ports at up to 2.5 MHz. It is
bi-directional between the ZL5011x and the
Ethernet station management entity. Data is
passed synchronously with respect to
M_MDC.
Table 7 - MII Management Interface Package Ball Definition
MII Port 0
Signal
I/O
Package Balls
Description
M0_LINKUP_LED
M0_ACTIVE_LED
M0_GIGABIT_LED
M0_REFCLK
O
G3
D17
E2
LED drive for MAC 0 to indicate port is linked
up.
Logic 0 output = LED on
Logic 1 output = LED off
O
O
LED drive for MAC 0 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
LED drive for MAC 0 to indicate operation at
Gbps.
Logic 0 output = LED on
Logic 1 output = LED off
I D D11
GMII/TBI - Reference Clock input at
125 MHz. Can be used to lock receive
circuitry (RX) to M0_GTXCLK rather than
recovering the RXCLK (or RBC0 and
RBC1). Useful, for example, in the absence
of valid serial data.
NOTE: In MII mode this pin must be driven
with the same clock as M0_RXCLK.
M0_RXCLK
I U C10
GMII/MII - M0_RXCLK.
Accepts the following frequencies:
25.0 MHz
MII 100 Mbps
GMII 1 Gbps
125.0 MHz
Table 8 - MII Port 0 Interface Package Ball Definition
31
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
MII Port 0
Signal
M0_RBC0
I/O
Package Balls
Description
TBI - M0_RBC0.
I U B9
Used as a clock when in TBI mode. Accepts
62.5 MHz and is 180°C out of phase with
M0_RBC1. Receive data is clocked at
each rising edge of M0_RBC1 and
M0_RBC0, resulting in 125 MHz sample
rate.
M0_RBC1
M0_COL
I U B8
TBI - M0_RBC1
Used as a clock when in TBI mode. Accepts
62.5 MHz, and is 180° out of phase with
M0_RBC0. Receive data is clocked at each
rising edge of M0_RBC1 and M0_RBC0,
resulting in 125 MHz sample rate.
I D A7
GMII/MII - M0_COL.
Collision Detection. This signal is
independent of M0_TXCLK and
M0_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
M0_RXD[7:0]
I U [7]
[6]
A4
A5
D8
A6
[3]
[2]
[1]
[0]
C8
D10
C9
B7
Receive Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M0_RXCLK (GMII/MII) or the rising
edges of M0_RBC0 and M0_RBC1 (TBI).
[5]
[4]
M0_RXDV /
M0_RXD[8]
I D C7
GMII/MII - M0_RXDV
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M0_RXCLK.
It is asserted when valid data is on the
M0_RXD bus.
TBI - M0_RXD[8]
Receive Data. Clocked on the rising edges
of M0_RBC0 and M0_RBC1.
M0_RXER /
M0_RXD[9]
I D D6
GMII/MII - M0_RXER
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M0_RXDV is asserted. Can be used in
conjunction with M0_RXD when M0_RXDV
signal is de-asserted to indicate a False
Carrier.
TBI - M0_RXD[9]
Receive Data. Clocked on the rising edges
of M0_RBC0 and M0_RBC1.
Table 8 - MII Port 0 Interface Package Ball Definition (continued)
32
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
MII Port 0
Signal
I/O
Package Balls
Description
GMII/MII - M0_CRS
M0_CRS /
I D B6
M0_Signal_Detect
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active high.
TBI - M0_Signal Detect
Similar function to M0_CRS.
M0_TXCLK
I U A3
MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz
MII 100 Mbps
M0_TXD[7:0]
O
O
[7]
[6]
[5]
[4]
C11
D12
B12
C12
[3]
[2]
[1]
[0]
B13
B14
D13
C13
Transmit Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M0_TXCLK (MII) or the rising edge
of M0_GTXCLK (GMII/TBI).
M0_TXEN /
M0_TXD[8]
A9
GMII/MII - M0_TXEN
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M0_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
TBI - M0_TXD[8]
Transmit Data. Clocked on rising edge of
M0_GTXCLK.
M0_TXER /
M0_TXD[9]
O
O
B10
GMII/MII - M0_TXER
Transmit Error. Transmitted synchronously
with respect to M0_TXCLK, and active high.
When asserted (with M0_TXEN also
asserted) the ZL5011x will transmit a
non-valid symbol, somewhere in the
transmitted frame.
TBI - M0_TXD[9]
Transmit Data. Clocked on rising edge of
M0_GTXCLK.
M0_GTX_CLK
A8
GMII/TBI only - Gigabit Transmit Clock
Output of a clock for Gigabit operation at
125 MHz.
Table 8 - MII Port 0 Interface Package Ball Definition (continued)
33
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
MII Port 1 (ZL50118/19/20 only)
Package Balls
Signal
I/O
Description
M1_LINKUP_LED
O
C17
B15
LED drive for MAC 1 to indicate port is
linked up.
Logic 0 output = LED on
Logic 1 output = LED off
M1_ACTIVE_LED
O
LED drive for MAC 1 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
M1_RXCLK
M1_COL
I U C4
I D C5
MII only - Receive Clock.
Accepts the following frequencies:
25.0 MHz
MII 100 Mbps
Collision Detection. This signal is
independent of M1_TXCLK and
M1_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
M1_RXD[3:0]
M1_RXDV
I U [3]
[2]
E1
D3
[1]
[0]
D1
D2
Receive Data. Clocked on rising edge of
M1_RXCLK.
I D D5
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M1_RXCLK.
It is asserted when valid data is on the
M1_RXD bus.
M1_RXER
I D E4
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M1_RXDV is asserted. Can be used
in conjunction with M1_RXD when
M1_RXDV signal is de-asserted to indicate
a False Carrier.
M1_CRS
I D F2
I U E3
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active
high.
M1_TXCLK
MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz
MII 100 Mbps
M1_TXD[3:0]
M1_TXEN
O
O
[3]
[2]
C1
B1
[1]
[0]
B5
B4
Transmit Data. Clocked on rising edge of
M1_TXCLK.
A2
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M1_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
Table 9 - MII Port 1 Interface Package Ball Definition
34
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
MII Port 1 (ZL50118/19/20 only)
Package Balls
Signal
M1_TXER
I/O
Description
O
C6
Transmit Error. Transmitted synchronously
with respect to M1_TXCLK, and active high.
When asserted (with M1_TXEN also
asserted) the ZL5011x will transmit a
non-valid symbol, somewhere in the
transmitted frame.
Table 9 - MII Port 1 Interface Package Ball Definition (continued)
4.4 CPU Interface
All CPU Interface signals are 5 V tolerant.
All CPU Interface outputs are high impedance while System Reset is LOW.
Signal
I/O
Package Balls
Description
CPU_DATA[31:0]
I/
OT
[31] C16
[15] E21
[14] E22
[13] B19
[12] A17
[11] G21
[10] H19
CPU Data Bus. Bi-directional data bus,
synchronously transmitted with
CPU_CLK rising edge.
[30] E19
[29] C18
[28] A11
[27] B16
[26] C19
[25] D20
[24] A12
[23] A14
[22] B17
[21] E20
[20] B18
[19] A16
[18] F20
[17] F21
[16] F22
NOTE: as with all ports in the ZL5011x
device, CPU_DATA[0] is the least
significant bit (lsb).
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
A18
A19
A20
D22
J20
H21
J21
K20
H20
G22
CPU_ADDR[23:2]
I
[23] D21
[22] N20
[21] P22
[20] R22
[19] N22
[18] P21
[17] P20
[16] T22
[15] U21
[14] T21
[13] R21
[12] U22
[11] R20
[10] V21
CPU Address Bus. Address input from
processor to ZL5011x, synchronously
transmitted with CPU_CLK rising edge.
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
V22
W22
Y22
NOTE: as with all ports in the ZL5011x
device, CPU_ADDR[2] is the least
significant bit (lsb).
AA22
AB21
W21
AB20
AB19
Table 10 - CPU Interface Package Ball Definition
35
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
Signal
I/O
I U N21
Package Balls
Description
CPU_CS
CPU Chip Select. Synchronous to rising
edge of CPU_CLK and active low. Is
asserted with CPU_TS_ALE. Must be
asserted with CPU_OE to
asynchronously enable the CPU_DATA
output during a read, including DMA
read.
CPU_WE
CPU_OE
I
I
M21
M22
CPU Write Enable. Synchronously
asserted with respect to CPU_CLK
rising edge, and active low. Used for
CPU writes from the processor to
registers within the ZL5011x. Asserted
one clock cycle after CPU_TS_ALE.
CPU Output Enable.
Synchronously asserted with respect to
CPU_CLK rising edge, and active low.
Used for CPU reads from the processor
to registers within the ZL5011x.
Asserted one clock cycle after
CPU_TS_ALE. Must be asserted with
CPU_CS to asynchronously enable the
CPU_DATA output during a read,
including DMA read.
CPU_TS_ALE
CPU_SDACK1
I
I
M20
A21
Synchronous input with rising edge of
CPU_CLK.
Latch Enable (ALE), active high signal.
Asserted with CPU_CS, for a single
clock cycle.
CPU/DMA 1 Acknowledge Input. Active
low synchronous to CPU_CLK rising
edge. Used to acknowledge request
from ZL5011x for a DMA write
transaction. Only used for DMA
transfers, not for normal register access.
CPU_SDACK2
CPU_CLK
I
I
L21
L19
CPU/DMA 2 Acknowledge Input Active
low synchronous to CPU_CLK rising
edge. Used to acknowledge request
from ZL5011x for a DMA read
transaction. Only used for DMA
transfers, not for normal register access.
CPU PowerQUICC™ II Bus Interface
clock input. 66 MHz clock, with minimum
of 6 ns high/low time. Used to time all
host interface signals into and out of
ZL5011x device.
Table 10 - CPU Interface Package Ball Definition (continued)
36
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
Signal
I/O
Package Balls
Description
CPU_TA
OT B22
CPU Transfer Acknowledge. Driven from
tri-state condition on the negative clock
edge of CPU_CLK following the
assertion of CPU_CS. Active low,
asserted from the rising edge of
CPU_CLK. For a read, asserted when
valid data is available at CPU_DATA.
The data is then read by the host on the
following rising edge of CPU_CLK. For a
write, is asserted when the ZL5011x is
ready to accept data from the host. The
data is written on the rising edge of
CPU_CLK following the assertion.
Returns to tri-state from the negative
clock edge of CPU_CLK following the
de-assertion of CPU_CS.
CPU_DREQ0
CPU_DREQ1
OT K22
OT C22
CPU DMA 0 Request Output Active low
synchronous to CPU_CLK rising edge.
Asserted by ZL5011x to request the host
initiates a DMA write. Only used for DMA
transfers, not for normal register access.
CPU DMA 1 Request
Active low synchronous to CPU_CLK
rising edge. Asserted by ZL5011x to
indicate packet data is ready for
transmission to the CPU, and request
the host initiates a DMA read. Only used
for DMA transfers, not for normal
register access.
CPU_IREQO
CPU_IREQ1
O
O
J22
CPU Interrupt 0 Request (Active Low)
CPU Interrupt 1 Request (Active Low)
G20
Table 10 - CPU Interface Package Ball Definition (continued)
37
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
4.5 System Function Interface
All System Function Interface signals are 5 V tolerant.
The core of the chip will be held in reset for 16383 SYSTEM_CLK cycles after SYSTEM_RST has gone HIGH to
allow the PLL’s to lock.
Signal
I/O
Package Balls
Description
SYSTEM_CLK
I
W13
System Clock Input. The system clock
frequency is 100 MHz. The frequency
must be accurate to within ±32 ppm in
synchronous mode. The quality of
SYSTEM_CLK, or the oscillator that
drives SYSTEM_CLK directly impacts
the adaptive clock recovery
performance. See Section 6.3.
SYSTEM_RST
I
I
AA12
AA11
System Reset Input. Active low. The
system reset is asynchronous, and
causes all registers within the /1/4 to be
reset to their default state. Recommend
external pull-up.
SYSTEM_DEBUG
System Debug Enable.
asynchronous signal
This is an
that, when
de-asserted, prevents the software
assertion of the debug-freeze command,
regardless of the internal state of
registers, or any error conditions. Active
high. Recommend external pull-down.
Table 11 - System Function Interface Package Ball Definition
4.6 Test Facilities
4.6.1 Administration, Control and Test Interface
All Administration, Control and Test Interface signals are 5 V tolerant.
Signal
GPIO[15:0]
I/O
Package Balls
Description
ID/ [15] W17
OT
[7]
[6]
AA15
AB13
AB12
AB11
AB10
AA14
AA13
AB9
General Purpose I/O pins. Connected to an
internal register, so customer can set
user-defined parameters. Bits [4:0] reserved
at start-up or reset for memory TDL setup.
See the ZL50115/16/17/18/19/20
Programmers Model for more details.
Recommend 5 kohm pulldown on these
signals.
[14] Y16
[13] AB16
[12] AA16
[11] AB15
[10] AB14
[5]
[4]
[3]
[2]
[1]
[0]
[9]
[8]
W15
Y15
Table 12 - Administration/Control Interface Package Ball Definition
38
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
Signal
I/O
Package Balls
Description
TEST_MODE[2:0]
I D [2]
[1]
AB17
Y17
Test Mode input - ensure these pins are tied
to ground for normal operation.
000 SYS_NORMAL_MODE
001-010 RESERVED
[0]
AA17
011 SYS_TRISTATE_MODE
100-111 RESERVED
Table 12 - Administration/Control Interface Package Ball Definition
4.6.2 JTAG Interface
All JTAG Interface signals are 5 V tolerant, and conform to the requirements of IEEE1149.1 (2001).
Signal
I/O
Package Balls
Description
JTAG_TRST
I U Y18
JTAG Reset. Asynchronous reset. In normal
operation this pin should be pulled low.
Recommend external pull-down.
JTAG_TCK
JTAG_TMS
I
V20
JTAG Clock - maximum frequency is
25MHz, typically run at 10 MHz. In normal
operation this pin should be pulled either
high or low. Recommend external pull-down.
I U U20
JTAG test mode select. Synchronous to
JTAG_TCK rising edge. Used by the Test
Access Port controller to set certain test
modes.
JTAG_TDI
I U AA18
JTAG test data input. Synchronous to
JTAG_TCK.
JTAG_TDO
O
W20
JTAG test data output. Synchronous to
JTAG_TCK.
Table 13 - JTAG Interface Package Ball Definition
4.7 Miscellaneous Inputs
The following unused inputs must be tied low or high as appropriate.
Signal
IC_GND
IC_VDD_IO
Package Balls
W11, Y11, Y19, AA19, AB18
L22
Description
Internally connected. Tie to GND.
Internally connected. Tie to VDD_IO.
Table 14 - Miscellaneous Inputs Package Ball Definitions
39
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
4.8 Power and Ground Connections
Signal
VDD_IO
Package Balls
Description
3.3 V VDD Power Supply for IO Ring
A1
A22
AA2
AB1
C14
D16
G19
N19
T4
AA21
AB22
C15
D19
G4
AA4
B2
AA5
B21
C3
C20
D4
D7
K4
M4
P3
T19
W16
W7
T20
W19
W8
U2
W4
W5
Y20
Y3
GND
A13
AA7
B3
A15
AB5
C2
AA20
B11
C21
J12
K10
K14
L10
L14
M11
M19
N12
P10
P14
U3
AA3
B20
H2
0 V Ground Supply
J10
J14
K12
K9
J11
J9
J13
K11
K19
L11
L20
M12
M9
K13
L1
L12
L9
L13
M10
M14
N11
N9
M13
N10
N14
P12
P9
N13
P11
P2
P13
R19
Y14
W12
Y21
Y13
Y2
VDD_CORE
A1VDD
D14
F19
J4
D15
D18
D9
1.8 V VDD Power Supply for Core
Region
F4
H4
J19
P19
W6
L4
N4
P4
U19
Y6
W14
W9
AA8
1.8 V PLL Power Supply
Table 15 - Power and Ground Package Ball Definition
40
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
4.9 Internal Connections
The following pins are connected internally, and must be left open circuit.
Signal
Package Balls
Description
Internally connected. Leave open circuit
IC
AA1
AB2
AB7
W1
AA10
AA6
AB4
H22
Y10
Y7
AA9
AB6
K21
Y12
Y8
AB3
AB8
Y1
Y4
Y5
Table 16 - Internal Connections Package Ball Definitions
4.10 No Connections
The following pins are not connected internally, and should be left open circuit.
Signal
Package Balls
Description
NC
F1
J3
H3
K1
J1
J2
No connection. Leave open circuit.
K2
K3
Table 17 - Miscellaneous Inputs Package Ball Definitions
4.11 Device ID
Signal
I/O
Package Balls
Description
DEVICE_ID[4:0]
O
[4]
[3]
[2]
[1]
[0]
A10
Device ID.
V19
W18
F3
ZL50115 = 00000
ZL50116 = 00001
ZL50117 = 00010
ZL50118 = 00011
ZL50119 = 00100
ZL50120 = 00101
G2
Table 18 - Device ID Ball Definition
41
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
5.0 Typical Applications
5.1 Leased Line Provision
Circuit emulation is typically used to support the provision of leased line services to customers using legacy TDM
equipment. For example, Figure 8 shows a leased line TDM service being carried across a packet network. The
advantages are that a carrier can upgrade to a packet switched network, whilst still maintaining their existing TDM
business.
The ZL5011x is capable of handling circuit emulation of both structured T1, E1, and J2 links (e.g., for support of
fractional circuits) and unstructured (or clear channel) T1, E1, J2, T3 and E3 links. The device handles the
data-plane requirements of the provider edge inter-working function (with the exception of the physical interfaces
and line interface units). Control plane functions are forwarded to the host processor controlling the ZL5011x
device.
The ZL5011x provides a per-stream clock recovery function to reproduce the TDM service frequency at the egress
of the packet network. This is required otherwise the queue at the egress of the packet network will either fill up or
empty, depending on whether the regenerated clock is slower or faster than the original.
Carrier Network
Customer
Premises
Customer
Premises
Packet
queue
TDM
TDM
Network
TDM to
packet
fservice
Extract
~
~
Clock
fservice
fservice
Provider Edge
Interworking
Function
Provider Edge
Interworking
Function
Figure 8 - Leased Line Services Over a Circuit Emulation Link
42
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
5.2 Remote Concentrator Unit
The remote concentrator application, shown in Figure 9, consists of a remote concentrators connected to the
Central Office (CO) by a dedicated fiber link running Gigabit Ethernet (GE) or Ethernet over SONET (EoS) rather
than by NxT1/E1 or DS3/E3. The remote concentrators provide both TDM service and native Ethernet service to
the Multi-Tenet Unit or Multi-Dwelling Unit (MTU/MDU).
The ZL5011x is used to emulate TDM circuits over Ethernet by establishing CESoP connections between the
remote concentrator and the CO. The native IP or Ethernet traffic is multiplexed with the CESoP traffic inside the
remote concentrator and sent across the same GE connection to the CO. At the CO the native IP or Ethernet traffic
is split from the CESoP connections at sent towards the packet network. Multiple T1/E1 CESoP connections from
several remote concentrators are aggregated in the CO using a larger ZL5011x variant, converted back to TDM
circuits, and connected to the PSTN through a higher bandwidth TDM circuit such as OC-3 or STM-1.
The use of CESoP here allows the convergence of voice and data on a single access network based on Ethernet.
This convergence on Ethernet, a packet technology, rather than SONET/SDH, a switched circuit technology,
provides cost and operational savings.
Figure 9 - Remote Concentrator Unit using CESoP
43
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
5.3 FTTP
The Fiber to the Premise (FTTP) application, shown in Figure 10, consists of an Ethernet Passive Optical Network
(EPON) deployed in the Wide Area Network (WAN). The Optical Network Units (ONU) sit at the curb while the
Optical Line Terminals (OLT) are located at the Central Office (CO). The ONUs are traditionally equipped with
Ethernet interfaces to provide video and data service to the customer premise.
The ONU includes a ZL5011x which enables the box to provide T1/E1 service to the customer. The ZL5011x is
used to establish CESoP connections between the ONU and the OLT to transparently carry TDM circuits across the
EPON. The ONU would use a smaller variant of the ZL5011x and the OLT would use a larger variant to aggregate
CESoP traffic from many ONUs and connect them at the CO to the PSTN. The native IP or Ethernet traffic from the
ONU would be split off at the OLT and connected to the packet network.
Customer Premises
Ethernet
Fiber Links
ONU
ONU
ONU
T1/E1
Ethernet
IP
GIGE Over
Fiber
Ethernet
T1/E1
Optical
Splitter
OLT
T1/E1
PSTN
Ethernet
T1/E1
CESoP
Figure 10 - EPON using CESoP
44
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
5.4 Wireless - WiFi or WiMAX
The wireless application, shown in Figure 11, may either be in the form of WiMAX for broadband access or Wi-Fi for
smaller-scale Loans. Both technologies carry Ethernet over radio links between sites or pieces of equipment.
An application for CESoP technology over a WiMAX network is to enable the service provider to sell T1/E1 service
in addition to video and data services that are natively carried across the WiMAX connection. A ZL5011x is used at
the customer premise to packetize the T1/E1, fractional T1/E1 or TDM circuit into Ethernet packets, which are
transported back to the Central Office (CO). At the CO the TDM circuit is re-assembled from the Ethernet packets
and send to the PSTN. The CESoP traffic is converged onto the same WiMAX connection as the native Ethernet
traffic for video and data.
An application for CESoP technology over a Wi-Fi network is to enable a distributed PBX system in either a single
building or between buildings in a campus environment. In this application the T1/E1 connection from a PBX is
connected using a CESoP to another PBX. A wireless site-to-site CESoP connection between buildings in a
campus would allow for deployment savings against having to run dedicated copper cables between buildings.
Wireless LAN
Access Point
WiMAX (802.16)
WiMAX
CESoP
T1/E1
MAC
Wireless LAN
Access Point
70 Mbps
Up to 48 Km
WiMAX
CESoP
T1/E1
MAC
CESoP
Wireless LAN
Access Point
Wi-Fi (802.11)
Wireless LAN
Access Point
Wi-Fi
CESoP
T1/E1
MAC
54 Mbps
Wi-Fi
Up to 100 m
CESoP
T1/E1
MAC
CESoP
Figure 11 - Wi-Fi and WiMAX using CESoP
45
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
5.5 Digital Loop Carrier
The Broadband Digital Loop Carrier (BBDLC) application, shown in Figure 12, consists of a BBDLC connected to
the Central Office (CO) by a dedicated fiber link running Gigabit Ethernet (GE) rather than by NxT1/E1 or DS3/E3.
The ZL5011x is used to emulate TDM circuits over Ethernet by establishing CESoP connections between the
BBDLC and the CO. At the CO the native IP or Ethernet traffic is split from the CESoP connections at sent towards
the packet network. Multiple T1/E1 CESoP connections from several BBDLC are aggregated in the CO using a
larger ZL5011x variant, converted back to TDM circuits, and connected to a class 5 switch destined towards the
PSTN.
In this configuration T3/E3 services can also be provided. Using CESoP allows voice and data traffic to be
converged onto a single link.
IP Edge Router or
POTS
Multi-Service
Switching Platform
GIGE Over
Fiber
N x GIGE
Digital
Loop
IP
Carrier
Dedicated
Central
Office
Fiber Links
T1/E1
Central Office
Switch (Class 5)
GIGE Over
Fiber
N x T1/E1
Broadband
DLC
PSTN
CESoP
Figure 12 - Digital Loop Carrier using CESoP
46
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
5.6 Integrated Access Device
The Integrated Access Device (IAD) application consists of an IAD located at the curb or customer premise with an
Ethernet connection to an TDM aggregation box sitting in the access area of the network.
The ZL5011x in the IAD modem packetizes the T1/E1 or fractional T1/E1 TDM circuit into Ethernet CESoP packets.
The CESoP traffic is multiplexed with the native Ethernet data traffic from the IAD’s Ethernet ports onto the Ethernet
link to the aggregation equipment. The aggregator will split off the native Ethernet traffic from multiple IADs and
send the traffic on to packet network. The aggregator will contain a larger ZL5011x that will terminate multiple
CESoP connections from multiple IADs and send the TDM circuits to the PSTN, perhaps over a higher bandwidth
TDM pipe such as DS3.
The use of CESoP in this application allows the IAD to support both native Ethernet service as well as T1/E1
service in the same box, while converging both types of traffic onto a single Ethernet connection back towards the
provider.
Small
IP Edge Router or
Multi-Service
business
Switching Platform
Ethernet
N x GIGE
Ethernet link
IP
IAD
IAD
T1/E1
TDM
Aggregation
Small
business
Central Office
Switch (Class 5)
Ethernet
N x T1/E1
Ethernet link
PSTN
T1/E1
CESoP
Figure 13 - Integrated Access Device Using CESoP
6.0 Functional Description
The ZL5011x family provides the data-plane processing to enable constant bit rate TDM services to be carried over
a packet switched network, such as an Ethernet, IP or MPLS network. The device segments the TDM data into
user-defined packets, and passes it transparently over the packet network to be reconstructed at the far end. This
has a number of applications, including emulation of TDM circuits and packet backplanes for TDM-based
equipment.
Transparent data flow between TDM equipment
TDM
CESoP
CESoP
TDM
equipment
equipment
TDM-Packet
conversion
TDM-Packet
conversion
constant bit rate
TDM link
constant bit rate
TDM link
packet switched
network
interworking
function
interworking
function
Figure 14 - ZL50115/16/17/18/19/20 Family Operation
47
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
6.1 Block Diagram
A diagram of the ZL5011x device is given in Figure 15, which shows the major data flows between functional
components.
Motorola PowerQUICCTM Compatible
DMA
Host Interface
Admin.
Control
Central
Payload
Packet
Task
Assembly
Transmit
Dual
Packet
Interface
MAC
Manager
TDM
Interface
TDM
Packet
Protocol
Engine
Formatter
Receive
Memory Management Unit
On-chip RAM Controller
Clock
JTAG Test
Controller
Recovery
Data Flows
Control Flows
JTAG Interface
Figure 15 - ZL50115/16/17/18/19/20 Data and Control Flows
6.2 Data and Control Flows
There are numerous combinations that can be implemented to pass data through the ZL5011x device depending
on the application requirements. The Task Manager can be considered the central pivot, through which all flows
must operate. The Task Manager acts as a “router” in the centre of the chip, directing packets to the appropriate
blocks for further processing. The task message contains a pointer to the relevant data, instructions as to what to
do with the data, and ancillary information about the packet. Effectively this means the flow of data through the
device can be programmed, by setting the task message contents appropriately.
Flow Number
Flow Through Device
1
2
3
TDM to (TM) to PE to (TM) to PKT
PKT to (TM) to PE to (TM) to TDM
TDM to (TM) to PKT
4
PKT to (TM) to TDM
5
TDM to (TM) to CPU
6
7
TDM to (TM) to PE to (TM) to CPU
CPU to (TM) to TDM
8
PKT to (TM) to CPU
9
CPU to (TM) to PKT
101
111
TDM to (TM) to TDM
PKT to (TM) to PKT
Table 19 - Standard Device Flows
1. This flow is for loopback and may be helpful for test purposes
48
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
Each of the 11 data flows uses the Task Manager to route packet information to the next block or interface for
onward transmission. The flow is determined by the Type field in the Task Message (see ZL50115/16/17/18/19/20
Programmers Model).
6.3 SYSTEM_CLK Considerations
The qualitiy of the 100 MHz SYSTEM_CLK or the oscillator that drives SYSTEM_CLK directly impacts the adaptive
clock recovery performance. Zarlink has a recommended oscillator and guidelines for the selection of an oscillator.
Please review application note ZLAN-159 “External Component Selection” before choosing an oscillator.
6.4 TDM Interface
The ZL5011x family offers the following types of TDM service across the packet network:
Service type
Unstructured
TDM interface
Interface type
Interfaces to
T1, E1, J2, E3, T3 and
STS-1
Bit clock in and out
Data in and out
Line interface unit
asynchronous
Structured synchronous T1, E1 and J2
Bit clock out
Framers
(N x 64 Kbps)
Framed TDM data
streams at 2.048 and
8.192 Mbps
Frame pulse out
Data in and out
TDM backplane (master)
Bit clock in
Frame in
Framers
TDM backplane (slave)
Data in and out
Table 20 - TDM Services Offered by the ZL50115/16/17/18/19/20 Family
Unstructured services are fully asynchronous, and include full support for clock recovery on a per stream basis.
Both adaptive and differential clock recovery mechanisms can be used.
Structured services are synchronous, with all streams driven by a common clock and frame reference. These
services can be offered in two ways:
•
Synchronous master mode - the ZL5011x provides a common clock and frame pulse to all streams, which
may be locked to an incoming clock or frame reference
•
Synchronous slave mode - the ZL5011x accepts a common external clock and frame pulse to be used by
all streams
In either structured mode, N x 64 Kbps trunking is supported as detailed in “Payload Order” on page 53.
6.4.1 TDM Interface Block
The TDM Interface contains two basic types of interface: unstructured clock and data, for interfacing directly to a
line interface unit; or structured, framed data, for interfacing to a framer or TDM backplane.
Unstructured data is treated asynchronously, with every stream using its own clock. Clock recovery is provided on
each output stream, to reproduce the TDM service frequency at the egress of the packet network. Structured data is
treated synchronously, i.e. all data streams are timed by the same clock and frame references. These can either be
supplied from an external source (slave mode) or generated internally using the on-chip stratum 3/4/4E PLL
(master mode).
49
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
6.4.2 Structured TDM Port Data Formats
The ZL5011x is programmable such that the frame/clock polarity and clock alignment can be set to any desired
combination. Table 21 shows a brief summary of four different TDM formats; ST-BUS, H.110, H-MVIP, and Generic
(synchronous mode only), for more information see the relevant specifications shown. There are many additional
formats for TDM transmission not depicted in Table 21, but the flexibility of the port will cover almost any scenario.
The overall data format is set for the entire TDM Interface device, rather than on a per stream basis. It is possible to
control the polarity of the master clock and frame pulse outputs, independent of the chosen data format (used when
operating in synchronous master mode).
Nominal
Frame
Pulse
Frame Boundary
Alignment
Number
of
channels
per
frame
Data
Rate
Clock
Freq.
Frame
Pulse
Polarity
Data
Format
Standard
Width
frame
clock
(Mbps)
(MHz)
pulse
(ns)
ST-bus
2.048
2.048
8.192
8.192
2.048
2.048
8.192
2.048
32
32
2.048
4.096
16.384
8.192
2.048
4.096
16.384
2.048
244
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Positive
Rising
Edge
Straddles MSAN-126
boundary
Rev B
(Issue 4)
Zarlink
244
61
Falling
Edge
Straddles
boundary
128
128
32
Falling
Edge
Straddles
boundary
H.110
122
244
244
244
488
Rising
edge
Straddles
boundary
ECTF
H.110
H-MVIP
Rising
Edge
Straddles
boundary
H-MVIP
Release
1.1a
32
Falling
Edge
Straddles
boundary
128
32
Falling
Edge
Straddles
boundary
Generic
Rising
Edge
Rising
edge of
clock
8.192
128
8.192
122
Positive
Rising
Edge
Rising
edge of
clock
Table 21 - Some of the TDM Port Formats Accepted by the ZL50115/16/17/18/19/20 Family
50
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
6.4.3 TDM Clock Structure
The TDM interface can operate in two modes, synchronous for structured TDM data, and asynchronous for
unstructured TDM data. The ZL5011x is capable of providing the TDM clock for either of the modes. The ZL5011x
supports clock recovery in both synchronous and asynchronous modes of operation. In asynchronous operation
each stream may have independent clock recovery.
6.4.3.1 Synchronous TDM Clock Generation
In synchronous mode all 4 streams will be driven by a common clock source. When the ZL5011x is acting as a
master device, the source can either be the internal DPLL or an external PLL. In both cases, the primary and
secondary reference clocks are taken from either two TDM input clocks, or two external clock sources driven to the
chip. The input clocks are then divided down where necessary and sent either to the internal DPLL or to the output
pins for connection to an external DPLL. The DPLL then provides the common clock and frame pulse required to
drive the TDM streams. See “DPLL Specification” on page 60 for further details.
PRS
PRD
DIV
TDM_CLKi[3:0]
TDM_CLKiP
PLL_PRI
PLL_SE
SRS
SRD
DIV
CLOCK
FRAME
Internal
DPLL
TDM_CLKiS
Figure 16 - Synchronous TDM Clock Generation
When the ZL5011x is acting as a slave device, the common clock and frame pulse signals are taken from an
external device providing the TDM master function.
6.4.3.2 Asynchronous TDM Clock Generation
Each stream uses a separate internal DCO to provide an asynchronous TDM clock output. The DCO can be
controlled to recover the clock from the original TDM source depending on the timing algorithm used.
6.5 Payload Assembly
Data traffic received on the TDM Interface is sampled in the TDM Interface block, and synchronized to the internal
clock. It is then forwarded to the payload assembly process. The ZL5011x Payload Assembler can handle up to 128
active packet streams or “contexts” simultaneously. Each context generates a single stream of packets identified by
a label in the packet header known as the "context ID". Packet payloads are assembled in the format shown in
Figure 17 - on page 52 in structured operation. This meets the requirements of the CESoPSN standard under
development in the IETF. Alternatively, packet payloads are assembled in the format shown in Figure 19 on
page 52. This format meets the requirements of the SAToP standard under development in the IETF.
When the payload has been assembled it is written into the centrally managed memory, and a task message is
passed to the Task Manager.
51
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
6.5.1 Structured Payload Operation
In structured mode a context may contain any number of 64 kbps channels. These channels need not be
contiguous and they may be selected from any input stream.
Channels may be added or deleted dynamically from a context. This feature can be used to optimize bandwidth
utilisation. Modifications to the context are synchronised with the start of a new packet.
The fixed header at the start of each packet is added by the Packet Transmit block. This consists of up to 64 bytes,
containing the Ethernet header, any upper layer protocol headers, and the two byte context descriptor field (see
section below). The header is entirely user programmable, enabling the use of any protocol.
The payload header and size must be chosen so that the overall packet size is not less than 64 bytes, the Ethernet
standard minimum packet size. Where this is likely to be the case, the header or data must be padded (as shown in
Figure 17 and Figure 19) to ensure the packet is large enough. This padding is added by the ZL5011x for most
applications.
may include VLAN tagging
e.g. IPv4, IPv6, MPLS
Ethernet Header
Network Layers
(added by Packet Transmit)
Header
e.g. UDP, L2TP, RTP,
CESoPSN, SAToP
Upper layers
(added by Protocol Engine)
Channel 1
Channel 2
Data for TDM Frame 1
Data for TDM Frame 2
Channel x
Channel 1
Channel 2
TDM Payload
(constructed by Payload Assembler)
Channel x
Channel 1
Channel 2
Data for TDM Frame n
Channel
Static Padding
may also be placed in the
packet header
(if required to meet minimum payload size)
Ethernet FCS
Figure 17 - ZL50115/16/17/18/19/20 Packet Format - Structured Mode
In applications where large payloads are being used, the payload size must be chosen such that the overall packet
size does not exceed the maximum Ethernet packet size of 1518 bytes (1522 bytes with VLAN tags). Figure 17
shows the packet format for structured TDM data, where the payload is split into frames, and each frame
concatenated to form the packet.
52
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
6.5.1.1 Payload Order
Packets are assembled sequentially, with each channel placed into the packet as it arrives at the TDM
Interface. A fixed order of channels is maintained (see Figure 18), with channel 0 placed before channel 1,
which is placed before channel 2. It is this order that allows the packet to be correctly disassembled at the far
end. A context must contain only unique channel numbers. As such a context that contains the same channel
from different streams, for example channel 1 from stream 2 and channel 1 from stream 3, would not be
permitted.
Stream 0
Channel 0
Channel 1
Channel 2
Channel 31
Stream 1
Stream 2
Stream 3
Channel 0
Channel 0
Channel 0
Channel 1
Channel 1
Channel 1
Channel 2
Channel 2
Channel 31
Channel 31
Channel 31
Channel 2
Channel Assem bly Order
Figure 18 - Channel Order for Packet Formation
Each packet contains one or more frames of TDM data, in sequential order. This groups the selected channels
for the first frame, followed by the same set of channels for the subsequent frame, and so on.
6.5.2 Unstructured Payload Operation
In unstructured mode, the payload is not split by defined frames or timeslots, so the packet consists of a continuous
stream of data. Each packet consists of a number of octets, as shown in Figure 19. The number of octets in a
packet need not be an integer number of frames. A typical value for N may be 192, as defined in the IETF PWE3
standard."
For example, consider mapping the unstructured data of a 25 timeslot DS0 stream. The data for each T1 frame
would normally consist of 193 bits, 192 data bits and 1 framing bit. If the payload consists of 24 octets it will be 1 bit
short of a complete frames worth of data, if the payload consists of 25 octets it will be 7 bits over a complete frames
worth of data. NOTE: No alignment of the octets with the T1 framing structure can be assumed.
may include VLAN tagging
e.g. IPv4, IPv6, MPLS
Ethernet Header
Network Layers
Header
(added by Packet Transmit)
e.g. UDP, L2TP, RTP,
CESoPSN, SAToP
Upper layers
(added by Protocol Engine)
Octet 1
Octet 2
N octets of data from unstructured stream
TDM Payload
No frame or channel alignment
NOTE:
(constructed by Payload Assembler)
46 to 1500 bytes
Octet N
Static Padding
may also be placed in the
packet header
(if required to meet minimum payload size)
Ethernet FCS
Figure 19 - ZL50115/16/17/18/19/20 Packet Format - Unstructured Mode
53
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
6.6 Protocol Engine
In general, the next processing block for TDM packets is the Protocol Engine. This handles the data-plane
requirements of the main higher level protocols (layers 4 and 5) expected to be used in typical applications of the
ZL5011x family: UDP, RTP, L2TP, CESoPSN, SAToP and CDP. The Protocol Engine can add a header to the
datagram containing up to 24 bytes. This header is largely static information, and is programmed directly by the
CPU. It may contain a number of dynamic fields, including a length field, checksum, sequence number and a
timestamp. The location, and in some cases the length of these fields is also programmable, allowing the various
protocols to be placed at variable locations within the header.
6.7 Packet Transmission
Packets ready for transmission are queued to the switch fabric interface by the Queue Manager. Four classes of
service are provided, allowing some packet streams to be prioritized over others. On transmission, the Packet
Transmit block appends a programmable header, which has been set up in advance by the control processor.
Typically this contains the data-link and network layer headers (layers 2 and 3), such as Ethernet, IP (versions 4
and 6) and MPLS.
6.8 Packet Reception
Incoming data traffic on the packet interface is received by the MACs. The well-formed packets are forwarded to a
packet classifier to determine the destination. When a packet is successfully classified the destination can be the
TDM interface, the LAN interface or the host interface. TDM traffic is then further classified to determine the context
it is intended for.
Each TDM interface context has an individual queue, and the TDM re-formatting process re-creates the TDM
streams from the incoming packet streams. This queue is used as a jitter buffer, to absorb variation in packet delay
across the network. The size of the jitter buffer can be programmed in units of TDM frames (i.e., steps of 125 µs).
There is also a queue to the host interface, allowing a traffic flow to the host CPU for processing. The host’s DMA
controller can be used to retrieve packet data and write it out into the CPU’s own memory.
6.9 TDM Formatter
At the receiving end of the packet network, the original TDM data must be re-constructed from the packets
received. This is known as re-formatting, and follows the reverse process from the Payload Assembler. The TDM
Formatter plays out the packets in the correct sequence, directing each octet to the selected timeslot on the output
TDM interface.
When lost or late packets are detected, the TDM Formatter plays out underrun data for the same number of TDM
frames as were included in the missing packet. Underrun data can either be the last value played out on that
timeslot, or a pre-programmed value (e.g., 0xFF). If the packet subsequently turns up it is discarded. In this way, the
end-to-end latency through the system is maintained at a constant value.
6.10 Ethernet Traffic Aggregation (ZL50118/19/20 only)
The ZL5011x allows native Ethernet traffic received on the customer side Fast Ethernet port to be aggregated with
the CESoP traffic from the TDM interface to the provider side Gigabit Ethernet port. Likewise, traffic from the
provider side Gigabit Ethernet port may be split between CESoP traffic destined towards the TDM interface and
native Ethernet traffic destined towards the customer side Fast Ethernet port. This functionality is achieved by
correctly programming the task manager and packet classifiers for flow 11.
From the provider side Gigabit Ethernet port to the customer side TDM and Fast Ethernet interfaces there is
sufficient internal bandwidth to avoid any prioritization issues. From the customer side TDM and Fast Ethernet
interfaces towards the Gigabit Ethernet ports the TDM CESoP traffic may be sent to a higher priority output queue
(there are four output queues total) than the native Fast Ethernet traffic. In this way the access to the provider side
Gigabit Ethernet port is prioritized for TDM traffic over native Ethernet traffic.
54
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
7.0 Clock Recovery
One of the main issues with circuit emulation is that the clock used to drive the TDM link is not necessarily linked
into the central office reference clock, and hence may be any value within the tolerance defined for that service.
The reverse link may also be independently timed, and operating at a slightly different frequency. In the
plesiochronous digital hierarchy the difference in clock frequencies between TDM links is compensated for using bit
stuffing techniques, allowing the clock to be accurately regenerated at the remote end of the carrier network.
With a packet network, that connection between the ingress and egress frequency is broken, since packets are
discontinuous in time. From Figure 8, the TDM service frequency f
at the customer premises must be exactly
service
reproduced at the egress of the packet network. The consequence of a long-term mismatch in frequency is that the
queue at the egress of the packet network will either fill up or empty, depending on whether the regenerated clock is
slower or faster than the original. This will cause loss of data and degradation of the service.
The ZL5011x provides a per-stream clock recovery function to reproduce the TDM service frequency at the egress
of the packet network. There are two schemes are employed, depending on the availability of a common reference
clock at each provider edge unit, within the ZL5011x - differential and adaptive. The clock recovery itself is
performed by software in the external processor, with support from on-chip hardware to gather the required
statistics.
7.1 Differential Clock Recovery
For applications where the wander characteristics of the recovered clock are very important, such as when the
emulated circuit must be connected into the plesiochronous digital hierarchy (PDH), the ZL5011x also offers a
differential clock recovery technique. This relies on having a common reference clock available at each provider
edge point. Figure 20 illustrates this concept with a common Primary Reference Source (PRS) clock being present
at both the source and destination equipment.
In a differential technique, the timing of the TDM service clock is sent relative to the common reference clock. Since
the same reference is available at the packet egress point and the packet size is fixed, the original service clock
frequency can be recovered. This technique is unaffected by any low frequency components in the packet delay
variation. The disadvantage is the requirement for a common reference clock at each end of the packet network,
which could either be the central office TDM clock, or provided by a global position system (GPS) receiver.
PRS
clock
ZL5011x
source
node
ZL5011x
destination
node
Data
Data
Packets
Packets
Timestamp
extraction
Network
LIU Source
Dest'n LIU
Clock
Clock
Timestamp
generation
DCO
Host CPU
Timing
recovery
Figure 20 - Differential Clock Recovery
55
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
7.2 Adaptive Clock Recovery
For applications where there is no common reference clock between provider edge units, an adaptive clock
recovery technique is provided. This infers the clock rate of the original TDM service clock from the mean arrival
rate of packets at the packet egress point.
The disadvantage of this type of scheme is that, depending on the characteristics of the packet network, it may
prove difficult to regenerate a clock that stays within the wander requirements of the plesiochronous digital
hierarchy (specifically MTIE). The reason for this is that any variation in delay between packets will feed through as
a variation in the frequency of the recovered clock. High frequency jitter can be filtered out, but any low frequency
variation or wander is more difficult to remove without a very long time constant. This will in turn affect the ability of
the system to lock to the original clock within an acceptable time.
With no PRS clock the only information available to determine the TDM transmission speed is the average arrival
rate of the packets, as shown in Figure 21. Timestamps representing the number of elapsed source clock periods
may be included in the packet header, or information can be inferred from a known payload size at the destination.
It is possible to maintain average buffer-fill levels at the destination, where an increase or decrease in the fill level of
the buffer would require a change in transmission clock speed to maintain the average. Additionally, the buffer-fill
depth can be altered independently, with no relation to the recovered clock frequency, to control TDM transmission
latency.
ZL5011x
source
node
ZL5011x
destination
node
Data
Data
Packets
Packets
Network
LIU Source
Dest'n LIU
Clock
Clock
DCO
Host CPU
Queue
monitor
Figure 21 - Adaptive Clock Recovery
8.0 System Features
8.1 Latency
The following lists the intrinsic processing latency of the ZL5011x. The intrinsic processing latency is dependent on
the number of channels in a context for structured operation, as detailed below. However, the intrinsic processing
latency is not dependent on the total number of contexts opened or the total number of channels being processed
by the device.
•
•
•
TDM to Packet transmission processing latency less than 125 µs
Packet to TDM transmission processing latency less than 250 µs (unstructured)
Packet to TDM transmission processing latency less than 250 µs (structured, more than 16 channels in
context)
•
Packet to TDM transmission processing latency less than 375 µs (structured, 16 or less channels in context)
56
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
End-to-end latency may be estimated as the transmit latency + packet network latency + receive latency. The
transmit latency is the sum of the transmit processing and the number of frames per packet x 125 µs. The receive
latency is the sum of the receive processing and the delay through the jitter buffer which is programmed to
compensate for packet network PDV.
The ZL5011x is capable of creating an extremely low latency connection, with end to end delays of less than
0.5 ms, depending on user configuration.
8.2 Loopback Modes
The ZL5011x devices support loopback of the TDM circuits and the circuit emulation packets.
TDM loopback is achieved by first packetizing the TDM circuit as normal via the TDM Interface and Payload
Assembly blocks. The packetized data is then routed by the Task Manager back to the same TDM port via the TDM
Formatter and TDM Interface.
Loopback of the emulated services is achieved by redirecting classified packets from the Packet Receive blocks,
back to the packet network. The Packet Transmit blocks are setup to strip the original header and add a new
header directing the packets back to the source.
8.3 Host Packet Generation
The control processor can generate packets directly, allowing it to use the network for out-of-band communications.
This can be used for transmission of control data or network setup information, e.g., routing information. The host
interface can also be used by a local resource for network transmission of processed data.
The device supports dual address DMA transfers of packets to and from the CPU memory, using the host's own
DMA controller. Table 22 illustrates the maximum bandwidths achievable by an external DMA master.
1
DMA Path
Packet Size
Max Bandwidth Mbps
ZL5011x to CPU only
ZL5011x to CPU only
CPU to ZL5011x only
CPU to ZL5011x only
>1000 bytes
60 bytes
>1000 bytes
60 bytes
>1000 bytes
60 bytes
50
6.7
60
43
2
Combined
58 (29 each way)
11 (5.5 each way)
2
Combined
Table 22 - DMA Maximum Bandwidths
Note 1: Maximum bandwidths are the maximum the ZL5011x devices can transfer under host control, and assumes only minimal
packet processing by the host.
Note 2: Combined figures assume the same amount of data is to be transferred each way.
8.4 Loss of Service (LOS)
During normal operation, a situation may arise where a Loss of Service occurs. This may be caused by a disruption
in the transmission line due to engineering works or cable disconnection, for example. The locally detected LOS
should be transferred across the emulated T1/E1 to the far end. The far end, in turn, should propagate AIS
downstream.
The handling of LOS over a CESoP connection is typically performed using (setting/clearing) the L bit in the
CESoPSN or SAToP control word of the packet header.
Refer to Application Note ZLAN-159, section 4.1 for details on a variety of different ways that LOS may be handled
in an application.
57
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
8.5 Power Up Sequence
To power up the ZL5011x the following procedure must be used:
•
•
•
The Core supply must never exceed the I/O supply by more than 0.5V
Both the Core supply and the I/O supply must be brought up together
DC
The System Reset and, if used, the JTAG Reset must remain low until at least 100 µs after the 100 MHz
system clock has stabilised. Note that if JTAG Reset is not used it must be tied low
This is illustrated in the diagram shown in Figure 22.
I/O supply (3.3 V)
<0.5 VDC
V
Core supply (1.8 V)
DD
t
t
t
RST
> 100 µs
SCLK
10 ns
Figure 22 - Powering Up the ZL5011x
8.6 JTAG Interface and Board Level Test Features.
The JTAG interface is used to access the boundary scan logic for board level production testing.
8.7 External Component Requirements
•
Direct connection to PowerQUICC™ II (MPC8260) host processor and associated memory, but can
support other processors with appropriate glue logic
•
•
TDM Framers and/or Line Interface Units
Ethernet PHY for each MAC port
58
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
8.8 Miscellaneous Features
•
•
•
•
•
•
•
System clock speed of 100 MHz
Host clock speed of up to 66 MHz
Debug option to freeze all internal state machines
JTAG (IEEE1149) Test Access Port
3.3 V I/O Supply rail with 5 V tolerance
1.8 V Core Supply rail
Fully compatible with MT90880/1/2/3 and ZL50110/11/14 Zarlink product line
8.9 Test Modes Operation
8.9.1 Overview
The ZL5011x family supports the following modes of operation.
8.9.1.1 System Normal Mode
This mode is the device's normal operating mode. Boundary scan testing of the peripheral ring is accessible in this
mode via the dedicated JTAG pins. The JTAG interface is compliant with the IEEE Std. 1149.1-2001; Test Access
Port and Boundary Scan Architecture.
Each variant has it's own dedicated.bsdl file which fully describes it's boundary scan architecture.
8.9.1.2 System Tri-State Mode
All output and I/O output drivers are tri-stated allowing the device to be isolated when testing or debugging the
development board.
8.9.2 Test Mode Control
The System Test Mode is selected using the dedicated device input bus TEST_MODE[2:0] as follows in Table 23.
System Test Mode
test_mode[2:0]
SYS_NORMAL_MODE
SYS_TRI_STATE_MODE
3’b000
3’b011
Table 23 - Test Mode Control
8.9.3 System Normal Mode
Selected by TEST_MODE[2:0] = 3'b000. As the test_mode[2:0] inputs have internal pull-downs this is the default
mode of operation if no external pull-up/downs are connected. The GPIO[15:0] bus is captured on the rising edge of
the external reset to provide internal bootstrap options. After the internal reset has been de-asserted the GPIO pins
may be configured by the ADM module as either inputs or outputs.
8.9.4 System Tri-state Mode
Selected by TEST_MODE[2:0] = 3'b011. All device output and I/O output drivers are tri-stated.
59
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
9.0 DPLL Specification
The ZL5011x family incorporates an internal DPLL that meets Telcordia GR-1244-CORE Stratum 3 and Stratum
4/4E requirements, assuming an appropriate clock oscillator is connected to the system clock pin. It will meet the
jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase
change slope, holdover frequency and MTIE requirements for these specifications. In structured mode with the
ZL5011x device operating as a master the DPLL is used to provide clock and frame reference signals to the internal
and external TDM infrastructure. In structured mode, with the ZL5011x device operating as a slave, the DPLL is not
used. All TDM clock generation is performed externally and the input streams are synchronised to the system clock
by the TDM interface. The DPLL is not required in unstructured mode, where TDM clock and frame signals are
generated by internal DCO’s assigned to each individual stream.
9.1 Modes of Operation
It can be set into one of four operating modes: Locking mode, Holdover mode, Freerun mode and Powerdown
mode.
9.1.1 Locking Mode (normal operation)
The DPLL accepts a reference signal from either a primary or secondary source, providing redundancy in the event
of a failure. These references should have the same nominal frequencies but do not need to be identical as long as
their frequency offsets meet the appropriate Stratum requirements. Each source is selected from any one of the
available TDM input stream clocks (up to 4 on the ZL50117/20 variants), or from the external TDM_CLKiP (primary)
or TDM_CLKiS (secondary) input pins, as illustrated in Figure 16 - on page 51. It is possible to supply a range of
input frequencies as the DPLL reference source, depicted in Table 24. The PRD register Value is the number (in
hexadecimal) that must be programmed into the PRD register within the DPLL to obtain the divided down frequency
at PLL_PRI or PLL_SEC.
Maximum
PRD/SRD
Frequency at
PLL_PRI or
PLL_SEC
(MHz)
Acceptable
Input Wander
tolerance
(UI)
Source
Input Frequency
(MHz)
Register
Value
Tolerance
(±ppm)
Divider
Ratio
(Hex)
(Note 1)
(Note 2)
0.008
1.544
30
130
50
50
50
50
30
20
20
20
1
1
1
1
0.008
1.544
2.048
4.096
8.192
16.384
6.312
0.008
0.064
0.064
±1
±1023
2.048
1
1
±1023
4.096
1
1
±1023
8.192
1
1
±1023
16.384
6.312
1
1
±1023
1
1
±1023
22.368
34.368
44.736 (Note 3)
2796
537
699
AEC
219
2BB
±1 (on 64k Hz)
±1 (on 64 kHz)
±1 (on 64 kHz)
Table 24 - DPLL Input Reference Frequencies
Note 1: A PRD/SRD value of 0 will suppress the clock, and prevent it from reaching the DPLL.
Note 2: UI means Unit Interval - in this case periods of the time signal. So ±1UI on a 64 kHz signal means ±15.625 µs, the period of
the reference frequency. Similarly ±1023UI on a 4.096 MHz signal means ±250 µs.
Note 3: This input frequency is supported with the use of an external divide by 2.
60
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
The maximum lock-in range can be programmed up to ±372 ppm regardless of the input frequency. The DPLL will
fail to lock if the source input frequency is absent, if it is not of approximately the correct frequency or if it is too
jittery. See Section 9.7 for further details. Limitations depend on the users programmed values, so the DPLL must
be programmed properly to meet Stratum 3, or Stratum 4/4E. The Application Program Interface (API) software that
accompanies the ZL5011x family can be used to automatically set up the DPLL for the appropriate standard
requirement.
The DPLL lock-in range can be programmed using the Lock Range register (see ZL50115/16/17/18/19/20
Programmers Model document) in order to extend or reduce the capture envelope. The DPLL provides
bit-error-free reference switching, meeting the specification limits in the Telcordia GR-1244-CORE standard. If
Stratum 3 or Stratum 4/4E accuracy is not required, it is possible to use a more relaxed system clock tolerance.
The DPLL output consists of three signals; a common clock (comclk), a double-rate common clock (comclkx2) and
a frame reference (8 kHz). These are used to time the internal TDM Interface, and hence the corresponding TDM
infrastructure attached to the interface. The output clock options are either 2.048 Mbps (comclkx2 at 4.096 Mbps)
or 8.192 Mbps (comclkx2 at 16.384 Mbps), determined by setup in the DPLL control register. The frame pulse is
programmable for polarity and width.
9.1.2 Holdover Mode
In the event of a reference failure resulting in an absence of both the primary and secondary source, the DPLL
automatically reverts to Holdover mode. The last valid frequency value recorded before failure can be maintained
within the Stratum 3 limits of ±0.05 ppm. The hold value is wholly dependent on the drift and temperature
performance of the system clock. For example, a ±32 ppm oscillator may have a temperature coefficient of
±0.1 ppm/°C. Thus a 10°C ambient change since the DPLL was last in the Locking mode will change the holdover
frequency by an additional ±1 ppm, which is much greater than the ±0.05 ppm Stratum 3 specification. If the strict
target of Stratum 3 is not required, a less restrictive oscillator can be used for the system clock.
Holdover mode is typically used for a short period of time until network synchronisation is re-established.
9.1.3 Freerun Mode
In freerun mode the DPLL is programmed with a centre frequency, and can output that frequency within the
Stratum 3 limits of ±4.6 ppm. To achieve this the 100 MHz system clock must have an absolute frequency accuracy
of ±4.6 ppm. The centre frequency is programmed as a fraction of the system clock frequency.
9.1.4 Powerdown Mode
It is possible to “power down” the DPLL when it is not in use. For example, an unstructured TDM system, or use of
an external DPLL would mean the internal DPLL could be switched off, saving power. The internal registers can still
be accessed while the DPLL is powered down.
9.2 Reference Monitor Circuit
There are two identical reference monitor circuits, one for the primary and one for the secondary source. Each
circuit will continually monitor its reference, and report the references validity. The validity criteria depends on the
frequency programmed for the reference. A reference must meet all the following criteria to maintain validity:
•
The “period in specified range” check is performed regardless of the programmed frequency. Each period
must be within a range, which is programmable for the application. Refer to the ZL50115/16/17/18/19/20
Programmers Model for details.
•
If the programmed frequency is 1.544 MHz or 2.048 MHz, the “n periods in specified range” check will be
performed. The time taken for n cycles must be within a programmed range, typically with n at 64, the time
taken for consecutive cycles must be between 62 and 66 periods of the programmed frequency.
61
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
The fail flags are independent of the preferred option for primary or secondary operation, will be asserted in the
event of an invalid signal regardless of mode.
9.3 Locking Mode Reference Switching
When the reference source the DPLL is currently locking to becomes invalid, the DPLL’s response depends on
which one of the failure detect modes has been chosen: autodetect, forced primary, or forced secondary. One of
these failure detect modes must be chosen via the FDM1:0 bits of the DOM register. After a device reset via the
SYSTEM_RESET pin, the autodetect mode is selected.
In autodetect mode (automatic reference switching) if both references are valid the DPLL will synchronise to the
preferred reference. If the preferred reference becomes unreliable, the DPLL continues driving its output clock in a
stable holdover state until it makes a switch to the backup reference. If the preferred reference recovers, the DPLL
makes a switch back to the preferred reference. If necessary, the switch back can be prevented by changing the
preferred reference using the REFSEL bit in the DOM register, after the switch to the backup reference has
occurred.
If both references are unreliable, the DPLL will drive its output clock using the stable holdover values until one of
the references becomes valid.
In forced primary mode, the DPLL will synchronise to the primary reference only. The DPLL will not switch to the
secondary reference under any circumstances including the loss of the primary reference. In this condition, the
DPLL remains in holdover mode until the primary reference recovers. Similarly in forced secondary mode, the
DPLL will synchronise to the secondary reference only, and will not switch to the primary reference. Again, a failure
of the secondary reference will cause the DPLL to enter holdover mode, until such time as the secondary reference
recovers. The choice of preferred reference has no effect in these modes.
When a conventional PLL is locked to its reference, there is no phase difference between the input reference and
the PLL output. For the DPLL, the input references can have any phase relationship between them. During a
reference switch, if the DPLL output follows the phase of the new reference, a large phase jump could occur. The
phase jump would be transferred to the TDM outputs. The DPLL’s MTIE (Maximum Time Interval Error) feature
preserves the continuity of the DPLL output so that it appears no reference switch had occurred. The MTIE circuit is
not perfect however, and a small Time Interval Error is still incurred per reference switch. To align the DPLL output
clock to the nearest edge of the selected input reference, the MTIE reset bit (MRST bit in the DOM register) can be
used.
Unlike some designs, switching between references which are at different nominal frequencies do not require
intervention such as a system reset.
9.4 Locking Range
The locking range is the input frequency range over which the DPLL must be able to pull into synchronization and to
maintain the synchronization. The locking range is programmable up to ±372 ppm.
Note that the locking range relates to the system clock frequency. If the external oscillator has a tolerance of
-100 ppm, and the locking range is programmed to ±200 ppm, the actual locking range is the programmed value
shifted by the system clock tolerance to become -300 ppm to +100 ppm.
9.5 Locking Time
The Locking Time is the time it takes the synchroniser to phase lock to the input signal. Phase lock occurs when the
input and output signals are not changing in phase with respect to each other (not including jitter).
Locking time is very difficult to determine because it is affected by many factors including:
•
•
initial input to output phase difference
initial input to output frequency difference
62
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
•
•
DPLL Loop Filter
DPLL Limiter (phase slope)
Although a short phase lock time is desirable, it is not always achievable due to other synchroniser requirements.
For instance, better jitter transfer performance is obtained with a lower frequency loop filter which increases locking
time; and a better (smaller) phase slope performance will increase locking time. Additionally, the locking time is
dependent on the p_shift value.
The DPLL Loop Filter and Limiter have been optimised to meet the Telcordia GR-1244-CORE jitter transfer and
phase alignment speed requirements. The phase lock time is guaranteed to be no greater than 30 seconds when
using the recommended Stratum 3 and Stratum 4/4E register settings.
9.6 Lock Status
The DPLL has a Lock Status Indicator and a corresponding Lock Change Interrupt. The response of the Lock
Status Indicator is a function of the programmed Lock Detect Interval (LDI) and Lock Detect Threshold (LDT) values
in the dpll_ldetect register. The LDT register can be programmed to set the jitter tolerance level of the Lock Status
Indicator. To determine if the DPLL has achieved lock the Lock Status Indicator must be high for a period of at least
30 seconds. When the DPLL loses lock the Lock Status Indicator will go low after LDI x 125 µs.
9.7 Jitter
The DPLL is designed to withstand, and improve inherent jitter in the TDM clock domain.
9.7.1 Acceptance of Input Wander
For T1(1.544 MHz), E1(2.048 MHz) and J2(6.312 MHz) input frequencies, the DPLL will accept a wander of up to
±1023UI at 0.1 Hz to conform with the relevant specifications. For the 8 kHz (frame rate) and 64 kHz (the divided
pp
down output for T3/E3) input frequencies, the wander acceptance is limited to ±1 UI (0.1 Hz). This principle is
illustrated in Table 24.
9.7.2 Intrinsic Jitter
Intrinsic jitter is the jitter produced by a synchronizer and measured at its output. It is measured by applying a jitter
free reference signal to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured
when the device is in a non synchronizing mode such as free running or holdover, by measuring the output jitter of
the device. Intrinsic jitter is usually measured with various band-limiting filters, depending on the applicable
standards.
1
The intrinsic jitter in the DPLL is reduced to less than 1 ns p-p by an internal Tapped Delay Line (TDL). The DPLL
can be programmed so that the output clock meets all the Stratum 3 requirements of Telcordia GR-1244-CORE.
Stratum 4/4E is also supported.
9.7.3 Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly without cycle slips (i.e., remain in lock and/or
regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its
reference. The applied jitter magnitude and the jitter frequency depends on the applicable standards.
The DPLL’s jitter tolerance can be programmed to meet Telcordia GR-1244-CORE DS1 reference input jitter
tolerance requirements.
1. There are 2 exceptions to this. a) When reference is 8 kHz, and reference frequency offset relative to the master is small, jitter up to 1 master
clock period is possible, i.e. 10 ns p-p. b) In holdover mode, if a huge amount of jitter had been present prior to entering holdover, then an
additional 2 ns p-p is possible.
63
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
9.7.4 Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than
larger ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter
signals (e.g., 75% of the specified maximum jitter tolerance).
The internal DPLL is a first order type 2 component, so a frequency offset doesn’t result in a phase offset. Stratum
3 requires a -3 dB frequency of less than 3 Hz. The nature of the filter results in some peaking, resulting in a -3 dB
frequency of 1.9 Hz and a 0.08 dB peak with a system clock frequency of 100 MHz assuming a p_shift value of 2.
The transfer function is illustrated in Figure 23 and in more detail in Figure 24. Increasing the p_shift value
increases the speed the DPLL will lock to the required frequency and reduces the peak, but also reduces the
tolerance to jitter - so the p_shift value must be programmed correctly to meet Stratum 3 or Stratum 4/4E jitter
transfer characteristics. This is done automatically in the API.
9.8 Maximum Time Interval Error (MTIE)
In order to meet several standards requirements, the phase shift of the DPLL output must be controlled. A potential
phase shift occurs every time the DPLL is re-arranged by changing reference source signal, or the mode. In order
to meet the requirements of Stratum 3, the DPLL will shift phase by no more than 20 ns per re-arrangement.
Additionally the speed at which the change occurs is also critical. A large step change in output frequency is
undesirable. The rate of change is programmable using the skew register, up to a maximum of 15.4 ns / 125 µs
(124 ppm).
Figure 23 - Jitter Transfer Function
64
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
Figure 24 - Jitter Transfer Function - Detail
10.0 Memory Map and Register Definitions
All memory map and register definitions are included in the ZL50115/16/17/18/19/20 Programmers Model
document.
11.0 DC Characteristics
Absolute Maximum Ratings*
Parameter
I/O Supply Voltage
Symbol
Min.
Max.
Units
V
-0.5
-0.5
-0.5
-0.5
-0.5
-
5.0
2.5
2.5
V
V
DD_IO
Core Supply Voltage
V
DD_CORE
PLL Supply Voltage
V
V
DD_PLL
Input Voltage
V
V
+ 0.5
DD
V
I
Input Voltage (5 V tolerant inputs)
Continuous current at digital inputs
Continuous current at digital outputs
Package power dissipation
Storage Temperature
V
7.0
±10
V
I_5V
I
mA
mA
W
°C
IN
I
-
±15
O
PD
TS
-
2.38
+125
-55
* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed. Voltage
measurements are with respect to ground (VSS) unless otherwise stated.
* The core and PLL supply voltages must never be allowed to exceed the I/O supply voltage by more than 0.5 V during power-up. Failure to
observe this rule could lead to a high-current latch-up state, possibly leading to chip failure, if sufficient cross-supply current is available. To be
safe ensure the I/O supply voltage supply always rises earlier than the core and PLL supply voltages.
65
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
Recommended Operating Conditions
Characteristics
Test
Condition
Symbol
Min.
Typ.
Max.
Units
Operating Temperature
T
-40
-40
3.0
1.65
1.65
-
25
-
+85
125
3.6
°C
°C
V
OP
Junction temperature
T
J
Positive Supply Voltage, I/O
Positive Supply Voltage, Core
Positive Supply Voltage, Core
Input Voltage Low - all inputs
Input Voltage High
V
3.3
1.8
1.8
-
DD_IO
V
1.95
1.95
0.8
V
DD_CORE
V
V
DD_PLL
V
V
IL
V
2.0
2.0
-
V
V
IH
DD_IO
Input Voltage High, 5 V tolerant inputs
V
-
5.5
V
IH_5V
Typical figures are at 25°C and are for design aid only, they are not guaranteed and not subject to production testing. Voltage measurements are
with respect to ground (VSS) unless otherwise stated.
66
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
DC Electrical Characteristics - Typical characteristics are at 1.8 V core, 3.3 V I/O, 25°C and typical processing. The min. and max.
values are defined over all process conditions, from -40 to 125°C junction temperature, core voltage 1.65 to 1.95 V and I/O voltage 3.0 and 3.6 V
unless otherwise stated.
Characteristics
Input Leakage
Symbol
Min. Typ. Max. Units.
Test Condition
I
±1
µA
µA
No pull up/down V
= 3.6 V
= 3.6 V
LEIP
DD_IO
DD_IO
Output (High impedance)
Leakage
I
2
No pull up/down V
LEOP
Input Capacitance
Output Capacitance
Pullup Current
C
1
4
pF
pF
µA
µA
IP
C
OP
PU
I
-27
-110
Input at 0 V
Input at 0 V
Pullup Current, 5 V tolerant
inputs
I
I
PU_5V
Pulldown Current
I
27
µA
µA
Input at V
Input at V
PD
DD_IO
DD_IO
Pulldown Current, 5 V tolerant
inputs
110
PD_5V
Core 1.8 V supply current
PLL 1.8 V supply current
I/O 3.3 V supply current
I
950
1.30
120
mA
mA
mA
Note 1,2
DD_CORE
I
DD_PLL
I
Note 1,2
DD_IO
Note 1: The IO and Core supply current worst case figures apply to different scenarios and can not simply be summed for a total
figure. For a clearer indication of power consumption, please refer to Section 13.0.
Note 2: Worst case assumes the maximum number of active contexts and channels. Figures are for the ZL50120. For an indication of
typical power consumption, please refer to Section 13.0.
Input Levels
Characteristics
Input Low Voltage
Symbol
Min.
Typ.
Max.
Units
Test Condition
V
0.8
V
V
V
V
IL
IH
T+
Input High Voltage
V
2.0
Positive Schmitt Threshold
Negative Schmitt Threshold
V
1.6
1.2
V
T-
Output Levels
Characteristics
Symbol
Min.
Typ.
Max.
Units
Test Condition
= 6 mA.
Output Low Voltage
V
0.4
V
I
I
OL
OL
OL
= 12 mA for packet interface
(m*) pins and GPIO pins.
I
= 24 mA for LED pins.
OL
Output High Voltage
V
2.4
V
I
I
= 6 mA.
OH
OH
OH
= 12 mA for packet interface
(m*) pins and GPIO pins.
I
= 24 mA for LED pins.
OH
67
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
12.0 AC Characteristics
12.1 TDM Interface Timing - ST-BUS
The TDM Bus either operates in Slave mode, where the TDM clocks for each stream are provided by the device
sourcing the data, or Master mode, where the TDM clocks are generated from the ZL5011x.
12.1.1 ST-BUS Slave Clock Mode
TDM ST-BUS Slave Timing Specification
Data Format
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
ST-BUS
8.192 Mbps
mode
TDM_CLKi Period
TDM_CLKi High
TDM_CLKi Low
TDM_CLKi Period
TDM_CLKi High
TDM_CLKi Low
t
54
27
27
-
60
66
33
33
-
ns
ns
ns
ns
ns
ns
ns
C16IP
t
-
C16IH
t
-
C16IL
ST-BUS
2.048 Mbps
mode
t
244.1
C4IP
t
110
110
-
-
134
134
C4IH
t
C4IL
All Modes
TDM_F0i Width
8.192 Mbps
t
FOIW
50
200
-
-
-
2.048 Mbps
300
TDM_F0i Setup Time
TDM_F0i Hold Time
TDM_STo Delay
t
5
5
1
-
-
-
-
ns
ns
ns
With respect to
TDM_CLKi
FOIS
FOIH
STOD
falling edge
t
-
With respect to
TDM_CLKi
falling edge
t
20
With respect to
TDM_CLKi
Load C = 50 pF
L
TDM_STi Setup Time
TDM_STi Hold Time
t
5
5
-
-
-
-
ns
ns
With respect to
TDM_CLKi
STIS
t
With respect to
TDM_CLKi
STIH
68
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
In synchronous mode the clock must be within the locking range of the DPLL to function correctly (± 245 ppm). In
asynchronous mode, the clock may be any frequency.
Channel 127 bit 1
Channel 127 bit 0
Channel 0 bit 7
tC16IP
Channel 0 bit 6
TDM_CKLI
TDM_F0i
tFOIH
tFOIS
tSTIH
tSTIS
tSTIH
tSTIS
tSTIH
tSTIS
Ch0 bit7
TDM_STi
TDM_STo
tSTOD
Channel 127 bit 0
tSTOD
Channel 0 bit 7
tSTOD
Channel 127 bit 1
Figure 25 - TDM ST-BUS Slave Mode Timing at 8.192 Mbps
Channel 31 Bit 0
Channel 0 Bit 7
Channel 0 Bit 6
t
C2IP
TDM_CLKI (2.048 MHz)
TDM_CLKI (4.096 MHz)
t
C4IP
t
FOIH
t
FOIS
t
FOIW
TDM_F0i
t
STIH
t
STIS
TDM_STi
TDM_STo
t
t
STOD
STOD
Ch 31 Bit 0
Ch 0 Bit 7
Ch 0 Bit 6
Figure 26 - TDM ST-BUS Slave Mode Timing at 2.048 Mbps
69
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
12.1.2 ST-BUS Master Clock Mode
Data Format
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
ST-BUS
8.192 Mbps
mode
TDM_CLKo Period
TDM_CLKo High
TDM_CLKo Low
TDM_CLKo Period
TDM_CLKo High
TDM_CLKo Low
TDM_F0o Delay
t
54.0
23.0
23.0
237.0
115.0
115.0
-
61.0
68.0
37.0
37.0
251.0
129.0
129.0
25
ns
ns
ns
ns
ns
ns
ns
C16OP
t
-
C16OH
t
-
C16OL
ST-BUS
2.048 Mbps
mode
t
244.1
C4OP
t
-
-
-
C4OH
t
C4OL
All Modes
t
With respect to
TDM_CLKo
falling edge
FOD
TDM_STo Delay
Active-Active
t
-
-
-
-
5
ns
ns
With respect to
TDM_CLKo
falling edge
STOD
TDM_STo Delay
Active to HiZ and
HiZ to Active
t
, t
33
With respect to
TDM_CLKo
falling edge
DZ ZD
TDM_STi Setup Time
t
5
5
-
-
-
-
ns
ns
With respect to
TDM_CLKo
STIS
TDM_STi Hold Time
t
With respect to
TDM_CLKo
STIH
Table 25 - TDM ST-BUS Master Timing Specification
Channel 127 Bit 0
Channel 0 Bit 7
Channel 0 Bit 6
tC16OP
TDM_CLKO
tFOD
tFOD
TDM_F0o
tSTIH
tSTIS
tSTIH
tSTIS
TDM_STi
TDM_STo
B0
B7
B6
tSTOD
tSTOD
Ch 127 Bit 0
Ch 0 Bit 7
Ch 0 Bit 6
Figure 27 - TDM Bus Master Mode Timing at 8.192 Mbps
70
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
Channel 31 Bit 0
Channel 0 Bit 7
tC2OP
Channel 0 Bit 6
TDM_CLKO (2.048 MHz)
TDM_CLKO (4.096 MHz)
TDM_F0o
tC4OP
tFOD
tFOD
tSTIH
tSTIS
TDM_STi
TDM_STo
tSTOD
tSTOD
Ch 31 Bit 0
Ch 0 Bit 7
Ch 0 Bit 6
Figure 28 - TDM Bus Master Mode Timing at 2.048 Mbps
12.2 TDM Interface Timing - H.110 Mode
These parameters are based on the H.110 Specification from the Enterprise Computer Telephony Forum (ECTF)
1997.
Parameter
TDM_C8 Period
Symbol
Min.
Typ.
Max.
Units
Notes
t
122.066-Φ
122
122.074+Φ
ns
Note 1
C8P
Note 2
TDM_C8 High
t
63-Φ
-
-
-
-
69+Φ
69+Φ
11
ns
ns
ns
ns
C8H
TDM_C8 Low
TDM_D Output Delay
TDM_D Output to HiZ
t
63-Φ
0
-
C8L
t
Load - 12 pF
DOD
t
33
Load - 12 pF
Note 3
DOZ
TDM_D HiZ to Output
t
0
-
11
ns
Load - 12 pF
Note 3
ZDO
TDM_D Input Delay to Valid
TDM_D Input Delay to Invalid
TDM_FRAME width
t
0
102
90
45
45
0
-
-
83
112
180
90
ns
ns
ns
ns
ns
ns
Note 4
Note 4
Note 5
DV
t
DIV
t
122
FP
FS
TDM_FRAME setup
t
-
-
-
TDM_FRAME hold
Phase Correction
t
90
10
FH
F
Note 6
Table 26 - TDM H.110 Timing Specification
Note 1: TDM_C8 and TDM_FRAME signals are required to meet the same timing standards and so are not defined independently.
Note 2: TDM_C8 corresponds to pin TDM_CLKi.
Note 3:
tDOZ and tZDO apply at every time-slot boundary.
Note 4: Refer to H.110 Standard from Enterprise Computer Telephony Forum (ECTF) for the source of these numbers.
Note 5: The TDM_FRAME signal is centred on the rising edge of TDM_C8. All timing measurements are based on this rising edge
point; TDM_FRAME corresponds to pin TDM_F0i.
Note 6: Phase correction (Φ) results from DPLL timing corrections.
71
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
Ts 127 Bit 8
Ts 0 Bit 1
tC8P
Ts 0 Bit 2
tC8H
tC8L
TDM_C8
TDM_FRAME
TDM_D Input
TDM_D Output
tFS
tFH
tFP
tDIV
tDV
tZDO
tDOZ
tDOD
Ts 127 Bit 8
Ts 0 Bit 1
Ts 0 Bit 2
Figure 29 - H.110 Timing Diagram
12.3 TDM Interface Timing - H-MVIP
These parameters are based on the Multi-Vendor Integration Protocol (MVIP) specification for an H-MVIP Bus,
Release 1.1a (1997).
Positive transitions of TDM_C2 are synchronous with the falling edges of TDM_C4 and TDM_C16. The signals
TDM_C2, TDM_C4 and TDM_C16 correspond with pins TDM_CLKi. The signals TDM_F0 correspond with pins
TDM_F0i. The signals TDM_HDS correspond with pins TDM_STi and TDM_STo.
Parameter
TDM_C2 Period
Symbol
Min.
Typ.
Max.
Units
Notes
t
487.8
220
220
243.9
110
110
60.9
30
488.3
488.8
268
268
244.4
134
134
61.1
31
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C2P
TDM_C2 High
t
-
C2H
TDM_C2 Low
t
-
C2L
C4P
C4H
TDM_C4 Period
t
244.1
TDM_C4 High
t
-
TDM_C4 Low
t
-
C4L
TDM_C16 Period
TDM_C16 High
t
61.0
C16P
C16H
t
-
TDM_C16 Low
t
30
-
31
C16L
TDM_HDS Output Delay
TDM_HDS Output Delay
TDM_HDS Output to HiZ
TDM_HDS Input Setup
TDM_HDS Input Hold
TDM_F0 width
t
t
-
-
30
At 8.192 Mbps
At 2.048 Mbps
PD
-
-
100
30
PD
t
-
-
HZD
t
30
-
-
0
S
H
t
30
0
t
200
244
300
FW
Table 27 - TDM H-MVIP Timing Specification
72
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
Parameter
TDM_F0 setup
TDM_F0 hold
Symbol
Min.
Typ.
Max.
Units
Notes
t
50
50
-
-
150
150
ns
ns
FS
t
FH
Table 27 - TDM H-MVIP Timing Specification (continued)
Ts 127 Bit 7
Ts 0 Bit 0
tC16H
Ts 0 Bit 1
tC16P
tC16L
TDM_C16
TDM_F0
tFS
tFH
tFW
tH
tS
TDM_HDS Input
tPD
tHZD
Ch 127 Bit 7
Ch 0 Bit 0
TDM_HDS Output
Figure 30 - TDM - H-MVIP Timing Diagram for 16 MHz Clock (8.192 Mbps)
73
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
12.4 TDM LIU Interface Timing
The TDM Interface can be used to directly drive into a Line Interface Unit (LIU). The interface can work in this mode
with E1, DS1, J2, E3 and DS3. The frame pulse is not present, just data and clock is transmitted and received.
Table 28 shows timing for DS3, which would be the most stringent requirement.
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
TDM_TXCLK Period
TDM_TXCLK High
t
22.353
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS3 clock
CTP
t
6.7
6.7
CTH
TDM_TXCLK Low
t
CTL
TDM_RXCLK Period
TDM_RXCLK High
t
22.353
-
DS3 clock
CRP
CRH
t
9.0
9.0
3
TDM_RXCLK Low
t
CRL
TDM_TXDATA Output Delay
TDM_RXDATA Input Setup
TDM_RXDATA Input Hold
t
10
PD
t
6
S
t
3
H
Table 28 - TDM - LIU Structured Transmission/Reception
tCTH
tCTP
tCTL
TDM_TXCLK
tPD
TDM_TXDATA
tCRH
tCRP
tCRL
TDM_RXCLK
tS
tH
TDM_RXDATA
Figure 31 - TDM-LIU Structured Transmission/Reception
74
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
12.5 PAC Interface Timing
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
TDM_CLKiP High / Low
Pulsewidth
t
10
-
-
ns
CPP
TDM_CLKiS High / Low
Pulsewidth
t
10
-
-
ns
CSP
Table 29 - PAC Timing Specification
12.6 Packet Interface Timing
Data for the MII/GMII/TBI packet switching is based on Specification IEEE Std. 802.3 - 2000.
12.6.1 MII Transmit Timing
100 Mbps
Parameter
TXCLK period
Symbol
Units
Notes
Min.
Typ.
Max.
t
-
14
14
-
40
-
-
ns
ns
ns
ns
ns
ns
CC
TXCLK high time
TXCLK low time
TXCLK rise time
TXCLK fall time
t
26
26
5
CHI
t
-
CLO
t
-
CR
t
-
-
5
CF
DV
TXCLK rise to TXD[3:0] active
delay (TXCLK rising edge)
t
1
-
25
Load = 25 pF
Load = 25 pF
Load = 25 pF
TXCLK to TXEN active delay
(TXCLK rising edge)
t
1
1
-
-
25
25
ns
ns
EV
TXCLK to TXER active delay
(TXCLK rising edge)
t
ER
Table 30 - MII Transmit Timing - 100 Mbps
75
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
tCL
tCH
tCC
TXCLK
TXEN
tEV
tEV
tDV
TXD[3:0]
TXER
tER
tER
Figure 32 - MII Transmit Timing Diagram
12.6.2 MII Receive Timing
Parameter
100 Mbps
Symbol
Units
Notes
Min.
Typ.
Max.
RXCLK period
t
t
-
14
14
-
40
20
20
-
-
26
26
5
ns
ns
ns
ns
ns
ns
CC
CH
RXCLK high wide time
RXCLK low wide time
RXCLK rise time
RXCLK fall time
t
CL
t
CR
t
-
-
5
CF
RXD[3:0] setup time (RXCLK
rising edge)
t
10
-
-
DS
RXD[3:0] hold time (RXCLK
rising edge)
t
5
10
5
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
DH
RXDV input setup time
(RXCLK rising edge)
t
DVS
DVH
RXDV input hold time (RXCLK
rising edge)
t
RXER input setup time (RXCL
edge)
t
10
5
ERS
RXER input hold time (RXCLK
rising edge)
t
ERH
Table 31 - MII Receive Timing - 100 Mbps
76
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
tCC
tCLO
tCHI
RXCLK
RXDV
tDVS
tDVH
tDH
tDS
RXD[3:0]
RXER
tERH
tERS
Figure 33 - MII Receive Timing Diagram
77
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
12.6.3 GMII Transmit Timing
1000 Mbps
Parameter
GTXCLK period
Symbol
Units
Notes
Min.
Typ.
Max.
t
7.5
2.5
2.5
-
-
-
-
-
-
-
8.5
-
ns
ns
ns
ns
ns
ns
GC
GTXCLK high time
GTXCLK low time
GTXCLK rise time
GTXCLK fall time
t
t
GCH
t
-
GCL
GCR
1
t
-
1
GCF
Load = 25 pF
Load = 25 pF
Load = 25 pF
GTXCLK rise to TXD[7:0]
active delay
t
1.5
6
DV
GTXCLK rise to TXEN active
delay
t
2
1
-
-
6
6
ns
ns
EV
GTXCLK rise to TXER active
delay
t
ER
Table 32 - GMII Transmit Timing - 1000 Mbps
tCC
tCL
tCH
GTXCLK
TXEN
tEV
tEV
tDV
TXD[3:0]
TXER
tER
tER
Figure 34 - GMII Transmit Timing Diagram
78
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
12.6.4 GMII Receive Timing
Parameter
1000 Mbps
Symbol
Units
Notes
Min.
Typ.
Max.
RXCLK period
t
t
7.5
2.5
2.5
-
-
-
-
-
-
-
8.5
-
ns
ns
ns
ns
ns
ns
CC
CH
RXCLK high wide time
RXCLK low wide time
RXCLK rise time
RXCLK fall time
t
-
CL
t
1
1
-
CR
t
-
CF
RXD[7:0] setup time (RXCLK
rising edge)
t
2
DS
RXD[7:0] hold time (RXCLK
rising edge)
t
1
2
1
2
1
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
DH
RXDV setup time (RXCLK
rising edge)
t
DVS
DVH
RXDV hold time (RXCLK
rising edge)
t
RXER setup time (RXCLK
rising edge)
t
ERS
RXER hold time (RXCLK
rising edge)
t
ERH
Table 33 - GMII Receive Timing - 1000 Mbps
tCC
tCLO
tCHI
RXCLK
RXDV
tDVS
tDVH
tDH
tDS
RXD[7:0]
RXER
tERH
tERS
Figure 35 - GMII Receive Timing Diagram
79
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
12.6.5 TBI Interface Timing
Parameter
1000 Mbps
Symbol
Units
Notes
Min.
Typ.
Max.
GTXCLK period
GTXCLK high wide time
GTXCLK low wide time
TXD[9:0] Output Delay
(GTXCLK rising edge)
t
t
t
7.5
2.5
2.5
1
-
-
-
-
8.5
-
-
ns
ns
ns
GC
GH
GL
DV
t
6
Load = 25 pF
RCB0/RBC1 period
t
t
t
t
t
15
5
5
-
-
2
16
-
-
-
-
17
-
-
2
2
-
ns
ns
ns
ns
ns
ns
RC
RH
RCB0/RBC1 high wide time
RCB0/RBC1 low wide time
RCB0/RBC1 rise time
RCB0/RBC1 fall time
RXD[9:0] setup time (RCB0
rising edge)
RL
RR
RF
DS
t
-
RXD[9:0] hold time (RCB0
rising edge)
t
1
-
-
ns
DH
REFCLK period
REFCLK high wide time
REFCLK low wide time
t
t
t
7.5
2.5
2.5
-
-
-
8.5
-
-
ns
ns
ns
FC
FH
FL
Table 34 - TBI Timing - 1000 Mbps
tGC
GTXCLK
tDV
TXD[9:0] /I/ /S/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /T/ /R/ /I/
Signal_Detect
Figure 36 - TBI Transmit Timing Diagram
80
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
tRC
RBC1
RBC0
tRC
tDH
tDH
tDS
tDS
RXD[9:0]
/I/
/S/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/D/ /D/ /D/ /D/ /T/ /R/
/I/
Signal_Detect
Figure 37 - TBI Receive Timing Diagram
12.6.6 Management Interface Timing
The management interface is common for all inputs and consists of a serial data I/O line and a clock line.
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
M_MDC Clock Output period
M_MDC high
M_MDC low
M_MDC rise time
M_MDC fall time
t
1990
900
900
-
-
10
2000
1000
1000
-
-
-
2010
1100
1100
5
5
-
ns
ns
ns
ns
ns
ns
Note 1
MP
t
MHI
t
MLO
tMR
t
t
MF
MS
M_MDIO setup time (MDC
Note 1
Note 1
Note 2
rising edge)
M_MDIO hold time (M_MDC
rising edge)
t
t
10
1
-
-
-
ns
ns
MH
MD
M_MDIO Output Delay
300
(M_MDC rising edge)
Table 35 - MAC Management Timing Specification
Note 1: Refer to Clause 22 in IEEE802.3 (2000) Standard for input/output signal timing characteristics.
Note 2: Refer to Clause 22C.4 in IEEE802.3 (2000) Standard for output load description of MDIO.
tMHI
tMLO
M_MDC
M_MDIO
tMS
tMH
Figure 38 - Management Interface Timing for Ethernet Port - Read
tMP
M_MDC
M_MDIO
tMD
Figure 39 - Management Interface Timing for Ethernet Port - Write
81
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
12.7 CPU Interface Timing
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
CPU_CLK Period
t
15.152
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CC
CPU_CLK High Time
t
6
6
CCH
CPU_CLK Low Time
t
CCL
CCR
CPU_CLK Rise Time
t
4
4
CPU_CLK Fall Time
t
t
CCF
CAS
CAH
CDS
CDH
CPU_ADDR[23:2] Setup Time
CPU_ADDR[23:2] Hold Time
CPU_DATA[31:0] Setup Time
CPU_DATA[31:0] Hold Time
CPU_CS Setup Time
4
2
4
2
4
2
5
2
4
2
2
t
t
t
t
CSS
CPU_CS Hold Time
t
CSH
CPU_WE/CPU_OE Setup Time
CPU_WE/CPU_OE Hold Time
CPU_TS_ALE Setup Time
CPU_TS_ALE Hold Time
t
CES
t
CEH
t
CTS
CTH
CKS
t
t
CPU_SDACK1/CPU_SDACK2
Setup Time
CPU_SDACK1/CPU_SDACK2
Hold Time
t
2
ns
Note 1
CKH
CPU_TA Output Valid Delay
t
2
2
11.3
6
ns
ns
Note 1, 2
Note 1
CTV
CPU_DREQ0/CPU_DREQ1
Output Valid Delay
t
CWV
CPU_IREQ0/CPU_IREQ1 Output
Valid Delay
t
2
2
6
7
ns
ns
Note 1
Note 1
CRV
CDV
CPU_DATA[31:0] Output Valid
Delay
t
CPU_CS to Output Data Valid
CPU_OE to Output Data Valid
t
3.2
3.3
3.2
10.4
10.4
9.5
ns
ns
ns
SDV
t
ODV
CPU_CLK(falling) to CPU_TA
Valid
t
OTV
Table 36 - CPU Timing Specification
Note 1: Load = 50 pF maximum
Note 2: The maximum value of tCTV may cause setup violations if directly connected to the MPC8260. See Section 14.2 for details of
how to accommodate this during board design.
82
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
The actual point where read/write data is transferred occurs at the positive clock edge following the assertion of
CPU_TA, not at the positive clock edge during the assertion of CPU_TA.
tCC
0 or more cycles
CPU_CLK
tCAH
tCAS
tCSS
CPU_ADDR[23:2]
CPU_CS
tCSH
tCEH
tCES
CPU_OE
CPU_WE
tCTH
tCTS
CPU_TS_ALE
CPU_DATA[31:0]
CPU_TA
tODV
tODV
tSDV
tSDV
tCDV
tCTV
tOTV
tCTV
tOTV
NOTE: CPU_DATA is valid when CPU_TA is asserted. CPU_DATA will remain valid while both CPU_CS
and CPU_OE are asserted. CPU_TA will continue to be driven until CPU_CS is deasserted.
CPU_CS and CPU_OE must BOTH be asserted to enable the CPU_DATA output.
Figure 40 - CPU Read - MPC8260
t
0 or more cycles
CC
0 or more cycles
CPU_CLK
t
CAH
t
t
CAS
CPU_ADDR[23:2]
t
CSS
CSH
CPU_CS
CPU_OE
t
t
CEH
CES
CPU_WE
CPU_TS_ALE
CPU_DATA[31:0]
CPU_TA
t
CTH
t
CTS
t
CDH
t
CDS
t
CTV
t
t
t
OTV
OTV
CTV
NOTE: Following assertion of CPU_TA, CPU_CS may be deasserted. The MPC8260 will continue to assert CPU_CS
until CPU_TA has been synchronized internally. CPU_TA will continue to be driven until CPU_CS is
finally deasserted. During continued assertion of CPU_CS, CPU_WE and CPU_DATA may be removed.
Figure 41 - CPU Write - MPC8260
83
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
t
0 or more cycles
CC
CPU_CLK
t
t
CWV
CWV
CPU_DREQ1
t
CKH
t
CKS
CPU_SDACK2
CPU_CS
t
t
t
CSH
CSS
t
t
CEH
CES
CPU_OE
CPU_WE
t
CTH
CTS
CPU_TS_ALE
CPU_DATA[31:0]
CPU_TA
t
t
t
ODV
ODV
SDV
t
t
t
SDV
CDV
CTV
t
t
t
OTV
OTV
CTV
Note 1: CPU_SDACK2 must be asserted during the cycle shown. It may then be deasserted at any time. CPU_DATA is valid
when CPU_TA is asserted (always timed as shown). CPU_DATA will remain valid while CPU_CS and CPU_OE are asserted.
CPU_TA will continue to be driven until CPU_CS is deasserted. CPU_CS and CPU_OE must BOTH be asserted to enable
the CPU_DATA output.
Note 2: CPU_DREQ1 shown with postive polarity
CPU_SDACK2 shown with negative polarity
Figure 42 - CPU DMA Read - MPC8260
t
0 or more cycles
CC
CPU_CLK
t
t
CWV
CWV
CPU_DREQ0
t
CKH
t
CKS
CPU_SDACK1
t
t
t
CSH
CSS
CPU_CS
CPU_OE
t
t
CEH
CES
CPU_WE
CPU_TS_ALE
CPU_DATA[31:0]
CPU_TA
t
CTH
CTS
t
CDH
t
CDS
t
CTV
t
t
t
OTV
OTV
CTV
Note 1: CPU_SDACK1 must be asserted during the cycle shown. It may then be deasserted at any time.
Following assertion of CPU_TA (always timed as shown), CPU_CS may be deasserted. The MPC8260
will continue to assert CPU_CS until CPU_TA has been synchronized internally. CPU_TA will continue
to be driven until CPU_CS is finally deasserted. During continued assertion of CPU_CS, CPU_WE and
CPU_DATA may be removed.
Note 2: CPU_DREQ0 shown with positive polarity
CPU_SDACK1 shown with negative polarity
Figure 43 - CPU DMA Write - MPC8260
84
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
12.8 System Function Port
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
SYSTEM_CLK Frequency
CLK
-
100
-
MHz
Note 1, Note 2
and Note 5
FR
SYSTEM_CLK accuracy
CLK
CLK
-
-
-
-
±30
ppm
ppm
Note 3
ACS
ACA
(synchronous master mode)
SYSTEM_CLK accuracy
(synchronous slave mode and
asynchronous mode)
±200
Note 4
Table 37 - System Clock Timing
Note 1: The system clock frequency stability affects the holdover-operating mode of the DPLL. Holdover Mode is typically used for a
short duration while network synchronisation is temporarily disrupted. Drift on the system clock directly affects the Holdover
Mode accuracy. Note that the absolute system clock accuracy does not affect the Holdover accuracy, only the change in the
system clock (SYSTEM_CLK) accuracy while in Holdover. For example, if the system clock oscillator has a temperature
coefficient of 0.1 ppm/ºC, a 10ºC change in temperature while the DPLL is in will result in a frequency accuracy offset of
1 ppm. The intrinsic frequency accuracy of the DPLL Holdover Mode is 0.06 ppm, excluding the system clock drift.
Note 2: The system clock frequency affects the operation of the DPLL in free-run mode. In this mode, the DPLL provides timing and
synchronisation signals which are based on the frequency of the accuracy of the master clock (i.e., frequency of clock output
equals 8.192 MHz ± SYSTEM_CLK accuracy ± 0.005 ppm).
Note 3: The absolute SYSTEM_CLK accuracy must be controlled to ± 30 ppm in synchronous master mode to enable the internal
DPLL to function correctly.
Note 4: In asynchronous mode and in synchronous slave mode the DPLL is not used. Therefore the tolerance on SYSTEM_CLK may
be relaxed slightly.
Note 5: The quality of SYSTEM_CLK, or the oscillator that drives SYSTEM_CLK directly impacts the adaptive clock recovery
performance. See Section 6.3.
85
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
12.9 JTAG Interface Timing
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
JTAG_CLK period
t
40
20
100
-
ns
ns
JCP
JTAG_CLK clock pulse width
t
-
LOW,
HIGH
t
JTAG_CLK rise and fall time
JTAG_TRST setup time
t
0
-
-
3
-
ns
ns
JRF
t
10
With respect to
JTAG_CLK
falling edge.
Note 1
RSTSU
JTAG_TRST assert time
Input data setup time
t
10
5
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
RST
t
Note 2
Note 2
Note 3
Note 3
JSU
Input Data hold time
t
15
0
-
JH
JTAG_CLK to Output data valid
t
20
20
JDV
JTAG_CLK to Output data high
impedance
t
0
JZ
JTAG_TMS, JTAG_TDI setup time
JTAG_TMS, JTAG_TDI hold time
JTAG_TDO delay
t
5
15
0
-
-
-
-
-
ns
ns
ns
ns
TPSU
t
-
TPH
t
15
15
TOPDV
JTAG_TDO delay to high
impedance
t
0
TPZ
Table 38 - JTAG Interface Timing
Note 1: JTAG_TRST is an asynchronous signal. The setup time is for test purposes only.
Note 2: Non Test (other than JTAG_TDI and JTAG_TMS) signal input timing with respect to JTAG_CLK.
Note 3: Non Test (other than JTAG_TDO) signal output with respect to JTAG_CLK.
t
LOW
t
t
HIGH
JCP
JTAG_TCK
t
TPH
t
TPSU
JTAG_TMS
JTAG_TDI
JTAG_TDO
t
t
TPH
TPSU
Don't Care
HiZ
DC
t
t
TPZ
TOPDV
HiZ
Figure 44 - JTAG Signal Timing
86
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
t
t
HIGH
LOW
JTAG_TCK
t
t
RSTSU
RST
JTAG_TRST
Figure 45 - JTAG Clock and Reset Timing
13.0 Power Characteristics
The following graph in Figure 46 illustrates typical power consumption figures for the ZL5011x family. Typical
characteristics are at 1.8 V core, 3.3V I/O, 25°C and typical processing.
ZL50118/19/20 Power Consumption
(Typical Conditions)
1.410
1.400
1.390
1.380
1.370
1.360
1.350
1
2
3
4
Number of Active E1 Unstructured Contexts
Figure 46 - ZL50115/16/17/18/19/20 Power Consumption Plot
87
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
14.0 Design and Layout Guidelines
This guide will provide information and guidance for PCB layouts when using the ZL5011x. Specific areas of
guidance are:
•
•
High Speed Clock and Data, Outputs and Inputs
CPU_TA Output
14.1 High Speed Clock & Data Interfaces
On the ZL5011x series of devices there are four high-speed data interfaces that need consideration when laying out
a PCB to ensure correct termination of traces and the reduction of crosstalk noise. The interfaces being:
•
•
•
GMAC Interfaces
TDM Interface
CPU Interface
It is recommended that the outputs are suitably terminated using a series termination through a resistor as close to
the output pin as possible. The purpose of the series termination resistor is to reduce reflections on the line. The
value of the series termination and the length of trace the output can drive will depend on the driver output
impedance, the characteristic impedance of the PCB trace (recommend 50 ohm), the distributed trace capacitance
and the load capacitance. As a general rule of thumb, if the trace length is less than 1/6th of the equivalent length of
the rise and fall times, then a series termination may not be required.
the equivalent length of rise time = rise time (ps) / delay (ps/mm)
For example:
Typical FR4 board delay = 6.8 ps/mm
Typical rise/fall time for a ZL5011x output = 2.5 ns
critical track length = (1/6) x (2500/6.8) = 61 mm
Therefore tracks longer than 61 mm will require termination.
As a signal travels along a trace it creates a magnetic field, which induces noise voltages in adjacent traces, this is
crosstalk. If the crosstalk is of sufficiently strong amplitude, false data can be induced in the trace and therefore it
should be minimized in the layout. The voltage that the external fields cause is proportional to the strength of the
field and the length of the trace exposed to the field. Therefore to minimize the effect of crosstalk some basic
guidelines should be followed.
First, increase separation of sensitive signals, a rough rule of thumb is that doubling the separation reduces the
coupling by a factor of four. Alternatively, shield the victim traces from the aggressor by either routing on another
layer separated by a power plane (in a correctly decoupled design the power planes have the same AC potential) or
by placing guard traces between the signals usually held ground potential.
Particular effort should be made to minimize crosstalk from ZL5011x outputs and ensuring fast rise time to these
inputs.
88
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
In Summary:
•
•
•
•
Place series termination resistors as close to the pins as possible
minimize output capacitance
Keep common interface traces close to the same length to avoid skew
Protect input clocks and signals from crosstalk
14.1.1 GMAC Interface - Special Considerations During Layout
The GMII interface passes data to and from the ZL5011x with their related transmit and receive clocks. It is
therefore recommended that the trace lengths for transmit related signals and their clock and the receive related
signals and their clock are kept to the same length. By doing this the skew between individual signals and their
related clock will be minimized.
14.1.2 TDM Interface - Special Considerations During Layout
Although the data rate of this interface is low the outputs edge speeds share the characteristics of the higher data
rate outputs and therefore must be treated with the same care extended to the other interfaces with particular
reference to the lower stream numbers which support the higher data rates. The TDM interface has numerous
clocking schemes and as a result of this the input clock traces to the ZL5011x devices should be treated with care.
14.1.3 Summary
Particular effort should be made to minimize crosstalk from ZL5011x outputs and ensuring fast rise time to these
inputs.
In Summary:
•
•
•
•
Place series termination resistors as close to the pins as possible
minimize output capacitance
Keep common interface traces close to the same length to avoid skew
Protect input clocks and signals from crosstalk
89
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
14.2 CPU TA Output
The CPU_TA output signal from the ZL5011x is a critical handshake signal to the CPU that ensures the correct
completion of a bus transaction between the two devices. As the signal is critical, it is recommend that the circuit
shown in Figure 46 is implemented in systems operating above 40 MHz bus frequency to ensure robust operation
under all conditions.
The following external logic is required to implement the circuit:
•
•
•
•
74LCX74 dual D-type flip-flop (one section of two)
74LCX08 quad AND gate (one section of four)
74LCX125 quad tri-state buffer (one section of four)
4K7 resistor x2
+3V3
+3V3
R1
R2
4K7
4K7
CPU_TA
CPU_TA
to CPU
from ZL5011x
Q
D
CPU_CS
CPU_CLK
to ZL5011x
to ZL5011x
Figure 47 - CPU_TA Board Circuit
The function of the circuit is to extend the TA signal, to ensure the CPU correctly registers it. Resistor R2 must be
fitted to ensure correct operation of the TA input to the processor. It is recommended that the logic is fitted close to
the ZL5011x and that the clock to the 74LCX74 is derived from the same clock source as that input to the ZL5011x.
90
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
15.0 Reference Documents
15.1 External Standards/Specifications
IEEE Standard 1149.1-2001; Test Access Port and Boundary Scan Architecture
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IEEE Standard 802.3-2000; Local and Metropolitan Networks CSMA/CD Access Method and Physical Layer
ECTF H.110 Revision 1.0; Hardware Compatibility Specification
H-MVIP (GO-MVIP) Standard Release 1.1a; Multi-Vendor Integration Protocol
MPC8260AEC/D Revision 0.7; Motorola MPC8260 Family Hardware Specification
RFC 768; UDP
RFC 791; IPv4
RFC2460; IPv6
RFC 1889; RTP
RFC 2661; L2TP
RFC 1213; MIB II
RFC 1757; Remote Network Monitoring MIB (for SMIv1)
RFC 2819; Remote Network Monitoring MIB (for SMIv2)
RFC 2863; Interfaces Group MIB
CCITT G.712; TDM Timing Specification (Method 2)
G.823; Control of Jitter/Wander with digital networks based on the 2.048 Mbps hierarchy
G.824; Control of Jitter/Wander with digital networks based on the 1.544 Mbps hierarchy
ANSI T1.101 Stratum 3/4
Telcordia GR-1244-CORE Stratum 3/4/4e
IETF PWE3 draft-ietf-l2tpext-l2tp-base-02
IETF PWE3 draft-ietf-pwe3-cesopsn
IETF PWE3 draft-ietf-pwe3-satop
ITU-T Y.1413 TDM-MPLS Network Interworking
15.2 Zarlink Standards
•
MSAN-126 Revision B, Issue 4; ST-BUS Generic Device Specification
91
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
16.0 Glossary
API
Application Program Interface
Asynchronous Transfer Mode
ATM
CDP
CESoP
Context Descriptor Protocol (the protocol used by Zarlink’s MT9088x family of TDM-Packet devices)
Circuit Emulation Services over Packet
CESoPSN Circuit Emulation Services over Packet Switched Networks
CONTEXT A programmed connection of a number of TDM timeslots assembled into a unique packet stream.
CPU
DMA
DPLL
DSP
GMII
Central Processing Unit
Direct Memory Access
Digital Phase Locked Loop
Digital Signal Processor
Gigabit Media Independent Interface
H.100/H.110High capacity TDM backplane standards
H-MVIP
IETF
IA
High-performance Multi-Vendor Integration Protocol (a TDM bus standard)
Internet Engineering Task Force
Implementation Agreement
IP
Internet Protocol (version 4, RFC 791, version 6, RFC 2460)
JTAG
Joint Test Algorithms Group (generally used to refer to a standard way of providing a board-level test
facility)
L2TP
LAN
LIU
Layer 2 Tunneling Protocol (RFC 2661)
Local Area Network
Line Interface Unit
MAC
MEF
MFA
MII
Media Access Control
Metro Ethernet Forum
MPLS and Frame Relay Alliance
Media Independent Interface
Management Information Base
Multi Protocol Label Switching
Maximum Time Interval Error
Multi-Vendor Integration Protocol (a TDM bus standard)
Plesiochronous Digital Hierarchy
Phase Locked Loop
MIB
MPLS
MTIE
MVIP
PDH
PLL
PRS
PRX
PSTN
Primary Reference Source
Packet Receive
Public Switched Telephone Circuit
92
Zarlink Semiconductor Inc.
ZL50115/16/17/18/19/20
Data Sheet
PTX
Packet Transmit
PWE3
QoS
RTP
Pseudo-Wire Emulation Edge to Edge (a working group of the IETF)
Quality of Service
Real Time Protocol (RFC 1889)
Protocol Engine
PE
SAToP
ST BUS
TDL
Structure-Agnostic TDM over Packet
Standard Telecom Bus, a standard interface for TDM data streams
Tapped Delay Line
TDM
UDP
UI
Time Division Multiplexing
User Datagram Protocol (RFC 768)
Unit Interval
VLAN
WFQ
Virtual Local Area Network
Weighted Fair Queuing
93
Zarlink Semiconductor Inc.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
相关型号：
©2020 ICPDF网 联系我们和版权申明