ZL20250/LCE [ZARLINK]
RF and Baseband Circuit, PQCC56, 8 X 8 MM, QFN-56;
| 型号： | ZL20250/LCE |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | RF and Baseband Circuit, PQCC56, 8 X 8 MM, QFN-56 |
| 文件： | 总56页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL20250
2.5G Multimode Transceiver
Data Sheet
September 2003
Features
•
Quad Band GSM (800/900/1800/1900 MHz)
Compatible
Ordering Information
•
•
•
•
•
•
•
•
•
•
•
Dual Band IS136 (800/1900 MHz) Compatible
GPRS Class 12 and EDGE Capable
Fully Integrated Dual Band Transceiver
Receive - IF to Baseband I and Q
Transmit - Baseband I / Q to RF
Integrated Filters
ZL20250/LCE (Tubes) 56 pin QFN
ZL20250/LCF (Tape and Reel) 56 pin QFN
-40°C to +85°C
Description
The ZL20250 is a fully integrated transceiver for
multimode IS136/GSM/GPRS/EDGE handsets. The
dual IF inputs to the receive path are amplified and
down-converted to baseband I and Q signals. Gain
control and baseband filtering are provided. A FM
demodulator is also provided where AMPS
compatibility is required.
FM Demodulator
RF and IF Synthesizers
Fully Programmable via serial bus
3 Volt operation
Small scale package
Applications
The transmit path consists of a quadrature modulator,
gain control at IF and up-conversion to RF. Dual band
RF outputs are provided.
•
GAIT IS136/GSM/EDGE Mobile Telephones
•
Dual Band (850/PCS1900) TDMA/AMPS Mobile
Telephones
ZL20250 also includes a fractional N RF synthesizer
and two IF synthesizers to provide all local oscillator
signals required.
•
Cellular 850MHz TDMA/AMPS Mobile
Telephones
•
•
PCS1900 TDMA Mobile Telephones
Flexible programming is provided via a 3 wire serial
bus. Additional control pins allow accurate timing
control when switching between modes.
2.5G World Phones - Quad Band
(850/900/1800/1900)
•
Cellular Telematic Systems
GSM/EDGE
Rx I
90°
Rx Q
IS136
FM
FM
Demod
RSSI
Rx VHF
PLL
LOCK DET
Serial
Interface
Control
Tx VHF
PLL
UHF LO O/P
UHF
PLL
UHF VCO
900 MHz Tx
Tx I
IQ
Mod
Tx Q
1900 MHz Tx
Tx IF Filter
(Opt)
Figure 1 - Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
ZL20250
Data Sheet
Package Diagram
RX Q-
SDAT
SCLK
RX Q+
RSSI
SLATCH
TCXO
RX CP
VCC VHF CP
VCC UHF PLL
UHF CP
ISET
LOCK DET
VCC UHF LO OUT
900 LO OUT
1900 LO OUT
RESETB
ZL20250
TX CP
TX RXB
TX I-
TX I+
ENABLE1
VCC TX PLL
TX VCO-
900 LO IN
VCC UHF LO
1900 LO IN
TX VCO+
Figure 2 - ZL20250 Package Diagram
2
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Pin Description Table
No
Pin Name
SDAT
Type
Input
Description
1
2
3
4
5
6
7
8
9
Serial Interface - Data
Serial interface - Clock
Serial Interface - Latch
Reference input from TCXO
Power
SCLK
Input
SLATCH
TCXO
Input
Input
VCC UHF PLL
UHF CP
Power
Output
UHF PLL Charge Pump Output
Power to LO output stages
900 MHz buffered LO output to external receiver mixer
1900 MHz buffered LO output to external receiver mixer
Reset (Active low)
VCC UHF LO OUT Power
900 LO OUT
1900 LO OUT
Output
Output
Input
10 RESETB
11 ENABLE1
12 900 LO IN
13 VCC UHF LO
14 1900 LO IN
15 VCC TX RF
16 TX 900
Input
Mode Control
Input
900 MHz LO input
Power
Input
Power to UHF LO input stage
1900 MHz LO input
Power
Output
Power to transmit RF output stages
900 MHz transmit output
17 TX DEG900
18 TX DEG1900
19 TX 1900
Degeneration for 900 MHz output
Degeneration for 1900 MHz output
1900 MHz transmit output
Output
Input
20 ENABLE2
21 TX GAIN
22 TX FILT IN+
23 TX FILT IN-
24 VCC TX
Mode Control
Input
Transmit gain control
Input
Input from transmit IF filter (optional)
Input
Power
Output
Output
Input
Power to transmit stages
25 TX FILT OUT+
26 TX FILT OUT-
27 TX Q+
Output to transmit IF filter (optional)
Q transmit signal from baseband
Transmit Oscillator tank circuit
28 TX Q-
Input
29 TX VCO+
30 TX VCO-
31 VCC TX PLL
32 TX I+
Power
Input
Power to Transmit VHF PLL
I transmit signal from baseband
33 TX I-
Input
34 TX RXB
Input
Transmit / Receive control
35 TX CP
Output
Output
Transmit VHF PLL charge pump output
PLL Lock Detect Output
36 LOCK DET
37 ISET
Connect 50 kohm resistor to ground to set internal reference current
Power to VHF charge pump outputs
38 VCC VHF CP
Power
3
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Pin Description Table (continued)
No
Pin Name
Type
Output
Description
39 RX CP
Receive VHF PLL charge pump output
RSSI Output
40 RSSI
Output
Output
Output
Output
Output
Output
41 RX Q+
Baseband Q signal
42 RX Q-
43 RX I+
Baseband I signal
44 RX I-
45 FM OUT
46 FM FB
Demodulated FM output
Feedback to FM output stage
Receive second LO Oscillator tank circuit
47 RX VCO-
48 RX VCO+
49 VCC RX PLL
50 VCC RX
51 RX GAIN
52 IF0 IN-
Power
Power
Input
Power to receive VHF PLL. Connect to VCC through 10 ohm resistor
Power to receive stages
Receive gain control
IF Input (0)
Input
53 IF0 IN+
54 IF1 IN-
Input
GSM
Input
IF Input (1)
55 IF1 IN+
56 VCC CONTROL
Input
IS136 Input
Power
Power to serial interface logic
4
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Table of Contents
1.0 General Description......................................................................................................................................... 8
1.1 Receive Path ............................................................................................................................................... 9
1.1.1 IS136.................................................................................................................................................. 9
1.1.2 AMPS FM......................................................................................................................................... 11
1.1.3 GSM................................................................................................................................................. 14
1.2 Transmit..................................................................................................................................................... 16
1.3 UHF LO and Frequency Doubler............................................................................................................... 19
1.4 UHF Frequency Synthesizer ..................................................................................................................... 19
1.5 VHF Frequency Synthesizer...................................................................................................................... 22
1.6 Internal Clock Generation.......................................................................................................................... 23
1.7 VHF VCO................................................................................................................................................... 23
1.8 Power Supply Connections ....................................................................................................................... 24
2.0 Programming and Control ............................................................................................................................ 25
2.1 Power Control Registers - Address 0 to 3 ................................................................................................. 25
2.1.1 Power Control Modes - TDMA (GSM and IS136) ............................................................................ 27
2.1.2 Power Control Modes - AMPS ......................................................................................................... 28
2.2 Operating Register Address 4 ................................................................................................................... 29
2.3 Synthesizer Register - Address 5.............................................................................................................. 33
2.3.1 UHF PLL and LO.............................................................................................................................. 33
2.3.2 UHF PLL Charge Pump Current ...................................................................................................... 34
2.3.3 Receive LO Set Up .......................................................................................................................... 34
2.3.4 Transmit LO Set Up ......................................................................................................................... 35
2.4 Control Register - Address 6 ..................................................................................................................... 35
2.4.1 IS136 Baseband Gain...................................................................................................................... 35
2.4.2 TCXO Reference Selection............................................................................................................. 36
2.4.3 Discriminator Output Filtering........................................................................................................... 36
2.4.4 Transmit baseband Gain.................................................................................................................. 37
2.4.5 Mode Control.................................................................................................................................... 37
2.5 GSM/EDGE Baseband Control Register - Address 7................................................................................ 37
2.5.1 Q Channel Gain Adjust .................................................................................................................... 38
2.5.2 Baseband Offset Correction............................................................................................................. 38
2.6 Test Mode Register - Address 8................................................................................................................ 38
2.7 UHF PLL Divider Programming Register - Address 9 ............................................................................... 39
2.8 UHF PLL Reference Divider and Fractional N Programming Register - Address 10 ................................ 39
2.9 Receive VHF PLL Divider Programming Register - Address 11 ............................................................... 39
2.10 Receive VHF PLL Reference Divider Programming Register - Address 12............................................ 40
2.11 Transmit VHF PLL Divider Programming Register - Address 13 ............................................................ 40
2.12 Transmit VHF PLL Reference Divider Programming Register Address 14............................................. 40
2.13 PLL Lock Detect & Fractional N Compensation Programming Register Address 15.............................. 40
2.13.1 Fractional N Compensation............................................................................................................ 41
2.13.2 PLL Lock detect counters............................................................................................................... 41
3.0 Absolute Maximum Ratings.......................................................................................................................... 41
4.0 Operating Conditions .................................................................................................................................... 41
5.0 Electrical Characteristics .............................................................................................................................. 43
6.0 Typical Performance Curves ........................................................................................................................ 51
6.1 Receive...................................................................................................................................................... 51
6.2 Transmit..................................................................................................................................................... 52
5
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
List of Figures
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL20250 Package Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3 - ZL20250 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4 - IS136 Receiver Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5 - AMPS Receive Signal Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6 - GSM Receive Signal Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7 - Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8 - External Transmit IF Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9 - UHF Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10 - Count Sequence for UHF PLL with 4 modulus prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11 - UHF Synthesizer - Fractional N Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12 - VHF Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13 - Typical VCO Tank Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14 - Serial Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15 - Transmit Output Stage Current versus Gain Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
List of Tables
Table 1 - IS136 Receive Gain and Filter Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2 - AMPS FM Receive Gain and Filter Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3 - GSM Receive Gain and Filter Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4 - Transmit Circuit blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
1.0 General Description
A detailed block diagram is shown in Figure 3. This shows the receive and transmit paths plus the LO generation
circuitry. Control is via a serial bus with the addition of direct inputs to control receive and transmit modes and
optimize power consumption.
43 RX I+
MUX
53
52
IF0 IN+
IF0 IN–
44 RX I–
FM OUT
46 FM FB
45
AMPS demod.
and RSSI
RX GAIN 51
π
/2
RSSI
40
60kHz
IF1 IN+ 55
IF1 IN– 54
41 RX Q+
42 RX Q–
dc
Offset
MUX
÷
N
π
/2
PLL
50
48
47
39
Tank
Circuit
Loop
Filter
Control
I SET 37
VCC RX PLL 49
36 LOCK DET
4
TCXO
10
RESETB
11 ENABLE1
20
Control
13
7
ENABLE2
900 LO IN
12
VCC TX PLL 31
34 TX RXB
VCC VHF CP 38
Loop
Filter
56 VCC CONTROL
Loop
Filter
1900
LO OUT
LO Select
and
Doubler
9
8
1
SDAT
900
LO OUT
Serial
interface
Option
2
3
SCLK
SLATCH
Tank
Circuit
14
1900 LO IN
29
6
5
30
35
PLL
PLL
π
/2
19
TX 1900
π
/2
TX I+
32
33 TX I–
π
/2
MUX
Σ
TX Q+
TX Q–
27
28
TX 900 16
21
24
18
17
15
23 22
25 26
Option
Figure 3 - ZL20250 Detailed Block Diagram
8
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
1.1 Receive Path
There are two IF inputs which will receive an input signal from IS136/AMPS and GSM IF filters. The differential input
stages are identical and are followed by an agc amplifier. Gain control is provided from an external analogue voltage.
After the agc amplifier the signal is then down-converted either to a low IF frequency or baseband and the signal flow
then depends on the mode selected. All internal signals are differential. The LO frequency for the down conversion
is derived from an on chip oscillator and PLL. The LO frequency can be programmed to be either oscillator frequency
divided by 2 or 4. When in divide by 2 mode a DLL (Delay Locked Loop) circuit can be selected to maintain accurate
quadrature. It is particularly important to have good quadrature in IS136/AMPS modes using a low IF frequency, to
achieve the required image rejection in conjunction with the following polyphase bandpass filter. It is also possible
to programme high side or low LO injection. Each receive mode will now be described in more detail
1.1.1 IS136
The IS136 receive signal path is shown in detail in Figure 4 and performance for each stage is summarized in the
following table.
Filter
Circuit
Block
Gain
(dB)
Bandwidth
Description
(If Applicable)
IF Input (IF0)
26
Differential IF input stage
max
AGC Amplifier
AGC Amplifier - Gain control range 90dB
Down-conversion to 60kHz IF
Quadrature
Down-converter
47
Anti-alias filter
230 kHz
Low pass Butterworth (n= 3)
Band Pass Filter
+/- 20 kHz
Switched capacitor polyphase Chebyshev. Also
provides typically 30 dB image rejection. Centre
frequency = 60 kHz. Clock frequencies 1.44 MHz and
720 kHz.
Gain Stage
Baseband Down-converter
Baseband filter 1
Down conversion to baseband I and Q signals
37.5 kHz
60 kHz
Switched capacitor low pass Chebyshev. Clock
frequency = 240 kHz
7
Baseband filter 2
Smoothing filter. Low pass Butterworth
Table 1 - IS136 Receive Gain and Filter Distribution
The output of the agc amplifier is down-converted using a quadrature mixer to a low IF of 60kHz. High side or low
side LO injection can be selected. The In Phase (I) and Quadrature (Q) signals at 60 kHz are then passed through
anti alias filter stage to remove any high frequency signals prior to subsequent sampling. The 60 kHz IF signals are
then fed into a switched capacitor polyphase bandpass filter which not only provides filtering but also provides image
rejection. This switched capacitor filter provides very stable performance and no calibration is required. After the
bandpass filter the 60 kHz IF signal is further amplified and then mixed down to baseband I and Q signals. Additional
filtering is required at baseband to remove spurii from the down-converter. This filtering is provide in two stages, the
first stage is a switched capacitor filter with the second stage being a smoothing filter to remove clock breakthrough
from the preceding switched capacitor filter. The differential baseband outputs can then be fed directly into analogue
to digital converters on a baseband processor.
9
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Figure 4 - IS136 Receiver Signal Flow
10
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
1.1.2 AMPS FM
FM demodulation can be performed using the I and Q baseband signals if supported by the baseband. However the
ZL20250 also contains an FM demodulator, the AMPS receive signal path using this mode is shown in detail in
Figure 5 and performance for each stage is summarized in the following table.
Filter
Circuit
Block
Gain
(dB)
Bandwidth
Description
(If Applicable)
IF Input (IF0)
Differential IF input stage
26
max
AGC Amplifier
AGC Amplifier - Gain control range 90dB. Includes IF input stage
gain.
Quadrature
Down-conversion to 60kHz IF
Down-converter
Anti-alias filter
230 kHz
Low pass Butterworth
73
Band Pass Filter
+/- 16 kHz
Switched capacitor polyphase Chebyshev. Also provides typically
30dB image rejection. Centre frequency = 60 kHz. Clock frequency
1.44 MHz and 720 kHz.
Limiter
Provides limited output to discriminator. Also provides RSSI output.
Digital FM discriminator
FM Discriminator
Baseband filter 2 (I
Channel)
30 kHz
25 kHz
Smoothing filter. Low pass Butterworth. Provides filtering of FM
discriminator output.
Baseband filter 1
(I Channel)
Switched capacitor low pass Chebyshev. Clock frequency = 240
kHz. Provides additional filtering of discriminator output. Selected
using PDF and LPC bits
Baseband filter 1
(Q Channel)
25 kHz
Switched capacitor low pass Chebyshev. Clock frequency = 240
kHz. Provides additional filtering of discriminator output. Selected
using PDF and LPC bits
Baseband filter 2 (Q
Channel)
60kHz
30kHz
Smoothing filter. Low pass Butterworth. Provides filtering of FM
discriminator output.
FM Output
Configured using external components as bandpass filter.
Table 2 - AMPS FM Receive Gain and Filter Distribution
The signal path is initially the same as for IS136 with the down conversion to 60 kHz and channel filtering in the
bandpass filter. In FM mode however, the baseband I and Q output stages are disabled, and the 60 kHz IF signal
from the bandpass filter is input to a limiting amplifier and FM discriminator. The FM discriminator consists of a shift
register acting as a delay line. The output of the discriminator is a digital signal which must then be filtered to recover
the audio signal. The discriminator output is therefore routed through the baseband I and Q filters. The default
condition is to use the cascaded I and Q smoothing filters (baseband filter 2) with the cut-off frequency set to 30kHz.
This connection is automatically selected when programming FM mode. There is an option to use the cascaded
switched capacitor filters (baseband filter 1) with the cut off frequency set to 25 kHz to provide extra filtering. These
filters are selected using the PDF and LPC bits in control register 6 and are inserted between the smoothing filters
as shown in Figure 5. The final output stage uses external feedback components to provide a bandpass filter with a
bandwidth of at least 300 Hz to 10 KHz to cover the demodulated audio and control signals. The feedback
components can be modified to change the output level to optimise compatibility with baseband.
A RSSI output is provided. This is a full wave rectified output of the 60 kHz IF and therefore has a high 120 kHz
content. This requires an external low pass filter - typically 10kohm and 2.7nF. There is a trade-off between settling
11
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
time and filtering. This is different to conventional RSSI circuits which operate at typically 450 kHz which is much
easier to filter.
Although the AMPS receive path includes a limiting amplifier, gain control is also required. This is because the band
pass filter has limited dynamic range (50dB). At low signal levels the agc should be set to 1.6 volts to set the gain
20dB below maximum to obtain optimum signal handling and noise performance. At higher signal levels the gain
setting should be reduced to maintain the RSSI level approximately 10dB below maximum. Gain control would be
provided by the baseband controller which would also monitor the RSSI level. Fine gain control is not required and
can be implemented in large steps eg 20dB, allowing the use of a relatively slow gain control loop giving optimum
performance under fading conditions.
12
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Figure 5 - AMPS Receive Signal Flow
13
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
1.1.3 GSM
The GSM receive signal path is shown in detail in Figure 6 and performance for each stage is summarized in the
following table.
Filter
Circuit
Block
Gain
(dB)
Bandwidth
Description
(If Applicable)
IF Input (IF0)
AGC Amplifier
Differential IF input stage
26
max
AGC Amplifier - Gain control range 90dB. Includes IF input
stage gain.
Quadrature
Down-conversion to baseband
Down-converter
54
Anti-alias filter
230 kHz
Low pass Butterworth. Provides channel filtering in
GSM/EDGE mode
Baseband Gain
Baseband gain with offset correction.
Nominal gain is 35 dB and can be reduced in 3 dB steps to
14 dB
Table 3 - GSM Receive Gain and Filter Distribution
In GSM mode the bandpass filter and IS136 baseband stages are disabled. After passing through the agc amplifier
the signal is mixed down to baseband I and Q signals rather than to a low IF. The baseband signal must be dc
coupled and this can introduce a dc offset in the output, which may vary with different gain settings. The ZL20250
therefore includes the facility to correct the dc offset for each channel using an 8 bit offset correction word that must
be supplied by the baseband via the serial bus.
GSM Baseband gain can be programmed via serial bus. Reducing the baseband gain can be used to improve output
signal to noise ratio. The IF gain should be increased to mainatin the total overall gain. In practice a gain reduction
of 6 or 9 dB would give optimum performance
14
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Figure 6 - GSM Receive Signal Flow
15
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
1.2 Transmit
Transmit operation is similar for all modes and a detailed diagram is shown in Figure 7. This diagram also shows the
UHF LO generation circuit blocks. A summary of the characteristics of the transmit path circuit blocks are given in
the table below. All circuit blocks are differential with the exception of the transmit RF outputs.
Circuit
Block
Gain
(dB)
Bandwidth
(If Applicable)
Description
Reconstruction Filters 0 -12
IS136/AMPS
12.5 kHz
GSM
Baseband input stage. Gain is programmable in 3 dB steps from 0 to 12
dB.
Filter bandwidth is selected for IS136/AMPS or GSM.
There is also a by-pass mode so that the baseband I and Q signal can go
direct to the modulator
100 kHz
Quadrature Modulator
Transmit IF
Generates a modulated IF signal
400 MHz
Provides gain control at IF frequency. This stage also includes a low
pass filter to remove harmonics and spurii from modulator output.
This stage also includes a buffered IF output which can be used with an
external IF filter.
Up-converter
Transmit RF
SSB up-converter to RF frequency. The IF path includes phase shift
networks for the up-converter. This stage also includes the input circuit
from the optional external IF filter
The 900 MHz and 1900 MHz RF stages each consist of 2 stages. The
first stage gain be set from -6 to +3 dB in 3 dB steps. Output stage
current is controlled by agc signal to reduce current consumption at low
output power levels. Each output stage requires an external
degeneration inductor
Table 4 - Transmit Circuit blocks
Differential baseband transmit I and Q signals from a baseband processor are input to the ZL20250. The baseband
signals are passed through filters - the filter bandwidth is selected for the appropriate mode i.e. IS136 or GSM. A
quadrature modulator modulates these baseband signals on to the transmit IF which is typically around 200 MHz.
This modulated IF signal is passed through an on chip low pass filter which removes harmonics of the IF and then
into a gain controlled amplifier. This amplifier is controlled by an external analogue signal and provides greater than
60dB gain control The output of the gain controlled amplifier can then be up-converted to RF or alternatively the
output can be sent to an off chip filter to provide further filtering and removal of noise before up-conversion. This filter
is a parallel tuned circuit as shown in Figure 8. The choice of component values is dependent on the IF frequency
being used. The filter output is then fed back on chip to the up-converter. A SSB mixer is used for the up-conversion
to remove the unwanted image. High side or low side LO injection can be selected
A buffer amplifier after the up-conversion provides a further 9 dB gain control in 3 dB increments. This gain is
programmable via the serial bus and can be used to optimize noise and linearity performance in particular
applications. Finally there are two RF output stages for 900 MHz and 1900 MHz frequency bands. Each RF output
is single ended and requires a simple matching network. The supply current of the output stages is automatically
reduced at low transmit gain control voltages improving the efficiency of the output buffer at low output power levels.
The supply current of the output buffer can also be controlled via the serial bus. This allows the supply current to be
reduced which is particularly useful when using AMPS or GSM where the linearity performance is less critical.
The FM modulation for AMPS can be done using I,Q modulation if available. Alternatively FM modulation can be
applied direct to the transmit IF VCO. The loop bandwidth for the transmit VHF PLL should be low ( ~100 Hz) to
ensure the PLL does not remove the modulation. A dc voltage should be applied across the Tx I+, Tx I- and the Tx
Q+, Tx Q- inputs to switch the modulator and generate an IF carrier signal. With a baseband gain of 0dB a dc voltage
of at least 1.5 volts should be applied; a lower voltage can be used with the baseband gain increased to compensate.
It is assumed that this bias can be provided by the baseband however if this is not possible then the simplest solution
is to connect 200kohm resistors between I+, Q+ inputs and Vcc and 200kohm resistors between I+,Q- inputs and
16
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
ground assuming the transmit outputs from the baseband are in a high impedance state in AMPS mode. These
resistors do produce a small dc offset in TDMA mode however this is insignificant if the output impedance of
baseband transmit outputs is less than 1 kohm.As the FM modulation is applied direct to the VCO in this mode and
is external to the ZL20250, any necessary filtering of the FM signal must be provided externally.
17
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Figure 7 - Transmit Path
18
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Figure 8 - External Transmit IF Filter
1.3 UHF LO and Frequency Doubler
Figure 8 also shows the UHF LO buffering and frequency doubler. The ZL20250 is designed to operate either with
separate external UHF VCOs for the 900 and 1900 MHz frequency bands, or alternatively a single 900 MHz VCO
can be used with the on-chip frequency doubler providing the LO for the 1900 MHz band. A UHF synthesizer is
included. The input to the UHF synthesizer will normally be the active UHF LO signal, however when using the
frequency doubler mode for 1900 MHz LO generation, the synthesizer input can be selected to be either the
frequency doubler output or the 900 MHz input LO signal. The UHF LO input buffer minimizes any load pulling effects
on the UHF VCO when internal modes are switched.
UHF LO output buffers are also provided. These can be used to drive an external mixer for the receive section. If not
required these buffers can be powered down.
1.4 UHF Frequency Synthesizer
A fractional N UHF synthesizer is included on the ZL20250 to provide LO signals for the transmit up-converter and
the external receive RF down-converters. The UHF synthesizer operates with an external VCO. A block diagram of
the synthesizer is shown in Figure 9.
.
Lock Detect
TCXO
Reference Counter
14 bit
UHF
CP
Phase
Detector
Charge
Pump
Quad Modulus
Prescaler
64/65/72/73
UHF LO
M Counter
13 bit
+1
+8
B
3 bit
Fractional N
Counter
A
4 bit
+1
5 bits
Frac N
Compensation
Fractional N
Scaling DAC
Fractional N
Compensation DAC
8 bits
Figure 9 - UHF Synthesizer
19
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
The synthesizer uses a 4 modulus prescaler with an 'M' counter and 'A' and 'B' swallow counters together with a
fractional N counter in the UHF counter allowing maximum flexibility. The reference counter is a simple 14 bit
counter. All counter values are programmed via the serial bus and programming details are shown in the
programming section. Each of the counters operates as count down. At the start of a count the counters are loaded
with their respective values. The initial prescaler ratio is dependent on the values loaded into the A and B counters;
when both the A and B counters reach zero the prescaler ratio is 64 and then remains until the M counter reaches
zero. The complete process is then repeated.
This can be shown in a simple example where M = 9, A = 4 and B = 2 which gives a total divide ratio of 596. The
count sequence is shown in Figure 10.
9
4
8
3
7
2
6
1
5
0
4
0
3
0
2
0
1
0
9
4
8
3
M Counter
A Counter
+1 Prescaler
2
1
0
0
0
0
0
0
0
2
1
B Counter
+8 Prescaler
Prescaler
73 73 65 65 64 64 64 64 64 73 73
Figure 10 - Count Sequence for UHF PLL with 4 modulus prescaler
At the start of the count sequence the '+1' and '+8' controls to the prescaler are both asserted and the prescaler ratio
is 73. After 2 cycles only the '+1' control is asserted and the divide ratio is 65. After a further 2 cycles the A counter
reaches zero as well and the prescaler ratio is 64 for the remainder of the count sequence. At the end of the
sequence all counters are reloaded and the sequence repeats.
The total divide ratio (N) for this type of counter is given by
N = 64*M + 8*B + A
M is always greater then A or B
A value of A = 0 does not support fractional N operation. Valid values of A are 1 to 8.
The values of M, B and A can be easily calculated from the total divide ratio as shown below.
M = INT ((N - 1)/64)
B = INT (((N - 1) - 64*M)/8)
A = N - 64*M - 8*B
The value of M must always be greater than A or B. The maximum value of B is 7.
20
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
The UHF synthesizer also includes a fractional N capability which allows the use of higher comparison frequencies
but maintain narrow channel spacing. The use of higher comparison frequencies allows faster loop settling and
reduces comparison spur level. This is particularly important in TDMA mode where settling times of < 1.5 ms are
required and still obtain good spur performance.
Fractional N allows the use of non-integer divide ratios. For example if the total divide ratio is N + 1/5 the counter will
divide by N for 4 count cycles and N+1 on the fifth cycle giving the required total divide ratio over five cycles. The
ZL20250 can use 5,8,13 or 20 as the fractional denominator (also referred to as the fractional modulus) allowing
maximum flexibility in the choice of comparison frequencies.
An extra counter - fractional N counter - is required. The input to this counter is from the M counter output. The
fractional N modulus can be programmed to be 5,8,13, or 20. Each output pulse from the M counter will increment
the fractional N divided by the required fractional numerator. For example if the fraction is 2/5 then the fractional N
counter will increment by 2 for each output pulse from the M counter. When the fractional N counter overflows the A
counter is incremented by 1, thus generating an additional '+1' count sequence.
An example is shown in Figure 11 for a divide ratio of 596+2/5. The values for M, A, B are calculated using the integer
value (596) as in the previous example. The fractional denominator is programmed as 5 and the fractional numerator
as 2. At the end of the first count cycle (596) the fractional counter is incremented to 2. At the end of the third count
cycle the fractional N counter overflows, incrementing the A counter by 1 which gives a subsequent count cycle of
597. After five count cycles the sequence repeats with a total count of 2982 over the five count cycle giving a mean
value of 596 + 2/5.
Total Count Cycle
Count Value
596
2
596
4
597
1
596
3
597
0
596
2
Fractional N
Counter
0
Initial A
Counter
Value
4
4
5
4
5
4
Figure 11 - UHF Synthesizer - Fractional N Operation
A result of this count sequence is that the output phase of the total counter changes through the count cycle, which
causes the output pulse from the phase detector, and therefore the charge pump, to vary. This would cause large
fractional spurs on the synthesizer output. These spurs can be compensated by applying a current pulse with the
opposite polarity to the charge pump output. This compensation pulse has a fixed width of two reference clock
(TCXO) periods; the amplitude is proportional to the value in the fractional N counter. The correction current is scaled
by a 8 bit compensation DAC, with an externally provided input from the serial bus. This allows performance to be
optimized in a given application.
21
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
The compensation value can be calculated from the following formula:
Comp Value = 255 - INT((Icp * Ftcxo)/(0.0245 * 6 * MOD *Fvco))
where
Icp
= charge pump current (uA)
Ftcxo = Reference frequency
MOD = Fractional Modulus
Fvco = UHF VCO Frequency
The synthesizer provides a lock detect output. When the output pulse from the phase detector is less than half a
reference clock period an in-lock signal is generated. These in-lock signals then clock a 4 bit counter into which a
threshold value has been programmed. When the required number of successive in-lock pulses have been
generated the lock detect output is set.
The ZL20250 has a single lock detect output pin for the UHF synthesizer and VHF synthesizers. The lock detect
signal is asserted when all active synthesizers are in lock. If a synthesizer has not been enabled in the power control
registers then that synthesizer will be inactive and will have no effect on the lock detect output.
1.5 VHF Frequency Synthesizer
The ZL20250 includes two VHF synthesizers to generate the second LO for the receiver and the transmit IF. They
operate with their respective on-chip VHF VCO's and off-chip loop filters. The tank circuits and tuning components
for the VCO's are also off chip. The two synthesizers are identical and are shown in Figure 12.
Lock Detect
TCXO
Reference Counter
14 bit
VHF
CP
Phase
Detector
Charge
Pump
Dual Modulus
Prescaler
16/17
VHF LO
M Counter
13 bit
+1
A
4 bit
Figure 12 - VHF Frequency Synthesizer
The synthesizer uses a 2 modulus 16/17 prescaler with an 'M' counter and an 'A' swallow counter. This allows
maximum flexibility when using this synthesizer. The reference counter is a simple 14 bit counter. All counter values
are programmed via the serial bus and programming details are shown in the programming section. Both counters
operate as count down. At the start of a count the counters are loaded with their respective values. The initial
22
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
prescaler ratio is 17 assuming A > 0; when the A counter reaches zero the prescaler ratio is 16 until the M counter
reaches zero. The complete process is then repeated.
The total divide ratio (N) for this type of counter is given by
N = 16*M + A
M is always greater then A
The values of M and A can be easily calculated from the total divide ratio N.
M = INT (N/16)
A = N - 16*M
The maximum value for A is 15 and M must always be greater than A.
The VHF PLLs do not have fractional N capability however it is recommended that thay are operated at as high a
comparison frequency as allowed by the chosen frequency plan to minimise spurs levels.
Both VHF synthesizers have lock detection circuits. These operate in the same way as described for the UHF
synthesizer.
1.6 Internal Clock Generation
ZL20250 can use 14.4 MHz or 19.44MHz reference frequency (standard for IS136), or 13 MHz or 26 MHz (standard
for GSM). The appropriate reference must be programmed via the serial bus. The clock signals for the switched
capacitor filters and FM demodulator are generated from the reference TCXO signal. The internal divide ratios are
switched to give the optimum ratio. For dual mode applications (GSM/IS136) a 13 MHz or 26 MHz reference should
be used. This will give a small error in the switched capactor clock frequency used for IS136 but has negligible effect
on performance.
1.7 VHF VCO
ZL20200 has two VHF VCOs which operate with the VHF PLLs to provide the IF LO signals for both receive and
transmit IF signals. The oscillators are a differential design and require an external tank circuit. A basic circuit with
varactor is shown in Figure 13. It is recommended to include series resistors (eg 43 ohms) in each arm of the tank
circuit to prevent any spurious high frequency oscillation due to parasitic capacitances.
From PLL
Loop
Filter
10k
VCO+
43R
18p
nm
VCO-
43R
18p
10k
33n
Figure 13 - Typical VCO Tank Circuit
23
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
1.8 Power Supply Connections
The circuit blocks within ZL20250 have separate supply connections to minimize interaction between circuit blocks.
Details are shown in the earlier ‘Pin Names’ section. These supplies are also grouped to allow different groups of
supply pins to be connected to separate supplies for example, receive or transmit. These groups are shown below:
VCC – Control Supply
Pin No.
Pin Name
56
VCC CONTROL
VCC – TxRx Common (Synth)
Pin No.
Pin Name
5
VCC UHF PLL
VCC UHF LO OUT
VCC UHF LO
VCC VHF CP
900 LO OUT
1900 LO OUT
7
13
38
8
9
VCC – Rx
Pin No.
Pin Name
VCC RX PLL
VCC RX
49
50
VCC – Tx
Pin No.
15
Pin Name
VCC TX RF
VCC TX
24
31
VCC TX PLL
TX 900
16
19
TX 1900
The LO OUT and TX 900/1900 pins require bias and are normally connected to VCC through an inductor.
All supply pins within a group must be powered together. Each group of pins can be powered up independent of the
other groups.
24
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
2.0 Programming and Control
Programming via the serial bus is via 24 bit words with a 4 bit address as shown below
23
22
21
20
19
18
17
17
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Data
Address
Bit23 (MSB) is loaded first. Bits 3:0 are used as address bits for the control registers. Details of serial bus timing are
shown in Figure 14.
t1
t2
t3
SCLK
SDAT
t6
Bit 23
Bit 22
Bit 21
Bit 0
t4
t5
SLATCH
t7
ENABLE1/2
Figure 14 - Serial Bus Timing
2.1 Power Control Registers - Address 0 to 3
These registers are used in conjunction with the TX RXB and ENABLE1 and ENABLE2 control pins to power up the
required sections of the device for any required mode. This enables power consumption to be optimized under all
conditions. Figures 4 - 7, which show the receive and transmit paths in detail, show which sections are powered up
by each control bit.
The assignment is common for each of the registers 0 to 3 and is shown below.
Bit
23
Circuit Section
Not used
22
21
20
Receive Baseband section
UHF LO Buffer
Receive VHF VCO
25
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Bit
19
Circuit Section
UHF synthesizer
18
17
16
15
14
13
12
11
10
9
Receive RSSI circuit
Not used
Receive Quadrature down-converter
Receive VHF PLL
Receive IF input
Receive AGC amplifier
Transmit reconstruction filters
Transmit RF
Transmit UHF LO
UHF LO input buffer
Transmit IF
8
7
Transmit quadrature modulator
Transmit VHF PLL
6
5
Transmit VHF VCO
Transmit up-converter IF input
4
Note 1: If a bit is set to logic 1 then that circuit section is powered on.
Note 2: UHF LO input (bit 9) must be enabled for Transmit UHF LO (bit 10), UHF synthesizer (bit 19) and UHF LO Buffer (bit 21) to be
active.
The 4 registers address 0 to 3 are assigned as follows:
Register
Address
Register
Name
Description
0
Receive
All circuit blocks required in receive mode should be set to 1. This register will be
selected when TX RXB is low. No circuits will be actually powered up if ENABLE1
and ENABLE 2 are both low.
1
Transmit
Transmit register All circuit blocks required in transmit mode should be set to 1. In
duplex modes e.g. AMPS then both receive and transmit circuits must be selected.
This register will be selected when TX RXB is high. No circuits will be actually
powered up if ENABLE1 and ENABLE 2 are both low
2
3
ENABLE1
This register determines which circuit sections are powered up when ENABLE1 is
Configuration high. The contents of this register are logical ANDed with the contents of the
Receive or Transmit register as selected by TX RXB input.
ENABLE2
This register determines which circuit sections are powered up when ENABLE2 is
Configuration high. The contents of this register are logical ANDed with the contents of the
Receive or Transmit register as selected by TX RXB input.
26
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
A feature of this programming approach is that once a phone operating mode has been selected and set up via the
serial bus, all power control can then be via the TX RXB, ENABLE1 and ENABLE2 control pins. Alternatively full
power control is possible via the 3 wire serial bus without the use of any external control pins.
If ENABLE1 and ENABLE2 are both low then the device is in Sleep mode. No circuits will be enabled unless either
ENABLE1 or ENABLE2 are high regardless of the contents of the receive and transmit registers.
An example of how these control bits can be used, is that the oscillators and PLL circuits can be powered up and
allowed to settle prior to powering up the complete transmit or receive path. In the case of the receive path the UHF
synthesizer, UHF LO input buffer, UHF LO Buffer and Receive VHF VCO, Receive VHF PLL bits would be set in the
ENABLE1 Configuration register. The ENABLE2 Configuration register would contain these bits plus the remainder
of the receive path bits, Receive IF input, Receive AGC amplifier, Receive quadrature down-converter and receive
baseband section.
This is demonstrated in the following examples.
2.1.1 Power Control Modes - TDMA (GSM and IS136)
In a TDMA system the transceiver will either operate in receive only, or transmit only mode. It is assumed that an
interim power on state will be used during which the oscillators and PLLs will be set up, and allowed to settle prior
to activating the full signal path. The suggested programming for the power control registers (0 - 3) is shown in the
table below.
Enable 1
Config.
Addr 2
Enable 2
Config.
Addr 3
Circuit
Section
Receive
Addr 0
Transmit
Addr 1
Bit
Comments
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Not used
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
1
0
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
Receive Baseband section
UHF LO Buffer
Note 1
Note 2
Receive VHF VCO
UHF synthesizer
Receive RSSI circuit
Not used
Receive Quadrature down-converter
Receive VHF PLL
Receive IF input
Receive AGC amplifier
Transmit reconstruction filters
Transmit RF
Transmit UHF LO
UHF LO input buffer
Transmit IF
8
7
Transmit quadrature modulator
Transmit VHF PLL
6
27
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Enable 1
Config.
Addr 2
Enable 2
Config.
Addr 3
Circuit
Section
Receive
Addr 0
Transmit
Addr 1
Bit
Comments
5
4
Transmit VHF VCO
Transmit up-converter IF input
0
0
1
1
1
0
1
1
Note 1: Not required if driving external receive mixer direct from UHF VCO.
Note 2: Can be used for IS136 if required.
The receive register contains all bits required when in receive mode: the transmit register contains all bits required
in transmit mode. The Enable1 configuration register contains all bits required to power up oscillators and
synthesizers in both receive and transmit mode. The Enable2 configuration register contains all bits required to
power up the complete receive and transmit modes (this register can be set to all '1's if preferred).
The following words should therefore be programmed on the serial bus (Hex format):
Receive register (0)
Transmit register (1)
Enable1 Config. register (2)
Enable2 Config. register (3)
59E200
081FF1
188262
59FFF3
2.1.2 Power Control Modes - AMPS
When operating in AMPS mode the ZL20250 will operate in either Receive only or Duplex. The enable registers
should therefore be programmed as shown below.
Enable 1
Config.
Addr 2
Enable 2
Config.
Addr 3
Receive
Addr 0
Transmit
Addr 1
Bit
Circuit Section
Comments
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Not used
0
1
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
Receive Baseband section
UHF LO Buffer
Note 1
Receive VHF VCO
UHF synthesizer
Receive RSSI circuit
Not used
Receive Quadrature down-converter
Receive VHF PLL
Receive IF input
Receive AGC amplifier
Transmit reconstruction filters
Transmit RF
Transmit UHF LO
UHF LO input buffer
Transmit IF
8
28
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Enable 1
Config.
Addr 2
Enable 2
Config.
Addr 3
Receive
Addr 0
Transmit
Addr 1
Bit
Circuit Section
Comments
7
6
5
4
Transmit quadrature modulator
Transmit VHF PLL
0
0
0
0
1
1
1
1
0
1
1
0
1
1
1
1
Transmit VHF VCO
Transmit up-converter IF input
Note 1: Not required if driving external receive mixer direct from UHF VCO.
The receive register contains all bits required when in receive mode: the transmit register contains all bits required
in duplex mode. The Enable1 configuration register contains all bits required to power up oscillators and synthesizers
in both receive and duplex mode. The Enable2 configuration register contains all bits required to power up the
complete receive and duplex modes (this register can be set to all '1's if preferred).
The following words should therefore be programmed on the serial bus (Hex format):
Receive register (0)
Transmit register (1)
Enable1 Config. register (2)
Enable2 Config. register (3)
5DE200
5DFFF1
188262
5DFFF3
2.2 Operating Register Address 4
This registers selects internal setups for example IS136 or GSM. The bits are assigned for control of receive and
transmit bits as shown below:
23
22
21
20
19
18
17
16
15
14
13
12
11
TX <11:0>
Transmit Set Up
10
9
8
7
6
5
4
3
0
2
1
1
0
0
0
RX<7:0>
Receive Set Up
Address
The function of the receive bits is shown below:
Register
Bit No.
Control
Bit
Action if '0'
Action if '1'
Receive DLL enabled
23
22
21
20
19
18
17
16
RX<7>
RX<6>
RX<5>
RX<4>
RX<3>
RX<2>
RX<1>
RX<0>
Receive DLL disabled
Bandpass Filter BW = +/- 20 kHz
GSM Filters active
Bandpass Filter BW = +/- 16 kHz
Receive GSM filters bypassed
LO Output = 1900 MHz
Receive output dc bias (I/Q) = Vcc/2
GSM Mode IF0 Input enabled
IS136
LO output = 900 MHz
Receive output dc bias (I/Q) = 1.25 V
IS136 Mode IF1 Input enabled
AMPS
Not used
Not used
Bit 23 RX<7> is only applicable when VCO divide by 2 mode is selected in register 5.
29
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
The function of the transmit bits is shown below:
Register Bit
No.
Control
Bit
Action if '0'
Transmit output stage gain control
Action if '1'
15
14
13
TX<11>
TX<10>
TX<9>
Control of RF Transmit output stage current with VGA control voltage.
Nominal value for TX<11:4> is 101010
12
11
10
9
TX<8>
TX<7>
TX<6>
TX<5>
TX<4>
TX<3>
TX<2>
TX<1>
TX<0>
8
7
900 MHz output
1900MHz output
6
Internal
External transmit IF Filter
GSM/EDGE baseband filters
Transmit baseband filters by-passed
5
IS136 baseband filters
Transmit baseband filters selected
4
Control bits TX<11:4> allow optimization of the transmit output stage. This allows variation of the decrease in supply
current with decreasing agc voltage and also allows optimization depending on output power and linearity
requirements. Figure 15 shows the variation of output stage supply current with agc voltage and the programmable
characteristics. The maximum current, agc threshold and slope can be programmed. The minimum current is not
programmable.
TX<11:10> (bits 15,14) allow the gain of the transmit output stage to be varied in 3 dB steps as shown in the table
below:
TX<11>
TX<10>
Gain (dB)
0
0
1
1
0
1
0
1
-6
-3
Nominal
+3
30
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Imax
Icc
Slope
Imin
Vagc
Vth
Figure 15 - Transmit Output Stage Current versus Gain Control
TX<9:8> (bits 13:12) control the agc voltage (Vth) at which the output stage current starts reducing. Typical values
are shown in the table below:
TX<9>
TX<8>
Vth (V)
0
0
1
1
0
1
0
1
1.09
1.25
1.48
2.81
TX<7:6> (bits 11,10) control the rate of current reduction as shown in Figure 15. Typical vales are shown in the
below:
TX<7>
TX<6>
Slope (mA/V)
0
0
1
1
0
1
0
1
8.5
10.5
12.0
14.0
31
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
TX<5:4> (bits 9:8) adjust the maximum current (Imax) of the transmit output stage. The gain of the output stage is
not changed. Typical values are shown in the table below:
TX<5>
TX<4>
Current
0
0
1
1
0
1
0
1
25%
50%
Nominal
150%
Using these controls allows the performance of the output stage to be optimized under various conditions; for
example, current cant can be reduced if non-linear operation is required.
The nominal value recommended for TX<11:4> is 10101010.
An example of setting up the control register (address 4) for various systems is shown below:
GSM
(850)
GSM
(1900)
IS136
(900)
IS136
(1900)
Bit
Name
AMPS
Comments
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
RX<7>
RX<6>
RX<5>
RX<4>
RX<3>
RX<2>
RX<1>
RX<0>
TX<11>
TX<10>
TX<9>
TX<8>
TX<7>
TX<6>
TX<5>
TX<4>
TX<3>
TX<2>
0
0
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
1
1
1
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
0
1
0
0
0
0
0
1
1
0
1
0
1
0
1
0
0
0
Note 1
8
7
6
Note 2
32
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
GSM
(850)
GSM
(1900)
IS136
(900)
IS136
(1900)
Bit
Name
AMPS
Comments
5
4
TX<1>
TX<0>
1
0
1
0
0
0
0
0
0
0
Note 1: The setting for RX<3> is dependent on the optimum common mode input voltage of the analog to digital converter in the
baseband.
Note 2: Selects external transmit IF filter if used.
The following hex words are therefore recommended for the control register (address 4):
GSM (850)
GSM (1900)
IS136 (900)
IS136 (1900)
AMPS
04AA24
4AAE4
03AA04
13AAC4
41AA04
2.3 Synthesizer Register - Address 5
This register sets up LO options for receive and transmit and also UHF synthesizer set up.
23 22 21 20 19 18
17
16 15
14
13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
1
UI
RX LO2 Set Up
UC
DL UD
TX LO Set Up
UHF PLL Set Up
Address
Bits 23,17,14 are also used for UHF PLL and LO set up.
Bits 16,15 are not used and should be set to zero.
2.3.1 UHF PLL and LO
Register
Action if '0'
Bit No.
Action if '1'
23
17
14
8
UHF PLL input = 900 MHz
UHF PLL input = 1900 MHz
Fractional N Compensation selected
UHF Doubler Selected
Fractional N Denominator - see table below
7
6
Not Used - Set to 0
5
UHF PLL Charge Pump Current - see table below
4
Note 1: Bit 14 is only effective if 1900 MHz mode has been selected (register 4 Bit 7).
Note 2: Bit 23 is only effective if 1900 MHz mode has been selected (register 4 Bit 7) and the UHF frequency doubler selected
(Register 5 Bit 14). This control allows the use of the doubled frequency to be used as the input to the UHF PLL.
Note 3: Fractional N Denominator
Note 4: Bits 8,7 select the fractional N denominator for the UHF PLL as shown below:
33
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
<8>
<7>
Frac N Denom.
0
0
1
1
0
1
0
1
5
8
13
20
2.3.2 UHF PLL Charge Pump Current
Bits 5,4 select the charge pump current for the UHF PLL as shown below:
<5>
<4>
Current (mA)
0
0
1
1
0
1
0
1
1.00
0.50
0.25
0.125
2.3.3 Receive LO Set Up
Register Bit No.
Action if '0'
Action if '1'
22
21
20
19
18
High side Rx second LO injection
Rx second LO = VCO/2
Low side Rx second LO injection
Rx second LO = VCO/4
Rx LO phase detector polarity normal
Rx LO phase detector polarity inverted
Receive VHF PLL Charge Pump Current - see table below
Bits 19,18 select the charge pump current for the receive VHF PLL as shown below:
<19>
<18>
Current (mA)
0
0
1
1
0
1
0
1
1.00
0.50
0.25
0.125
34
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
2.3.4 Transmit LO Set Up
Register
Bit No.
Action if '0'
Transmit DLL disabled
Action if '1'
Transmit DLL enabled
15
13
12
11
10
9
Low side Tx up-converter LO injection
Tx second LO = VCO/2
High side Tx up-converter LO injection
Tx second LO = VCO/4
Tx LO phase detector polarity normal
Tx LO phase detector polarity inverted
Transmit VHF PLL Charge Pump Current - see table below
Bits 10,9 select the charge pump current for the receive VHF PLL as shown below:
<10>
<9>
Current (mA)
0
0
1
1
0
1
0
1
1.00
0.50
0.25
0.125
2.4 Control Register - Address 6
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
0
2
1
1
1
0
0
0
0
BBG
TCXO
PDF
LPC
Tx Gain
R
Mode Control
Address
2.4.1 IS136 Baseband Gain
Bits 22:21 can be used to vary the gain of the baseband output stages in IS136 mode only. The gain of the 60 kHz
IF stage preceding the baseband mixer is also varied so that the overall gain of the device can be maintained if
required. The nominal gain is 20 dB and the recommended setting is BBG<1:0> = 11 to minimize output dc offsets.
BBG<1>
Bit 22
BBG<0>
Bit 21
IF Gain
(dB)
Baseband Gain
(dB)
Overall Gain
(dB)
0
0
1
1
0
1
0
1
14
17
17
20
6
6
0
0
20
23
17
20
35
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
2.4.2 TCXO Reference Selection
Bits 20:19 are used to set the device to the required TCXO reference frequency.
TCXO<1>
Bit 20
TCXO<0>
Bit 19
TCXO Frequency
(MHz)
0
0
1
1
0
1
0
1
13.0
14.4
19.44
26.0
2.4.3 Discriminator Output Filtering
Bits 17:14 set up on chip filtering of the FM output signal and are therefore only used in AMPS mode. Two cascaded
filters can be selected and the bandwidth can be set to 25 or 37.5 kHz cut-off. Bits 17,16 (PDF) select the filters and
bits 15,14 set the cutoff frequency.
<17> <16> <15>
<14>
Filter Selection
0
0
0
1
X
X
X
X
0
0
1
1
X
X
X
X
0
1
0
1
No filters
Filter 1 selected
Filter 2 selected
1
0
1
1
Filters 1 and 2 selected
Both filters 37.5 kHz
X
X
X
X
X
X
X
X
Filter 1 25kHz, Filter 2 37.5kHz
Filter 1 37.5 kHz, Filter 2 25 kHz
Both filters 25kHz
In GSM and IS136 modes Bits <17:14> should be set to 0000. It is recommended that if the additional discriminator
filtering is required in AMPS mode then both filters should be used with 25 kHz bandwidth, i.e. Bits<17:14> should
be set 1111.
36
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
2.4.4 Transmit baseband Gain
Bits 13:11 set the transmit baseband gain as shown below:
<13>
<12>
<11>
Gain (dB)
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
3
6
9
12
2.4.5 Mode Control
Bit 10 resets the contents of all registers to '0'. After the reset is complete bit 10 is also reset to '0'.
Bits 9:4 allow TXRXB, ENABLE1 and ENABLE2 to be programmed by either the external pins or via the serial bus.
This allows mode control to be either via the external pins or the serial bus. The default state is using the external
pins as this allows more accurate timing of power control.
Register Bit No.
Action if '0'
Action if '1'
9
8
7
6
5
4
Receive Register (0) selected
Transmit Register (1) selected
Enable2 Configuration Register (3) selected
Enable1 Configuration Register (2) selected
Serial Bus selected - Bit 9
TXRXB Pin (34) selected
Enable2 Pin (20) selected
Enable1 Pin (11) selected
Serial Bus selected - Bit 8
Serial Bus selected - Bit 7
Bits 9:7 can only be used if the appropriate bits 6:4 have been set to disable the external pins. If serial mode has
been selected then the operation of bits 9:7 is the same as the external TX RXB, ENABLE1 and ENABLE2 pins
respectively.
2.5 GSM/EDGE Baseband Control Register - Address 7
23
22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
0
2
1
1
1
0
1
OE
BB Gain
Q Offset
I Offset
Address
This register is only used when in GSM/EDGE mode. The BB Gain bits enable the GSM baseband gain section to
be reduced in 3 dB increments. The nominal gain is 35 dB (000). The I and Q offset bits allow the GAM baseband
dc offset to be cancelled.
37
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
2.5.1 Q Channel Gain Adjust
Bits 22:20 adjust Q channel gain.
<22>
<21>
<20>
Gain Adjustment(dB)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-3
-6
-9
-12
-15
-18
-21
2.5.2 Baseband Offset Correction
Bits 19:12 adjust the dc offset for the Q channel. Bit 19 is the sign bit and bit 12 the LSB. Bits 11:4 adjust the dc offset
for the I channel with bit 11 the sign bit and bit 4 the LSB. The coding is the same for both I and Q channels and is
shown below:
00000000
Maximum positive correction
00000001
01111110
01111111
11111111
11111110
Zero positive correction
Zero negative correction
10000001
10000000
Maximum negative correction
Bit 23 must be set to '1' to enable dc offset correction.
2.6 Test Mode Register - Address 8
This register is used for test purposes only and should not be used.
38
Zarlink Semiconductor Inc.
ZL20250
2.7 UHF PLL Divider Programming Register - Address 9
23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data Sheet
9
8
7
0
x
6
5
4
3
1
2
0
1
0
0
1
M Counter
Value
B Counter
Value
A Counter
Value
Address
Bits 23:11 set M counter value (Bit 23 = MSB)
Bits 10:8 set B counter value - max value = 7 (Bit 10 = MSB)
Bits 7:4 set A counter value - max value = 7 (Bit 6 = MSB)
The A counter is a 4 bit counter to enable correct fractional N operation. Valid values of A are in the range 1 to 8.
Using the 64/65/72/73 four modulus prescaler the divide ratio (N) is given by:
N = 64 * M + 8 * B + A
Values of M, B, A can be easily calculated using the formulae in the synthesizer section.
2.8 UHF PLL Reference Divider and Fractional N Programming Register - Address 10
23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
9
8
7
6
5
4
3
1
2
0
1
1
0
0
X
Frac N Numerator
UHF PLL Reference Counter Value
Address
Bit 23 is unused and should be set to '0'
Bits 22:18 set the fractional N numerator (Bit 22 = MSB)
Bits 17:4 set the Reference counter value (Bit 17 = MSB)
2.9 Receive VHF PLL Divider Programming Register - Address 11
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
1
2
0
1
1
0
0
0
0
1
X
X
X
M Counter Value
A Counter Value
Address
Bits 23:21 are unused and should be set to '0'
Bits 20:8 set M counter value (Bit 20 = MSB)
Bits 7:4 set A counter value - max value = 15 (Bit 7 = MSB)
Using the 16/17 two modulus prescaler the divide value (N) is given by:
N = 16 * M + A
Values of M, A can be easily calculated using the formulae in the synthesizer section, however the programming
register has been organized to simplify this.
39
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
For example for a divide ratio of 13235, the binary equivalent is: 11001110110011. The programming values can be
selected as shown below:
Bit No.
20
0
19
0
18
0
17
1
16
1
15
0
14
0
13
1
12
1
11
1
10
0
9
1
8
1
7
0
6
0
5
1
4
1
Count Value
M
A
2.10 Receive VHF PLL Reference Divider Programming Register - Address 12
23 22 21 20 19
18
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
1
2
1
0
0
0
0
0
0
0
0
1
X
X
X
X
X
RS
Receive VHF PLL Reference Counter Value
Address
Bits 23:19 are unused and should be set to '0'
Bit 18 selects common reference divider for VHF receive and transmit PLLs ('0' to select). If a common reference
divider is selected then the transmit VHF reference divider is used which must be programmed in register 13.
Bits 17:4 set the Reference divider value (Bit 17 = MSB)
2.11 Transmit VHF PLL Divider Programming Register - Address 13
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
1
2
1
1
0
0
1
0
0
0
X
X
X
M Counter Value
A Counter Value
Address
Bits 23:21 are unused and should be set to '0'
Bits 20:8 set M counter value (Bit 20 = MSB)
Bits 7:4 set A counter value - max value = 15 (Bit 7 = MSB)
Programming is identical to that for the receive VHF PLL register 11.
2.12 Transmit VHF PLL Reference Divider Programming Register Address 14
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
1
2
1
1
0
0
0
0
0
0
0
1
0
X
X
X
X
X
X
Transmit VHF PLL Reference Counter Value
Address
Bits 23:18 are unused and should be set to '0'
Bits 17:4 set the Reference counter value (Bit 17 = MSB)
2.13 PLL Lock Detect & Fractional N Compensation Programming Register Address 15
23 22 21 20 19 18 17 16 15 14 13 12 11
10
9
8
7
6
5
4
3
1
2
1
1
0
1
1
Fractional N Compensation
UHF PLL
Lock Count
Transmit VHF PLL Receive VHF PLL
Lock Count Lock Count
Address
40
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
2.13.1 Fractional N Compensation
Bits 23:16 set the value for fractional N compensation in the UHF PLL with bit 23 as MSB. The value for the
compensation is dependent on a number of parameters which are described in the synthesizer section.
2.13.2 PLL Lock detect counters
These 4 bit counters count the consecutive comparison cycles where the lock detect circuit gives an in-lock result.
When the counter reaches its programmed count then that PLL is deemed to have achieved full lock. This prevents
spurious false in-lock signals while the PLL is achieving lock up. There are separate counters for the UHF, Rx VHF
and Tx VHF PLLs which are programmed as shown above. Bits 15,11,7 are the MSB's for the UHF, Rx VHF and Tx
VHF PLL lock detector counters respectively. A non zero value must be programmed for the lock detect to operate
correctly.
3.0 Absolute Maximum Ratings
Supply Voltage
-0.3 to 3.6V
Voltage applied to any pin
Operating Temperature
Storage Temperature
Max Junction Temperature
-0.3 to Vcc + 0.3 V
-40°C to 85°C
-55°C to 125°C
125°C
This device is sensitive to ESD. Most pins have an ESD rating greater than 2000V (Human Body Model HBM),
however some pins have limited protection (800 to 2000V )in order to meet the RF performance. Anti-static
precautions should be used when handling this device.
4.0 Operating Conditions
Device operation is guaranteed under the following coonditions:
Value
Typ
Condition
Min
Max
Units
Comments
General
Supply Voltage
2.7
-40
3.3
V
Operating Temperature
+85
°C
Logic Input Voltage High – VIH
Logic Input Voltage Low – VIL
TCXO Reference Frequency
Frequency
0.8Vcc
Volts
Volts
0.2Vcc
13.0
14.4
MHz
MHz
MHz
GSM
IS136
IS136
Frequency
Frequency
19.44
41
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Value
Typ
Condition
Min
Max
Units
Comments
Receiver
Receiver IF Frequency
70
50
215
MHz
Transmitter
Transmit IF Frequency
I & Q common mode voltage
I & Q input voltage level
215
1.5
MHz
V
1.2
V p-p
0dB input buffer gain
Cellular band LO input level
PCS band LO input level
Cellular band LO frequency
PCS1900 band frequency
-15
-15
-10
-10
-5
-5
dBm
dBm
900
1900
1100
2200
MHz
Serial Control Timing
SDATA Set Up t1
See Figure 14
20
20
50
20
ns
ns
ns
ns
SDATA Hold t2
SCLK Pulse Width t3
SLATCH Set up t4
Serial Control Timing (cont’d)
SLATCH Pulse Width t5
SCLK Period t6
50
100
20
ns
ns
ns
Power Control Set up t7
42
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
5.0 Electrical Characteristics
The electrical characteristics are guaranteed under the following conditions unless stated otherwise. Vcc =3.0 V, T
= 25°C, TCXO Ref Frequency = 19.44 MHz.
Value
Typ
Characteristics
Supply Current
Min
Max
Units
Comments
Sleep
10
40
µA
Logic inputs = 0V or Vcc
Receive Operation
AMPS
32
33
30
38
39
36
mA
mA
mA
Note 1, AGC = 1.6V
Note 1, AGC = 1.6V
Note 1, AGC = 1.6V
IS136
GSM/EDGE
Transmit Operation
900 MHz Output
141
106
170
125
mA
mA
VGA = 2.4V, Note 2
VGA = 1V , Note 2
1900 MHz Output
120
102
145
120
mA
mA
VGA = 2.4V, Note 2
VGA = 1V, Note 2
Standby Operation
UHF PLL
12.5
5.2
15.0
6.3
mA
mA
mA
Note 3
Receive VHF PLL
Transmit VHF PLL
4.9
6.0
Additional Circuits
Frequency Doubler
UHF LO Output Buffer
Logic Inputs
4
5
mA
mA
Note 4
4.5
5.5
900 or 1900 Band Note 5
Input Current
10
10
nA
pF
Vin = 0 to Vcc
Input Capacitance
Lock Detect Output
43
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Value
Typ
Characteristics
Output Voltage Low
Min
Max
Units
Comments
0.2Vcc
Volts
Volts
I out = 1mA
I out = -1 mA
Output Voltage High
0.8Vcc
TCXO Input
Input Resistance
Input Capacitance
Input Sensitivity
10
kΩ
pF
10
2
0.5
V p-p
ac coupled
Receiver - IS136
All parameters are measured at
an IF frequency of 135.06 MHz,
Rx VCO = 270 MHz unless
stated otherwise
Input impedance
Max Voltage Gain
Min Voltage Gain
Gain slope
500
80
1500
Ω
dB
91
-13
56
8
AGC = 2.4 V
AGC = 0.3 V
AGC = 0.3 to 2V
Rs =800Ω
5
dB
50
62
dB/V
dB
NF Gainmax
Input V1dB Gainmin
IIP3 Gainmax
101
104
74
dBµV
dBµV
dB
Minimum gain
Max Gain
I/Q Amplitude Matching
I/Q Quadrature Accuracy
Output 1dB Compression
Output dc Offset
+/- 0.5
+/- 2
°
3
V p-p
mV
+/-20
Receiver AMPS (Fixed Gain)
All parameters are measured at
an IF frequency of 135.06 MHz,
Rx VCO = 270 MHz unless
stated otherwise.
Vagc = 1.6V (Gain 20 dB below
maximum)
Input impedance
Input Sensitivity
Noise Figure
Input IP3
500
1500
Ω
14
12
93
dBµV
dB
Note 6
dBµV
44
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Value
Characteristics
Audio Output
Min
Max
Units
Comments
Typ
900
1000
1100
mV
Note 7
RSSI Dynamic Range
Accuracy
50
dB
dB
-3
+3
RSSI Slope
16
25
mV/dB
dBµV
dBµV
Input Signal - Min
Input Signal - Max
Min RSSI Level
Max RSSI Level
RSSI Output Impedance
75
0.35
1.45
0.5
1.55
1
0.70
1.65
V
kΩ
Bandpass Filter
IS136 and AMPS
Narrow bandwidth mode
Centre Frequency
3dB Bandwidth
60
kHz
kHz
+/- 16
+/- 18
Stop Band Attenuation
0 to 3 kHz
Relative to signal at 60kHz
67
61
48
18
18
48
61
68
71
36
71
69
63
51
20
20
50
63
70
73
48
73
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
3 kHz to 10 kHz
10 kHz to 22 kHz
38 kHz
82 kHz
98 kHz to 110 kHz
110 kHz to 117 kHz
117 kHz to 123 kHz
123 kHz to 1.36 MHz
1.36 MHz to 1.52 MHz
1.52 MHz to 10 MHz
Image Attenuation
0 to -10kHz
61
40
dB
dB
-10 kHz to -42 kHz
45
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Value
Characteristics
- 42 kHz to -78 kHz
Min
Max
Units
Comments
Typ
30
40
61
36
61
40
dB
dB
dB
dB
dB
- 78 kHz to -105 kHz
-105 kHz to -1.36 MHz
-1.36 MHz to -1.52 MHz
-1.52 MHz to -10 MHz
48
Gain Ripple
1.0
1.5
dB
60kHz +/- 12.5kHz
Receiver - GSM
All parameters are measured at
an IF frequency of 135.0 MHz,
Rx VCO = 270 MHz unless
stated otherwise. TCXO =
13.0MHz.
IF Frequency
Input impedance
Max Voltage Gain
Min Voltage Gain
Gain slope
70
500
80
215
MHz
Ω
1500
91
-13
56
8
dB
AGC = 2.4 V
AGC = 0.3 V
AGC = 0.3 to 2V
Rs =800Ω
+5
62
dB
50
dB/V
dB
NF Gainmax
Input V1dB Gainmin
IIP3 Gainmax
Baseband filter attenuation
100kHz
100
104
73
dBµV
dBµV
Minimum gain
Max Gain
1
dB
dB
dB
dB
dB
mV
315kHz
15
30
60
600kHz
10MHz
Filter Ripple
1
0 to 100kHz
Output dc Offset
10
20
After offset calibration. Maximum
Base band gain
I/Q Amplitude Matching
I/Q Quadrature Accuracy
Output 1dB Compression
+/- 0.5
+/- 2
dB
°
3
V p-p
46
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Value
Typ
Characteristics
Min
Max
Units
Comments
Baseband Gain Adjust
-21
0
dB
dB
3dB steps
Baseband Gain Step Resolution
3
Transmitter
All parameters are measured at
an IF frequency of 180.0 MHz,
Tx VCO = 360 MHz unless
stated otherwise
I & Q modulator
I/Q Input Buffer Gain
I/Q Input Buffer Gain
I/Q Input Buffer Gain
I/Q Input Buffer Gain
I/Q Input Buffer Gain
I & Q differential input resistance
-1
0
3
+1
dB
dB
dB
dB
dB
kΩ
6
9
12
80
I & Q Baseband Filter
Attenuation (IS136/AMPS)
dc - 12.5 kHz
85 - 180 kHz
> 180 kHz
0.5
dB
dB
dB
12
25
17
33
I & Q Baseband Filter
Attenuation (GSM/EDGE)
dc to 100kHz
1
dB
dB
dB
dB
> 4MHz
55dB
30
Carrier Suppression
Sideband Suppression
40
40
30
IF Variable gain amplifiers
Gain control range
45
60
38
dB
V
Control voltage for minimum
gain
0.10
Control voltage for maximum
gain
2.4
43
V
AGC control voltage slope
33
dB/V
VGA = 0.5 to 1.2V
47
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Value
Typ
Characteristics
Min
Max
Units
Comments
IF Output Filter (option)
IF output impedance
IF input impedance
IF output level
500
1.5
Ω
To external filter
From external filter
kΩ
mV
100
800MHz RF output stage
Specifications assume 50 ohm
load driven via a matching
network.
Output Frequency = 836 MHz,
UHF LO = -10 dBm at 1016
MHz.
RF amplifier operating
frequency range
824
+8
849
MHz
Output power
ACPR (TDMA)
+10
-36
dBm
dBc
dBc
dBm
Pout = +8dBm, Offset = 30kHz
Pout = +8dBm, Offset = 60kHz
-56
Output power AMPS
+10
+14
-124
Receive band noise (869 - 894
MHz)
dBm/Hz ftx = 849 MHz Pout = +8dBm
With external IF filter
Spurious Outputs
LO Leakage
-25
-27
-21
-21
-20
dBc
dBc
dBm
Pout = +8dBm
Pout = +8dBm
Image Rejection
Other Spurii
1900MHz RF output stage
(PCS)
Specifications assume 50 ohm
load driven via a matching
network
Output Frequency = 1880 MHz,
UHF LO = -10 dBm at 2060
MHz.
RF amplifier operating
frequency range
1.88
+8
1.91
GHz
Output power
ACPR (TDMA)
+10
-36
-56
dBm
dBc
dBc
Pout = +8dBm, Offset = 30kHz
Pout = +8dBm, Offset = 60kHz
48
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Value
Typ
Characteristics
Min
Max
Units
Comments
Receive band noise (1930-1990
MHz)
-128
dBm/Hz ftx = 1910 MHz, Pout = +8dBm
With external IF filter
Spurious Outputs
LO Leakage
-30
-30
-25
-25
-20
dBc
dBc
dBm
Pout = +8dBm
Pout = +8dBm
Image Rejection
Other Spurii
UHF Synthesiser
Input Frequency
800
0.9
2200
1.1
MHz
mA
mA
mA
mA
V
Charge Pump Current
1
0.45
0.22
0.11
0.4
0.5
0.55
0.28
0.14
0.25
0.125
Charge Pump Output
Compliance
Vdd -
0.4
Less than +/-10 % variation in
Iout
Charge Pump sink/source
mismatch
15
%
Charge Pump off-state current
Fractional Compensation
5
nA
µA
88
98
108
Full Scale
UHF Buffers
Load Impedance
200
-11
-40
Ω
Output Level (900 and 1900)
Harmonic Level
dBm
dBc
Load = 200 ohms
LO1900 Output
Rx and Tx IF Synthesisers
Input Frequency
100
0.9
430
1.1
MHz
mA
mA
mA
mA
Charge Pump Current
1
0.45
0.22
0.11
0.5
0.55
0.28
0.14
0.25
0.125
49
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Value
Typ
Characteristics
Min
Max
Units
Comments
Charge Pump Output
Compliance
0.4
Vcc -
0.4
V
Less than +/-10 % variation in
Iout
Charge Pump sink/source
mismatch
15
%
Charge Pump off-state current
5
nA
Rx LO Oscillator
Frequency
140
260
430
430
MHz
Phase Noise
-99
-99
dBc/Hz
Freq = 270 MHz, Offset = 30
kHz
Tx LO Oscillator
Frequency
MHz
Phase Noise
dBc/Hz
Freq = 360 MHz, Offset = 30
kHz
Note 1: All receive currents include all receiver sections plus Rx VHF and UHF PLL's, and UHF LO input buffer circuits. The LO output
buffer and frequency doubler are not included.
Note 2: All transmit currents include all transmit sections plus Tx VHF and UHF PLL's, and UHF LO input buffer circuits. The LO
output buffer and frequency doubler are not included.
Note 3: Includes UHF LO input buffer
Note 4: This is only applicable in 1900 MHz band
Note 5: The UHF LO output buffer need only be powered up if required to drive an external circuit, for example, a receive front end
mixer.
Note 6: Input signal FM modulated with 8 kHz deviation by 1 kHz modulating signal. Specification is minimum input level to obtain 12
dB SINAD at FM Output (pin 45) using CCITT filter.
Note 7: Input modulation: 1kHz modulating signal with 8 kHz deviation. Output level at FM out (pin 45) is set by external components.
See application section for details.
50
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
6.0 Typical Performance Curves
6.1 Receive
AMPS Rx. - Icc v Temperature
IS136 Rx. - Icc v Temperature
35
38
37
36
35
34
33
32
31
30
29
34
33
32
31
30
Vcc = 2.7V
Vcc = 2.7V
Vcc = 3.0V
Vcc = 3.3V
29
Vcc = 3.0V
Vcc = 3.3V
28
27
-40
25
85
-40
25
85
Temperature °C
Temperature °C
Rx. Gain v AGC (Vcc)
Rx. Gain v AGC (Temperature)
120
100
80
60
40
20
0
120
100
80
60
40
20
0
T = -40°C
T = 25°C
T = 85°C
Vcc = 2.7V
Vcc = 3.0V
Vcc = 3.3V
-20
-20
0
1
2
3
0
1
2
3
AGC Volts
AGC Volts
51
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
Rx. RSSI
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40°C
25°C
85°C
-150
-100
-50
0
Input Level dBm
6.2 Transmit
IS136 Tx. 900 MHz - Icc v AGC (Vcc)
IS136 Tx. 900 MHz - Icc v AGC (Temperature)
180
160
140
120
100
80
180
160
140
120
100
80
Vcc = 2.7V
60
Vcc = 3.0V
Vcc = 3.3V
60
-40°C
25°C
85°C
40
40
20
20
0
0
0
1
2
3
0
1
2
3
AGC Volts
AGC Volts
52
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
IS136 Tx.1900 MHz - Icc v AGC (Temperature)
160
IS136 Tx. 1900 MHz - Icc v AGC (Vcc)
160
140
120
100
80
140
120
100
80
-40°C
25°C
85°C
Vcc = 2.7V
Vcc = 3.0V
Vcc = 3.3V
60
60
40
40
20
20
0
0
0
1
2
3
0
1
2
3
AGC Volts
AGC Volts
IS136 Tx. 900 MHz - Power Out v AGC (Vcc)
20
IS136 Tx. 900 MHz - Power Out v AGC (Temp.)
20
10
0
10
0
-10
-20
-30
-40
-50
-60
-10
-20
-40°C
25°C
85°C
Vcc = 2.7V
Vcc = 3.0V
Vcc = 3.3V
-30
-40
-50
-60
0
1
2
3
0
1
2
3
AGC Volts
AGC Volts
53
Zarlink Semiconductor Inc.
ZL20250
Data Sheet
IS136 Tx. 1900 MHz - Power Out v AGC (Vcc)
IS136 Tx 1900MHz - Power Out v AGC (Temp.)
20
10
20
10
0
0
-10
-20
-30
-40
-50
-60
-10
-20
-30
-40
-50
-60
-40°C
25°C
85°C
Vcc = 2.7V
Vcc = 3.0V
Vcc = 3.3V
0
1
2
3
0
1
2
3
AGC Volts
AGC Volts
54
Zarlink Semiconductor Inc.
L
Package Code
c
Zarlink Semiconductor 2002 All rights reserved.
Previous package codes
ISSUE
ACN
1
2
211130
213841
16Jun01
12Dec02
DATE
APPRD.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
相关型号：
©2020 ICPDF网 联系我们和版权申明