VP5511B/CG/GP1N [ZARLINK]
NTSC/PAL Digital Video Encoder; NTSC / PAL数字视频编码器
| 型号： | VP5511B/CG/GP1N |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | NTSC/PAL Digital Video Encoder |
| 文件： | 总17页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
VP5311B/VP5511B
NTSC/PAL Digital Video Encoder
Advance Information
Supersedes DS4575 1.5 May 1997 version
DS4575 - 2.2 October 1998
The VP5311/VP5511 converts digital Y, Cr, Cb, data
intoanalogNTSC/PALcompositevideoandS-videosignals.
The outputs are capable of driving doubly terminated 75
ohm loads with standard video levels.
The device accepts data inputs complying with CCIR
Recommendation 601 and 656. The data is time multiplexed
on an 8 bit bus at 27MHz and is formatted as Y, Cr, Y, Cb
(i.e. 4:2:2). The video blanking and sync information from
REC 656 is included in the data stream when the VP5311/
VP5511 is working in slave mode.
The output pixel rate is 27MHz and the input pixel rate
is half this frequency, i.e. 13.5MHz.
All necessary synchronisation signals are generated
internally when the device is operating in master mode. In
slave mode the device will lock to the TRS codes or the HS
and VS inputs.
PIN 64
The rise and fall times of sync, burst envelope and
video blanking are internally controlled to be within
composite video specifications.
Three digital to analog converters (DACs) are used to
convert the digital luminance, chrominance and composite
data into true analog signals. An internally generated
reference voltage provides the biasing for the DACs.
PIN 1
GP64
Figure 1 Pin connections (top view)
PIN
1
2
3
4
5
6
7
8
FUNCTION
VDD
GND
PIN
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
FUNCTION
VDD
RESET
REFSQ
GND
VDD
GND
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
GND
VDD
FEATURES
D0 (VS I/O)
D1 (HS I/O)
D2 (FC0 O/P)
D3 (FC1 O/P)
D4 (FC2 O/P)
D5
D6 (SCSYNC I/P)
D7 (PALID I/P)
GND
VDD
GND
GND
PXCK
■ Converts Y, Cr, Cb data to analog composite video and
S-video
■ Supports CCIR recommendations 601 and 656
■ All digital video encoding
■ Selectable master/slave mode for sync signals
■ Switchable chrominance bandwidth
■ Switchable pedestal with gain compensation
■ SMPTE 170M NTSC or CCIR 624 PAL compatible
outputs
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
■ GENLOCK mode
■ Line 21 Closed Caption encoding
■ I2C bus serial microprocessor interface
■ VP5311B supports Macrovision anti-taping format Rev.
6.1, in PAL and Rev. 7.01 in NTSC.
VDD
CLAMP
COMPSYNC
GND
VDD
TDO
TDI
TMS
TCK
GND
SA1
SA2
SCL
VDD
SDA
GND
VDD
AGND
VREF
DACGAIN
COMP
AVDD
LUMAOUT
AGND
COMPOUT
AGND
CHROMAOUT
AVDD
N/C
APPLICATIONS
■ Digital Cable TV
■ Digital Satellite TV
■ Multi-media
■ Video games
■ Karaoke
■ Digital VCRs
ORDERING INFORMATION
VP5311B/CG/GP1N
VP5511B/CG/GP1N
N/C
AVDD
AVDD
N/C
VP5311B/VP5511B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions
DC CHARACTERISTICS
Parameter
Conditions
Typ.
Units
Symbol Min.
Max.
Digital Inputs TTL compatible (except SDA, SCL)
Input high voltage
VIN
VIL
2.0
V
V
0.8
Input low voltage
Digital Inputs SDA, SCL
Input high voltage
VIH
VIL
IIH
IIL
0.7 VDD
V
V
0.3 VDD
10
Input low voltage
µA
µA
Input high current
VIN = VDD
-10
Input low current
VIN = VSS
Digital Outputs CMOS compatible
Output high voltage
VOH
VOL
3.7
V
V
IOH = -1mA
IOL = +4mA
0.4
0.6
Output low voltage
Digital Output SDA
VOL
V
Output low voltage
IOL = +6mA
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions
DC CHARACTERISTICS DACs
Parameter
Accuracy (each DAC)
Typ.
Units
Symbol Min.
Max.
INL
DNL
±1.5
±1
±5
LSB
LSB
%
Integral linearity error
Diffential linearity error
DAC matching error
Monotonicity
LSB size
Internal reference voltage
Internal reference voltage output impedance
Reference Current (VREF/RREF) RREF = 769Ω
DAC Gain Factor (VOUT = KDAC x IREF x RL), VOUT = DAC code 511
Peak Glitch Energy (see fig.3)
guaranteed
66.83
1.050
27k
1.3699
24.93
50
µA
V
Ω
VREF
ZR
IREF
KDAC
mA
pV-s
CVBS, Y and C - NTSC (pedestal enabled)
Maximum output, relative to sync bottom
White level relative to black level
Black level relative to blank level
Blank level relative to sync level
Colour burst peak - peak
mA
mA
mA
mA
mA
mA
33.75
17.64
1.40
7.62
7.62
0.40
DC offset (bottom sync)
CVBS, Y and C - PAL
mA
mA
mA
mA
mA
mA
34.15
18.71
26.73
8.02
8.02
0.00
Maximum output
White level relative to black level
White level relative to sync level
Black level relative to sync level
Colour burst peak - peak
DC offset (bottom sync)
Note: All figures are for: RREF = 769Ω RL = 37.5Ω. When the device is set up in NTSC mode there is a +0.25% error in the PAL
levels. If RL = 75Ω then RREF = 1538Ω.
ABSOLUTE MAXIMUM RATINGS
Note: Stresses exceeding these listed under Absolute
Maximum Ratings may induce failure. Exposure to Absolute
Maximum Ratings for extended periods may reduce
reliability. Functionality at or above these conditions is not
implied.
Supply voltage
VDD, AVDD
-0·3 to 7·0V
-0·3 to VDD+0·3V
0 to 70°C
Voltage on any non power pin
Ambient operating temperature
Storage temperature
-55°C to 150°C
2
VP5311B/VP5511B
RECOMMENDED OPERATING CONDITIONS
Parameter
Typ.
Units
Symbol
Min.
Max.
Power supply voltage
Power supply current (including analog outputs)
Input clock frequency
SCL clock frequency
Analog video output load
DAC gain resistor
VDD, AVDD
IDD
4.75
5.25
V
mA
5.00
150
27.00
PXCK
fSCL
-50ppm
0
+50ppm MHz
500
70
kHz
Ω
Ω
37.5
769
Ambient operating temperature
°C
VIDEO CHARACTERISTICS
Parameter
Typ.
Units
Symbol Min.
Max.
Luminance bandwidth
5.5
1.3
650
MHz
MHz
kHz
MHz
MHz
MHz
Chrominance bandwidth (Extended B/w mode)
Chrominance bandwidth (Reduced B/w mode)
Burst frequency (NTSC)
Burst frequency (PAL-B, D,G,H,I)
Burst frequency (PAL-N Argentina)
Burst cycles (NTSC )
3.57954545
4.43361875
3.58205625
9
Fsc cycles
Burst cycles (NTSC and PAL-B, D, G, H,I)
Burst envelope rise / fall time (NTSC and PAL-N)
Burst envelope rise / fall time (NTSC and PAL-B, D, G, H,I)
Analog video sync rise / fall time (NTSC and PAL-N)
Analog video blank rise / fall time (NTSC and PAL-B, D, G, H,I)
Differential gain
10
Fsc cycles
300
300
145
245
1.5
0.5
-61
-56
-58
ns
ns
ns
ns
% pk-pk
° pk-pk
dB
Differential phase
Signal to noise ratio (unmodulated ramp)
Chroma AM signal to noise ratio (100% red field)
Chroma PM signal to noise ratio (100% red field)
Hue accuracy
Colour saturation accuracy
Residual sub carrier
-61
-56
-58
2.5
2.5
dB
dB
%
%
dB
ns
-60
10
Luminance / chrominance delay
ESD COMPLIANCE
Pins
Test Levels
Notes
Meets Mil-Std-883 Class 2
Test
All pins
All pins
2kV on 100pF through 1k5Ω
200V on 200pF through 0Ω & 500nH
Human body model
Machine model
3
VP5311B/VP5511B
SDA
SET-UP
REGISTERS
ANTI-TAPING
CONTROL
CLOSED
CAPTION
SCL
SA1
SA2
I2C INTERFACE
CLAMP
RESET
VIDEO TIMING GENERATOR
+
+
COMPSYNC
LUMA OUT
SYNC
BLANK
INSERT
LUMA
DAC
Y
INTERPOLATOR
COMP
OUT
INPUT
DEMUX
COMP
DAC
+
8
&
PD7-0
Cr
CHROMA
CHROMA
LOW-PASS
FILTER
INTERP
CHROMA
DAC
INTERPOLATOR
MODULATOR
Cb
CHROMA OUT
PXCK
8
GENERAL
PURPOSE PORT
DAC
REF
DIGITAL
PHASE COMP
COLOUR SUBCARRIER
GENERATOR
DACGAIN
VREF
JTAG.
D7-0
TDO
TDI
REFSQ
TMS TCK
COMP
Figure 2 Functional block diagram of the VP5311B, the VP5511B is identical except there is no Anti-Taping Control
V
W
H
Peak Glitch Area = H x W/2
t(ps)
The glitch energy is calculated by measuring the area under the voltage
time curve for any LSB step, typically specified in picoVolt-seconds (pV-s)
Figure 3 Glitch Energy
4
VP5311B/VP5511B
PIN DESCRIPTIONS
Pin Name
Pin No.
Description
PD0-7
39 - 46
3 - 10
15
8 Bit Pixel Data inputs clocked by PXCK. PD0 is the least significant bit, corresponding to Pin
46. These pins are internally pulled low.
D0-7
8 Bit General Purpose Port input/output. D0 is the least significant bit, corresponding to Pin 3.
These pins are internally pulled low.
PXCK
CLAMP
27MHz Pixel Clock input. The VP5311 internally divides PXCK by two to provide the pixel
clock.
17
The CLAMP output signal is synchronised to COMPSYNC output and indicates the position of
the BURST pulse, (lines 10-263 and 273-525 for NTSC; lines 6-310 and 319-623 for PAL-
B,D, G,I,N(Argentina)).
COMPSYNC
TDO
18
21
22
23
24
26
27
28
30
34
Composite sync pulse output. This is an active low output signal.
JTAG Data scan output port.
TDI
JTAG Data scan input port.
TMS
JTAG Scan select input.
TCK
JTAG Scan clock input.
SA1
Slave address select.
SA2
Slave address select.
SCL
Standard I2C bus serial clock input.
Standard I2C bus serial data input/output.
SDA
RESET
Master reset. This is an asynchronous, active low, input signal and must be asserted for a
minimum 200ns in order to reset the VP5311.
REFSQ
VREF
35
50
Reference square wave input used only during Genlock mode.
Voltage reference output. This output is nominally 1·055V and should be decoupled with a
100nF capacitor to GND.
DAC GAIN
COMP
51
52
DAC full scale current control. A resistor connected between this pin and GND sets the
magnitude of the video output current. An internal loop amplifier controls a reference current
flowing through this resistor so that the voltage across it is equal to the Vref voltage.
DAC compensation. A 100nF ceramic capacitor must be connected between pin 52 and pin
53.
LUMAOUT
COMPOUT
CHROMAOUT
NOT USED
VDD
54
56
True luminance, composite and chrominance video signal outputs. These are high
impedance current source outputs. A DC path to GND must exist from each of these pins.
58
60, 61, 64
1, 12, 16, Positive supply input. All VDD pins must be connected.
20, 29,
32, 33,
37, 48
AVDD
GND
53, 59
62, 63
Analog positive supply input. All AVDD pins must be connected.
2, 11, 13, Negative supply input. All GND pins must be connected.
14, 19,
25, 31,
36, 38, 47
AGND
49, 55, 57 Negative supply input. All AGND pins must be connected.
All other pins are N/C and should not be connected.
5
VP5311B/VP5511B
REGISTERS MAP
See Register Details for further explanations.
ADDRESS REGISTER
DEFAULT
hex
hex
NAME
7
6
5
4
3
2
1
0
R/W
BAR
RA5
RA4
RA3
RA7
RA6
RA2
RA1
RA0
W
00
01
02
03
PART ID2
PART ID1
PART ID0
REV ID
ID17
ID0F
ID07
REV7
ID16
ID0E
ID06
ID15
ID0D
ID05
ID14
ID0C
ID04
ID13
ID0B
ID03
ID12
ID0A
ID02
ID11
ID09
ID01
REV1
ID10
ID08
ID00
REV0
13
66
58
05
R
R
R
R
REV6
REV5
REV4
REV3
REV2
04
05
06
07
08
09
0A
0B
0C
0D
GCR
VOCR
HANC
-
-
-
-
YCDELAY RAMPEN
CLAMPDIS CHRBW SYNCDIS BURDIS
SLH&V CVBSCLP
VFS1
CHRDIS
Reserved ACTREN
AN1
SC1
FR11
FR09
FR01
-
VFS0
PEDEN
00
00
00
00
9C
87
C1
F1
00
00
R/W
R/W
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LUMDIS
Reserved
AN2
-
DFI2
AN5
SC5
FR15
FR0D
FR05
-
DFI1
AN4
SC4
FR14
FR0C
FR04
-
DFI0
AN3
SC3
FR13
FR0B
FR03
-
ANCID
AN7
SC7
FR17
FR0F
FR07
-
AN6
SC6
FR16
FR0E
FR06
-
PARITY
SC0
SC_ADJ
FREQ2
FREQ1
FREQ0
SCHPHM
SCHPHL
SC2
FR12
FR0A
FR02
-
FR10
FR08
FR00
SCH8
SCH0
SCH7
SCH6
SCH5
SCH4
SCH3
SCH2
SCH1
0E to 1F Reserved
20
21
22
GPPCTL
GPPRD
GPPWR
CTL7
RD7
WR7
CTL6
RD6
WR6
CTL5
RD5
WR5
CTL4
RD4
WR4
CTL3
RD3
WR3
CTL2
RD2
WR2
CTL1
RD1
WR1
CTL0
RD0
WR0
FF
-
00
W
R
W
23 to EF Not used
F0
F1
F2
F3
F4
CCREG1
CCREG2
CCREG3
CCREG4
CC_CTL
-
-
-
-
-
F1W1D6 F1W1D5
F1W2D6 F1W2D5
F2W1D6 F2W1D5
F2W2D6 F2W2D5
F1W1D4
F1W2D4
F2W1D4
F2W2D4
-
F1W1D3 F1W1D2
F1W2D3 F1W2D2
F2W1D3 F2W1D2
F2W2D3 F2W2D2
F1W1D1
F1W2D1
F2W1D1
F2W2D1
F2EN
F1W1D0
F1W2D0
F2W1D0
F2W2D0
F1EN
00
00
00
00
00
R/W
R/W
R/W
R/W
R/W
-
-
F2ST
F1ST
F0 to F7 Reserved
F8
F9
FB
FC
FD
FE
FF
HSOFFL
HSOFFM
HSOFF7
-
HSOFF6 HSOFF5
HSOFF4
-
HSOFF3 HSOFF2
HSOFF1
HSOFF9
HCNT9
HCNT1
HS0FF0
HSOFF8
HCNT8
HCNT0
7E
00
00
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
SLAVE1 NCORSTD VBITDIS VSMODE F_SWAP
SLAVE2
TEST1
TEST2
GPSCTL
SL_HS1
HCNT3
FOR
SL_HS0
HCNT2
TEST
HCNT7
HCNT6
HCNT5
HCNT4
REGISTER RESERVED
REGISTER RESERVED
GENLKEN NOLOCK
FOR
TEST
FSC4SEL GENDITH
PALIDEN TSURST CHRMCLIP TRSEL
00
Table.1 Register map
NOTE * For register HANC, bits 3, 4 and 5 are read only. Bits 1 and 2 are reserved. N/A = not applicable.
For register PART ID0 the VP551 value is AB
SC_ADJ
register
hex
Number of Horizontal Subcarrier
fSC/fH
Standard
Field
freq. Hz
59.94
50
FREQ2-0
Lines/
field
525
pixels/line freq. kHz.
freq. kHz.
fSC
registers hex
87 C1 F1
at 27MHz
fH
15.734266
NTSC (default)
PAL-B, G, H, I
1716
(455/2)
xx
3.57954545
15.625000
15.625000
1728
1728
(1135/4+1/625)
(917/4+1/625)
9C
57
A8 26 2B
625
4.43361875
3.58205625
PAL-N (Argentina)
50
87 DA 51
625
Table.2 Line, field and subcarrier standards and register settings
xx = don’t care.
The calculation of the FREQ register value is according to the following formula:-
FREQ = 226 x fSC/PXCK hex, where PXCK = 27.00MHz
NTSC value is rounded UP from the decimal number. PAL-B, D, G, H, I and N (Argentina) are rounded DOWN. The SC_ADJ
value is derived from the adjustment needed to be added after 8 fields to ensure accuracy of the Subcarrier frequency. Note the
SC_ADJ value of 9C required for PAL-B, D, G, H, I, is different to the default state of the register.
In NTSC the NCO is reset at the end of every line, this can be disabled by setting the NCORSTD bit in SLAVE1, this allows the
VP5311 to cope with line lengths that are not exactly as specified in REC656.
6
VP5311B/VP5511B
REGISTER DETAILS
PEDEN
High = Pedestal (set-up) enable a
7·5 IRE pedestal on lines 23-262 and
286-525. Valid for NTSC
BAR
Base register
RA7-0
Register address.
HANC
Horizontal Ancillary Data Control
PART ID 2-0
Part number
DFI2-0(read only)Digital Field Identification, 000=Field1
ID17-00
Chip part identification (ID) number.
ANCTREN
Ancillary timing reference enable. When
High use FIELD COUNT from ancillary
data stream. When low, data is ignored.
REV ID
Revision number
REV7-0
Chip revision ID number.
ANCID
AN7-1
AN0
Ancillary data ID
Ancillary data ID
Parity bit (odd)
GCR
YCDELAY
Global Control
Luma to Chroma delay.
High = 37ns luma delay, this may be
used to compensate for group delay in
external filters.
Only ancillary data in REC 656 data
stream with the same ID as this byte will
be decoded by the VP5311/VP5511 to
produce H and V synchronisation and
FIELD COUNT.
Low = normal operation (default).
RAMPEN
Modulated ramp enable.
High = ramp output for differential phase
and gain measurements. A 27MHz clock
must be applied to PXCK pin.
Low = normal operation (default).
1 = Slave to HS and VS inputs
1 = Enables clamp on composite output,
to prevent flatenning of chroma peak
throughs
SC_ADJ
SC7-0
Sub Carrier Adjust
Sub carrier frequency seed value, see
table 2.
SL_HS_VS
CVBSCLMP
FREQ2-0
FR17-00
Sub carrier frequency
24 bit Sub carrier frequency programmed
via I2C bus, see table 2. FREQ2 is the
most significant byte (MSB).
VFS1-0
Video format select
VFS1 VFS0
SCHPHM-L
SCH9-0
Sub carrier phase offset
9 bit Sub carrier phase relative to the
50% point of the leading edge of the
horizontal part of composite sync.
SCHPHM bit 0 is the MSB. The nominal
value is zero. This register is used to
compensate for delays external to the
VP5311/VP5511.
0
0
1
1
0
1
0
1
NTSC (default)
PAL-B, D, G,H,I,N(Argentina)
Reserved
Reserved
VOCR
Video Output Control
CLAMPDIS
High = Clamp signal disable
Low = normal operation with clamp signal
enabled (default).
GPPCTL
General purpose port control
CTL7-0
Each bit controls port direction
Low = output
High = input
CHRBW
Chroma bandwidth select.
High = ±1·3MHz.
GPPRD
RD7-0
General purpose port read data
I2C bus read from general purpose port
(only INPUTS defined in GPPCTL)
Low = ±650kHz (default)
SYNCDIS
High = Sync disable (in composite video
signal). COMPSYNC is not affected.
Low = normal operation with sync
enabled (default).
GPPWR
WR7-0
General purpose port write data
I2C bus write to general purpose port
(only OUTPUTS defined in GPPCTL)
BURDIS
LUMDIS
High = Chroma burst disable.
Low = normal operation, with burst
enabled (default).
CCREG1
F1W1D6-0
Closed Caption register 1
Field one (line 21), first data byte
CCREG2
F1W2D6-0
Closed Caption register 2
Field one (line 21), second data byte
High = Luma input disable - force black
level with synchronisation pulses main-
tained.
CCREG3
Closed Caption register 3
Low = normal operation, with Luma input
enabled (default).
F2W2D6-0
Field two (line 284), first data byte
CCREG4
Closed Caption register 4
CHRDIS
High = Chroma input disable - force
monochrome.
F2W2D6-0
Field two (line 284), second data byte
Low = normal operation, with Chroma
input enabled (default).
7
VP5311B/VP5511B
CCCTL
F1ST
Closed Caption control register
TSURST
High = chip soft reset. Registers are NOT
reset to default values.
Low = normal operation (default).
Field one (line 21) status
High = data has been encoded
Low = new data has been loaded to
CCREG1-2
CHRMCLIP
High = enable clipping of chroma data
when luma goes below black level and is
clipped.
F2ST
Field two (line 284) status
High = data has been encoded
Low = new data has been loaded to
CCREG3-4
Low = no chroma clipping (default).
TRSEL
High = master mode, GPP bits D0 - 4 are
forced to become a video timing port with
VS, HS and FIELD outputs.
F1EN
F2EN
Closed Caption field one (line 21)
High = enable
Low = disable (default)
Low = slave mode, timing from REC656.
Closed Caption field two (line 284)
High = enable
Low = disable (default)
I2C BUS CONTROL INTERFACE
I2C bus address
HSOFFM-L
HSOFF9-0
HS offset
This is a 10 bit number which allows the
user to offset the start of digital data input
with reference to the pulse HS.
A4
A6
A5
A3
A2
A1
A0
R/ W
X
0
0
1
1
SA2 SA1
0
SLAVE1
NCORSTD
H &V Slave mode control register
1 = NCO Line Reset Disable (NTSC only)
The serial microprocessor interface is via the bi-
directional port consisting of a data (SDA) and a clock (SCL)
line. It is compatible to the Philips I2C bus standard (Jan. 1992
publication number 9398 393 40011). The interface is a slave
transmitter - receiver with a sub-address capability. All
communication is controlled by the microprocessor. The SCL
line is input only. The most significant bit (MSB) is sent first.
Data must be stable during SCL high periods.
A bus free state is indicated by both SDA and SCL lines
being high. START of transmission is indicated by SDA being
pulled low while SCL is high. The end of transmission,
referred to as a STOP, is indicated by SDA going from low to
high while SCL is high. The STOP state can be omitted if a
repeated START is sent after the acknowledge bit. The
reading device acknowledges each byte by pulling the SDA
line low on the ninth clock pulse, after which the SDA line is
released to allow the transmitting device access to the bus.
The device address can be partially programmed by the
setting of the pins SA1 and SA2. This allows the device to
respond to one of four addresses, providing for system
flexibility. The I2C bus address is seven bits long with the last
bit indicating read / write for subsequent bytes.
VBITDIS
0 = Video blanked when Rec601 V bit set
1 = V bit is ignored
The odd and even fields are swapped
Selects pixel sample (1 to 4)
As HCNT7-0 but MSBs
H &V Slave position register
Adjusts for delay at which pixel data
occurs relative to HS
F_SWAP
SL_HS1-0
HCNT9-8
SLAVE2
HCNT7-0
GPSCTL
FSC4SEL
GPS Control
When high, REFSQ = 4xFSC and GPP
bit D6 is forced to become an input for a
SCSYNC signal (high = reset), which
provides a synchronous phase reset for
FSC divider. Low = normal operation with
REFSQ = 1xFSC. (default).
GENDITH
GENLKEN
1 = Gen lock dither added.
High = enable Genlock to REFSQ signal
input.
Low = internal subcarrier generation
(default).
The first data byte sent after the device address, is the
sub-address-BAR(baseaddressregister). Thenextbytewill
be written to the register addressed by BAR and subsequent
bytestothesucceedingregisters. TheBARmaintainsitsdata
after a STOP signal.
NOLOCK
PALIDEN
Genlock status bit (read only)
Low = Genlocked.
High = cannot lock to REFSQ. This bit is
cleared by reading and set again if lock
cannot be attained.
NTSC/PAL Video Standards
Both NTSC (4-field, 525 lines) and PAL (8-field, 625 lines)
video standards are supported by the VP5311/VP5511. All
raster synchronisation, colour sub-carrier and burst
characteristics are adapted to the standard selected. The
VP5311/VP5511 generates outputs which follow the
requirementsofSMPTE170MandCCIR624forPALsignals.
High = enable external PAL ID phase
control and GPP bit D7 is forced to
become an input for PAL ID switch signal,
(GPP bit D7 - Low = +135°,
High = -135°).
Low = normal operation, internal PAL ID
phase switch is used (default).
The device supports the following:
NTSC,
PAL B, D, G, H, I, N (Argentina).
8
VP5311B/VP5511B
Video Blanking
enables an envelope prediction circuit that establishes if the
chroma and luma added together is likely to go outside the
CVBS DAC limits. If it is, then a smooth rounding of the
chroma peaks is made to stop this happening. This prevents
any high frequency components being produced as with the
clipping function which will produce flat peaks. In practice
there will be some loss of saturation in the colour.
Output sinx/x compensation filters are required on all
video output, as shown in the typical application diagram, see
figs. 8 & 9.
The VP5311/VP5511 automatically performs standard
composite video blanking. Lines 1-9, 264-272 inclusive, as
well as the last half of line 263 are blanked in NTSC mode. In
PAL mode, lines 1-5, 311-318, 624-625 inclusive, as well as
the last half of line 623 are blanked.
The V bit within REC656 defines the video blanking when
TRSEL (bit 0 of GPSCTL register) is set low. When in
MASTER mode with TRSEL set high the video encoder is still
enabled. Therefore if these lines are required to be blank they
must have no video signal input.
Video Timing - Slave sync mode
Interpolator
The VP5311/VP5511 has an internal timing generator
which produces video timing signals appropriate to the mode
of operation. In the default (power up) slave mode, all timing
signalsarederivedfromtheinputclock, PXCK, whichmustbe
derived from a crystal controlled oscillator. Input pixel data is
latched on the rising edge of the PXCK clock.
The video timing generator produces the internal blanking
and burst gate pulses, together with the composite sync
output signal, using timing data (TRS codes) from the
Ancillary data stream in the REC656 input signal, (when
TRSEL (bit 0 of GPSCTL register) is set low).
The luminance and chrominance data are separately
passed through interpolating filters to produce output
sampling rates double that of the incoming pixel rate. This
reduces the sinx/x distortion that is inherent in the digital to
analog converters and also simplifies the analog
reconstruction filter requirements.
Digital to Analog Converters
The VP5311/VP5511 contained three 9 bit digital to
analog converters which produce the analog video signals.
The DACs use a current steering architecture in which bit
currents are routed to one of two outputs; thus the DAC has
true and complementary outputs. The use of identical current
sources and current steering their outputs means that
monotonicity is guaranteed. An on-chip voltage reference of
1.050V provides the necessary biasing. However, the
VP5311/VP5511 may be used in applications where an
external 1V reference is provided on the VREF pin, to adjust
the video levels. In this case, the external reference should be
temperature compensated and provide a low impedance
output.
The full-scale output currents of the DACs is set by an
external 769Ω resistor between the DACGAIN and GND pins.
An on-chip loop amplifier stabilises the full-scale output
current against temperature and power supply variations.
The analog outputs of the VP5311/VP5511 are capable of
directly driving doubly terminated 75Ω load then the
DACGAIN resistor is simply doubled.
HCNT
Toensurethattheincomingdataissampledcorrectlya10
bit binary number (HCNT) has to be programmed into the
SLAVE1 and 2 registers. This will allow the device's internal
horizontal counter to align with the video data, each bit
represents one 13.5MHz cycle. To calculate this use the
formula below:
NTSC
HCNT = SN + 119 (SN = 0 - 738)
HCNT = SN + 739 (SN = 739 - 857)
PAL
HCNT = SN + 127 (SN = 0 - 738)
HCNT = SN + 737 (SN = 737 - 863)
where SN is Rec. 656/601 sample number on which the
negative edge of HSYNC occurs.
Luminance, Chrominance and Composite Video Outputs
The Luminance video output (LUMAOUT pin 54) drives a
37.5Ω load at 1.0V, sync tip to peak white. It contains only the
luminance content of the image plus the composite sync
pulses. In the NTSC mode, a set-up level offset can be added
during the active video portion of the raster.
SL_HS
A further adjustment is also required to ensure that the
correct Cr and Cb sample alignment. The bits SL_HS1-0
allows for four sampling positions in the CbYCrY sequence,
failure to set this correctly will mean corruption of the colour or
colour being interpreted as luma.
The Chrominance video output (CHROMAOUT pin 58)
drives a 37.5Ω load at levels proportional in amplitude to the
lumaoutput(40IREpk-pkburst).Thisoutputhasafixedoffset
current which will produce approximately a 0.5V DC bias
across the 37.5Ω load. Burst is injected with the appropriate
timing relative to the luma signal.
F_SWAP
If the field synchronisation is wrong it can be swapped by
setting this bit.
V_SYNC
The composite video output (COMPOUT pin 56) will also
drive a 37.5Ω load at 1.0V, sync tip to peak white. It contains
both the luminance and chrominance content of the signal
plus the composite sync pulses.
When set to a '1' this bit allows an odd/even square wave
to provide the field synchronisation.
Example
NTSC
The CVBS DAC output clipping feature limits the digital
data going into the DAC so that if it goes outside the range it
is limited to the maximum or minimum (511 or 000). This
feature is permanently enabled.
HSYNC occurs on Rec656 sample 721 (end of active
video), then;
HCNT = 721 + 119 = 839 = 348 Hex
SL_HS = 10 (for correct sample)
to set slave mode send .04w08pzfbw48pzffw01
CVBSCLP in register GCR. When set to a '1' this bit
9
VP5311B/VP5511B
this sets registers as follows:
Genlock using REFSQ input
TheVP5311canbeGenlockedtoanothervideosourceby
setting GENLKEN high (in GPSCTL register) and feeding a
phase coherent sub carrier frequency signal into REFSQ.
Under normal circumstances, REFSQ will be the same
frequency as the sub carrier. But by setting FSC4SEL high (in
GPSCTL register), a 4 x sub carrier frequency signal may be
input to REFSQ. In this case, the Genlock circuit can be reset
to the required phase of REFSQ, by supplying a pulse to
SCSYNC (pin 9). The frequency of SCSYNC can be at sub
carrier frequency, but once per line, or once per field could be
adequate, depending on the application. When GENLKEN is
set high, the direction setting of bit 6 in the GPPCTL register
is igonred.
reg
04
08
fb
ff
data
0b
01
Note: HSOFFshouldalwaysbezerowhenusingslavemode.
Video Timing - Master sync mode
When TRSEL (bit 0 of GPSCTL register) is set high, the
VP5311 operates in a MASTER sync mode, all REC656
timing reference codes are ignored and GPP bits D0 - 4
become a video timing port with VS, HS and FIELD outputs.
ThePXCKsignalis, however, stillusedtogenerateallinternal
clocks. When TRSEL is set high, the direction setting of bits 4
- 0 of the GPPCTL register is ignored.
VS is the start of the field sync datum in the middle of the
equalisation pulses. HS is the line sync which is used by the
preceding MPEG2 decoder to define when to output digital
video data to the VP5311. The position of the falling edge of
HS relative to the first data Cb0, can be programmed in
HSOFFM-L registers, see fig. 4.
PALID Input
When in Genlock mode with GENLKEN set high (in
GPSCTL register), the VP5311 requires a PAL phase
identification signal, to define the correct phase on every line.
This is supplied to PALID input (pin 10), High = -135° and low
= +135°. The signal is asynchronous and should be changed
before the sub carrier burst signal. PALID input is enabled by
setting PALIDEN high (in GPSCTL register). When
GENLKEN is high, the direction setting of bit 7 of the GPPCTL
register is ignored
HS offset
The position of the falling edge of HS relative to the first
data Cb0, can be programmed in HSOFFM-L registers, see
figure 4, this is called the pipeline delay and may need
adjusting for a particular application. This is done by
programming a 10 bit number called HSOFF into the
HSOFFM and HSOFFL registers, HSOFFM being the most
significanttwobitsandHSOFFLtheleastsignificanteightbits.
A default value of 07EH is held in the registers.
Master Reset
The VP5311/VP5511 must be initialised with the RESET
pin 34. This is an asynchronous active low signal and must be
active for a minimum of 200ns in order for the VP5311/
VP5511 to be reset. The device resets to line 64, start of
horizontal sync (i.e. line blanking active). There is no on-chip
power on reset circuitry.
The value to program into HSOFF can be looked up in
tables 3 &4:
Line 21 coding
NCK
HSOFF
126 to 6
Comment
Two bytes of data are coded on the line 21 of each field,
see figure 7. In the NTSC Closed Caption service, the default
state is to code on line 21 of field one only. An additional
service can also be provided using line 21 (284) of the second
field. The data is coded as NRZ with odd parity, after a clock
run-in and framing code. The clock run-in frequency =
0.5034965MHz which is related to the nominal line period, D
= H / 32.
0 to 120
HS normal (64 cks)
HS pulse shortened*
HS normal (64 cks)
121 to 138
184 to 857
863 to 801
800 to 127
Table.3 for NTSC
NCK
HSOFF
137 to 6
Comment
0 to 131
HS normal (64 cks)
HS pulse shortened*
HS normal (64 cks)
D = 63.55555556 / 32µs
132 to 194
195 to 863
869 to 807
806 to 138
Two data bytes per field are loaded via I2C bus registers
CCREG1-4. Each field can be independently enabled by
programmingtheenablebitsinthecontrolregister(CC_CTL).
The data is cleared to zero in the Closed Caption shift
registers after it has been encoded by the VP5311/VP5511.
Two status bit are provided (in CC_CTL), which are set high
when data is written to the registers and set low when the data
has been encoded on the Luma signal. The data is cleared to
zero in the Closed Caption shift registers after it has been
encoded by the VP5311/VP5511. The next data bytes must
be written to the registers when the status bit goes high,
otherwise the Closed Caption data output will contain Null
characters. If a transmission slot is missed (ie. no data
received) the encoder will send Null characters. Null
characters are invisible to a closed caption reciever. The MSB
(bit 7) is the parity bit and is automatically added by the
encoder.
Table.4 for PAL-B, D, G, H, I, N
where NCK = number of 13.5MHz clock cycles between the
falling edge of HS and Cb0 (first data I/P on PD7-0) see fig. 4.
Decreasing HSOFF advances the HS pulse (numbers are in
decimal).
*HS pulse shortened means that the width of the pulse will be
less than the normal 64 13.5MHz clock cycles.
The interruption in the sequence of values is because the HS
signalisjumpingacrossalineboundarytothepreviouslineas
the offset is increased. The register default value is 7EH and
this sets Nck to 0, ie. the HS negative edge and Cb0 are co-
incident in NTSC mode.
10
VP5311B/VP5511B
PXCK Input (27MHz)
SU; PD
t
HS
t
HD; PD
Nck=2
Nck=0
Cb0 Y0 Cr0
Y1 Cb1 Y2 Cr1
Y3
Pixel Data Input (PD[7,0])
Figure 4 REC 656 interface with HS output timing
2:1 mux
REFSQ
f
SC
0
1
Divide by 4
Synchronous
Counter
Input to
Genlocking
Block
Q
RESET
FSC4_SEL
SC_SYNC
REFSQ
(register bit)
SC_SYNC
1/ f
PWH; SC_SYNC
t
t
SU; SC_SYNC
HD; SC_SYNC
t
SC_SYNC
Q
Figure 5 REFSQ and SC_SYNC input timing
Pixel Data Input (PD[7,0\)
Sample Number
1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450
Y719 $FF $00 $00 $XY
ANCILLARY DATA...
EAV SEQUENCE
t
SU; PD
t
HD; PD
t
PWL; PXCK
t
PWH; PXCK
PXCK Input (27MHz)
t
DUR; PAL_ID
t
SU; PAL_ID
t
HD; PAL_ID
PAL_ID Stable
Input (PAL_ID)
Figure 6 PAL_ID input timing
11
VP5311B/VP5511B
TIMING INFORMATION
Symbol
Conditions
Parameters
Master clock frequency (PXCK input)
PXCX pulse width, HIGH
PXCX pulse width, LOW
PXCX rise time
Typ.
Min.
Max.
Units
MHz
ns
fPXCK
tPWH; PXCK
tPWL; PXCK
tRP
27.0
10
14.5
ns
TBD
TBD
ns
10% to 90% points
90% to 10% points
tFP
PXCX fall time
ns
10
5
PD7-0 set up time
tSU;PD
ns
PD7-0 hold time
tHD;PD
ns
tSU;SC_SYNC
tHD;SC_SYNC
tSU;PAL_ID
tHD;PAL_ID
tDUR;PAL_ID
10
0
SC_SYNC set up time
SC_SYNC hold time
PAL_ID set up time
PAL_ID hold time
ns
ns
10
0
ns
ns
9
PAL_ID duration
PXCX
periods
ns
tDOS
Output delay
25
PXCK to COMPSYNC
PXCK to CLAMP
Note: Timing reference points are at the 50% level. Digital C LOAD <40pF.
H
C D
E
B
A
START BITS
CLOCK RUN-IN
HSYNC COLOUR BURST
DATA BYTE 1
DATA BYTE 2
1
13
50
0
P
P
BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7
S1 S2 S3
-40
0
1
0 0 0 0 1 1
IRE
FRAME CODE
P = Parity Bit
Figure 7 Closed Capation format
12
VP5311B/VP5511B
Encoder minimum
Encoder nominal
Encoder maximum
Interval
Description
H-sync to clock run-in
Clock run-in2, 3
Clock run-in to third start bit 3
Data bit 1, 3
Data characters 4
Horizontal line 1
Rise / fall time of data bit transitions 5
A
B
C
D
E
H
10.250µs
10.500µs
6.5D (12.910µs)
2.0D (3.972µs)
1.0D (1.986µs)
16.0D (31.778µs)
32.0D (63.556)
0.240µs
10.750µs
0.288µs
Data bit high (logic level one) 6
Clock run-in maximum
Data bit low (logic level zero) 6
Clock run-in minimum
48 IRE
0 IRE
50 IRE
52 IRE
0 IRE
2 IRE
48 IRE
Data bit differential (high - low)
50 IRE
52 IRE
Clock run-in differential (max. - min)
Table. 5 Closed Caption data timing. (source EIA R - 4.3 Sept 16 1992)
Notes
1. The Horizontal line frequency f is nominally 15734.26Hz ±0.05Hz. Interval D shall be adjusted to D = 1/(f x 32) for the
H
H
instantaneous f at line 21.
H
2. The clock run-in signal consists of 7.0 cycles of a 0.5034965MHz (1/D) sine wave when measured from the leading to trailing
0 IRE points. The sine wave is to be symmetrical about the 25 IRE level.
3. The negative going midpoints (half amplitude) of the clock run-in shall be coherent with the midpoints (half amplitude) of the
Start and Data bit transitions.
4. Two characters, each consisting of 7 data bits and 1 odd parity bit.
5. 2 T Bar, measured between the 10% and 90% amplitude points.
6. The clock run-in maximum level shall not differ from the data bit high level by more than ±1 IRE. The clock run-in minimum
level shall not differ from the data bit low level by more than ±1 IRE.
13
VP5311B/VP5511B
FERRITE
BEAD
VDD
GND
+5V
AT EVERY
VDD PIN
10nF
100µF
2k2Ω
2k2Ω
VDD, AVDD
SCL
28
30
26
54
OUTPUT
FILTER
SCL
SDA
SA1
SA2
I2C
LUMA OUT
LUMA
SDA
SA1
SA2
100µF
+5V
BUS
52
COMP
27
39-46
35
PD0-7
VIDEO IN
REFSQ
8
58
51
OUTPUT
FILTER
CHROMA
CHROMA OUT
REFSQ
769Ω
DACGAIN
15
PXCK
GPP
PXCK
D0-7
3-10
50
56
VREF
VREF
8
100nF
34
RESET
RESET
CLAMP
OUTPUT
FILTER
COMP
OUT
COMP OUT
17
18
CLAMP
COMP
SYNC
COMP
SYNC
GND, AGND
GND
Figure 8 Typical application diagram, SLAVE mode. (Output filter - see Fig.9)
15pF
1.0µH
EXT
75Ω
75Ω
470pF
220pF
GND
Figure 9 Output reconstruction filter
14
VP5311B/VP5511B
Note:
The VP5311 is only available to customers with a valid and existing authorisation to purchase issued by MACROVISION
CORPORATION.
This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of
the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial, home and limited exhibition uses
only. Reverse engineering or disassembly is prohibited.
15
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